CN111755458B

CN111755458B - Three-dimensional memory

Info

Publication number: CN111755458B
Application number: CN202010655143.1A
Authority: CN
Inventors: 徐伟; 杨星梅; 王健舻; 吴继君; 黄攀; 周文斌
Original assignee: Yangtze Memory Technologies Co Ltd
Current assignee: Yangtze Memory Technologies Co Ltd
Priority date: 2020-07-09
Filing date: 2020-07-09
Publication date: 2021-12-21
Anticipated expiration: 2040-07-09
Also published as: CN111755458A

Abstract

The invention provides a three-dimensional memory, belongs to the technical field of semiconductor storage, and aims to solve the problem that a functional layer at the joint of a first channel hole and a second channel hole is damaged when a channel structure at the bottom of the channel hole is opened. The three-dimensional memory includes a semiconductor layer passing through a gate layer closest to a substrate and contacting the substrate, and in a direction parallel to the substrate, passing through a functional layer closest to the substrate and contacting a channel layer; so that the channel layer contacts the substrate through the semiconductor layer and forms an electrical connection. The three-dimensional memory provided by the invention can avoid damaging the functional layer at the joint of the second channel hole and the first channel hole while realizing the electrical connection between the substrate and the channel layer, thereby improving the yield and the reliability of the three-dimensional memory.

Description

Three-dimensional memory

Technical Field

The invention relates to the technical field of semiconductor storage, in particular to a three-dimensional memory.

Background

With the development of semiconductor memory devices, the demand for semiconductor memory devices having high-density data memory cells is also continuously increasing; therefore, a three-dimensional memory having a plurality of data storage unit layers vertically stacked has been a hot spot of research.

The three-dimensional memory comprises a substrate and a plurality of stack structures stacked on the substrate, for example, two stack structures are stacked on the substrate: an upper stack structure and a lower stack structure; the upper stacking structure is provided with a second channel hole, the lower stacking structure is provided with a first channel hole, and the second channel hole is communicated with the first channel hole to form a channel hole penetrating through the two stacking structures; and a functional layer and a channel layer positioned on the inner surface of the functional layer are formed on the inner surface of the channel hole, and one end of the functional layer facing the substrate is required to be etched to form a through hole communicated with the substrate epitaxial region so that the channel layer penetrates through the through hole and is electrically connected with the substrate epitaxial region.

However, in the process of manufacturing the three-dimensional memory, a misalignment phenomenon is likely to occur between the second channel hole and the first channel hole, so that when the bottom of the functional layer is etched on the front side to form a through hole, the functional layer at the joint of the second channel hole and the first channel hole is damaged, the storage function of the three-dimensional memory is disabled, and the yield and the reliability of the three-dimensional memory are reduced.

Disclosure of Invention

The embodiment of the invention provides a three-dimensional memory, which can avoid damaging a functional layer at the joint of a second channel hole and a first channel hole while realizing the electrical connection between a substrate and the channel layer, and improve the yield and the reliability of the three-dimensional memory.

In order to achieve the above purpose, the embodiment of the invention adopts the following technical scheme:

an embodiment of the present invention provides a three-dimensional memory, including: a substrate; the stack structure is positioned on the substrate and comprises a plurality of layers of gate layers and insulating layers which are alternately arranged; a channel structure passing through the stack structure and extending to the substrate, the channel structure comprising a channel layer and a functional layer surrounding the channel layer; a semiconductor layer in contact with the substrate through a gate layer closest to the substrate, the semiconductor layer also in contact with the channel layer through the functional layer in a direction parallel to the substrate.

In an alternative embodiment, further comprising: peripheral circuitry located on the stack structure, the peripheral circuitry to implement logic control.

In an alternative embodiment, further comprising: a drain on the channel structure, the drain in contact with the channel layer; an interconnect structure between the drain and the peripheral circuitry, the interconnect structure being electrically connected to the drain and the peripheral circuitry, respectively.

In an alternative embodiment, further comprising: the isolation structure penetrates through the stack structure and extends along a set direction to divide the stack structure into a plurality of blocks.

In an alternative embodiment, the isolation structure is an insulating pillar.

In an alternative embodiment, the stack structure includes an etch stop layer between the gate layer closest to the substrate and the gate layer adjacent to the gate layer, and the channel structure passes through the etch stop layer.

In an alternative embodiment, further comprising: a bottom selection gate; and the gate layer positioned between the etching barrier layer and the substrate is used as the bottom selection gate.

In an alternative embodiment, further comprising: a first doped well within the substrate; a second doped well located within the first doped well, the first doped well being of an opposite doping type to the second doped well; the projection of the isolation structure in the direction perpendicular to the substrate is located in the second doped well.

In an alternative embodiment, further comprising: a conductive plug passing through the second doped well.

In an alternative embodiment, an ohmic contact layer is disposed between the conductive plug and the second doping well; the ohmic contact layer is located on the side wall of the conductive plunger and is in contact with the second doping well.

In an optional embodiment, the doping type of the first doping well is P-type, and the doping type of the second doping well is N-type.

In an alternative embodiment, the stack structure includes a first stack structure and a second stack structure located on the first stack structure; the channel structure comprises a first channel structure and a second channel structure which are stacked; the first channel structure passes through the first stack structure and the second channel structure passes through the second stack structure.

In an alternative embodiment, the first channel structure protrudes radially beyond the second channel structure at the junction of the first channel structure and the second channel structure.

In an alternative embodiment, further comprising: a conductive member located on a back surface of the substrate and in contact with the substrate.

In an alternative embodiment, the semiconductor layer further comprises a first skin layer and a second skin layer surrounding the gate layer closest to the substrate; the first surface layer is located on the side, facing the substrate, of the gate layer closest to the substrate, and the second surface layer is located on the side, facing away from the substrate, of the gate layer closest to the substrate.

In an alternative embodiment, a first insulating layer is disposed between the gate layer closest to the substrate and the first surface layer; a second insulating layer is arranged between the gate layer closest to the substrate and the second surface layer.

In an alternative embodiment, the material of the semiconductor layer comprises polysilicon.

In an alternative embodiment, the material of the gate layer closest to the substrate comprises tungsten.

Compared with the related art, the three-dimensional memory provided by the embodiment of the invention has the following advantages;

the three-dimensional memory provided by the embodiment of the invention comprises a semiconductor layer, a first electrode, a second electrode, a third electrode and a fourth electrode, wherein the semiconductor layer penetrates through a grid layer closest to a substrate and is in contact with the substrate, and in the direction parallel to the substrate, the semiconductor layer penetrates through a functional layer closest to the substrate and is in contact with a channel layer; so that the channel layer contacts the substrate through the semiconductor layer and forms an electrical connection. Compared with the related art, the semiconductor layer electrically connected with the channel layer is formed on one side, close to the substrate, of the stack structure, and the bottom of the channel structure is not required to be etched by adopting front etching, so that the channel layer is exposed and is electrically connected with the substrate; the functional layer at the joint of the second channel hole and the first channel hole can be prevented from being damaged, and the yield and the reliability of the storage function of the three-dimensional memory are improved.

In addition to the technical problems solved by the embodiments of the present invention, the technical features constituting the technical solutions, and the advantages brought by the technical features of the technical solutions described above, other technical problems that can be solved by the three-dimensional memory provided by the embodiments of the present invention, other technical features included in the technical solutions, and advantages brought by the technical features will be further described in detail in the detailed description.

Drawings

In order to more clearly illustrate the embodiments of the present invention or technical solutions in related arts, the drawings used in the description of the embodiments of the present invention or related arts will be briefly introduced below, it is obvious that the drawings in the following description are only a part of the embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.

Fig. 1 is a schematic cross-sectional view of a three-dimensional memory according to an embodiment of the invention;

FIG. 2 is a flowchart illustrating a method for fabricating a three-dimensional memory according to an embodiment of the present invention;

fig. 3 to fig. 22 are schematic cross-sectional views of stages of fabricating a three-dimensional memory according to an embodiment of the invention;

fig. 23 is a schematic cross-sectional view of a three-dimensional memory according to a second embodiment of the invention;

FIG. 24 is a flowchart illustrating a method for fabricating a three-dimensional memory according to a second embodiment of the present invention;

fig. 25 to 37 are schematic cross-sectional views of stages of fabricating a three-dimensional memory according to a second embodiment of the invention;

fig. 38 is a schematic cross-sectional view of a three-dimensional memory according to a third embodiment of the invention;

FIG. 39 is a flowchart illustrating a method for fabricating a three-dimensional memory according to a third embodiment of the present invention;

fig. 40 to 55 are schematic cross-sectional views of stages of fabricating a three-dimensional memory according to a third embodiment of the invention.

Description of reference numerals:

10-a substrate; 11-a semiconductor plunger;

12-a first via; 13-a second via;

14-a first doping well; 15-a second doping well;

16-a conductive member; 20-a first protective layer;

21-a first dielectric layer; 22-replacement layer;

23-a second dielectric layer; 24-a second cavity;

25-a first gate layer; 26-a semiconductor layer;

30-etching the barrier layer; 40-a laminated structure;

40 a-stacked configuration; 41-a first stack;

41 a-a first stack structure; 42-a second laminate structure;

42 a-a second stack structure; 43-gate gap;

44-an isolation structure; 50-channel holes;

51-a first channel hole; 52-second channel hole;

60-channel structure; 61-a first channel structure;

61 a-a first functional layer; 61 b-a first channel layer;

62-a second channel structure; 62 a-a second functional layer;

62 b-a second channel layer; 63-a trench filling layer;

64-a drain electrode; 70-an interconnect structure;

80-peripheral circuitry; 131-a conductive plunger;

132-ohmic contact layer; 241-a first insulating protection layer;

242-a first spacer layer; 243-first skin layer;

244-a second skin layer; 245-a second barrier layer;

246-a first insulating layer; 247-a second insulating layer;

248-a second insulating protection layer; 249-a third barrier layer;

511-a first filling layer; 512-first support layer;

513 — a second support layer.

Detailed Description

In the related art, a three-dimensional memory includes a substrate and at least two stacked structures disposed on the substrate; for example, a first stacked structure and a second stacked structure are stacked in this order on a substrate; the first laminated structure is provided with a first channel hole, the second laminated structure is provided with a second channel hole, and the second channel hole is communicated with the first channel hole to form a channel hole penetrating through the two laminated structures. A channel structure is formed in the channel hole, and the channel structure comprises a functional layer and a channel layer, wherein the functional layer is sequentially formed on the inner surface of the channel hole, and the channel layer is positioned on the inner surface of the functional layer; in order to electrically connect one end of the channel layer close to the substrate with the epitaxial region of the substrate, the functional layer at the bottom of the channel hole needs to be opened to form a through hole communicated with the epitaxial region of the substrate. One end of the channel layer close to the substrate extends to the substrate through the through hole and is electrically connected with the epitaxial region of the substrate.

However, in the process of manufacturing the three-dimensional memory, misalignment is likely to occur between the second channel hole and the first channel hole, so that when the channel hole is used as an etching channel to perform front etching on the bottom of the functional layer, the functional layer at the connection position of the second channel hole and the first channel hole is easily damaged, the storage function of the three-dimensional memory is further failed, and the yield and the reliability of the three-dimensional memory are reduced.

In order to solve the above problem, an embodiment of the invention provides a three-dimensional memory, in which a second through hole is formed through a back surface of a substrate, a semiconductor layer is formed on a side of a stack structure close to the substrate by using the second through hole, the semiconductor layer is electrically connected to a channel structure closest to the substrate, and the semiconductor layer is electrically connected to the substrate, so that a loop is formed between the channel layer and the substrate through the semiconductor layer. Compared with the prior art, the embodiment can avoid the phenomenon that the functional layer at the joint of the second channel hole and the first channel hole is damaged when the front etching is carried out on the bottom of the channel structure by using the channel hole as the etching channel, so that the yield and the reliability of the storage function of the three-dimensional memory are improved.

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below. It is to be understood that the described embodiments are merely a few embodiments of the invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

Example one

FIG. 1 is a schematic structural diagram of a three-dimensional memory according to an embodiment of the invention; as shown in fig. 1, the three-dimensional memory provided by the embodiment of the present invention includes a substrate 10, the substrate 10 may be made of a semiconductor material, the material of the substrate 10 includes, but is not limited to, silicon, germanium, silicon germanium, and the like, and the substrate 10 may be made of monocrystalline silicon.

A stack structure 40a is provided on the substrate 10; illustratively, the substrate 10 is sequentially provided with a first stack structure 41a and a second stack structure 42a, i.e., the second stack structure 42a is located above the first stack structure 41 a. The first stack structure 41a and the second stack structure 42a each include a plurality of insulating layers and a plurality of gate layers alternately arranged; the thickness of the gate layer and the thickness of the insulating layer may be the same or different.

The gate layer is made of a conductive material including, but not limited to, tungsten, copper, aluminum, doped silicon, and/or silicide. The insulating layer is made of an insulating material, and the insulating material for forming the insulating layer includes, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. Of course, more than three stack structures may be stacked on the substrate 10 in sequence, and the number of the stacked gate layers may be specifically set according to the number of the gate layers actually stacked.

The stack structure 40a is provided with a vertical structure therethrough, which includes the channel structure 60 and the semiconductor plug 11 in a stacked arrangement. For example, the channel structure 60 includes a first channel structure 61 and a second channel structure 62; the second channel structure 62 is located above the first channel structure 61, and the second channel structure 62 and the first channel structure 61 are connected together. At the junction of the first channel structure 61 and the second channel structure 62, the first channel structure 61 protrudes the second channel structure 62 in the radial direction, so that the second channel structure 62 is aligned and connected with the first channel structure 61.

As shown in fig. 6-10; in the present embodiment, the first channel structure 61 penetrates through the first stack structure 41a, the first stack structure 41a is disposed on the substrate 10, the first stack structure 41a is provided with a first channel hole 51 penetrating therethrough, and one end of the first channel hole 51 close to the substrate 10 may extend to the inside of the substrate 10. A first channel structure 61 is located within the first channel hole 51, the first channel structure 61 including, but not limited to, a first functional layer 61a and a first channel layer 61 b; the first functional layer 61a is disposed on an inner sidewall of the first channel hole 51, the first channel layer 61b is disposed on an inner sidewall of the first functional layer 61a, and a bottom of the first channel layer 61b passes through the first functional layer 61a and is coupled with the substrate 10.

The surface of the first stack structure 41a away from the substrate 10 is provided with a second stack structure 42a, the second stack structure 42a is provided with a second channel hole 52 penetrating therethrough, and the second channel hole 52 is communicated with the first channel hole 51. A second channel structure 62 is formed within the second channel hole 52, the second channel structure 62 including, but not limited to, a second functional layer 62a and a second channel layer 62 b; the second functional layer 62a is disposed on an inner sidewall of the second channel hole 52, and the second functional layer 62a is connected with the first functional layer 61 a; the second channel layer 62b is disposed on an inner sidewall of the second functional layer 62a, and the second channel layer 62b is connected with the first channel layer 61 b; a drain electrode 64 is provided at an end of the second channel layer 62b remote from the substrate 10, and the drain electrode 64 is in contact with the second channel layer 62 b.

Further, the first functional layer 61a and the second functional layer 62a each include a blocking dielectric layer, a charge storage layer, and a tunneling dielectric layer sequentially stacked along the inner surface of the channel hole 50; the charge storage layer is arranged between the blocking dielectric layer and the tunneling dielectric layer; the tunneling dielectric layer and the blocking dielectric layer are respectively composed of oxides, such as silicon oxide; the charge storage layer is made of materials including but not limited to silicon nitride, silicon oxynitride, or a combination of silicon oxide and silicon nitride, or a combination of the above materials; the tunneling dielectric layer, the charge storage layer and the blocking dielectric layer are connected with the plurality of grid layers to form a plurality of storage units.

Referring to fig. 1, the semiconductor plug 11 is located at an end of the first channel structure 61 close to the substrate 10, that is, the semiconductor plug 11 is located at an end of the first channel structure 61 away from the second channel structure 62, and the semiconductor plug 11 penetrates through the gate layer closest to the substrate 10 and contacts the first channel layer 61b of the first channel structure 61.

Specifically, the semiconductor plug 11 is disposed on the back side of the substrate 10 and extends toward the stack structure 40a, and the semiconductor plug 11 penetrates the substrate 10 and is connected to the first channel layer 61b in the first channel structure 61. For example, a plurality of first through holes 12 are formed in the substrate 10, each first through hole 12 is respectively opposite to one first channel structure 61, a semiconductor plunger 11 is arranged in each first through hole 12, and the semiconductor plunger 11 is made of a conductive material; that is, the semiconductor plug 11 is disposed opposite to the first channel structure 61, and one end of the semiconductor plug 11 facing the first channel structure 61 is electrically connected to the first channel layer 61b, thereby forming a loop between the first channel layer 61b and the substrate 10.

In the three-dimensional memory provided by the embodiment, the first through hole 12 penetrating through the substrate 10 is arranged on the back surface of the substrate 10, the first through hole 12 is used for etching and opening the bottom of the first channel structure 61 from the back side of the substrate 10, and the semiconductor plunger 11 electrically connected with the first channel layer 61b is arranged in the first through hole 12, so that the phenomenon that the functional layer at the connection position of the second channel hole and the first channel hole is damaged when the channel hole is used as an etching channel for carrying out front etching on the bottom of the channel structure can be avoided, and the yield and the reliability of the storage function of the three-dimensional memory are improved.

Further, as shown in fig. 13 and 14, in order to improve the stability of the electrical connection between the semiconductor plug 11 and the first channel layer 61b, the first channel layer 61b protrudes the first functional layer 61a in a direction perpendicular to the substrate 10, that is, a portion of the first channel layer 61b protruding the first functional layer 61a is wire-connected to the semiconductor plug 11.

The present embodiment further includes an etching stop layer 30 in the stack structure 40a on a side close to the substrate 10, and the etching stop layer 30 is used for protecting a portion of the stack structure 40a when the substrate 10 is etched and the semiconductor plug 11 is formed.

Specifically, the first stack structure 41a includes a gate layer closest to the substrate 10, and for convenience of describing the present embodiment, the gate layer closest to the substrate may be defined as the first gate layer 25, and the gate layer adjacent to the first gate layer 25 is the second gate layer. The etching barrier layer 30 is disposed between the first gate layer 25 and the second gate layer, and a dielectric layer is disposed between the first gate layer 25, the second gate layer and the etching barrier layer 30, respectively, and the semiconductor plug 11 passes through the first gate layer 25, the etching barrier layer 30 and is electrically connected to the first channel layer 61 b.

Further, on the basis of the above embodiment, the first gate layer 25 located between the etch stop layer 30 and the substrate 10 may be used as a bottom select gate; the first gate layer 25 is a conductive layer made of metal tungsten, and the first gate layer 25, the first dielectric layer 21 and the second dielectric layer 23 on two sides of the first gate layer are provided with a plurality of openings, and each opening is opposite to the semiconductor plunger 11, so that the semiconductor plunger 11 can penetrate through the first gate layer 25 and be electrically connected with the first channel layer 61 b; meanwhile, dielectric layers are arranged on two sides of the first gate layer 25, namely a second dielectric layer 23 is arranged between the first gate layer 25 and the etching barrier layer 30, and a first dielectric layer 21 is arranged between the first gate layer 25 and the substrate 10; and at the opening, the first dielectric layer 21 and the second dielectric layer 23 are connected together so that the first gate layer 25 is insulated from the semiconductor plug 11, and at the same time, the first gate layer 25 is also insulated from the substrate 10.

Referring to fig. 1, the three-dimensional memory provided in this embodiment further includes an isolation structure 44, wherein the isolation structure 44 penetrates through the first stack structure 41a and the second stack structure 42a, and the isolation structure 44 extends along a predetermined direction, and the isolation structure 44 may extend to the etch stop layer 30. For example, the isolation structure 44 extends in a direction perpendicular to the first and

second stack structures

41a and 42a, and the isolation structure 44 penetrates through the first and

second stack structures

41a and 42a and extends to the etch stop layer 30, so as to divide the stack structure 40a into a plurality of blocks, and each block is independent from each other.

Referring to fig. 8, the isolation structure 44 may be disposed in the gate slit 43 of the stack structure 40a, the isolation structure 44 may be formed by filling an insulating material in the gate slit 43 to form an insulating pillar, one end of the insulating pillar abuts against the etch stop layer 30, the other end of the insulating pillar may extend to a surface of the second stack structure 42a away from the first stack structure 41a, and the insulating pillar may be flush with the surface of the second stack structure 42 a.

Referring to fig. 15 and 22, in the present embodiment, no specific requirement is made on the arrangement position of the semiconductor plug 11 on the substrate 10; the substrate 10 includes a first doping well 14, and at least one second doping well 15 is disposed in the first doping well 14, and the doping type of the first doping well 14 is opposite to that of the second doping well 15. Illustratively, the doping type of the first doping well 14 is P-type, the doping type of the second doping well 15 is N-type, that is, a P-type doping region and an N-type doping region are disposed on the substrate 10, two sides of the first doping well 14 are respectively provided with one second doping well 15, and a projection of the isolation structure 44 perpendicular to the direction of the substrate 10 is located in the second doping well 15.

The first doping well 14 may be disposed opposite to the first channel structure 61, and the semiconductor plug 11 is located in the first doping well 14, and the doping type of the semiconductor plug 11 is the same as that of the first doping well 14. Conductive plugs 131 are arranged in the second doping well 15 at two sides of the first doping well 14, and ohmic contact layers 132 are formed in the contact regions of the conductive plugs 131 and the second doping well 15.

Specifically, the second doping well 15 is provided with a second via 13 interposing the conductive plug 131, and the second via 13 extends from the back side of the substrate 10 (the side of the substrate 10 facing away from the first stack structure 41 a) to the front side of the substrate 10 (the side of the substrate 10 facing toward the first stack structure 41 a). The conductive plug 131 may be a conductive block made of tungsten, and an ohmic contact layer 132 is formed on a contact surface of the conductive plug 131 and the second doped well 15, where the ohmic contact layer 132 may reduce the resistance between the conductive plug 131 and the second doped well 15.

On the basis of the above embodiment, the three-dimensional memory provided by the present embodiment further includes a conductive member 16, the conductive member 16 is located on the back surface of the substrate 10, and the conductive member 16 covers the back surface of the substrate 10; the side of the conductive part 16 facing the substrate 10 is electrically connected with the semiconductor plunger 11 and the conductive plunger 131 on the substrate 10, and the side of the conductive part 16 facing away from the substrate 10 can be electrically connected with peripheral devices.

On the basis of the above embodiment, the three-dimensional memory further includes a peripheral circuit 80 disposed on the second stack structure 42a and an interconnect structure 70 located between the peripheral circuit 80 and the second stack structure 42 a. Specifically, the interconnect structure 70 is disposed on a surface of the second stack structure 42a away from the substrate 10, a side of the interconnect structure 70 facing the second stack structure 42a is electrically connected to the drain 64 formed in the second stack structure 42a, and a side of the interconnect structure 70 away from the second stack structure 42a is electrically connected to the peripheral circuit 80. The interconnection structure 70 includes a plurality of interconnection layers, and two adjacent interconnection layers are electrically connected through a conductive plug; the peripheral circuit 80 includes a substrate and a complementary metal oxide semiconductor (cmos) circuit formed on the substrate, wherein the cmos circuit is electrically connected to the second channel structure 62 through the interconnect structure 70 to implement logic control.

FIG. 2 is a method of fabricating a three-dimensional memory according to one embodiment; FIGS. 3-22 are schematic structural diagrams illustrating stages in forming a three-dimensional memory according to a first embodiment; a method for fabricating a three-dimensional memory according to a first embodiment is described below with reference to fig. 2 to 22.

First, step S100 is performed: as shown in fig. 3, a substrate 10 is provided, for example, the substrate 10 may be made of single crystal silicon for protecting and supporting a subsequently formed stacked structure.

Next, step S200 is executed: a first protective layer 20 and an etch stopper 30 are sequentially formed on a substrate 10. Illustratively, the first protective layer 20 may be considered as a part of a stacked structure, the first protective layer 20 including a first dielectric layer 21, a replacement layer 22, and a second dielectric layer 23 sequentially deposited and formed on the substrate 10; the material of the first dielectric layer 21 and the second dielectric layer 23 includes, but is not limited to, silicon oxide, and the replacement layer 22 is removed and replaced by a gate layer (the gate layer closest to the substrate 10, which may be defined as a first gate layer) in a subsequent process, so that the material of the replacement layer 22 may be selected to have a higher etching selectivity with respect to the first dielectric layer 21 and the second dielectric layer 23, and the material of the replacement layer 22 may include, but is not limited to, titanium nitride.

After forming the first protection layer 20 on the substrate 10, an etching stop layer 30 may be deposited on a side of the first protection layer 20 away from the substrate 10, and the structure formed by this step is as shown in fig. 3. Illustratively, the etch stop layer 30 is made of a material including, but not limited to, alumina, and the thickness thereof may be set to 50 nm; the etching barrier layer 30 is a laminated structure which prevents the replacement layer 22 from being excessively etched and damages one side of the etching barrier layer 30 far away from the substrate 10 when the replacement layer 22 in the first protective layer 20 is subsequently etched; that is, in the subsequent manufacturing process, when the first gate layer 25 is formed at the position of the replacement layer 22, the replacement layer 22 needs to be etched to form a cavity for forming the first gate layer 25, so as to prevent the second dielectric layer 23 in the first protective layer 20 from being excessively etched in the etching process, and avoid damage to the stacked structure located on the side of the second dielectric layer 23 away from the substrate.

After the first protection layer 20 and the etching stop layer 30 are formed on the substrate 10, step S300 is performed: at least two stacked structures are stacked on the substrate 10, and a channel hole 50 penetrating the stacked structures is formed.

Illustratively, as shown in fig. 6, a first stacked structure 41 and a second stacked structure 42 on the first stacked structure 41 are sequentially stacked on the substrate 10, the first stacked structure 41 is etched in a direction perpendicular or approximately perpendicular to the substrate 10 to form a first channel hole 51, the second stacked structure 42 is formed on a surface of the first stacked structure 41 away from the substrate 10, the second stacked structure 42 is etched in a direction perpendicular or approximately perpendicular to the substrate 10 to form a second channel hole 52, the second channel hole 52 is communicated with the first channel hole 51 to form a channel hole 50 penetrating through the second stacked structure 42 and the first stacked structure 41 and extending to the substrate 10, and is located at a connection position of the first channel hole 51 and the second channel hole 52, and the first channel hole 51 protrudes in a radial direction out of the second channel hole 52 to facilitate alignment of the first channel hole 51 and the second channel hole 52.

There are various specific ways to form the stacked structure 40 on the substrate 10, and in an alternative embodiment, the step S300 includes:

after forming the etch stop layer 30 on the first protective layer 20, a first stacked structure 41 is formed on the etch stop layer 30, and the structure formed in this step is shown in fig. 3. Illustratively, a plurality of sacrificial layers and a plurality of insulating layers are alternately deposited on the etch stop layer 30, and a structure formed by alternately stacking the sacrificial layers and the insulating layers is the first stacked structure 41; the insulating layer is made of a material including, but not limited to, silicon oxide, the sacrificial layer is made of a material including, but not limited to, silicon nitride, and the sacrificial layer is replaced by the gate layer in a subsequent process to form the first stack structure. The sacrificial layer and the insulating layer may be sequentially deposited on the substrate 10 by Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD), or other suitable deposition methods during the process of forming the sacrificial layer and the insulating layer.

After forming the first stacked structure 41 on the substrate 10, a first channel hole 51 penetrating through the first stacked structure 41 is formed in the first stacked structure 41, and an end of the first channel hole 51 facing the substrate 10 may extend into the substrate 10, so as to thin the back surface of the subsequent substrate 10 and expose the first channel structure 61 at the bottom of the first channel hole 51.

Illustratively, the first stacked structure 41, the etch stopper 30, and the first protection layer 20 formed of the plurality of sacrificial layers and the plurality of insulation layers may be etched in a direction perpendicular or approximately perpendicular to the substrate 10, the etching is stopped inside the substrate 10, and the first channel hole 51 is formed. For example, the first stacked structure 41, the etch stopper 30, and the first protection layer 20 may be etched by dry etching, and the substrate 10 may be partially etched to form a groove in the substrate 10, i.e., the first channel hole 51 may extend to the inside of the substrate 10.

After forming the first channel hole 51 in the first stacked structure 41, a first filling layer 511 is formed at the bottom of the first channel hole 51, and the structure formed in this step is as shown in fig. 4. Illustratively, the first filling layer 511 is formed by filling an easily-etched material in the first channel hole 51, the etching material for forming the first filling layer 511 includes, but is not limited to, silicon oxide, and a surface of the first filling layer 511 away from the substrate 10 may protrude from a surface of the first protection layer 20 away from the substrate 10 and be lower than a surface of the etch stop layer 30 away from the substrate 10, so that a bottom of the first channel structure 61 subsequently formed in the first channel hole 51 is located on a side of the first protection layer 20 away from the substrate 10.

After the first filling layer 511 is formed at the bottom of the first channel hole 51, the first channel hole 51 may be filled with a sacrificial material to form the first support layer 512, which is shown in fig. 5. Illustratively, the sacrificial material for making the first support layer 512 includes, but is not limited to, polysilicon, an end of the first support layer 512 facing the substrate 10 is attached to the first filling layer 511, and an end of the first support layer 512 away from the substrate 10 extends toward the first stacked structure 41 away from the substrate 10. In this embodiment, the first trench 51 is filled with the first filling layer 511 and the first supporting layer 512, and the first supporting layer 512 and the first filling layer 511 support the second stacked structure 42 formed above the first stacked structure 41, so as to prevent the first stacked structure 41 from being deformed, thereby improving the stability of the stacked structures in the three-dimensional memory.

Further, after the first support layer 512 is formed in the first channel hole 51, in order to ensure that the surface of the first support layer 512 away from the substrate 10 and the surface of the first stacked structure 41 away from the substrate 10 are located on the same horizontal plane, the first support layer 512 may be subjected to planarization processing. For example, the upper surface of the first support layer 512 may be subjected to Chemical Mechanical Polishing (CMP) to make the upper surface of the first stacked structure 41 and the upper surface of the first support layer 512 flush, so as to improve the stability of the second stacked structure 42 formed on the first stacked structure 41 and reduce the possibility of tilting or collapsing of each stacked structure.

As shown in fig. 6, after the first support layer 512 is formed in the first channel hole 41, the second stacked structure 42 is formed on the surface of the first stacked structure 41 away from the substrate 10 and the surface of the first support layer 512 away from the substrate 10.

After the second stacked structure 42 is formed on the first stacked structure 41, a second channel hole 52 penetrating the second stacked structure 42 is formed in the second stacked structure 42, the second channel hole 52 communicates with the first channel hole 51 to form a channel hole 50 penetrating the second stacked structure 42 and the first stacked structure 41, and one end of the channel hole 50 near the substrate 10 extends into the substrate 10. Illustratively, the second stacked structure 42 is etched in a direction perpendicular or approximately perpendicular to the substrate 10; for example, a second channel hole 52 is formed to penetrate the second stacked structure 42 by dry etching, and a lower end of the second channel hole 52 communicates with an upper end of the first channel hole 51.

After the second stacked structure 42 forms the second channel hole 52 penetrating through it, etching and removing the first supporting layer 512 located in the first channel hole 51, and remaining the first filling layer 511 located in the first channel hole 51; the first channel hole 51 may be newly formed in the first laminate structure 41, thereby achieving communication of the second channel hole 52 with the first channel hole 51; i.e. the channel hole 50 is reformed in the entire stack 40.

After forming the trench hole 50 penetrating the entire stacked structure 40 on the substrate 10, step S400 is performed: a channel structure 60 is formed within channel hole 50 and the resulting structure is shown in fig. 7. Illustratively, the channel structure 60 includes a first channel structure 61 formed within the first channel hole 51, and a second channel structure 62 formed within the second channel hole 52; a first functional layer 61a and a first channel layer 61b on the inner surface of the first functional layer 61a are sequentially formed on the inner surface of the first channel hole 51; a second functional layer 62a and a second channel layer 62b on the inner surface of the second functional layer 62a are sequentially formed on the inner surface of the second channel hole 52.

The bottom of the first channel structure 61 is formed on the first filling layer 511, the first filling layer 511 is interposed between the bottom of the first channel structure 61 and the substrate 10, the second channel structure 62 is formed above the first channel structure 61, the first channel layer 61b is connected to the second channel layer 62b, and the first functional layer 61a is connected to the second functional layer 62 a.

The functional layers include, but are not limited to, a blocking dielectric layer, a charge storage layer and a tunneling dielectric layer; the blocking dielectric layer is in contact with the inner side wall of the channel hole 50 and the substrate 10 positioned in the channel hole 50, namely the blocking dielectric layer is positioned on the outermost layer of the three-layer structure of the functional layer, the tunneling dielectric layer is positioned on the innermost layer, and the charge storage layer is positioned between the blocking dielectric layer and the tunneling dielectric layer.

The tunneling dielectric layer may be made of an insulating material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. The charge storage layer is used for storing charges, and the charge storage layer is made of a material including, but not limited to, silicon nitride, silicon oxynitride, or a combination of silicon oxide and silicon nitride, or a combination of the above materials. The blocking dielectric layer may be an insulating material layer, for example, the material of the blocking dielectric layer may be silicon oxide or silicon nitride. The channel layer may be made of a material including, but not limited to, polysilicon.

It is understood that the functional layer and the channel layer may be formed by Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), or Atomic Layer Deposition (ALD), among other suitable methods. And after the first channel structure 61 is formed in the first channel hole 51 and the second channel structure 62 is formed in the second channel hole 52, a channel filling layer 63 may be further disposed in the first channel layer 61b and the second channel layer 62b, and the channel filling layer 63 may effectively support the first channel structure 61 and the second channel structure 62, respectively.

In some embodiments, after forming the channel structure 60 in the channel hole 50, further comprising: the sacrificial layer in each stacked structure 40 is replaced with a gate layer, and a stacked structure 40a is formed. Specifically, etching is performed on the surface of the second stacked structure formed by the plurality of sacrificial layers and the plurality of insulating layers to form a gate gap 43 penetrating the first stacked structure and the second stacked structure, and this structure is shown in fig. 8. Illustratively, a photoresist mask may be formed on the surface of the second stacked structure, and then anisotropic etching may be performed, where the anisotropic etching may be dry etching, and the dry etching includes ion milling etching, plasma etching, reactive ion etching, laser ablation, and the like; for example, by controlling the etching time so that etching stops near the surface of the etch stop layer to form a gate gap extending to the etch stop layer; finally, the photoresist mask is removed by dissolution or ashing in a solvent.

As shown in fig. 9, the gate slits 43 serve as an etchant passage, and the etchant removes the sacrificial layers in the first and second

stacked structures

41 and 42 to form cavities; for example, the first stacked structure 41 and the second stacked structure 42 are immersed in an etching solution using the etching solution as an etchant in wet etching; the end of the sacrificial layer is exposed in the gate gap, and the sacrificial layer can be contacted with the etching solution, so that the sacrificial layer can be removed due to the selectivity of the etching solution.

After the wet etching step, the gate gap is used as a deposition channel, and an atomic layer deposition method is used to fill a conductive material in the gate gap and the cavity to form a gate layer, and then the conductive material filling layer formed in the gate gap is etched to reform the gate gap, that is, the first stacked structure 41 forms a first stacked structure 41a, the second stacked structure 42 forms a second stacked structure 42a, and the stacked structure 40a can be formed on the substrate 10. Further, referring to fig. 9, an isolation structure 44 is formed in the gate gap 43; specifically, silicon oxide is deposited in the gate gap 43 to form an insulating pillar, which may divide the stacked structure 40a into a plurality of relatively independent regions.

In some embodiments, after forming the channel structure 60 in the channel hole 50, or after forming the isolation structure 44 in the stack structure 40a, further comprising: forming a drain electrode 64 at an end portion of the second stack structure 42a away from the first stack structure 41a, wherein the drain electrode 64 is electrically connected to the second channel layer 62b of the second stack structure 42 a; the structure formed in this step is shown in fig. 10. Specifically, the drain electrode 64 is formed in the channel filling layer 63 of the second stacked-layer structure 42a and electrically connected to the second channel layer 62b, the channel filling layer 63 in the second stacked-layer structure 62 may be etched and recessed, and a conductive material may be deposited in the recessed portion to form the drain electrode 64, and the drain electrode 64 is partially connected to the second channel layer 62b, so that the drain electrode 64 is electrically connected to the channel structure 60.

In some embodiments, after forming the drain 64 on the second stack structure 42a, the method further includes: the peripheral circuit 80 may be electrically connected to an end of the second channel structure 62 in the second stack structure 42a away from the substrate 10, and the structure formed in this step is as shown in fig. 11; illustratively, an interconnect structure 70 is formed on a surface of the second stack structure 42a, the interconnect structure 70 is located on a side of the second stack structure 42a away from the substrate 10 and electrically connected to the drain 64, and a peripheral circuit 80 is formed on a side of the interconnect structure 70 away from the second stack structure 42a, and the peripheral circuit 80 is electrically connected to the second channel structure 62 through the interconnect structure 70.

As shown in fig. 12, after the second trench structure 62 is electrically connected to the peripheral circuit 80 through the interconnect structure 70 and before the etching is performed on the back side of the substrate 10 to form the first via 12, the method further includes: the back surface of the substrate 10 is thinned, the first filling layer 511 is exposed, and then the first filling layer 511 is etched and removed to form an etching channel penetrating to the first channel structure 61.

After thinning the substrate 10, step S500 is performed: a first via 12 is formed through the substrate 10, and the first via 12 is opposite to an end of the channel structure 60 facing the substrate 10, and the structure formed in this step is as shown in fig. 13.

Illustratively, etching is performed on the back surface of the substrate 10 opposite to the bottom of the first channel structure 61, and a first via 12 is formed through the substrate 10. The first through hole 12 is disposed opposite to the first filling layer 511, and the first through hole 12 communicates to the surface of the first filling layer 511 facing the substrate 10; the first filling layer 511 may be etched using the first via 12 to remove the first filling layer 511 located in the substrate 10, thereby forming an etching channel communicating to the bottom of the first trench structure 61. For example, the substrate 10 may be etched by dry etching to form a first via 12 penetrating through the substrate 10, and the first filling layer 511 is continuously etched by using the first via 12 as an etching channel to remove the first filling layer 511, thereby exposing the bottom of the first trench junction 61 in the formed etching channel.

After forming the first via hole 12 penetrating to the first channel structure 61 on the substrate 10, step S600 is performed: a semiconductor plug 11 electrically connected to the first channel layer 61b is formed in the first via hole 12, and the structure formed in this step is as shown in fig. 14. Illustratively, forming the semiconductor plug 11 in the first through hole 12, and electrically connecting the semiconductor plug 11 and the first channel layer 61b together, may specifically include the following steps:

after forming an etching channel penetrating to the bottom of the first channel structure 61 on the substrate 10, the first functional layer 61a and the first channel layer 61b at the bottom of the first channel structure 61 may be removed first; the first functional layer 61a on the sidewall of the first channel hole 51 is further partially etched, so that the first channel layer 61b on the inner sidewall of the first channel hole 51 protrudes from the first functional layer 61a, and the structure formed in this step can be referred to fig. 13.

Finally, a conductive material is deposited in the first via hole 12 to form the semiconductor plug 11 electrically connected to a portion of the first channel layer 61b located on the inner sidewall of the first channel hole 51. For example, the material for manufacturing the semiconductor plug 11 may be doped polysilicon or polysilicon, and one end of the semiconductor plug 11 is electrically connected to the first channel layer 61b, and the other end of the semiconductor plug 11 is electrically connected to the substrate 10, so as to electrically connect the substrate 10 and the first channel layer 61b together.

In some embodiments, after forming the semiconductor plug 11 between the substrate 10 and the channel structure 60, step S700 is performed: forming a gate layer closest to the substrate 10 in the first protective layer 20, that is, forming a first gate layer 25 in the first protective layer 20; illustratively, forming the first gate layer 25 within the first protection layer 20 may include the steps of:

a second via 13 is formed in the substrate 10, and the second via 13 is offset from the first via 12, and the structure formed in this step is as shown in fig. 15. Illustratively, the substrate 10 includes a first doping well 14 and a second doping well 15, and accordingly, the first doping well 14 is a P-type doping region, the second doping well 15 is an N-type doping region, and the N-type doping region is located in the P-type doping region; the N-type doped region may be opened to form a second via 13, and the second via 13 may penetrate through the substrate 10 and extend to the surface of the first protection layer 20.

After forming the second via hole 13 on the substrate 10, the replacement layer of the first protective layer is removed by using the second via hole 13 pair to form the first cavity 24, and the structure formed by this step is shown in fig. 17. Illustratively, the first protective layer 20 is first vertically etched by using the second via 13, and the etching stops on the surface of the second dielectric layer 23 to form an etching channel, and the structure formed by this step is shown in fig. 16; then, a portion of the first passivation layer 20 is laterally etched by using the formed etching channel to remove a portion of the structural layer in the first passivation layer 20, and a first cavity 24 is formed in the first passivation layer 20, where the structure formed in this step is as shown in fig. 17.

For example, the replacement layer 22 in the first protection layer 20 may be removed by etching to form a first cavity 24, and the first cavity 24 is formed between the first dielectric layer 21 and the second dielectric layer 23. Since the surface of the first filling layer 511 away from the substrate 10 is lower than the surface of the etch stop layer 30 away from the substrate 10 in the embodiment of the present application; that is, the bottom of the first channel structure 60 formed in the channel hole 50 is located on the side of the first protection layer 20 away from the substrate 10, so that the first channel structure 61 located on the inner sidewall of the first channel hole 51 can be prevented from being damaged when the first protection layer 20 is etched.

After forming the first cavity 24 in the first protection layer 20, a gate layer insulated from the substrate 10 may be formed in the first cavity 24, i.e., a first gate layer 25 closest to the substrate 10 is formed in the first cavity 24, and the first gate layer 25 forms a bottom select gate; exemplarily, the following steps may be included;

as shown in fig. 18, after the first protection layer 20 forms the first cavity 24, silicon oxide may be deposited on the exposed back surface of the substrate 10 and in the first cavity 24 to form a first insulating protection layer 241, that is, the first insulating protection layer 241 may be formed on the back surface of the substrate 10, the inner wall of the second through hole 13 and the surface of the first cavity 24, so as to insulate the first gate layer 21 formed in the first cavity 24 from the substrate 10, and at the same time, prevent a conductive material from being deposited on the inner wall of the second through hole 13.

After forming the first insulating protection layer 241 in the first cavity 24, tungsten deposition is performed on the first cavity 24, or titanium nitride or tungsten deposition is performed in sequence to form the first gate layer 25, and the structure formed in this step is as shown in fig. 19.

After the first gate layer 25 is formed in a portion of the first cavity 24, at this time, the first insulating protection layer 241 is further attached to the back surface of the substrate 10 and the inner wall of the second via 13, and the first insulating protection layer 241 on the back surface of the substrate 10 and the inner wall of the second via 13 needs to be removed, at this time, the first insulating protection layer 241 remaining in the first cavity 24 may be used as a portion of the first dielectric layer 21 and the second dielectric layer 23, and the dielectric layer may be made of the same material as the first insulating protection layer 241. The structure formed in this step is shown in fig. 20.

After removing the first insulating protection layer 241 on the back surface of the substrate and the inner wall of the second via hole 13, the remaining first cavity 24 may be filled with silicon oxide to form a first isolation layer 242, and the structure formed in this step is as shown in fig. 21; illustratively, a side of the first isolation layer 242 away from the second dielectric layer 23 may be flush with the front surface of the substrate 10, that is, the first isolation layer 242 may be formed by filling an insulating material at the second via 13 in the first cavity 24, and the first isolation layer 242 communicates with the second via 13 to isolate the first gate layer 25 formed in the second cavity 24 from the conductive plug 131 subsequently formed in the second via 13.

As shown in fig. 22, after the first cavity 24 is filled with silicon oxide to form the first isolation layer 242, a conductive material may be sequentially deposited in the second via 13 to form the ohmic contact layer 132 and the conductive plug 131, i.e., the conductive plug 131 and the ohmic contact layer 132 between the conductive plug 131 and the substrate 10 may be formed in the second via 13 of the substrate 10.

For example, titanium nitride may be deposited on the inner wall of the second via hole 13 to form the ohmic contact layer 132, and tungsten may be deposited in a space formed by the ohmic contact layer 132 and the first isolation layer 242 to form the conductive block. In the present embodiment, the conductive plug 131 and the ohmic contact layer 132 between the conductive plug 131 and the substrate 10 are formed in the second via 13, so that the resistance between the conductive plug 131 and the N-type doped region of the substrate 10 can be reduced.

After forming the conductive plug 131 on the substrate 10, a conductive component 16 may be formed on the back surface of the substrate 10, and the conductive component 16 may be a conductive pad, and the conductive pad is attached to the back surface of the substrate 10, and the conductive pad is electrically connected to the semiconductor plug 11 and the conductive plug 131 formed on the substrate 10 respectively, and the structure formed in this step is as shown in fig. 1.

In the method for manufacturing the three-dimensional memory according to the embodiment of the invention, the first through hole 12 opposite to the first channel structure 61 is formed on the back surface of the substrate 10, and the semiconductor plunger 11 in contact with the first channel structure 61 is formed in the first through hole 12, so that the first channel layer 61b is in contact with the substrate 10 through the semiconductor plunger 11 and forms an electrical connection. In the embodiment, the semiconductor plunger 11 electrically connected with the channel structure 60 is formed on the back surface of the substrate 10, and the bottom of the channel structure is not required to be etched by adopting front etching, so that the channel layer is exposed and is electrically connected with the substrate; the functional layer at the joint of the second channel hole and the first channel hole can be prevented from being damaged, and the yield and the reliability of the storage function of the three-dimensional memory are improved.

Example two

FIG. 23 is a schematic diagram of a three-dimensional memory in a second embodiment of the present invention; it should be noted that: the structure of the three-dimensional memory provided in the second embodiment is the same as that of the three-dimensional memory provided in the first embodiment, and details are not repeated. The structure of the three-dimensional memory provided in the second embodiment is different from the structure of the three-dimensional memory provided in the first embodiment in that in the second embodiment, a gate layer closest to the substrate 10 (i.e., the first gate layer 25 located between the substrate 10 and the etch stop layer 30 in the first embodiment) is disposed between the etch stop layer 30 and the substrate 10, and the first channel structure 61 passes through the gate layer closest to the substrate 10 and extends into the substrate 10, and the semiconductor layer 26 is disposed on two sides of the gate layer closest to the substrate 10.

As shown in fig. 23 in conjunction with fig. 30, a region of the substrate 10 opposite to the first channel structure 61 is provided with a semiconductor plug 11. Exemplarily, the substrate 10 may be provided with a plurality of first vias 12 in the middle region, each first via 12 corresponds to one first channel structure 61, and an end of the first channel structure 61 opposite to the substrate 10 may extend into the first via 12, that is, the first channel structure 61 passing through the first gate layer 25 also passes through a part of the thickness of the substrate 10, that is, the bottom of the first channel structure 61 is located in the substrate 10.

The semiconductor plunger 11 is disposed in the first through hole 12, the semiconductor plunger 11 is in contact with the substrate 10, that is, the semiconductor plunger 11 is electrically connected to the substrate 10, and an end of the semiconductor plunger 11 facing the first channel structure 61 is electrically connected to the first channel layer 61b, so that the first channel layer 61b is electrically connected to the substrate 10 and forms a loop.

Similarly, in order to improve the connection stability between the semiconductor plug 11 and the first channel layer 61b, in the second embodiment, reference may be made to the first embodiment in which the first channel layer 61b is protruded from the first functional layer 61a in a direction perpendicular to the substrate 10. For example, the first channel structure 61 at the bottom of the first channel hole 51 may be removed by using the first through hole 12 as an etching channel, and the first functional layer 61a located on the inner sidewall of the first channel hole 51 is etched, so that the first channel layer 61b on the inner sidewall of the first functional layer 61a protrudes from the first functional layer 61a, and a portion of the first channel layer 61b protruding from the first functional layer 61a is electrically connected to the semiconductor plunger 11.

In addition, the semiconductor plug 11 may be made of, but not limited to, polysilicon or doped polysilicon, and for the portion of the first channel layer 61b protruding the first functional layer 61a, the length of the portion protruding the first functional layer 61a may be greater than 50nm, so as to ensure the stability of the electrical connection between the first channel layer 61b and the semiconductor plug 11.

In this embodiment, the three gate layers below the etch stop layer 30 and closest to the etch stop layer 30 are used as bottom selection switches, and a conduction path for passing a read/write current is formed in the first protection layer 20, which may be the first gate layer 25 formed in the first protection layer.

For example, referring to fig. 34, a gate layer closest to the substrate 10 and a semiconductor layer 26 are disposed in the first protection layer 20, and the semiconductor layer 26 wraps the gate layer closest to the substrate 10. The semiconductor layer 26 includes a first surface layer 243 and a second surface layer 244, and the first surface layer 243 is located on a side of the first gate layer 25 facing the substrate 10, and the second surface layer 243 is located on a side of the first gate layer 25 facing away from the substrate 10. That is, the first gate layer 25 is located between the first surface layer 243 and the second surface layer 244, the first dielectric layer 21 is disposed between the first surface layer 243 and the substrate 10, and the second dielectric layer 23 is disposed between the second surface layer 244 and the etch stop layer 30, so that the semiconductor layer 26 is electrically insulated from the substrate 10 and the etch stop layer 30, respectively.

The semiconductor layer 26 wraps the first gate layer 25, and the first gate layer 25 is electrically connected to the semiconductor layer 26. In order to make the first channel structure 61 penetrate through the first protection layer 20 and extend toward the substrate 10, the first protection layer 20, the first gate layer 25 inside the first protection layer, and the semiconductor layer 26 are provided with openings matching with the first channel structure 61, so that an end of the first channel structure 61 facing the substrate 10 can extend into the substrate 10.

A notch is formed in a position of the first gate layer 25 opposite to the first channel structure 61, the first channel layer 61b is exposed in the notch, the semiconductor layer 26 is provided with a first extension portion matched with the notch, the first extension portion can be embedded in the notch, and the first extension portion is electrically connected with the first channel layer 61 b; that is, the first skin 243 and the second skin 244 may extend into the gap near the gap, and the first skin 243 and the second skin 244 in the gap are connected together to form a first extension; the first gate layer 25 may be electrically connected to the first channel layer 61b through the first extension portion.

It is understood that the first protection layer 20 can be made of, but not limited to, silicon oxide, and a part of the structure layer of the first protection layer 20 can be etched to form a cavity for accommodating the first gate layer 25 and the semiconductor layer 26 in the first protection layer 20, and the semiconductor layer 26 and the first gate layer 25 can be disposed in the cavity; the material for forming the first gate layer 25 includes, but is not limited to, tungsten, and the material for forming the semiconductor layer 26 includes, but is not limited to, polysilicon.

Fig. 24 is a manufacturing method of forming a three-dimensional memory according to a second embodiment, and fig. 25 to 37 are schematic structural diagrams of stages of forming the three-dimensional memory according to the second embodiment.

As shown in fig. 24, an embodiment of the present invention further provides a manufacturing method for forming a three-dimensional memory according to a second embodiment, including the following steps:

step S100': a substrate 10 is provided, for example, the substrate 10 may be fabricated from single crystal silicon for protecting and supporting subsequently formed stacked structures.

Step S200': the first protection layer 20 and the etching stop layer 30 are sequentially formed on the substrate 10, and the implementation process of this step is the same as that of step S200 in the first embodiment, and will not be described again here.

After the first passivation layer 20 and the etching stop layer 30 are formed on the substrate 10, step 300' is performed: at least two stacked structures, a first stacked structure 41 and a second stacked structure 42, respectively, are formed on the substrate 10, and a channel hole 50 penetrating the stacked structure 40 is formed. The implementation process of step S300' is the same as the implementation process of step S300 in the first embodiment, and is not repeated.

The implementation process of step S300' is different from that of step S300 in the first embodiment, as shown in fig. 25: in the present embodiment, before the first stacked structure 41 forms the second stacked structure 42, the bottom of the first channel hole 51 is not provided with the first filling layer; in the present embodiment, the first support layer 512 is formed only in the first channel hole 51, that is, the bottom of the first support layer 512 is located in the substrate 10, so that the bottom of the first channel structure 61 is formed in the substrate 10.

After the second stacked structure 42 is formed on the first stacked structure 41, the second channel hole 52 penetrating the second stacked structure 42 is formed in the second stacked structure 42 according to the present embodiment. Illustratively, the second stacked structure 42 is etched in a direction perpendicular or approximately perpendicular to the substrate 10; for example, dry etching is used to form a second trench hole 52 penetrating the second stacked structure 42; the lower end of the second channel hole 52 communicates with the upper end of the first channel hole 51. After the second stacked structure 42 forms the second channel hole 52 penetrating through it, the first support layer 512 located in the first channel hole 51 is etched and removed, so that the first channel hole 51 can be formed again in the stacked structure 40, thereby realizing the channel hole 50 penetrating through the entire stacked structure 40.

After forming the channel hole 50 penetrating the stacked structure 40, the etch stopper 30, and the first protective layer 20 on the substrate 10, step S400' is performed: forming a channel structure 60 in channel hole 50, the resulting structure of this step being shown in fig. 26; it should be noted that the present embodiment is different from the step S400 in the first embodiment:

in the second embodiment, in the channel structure 60 in the channel hole 50, one end of the channel structure 60 close to the substrate may pass through the first protection layer 20 and extend to the inside of the substrate 10, that is, the bottom of the first channel structure 61 is attached to the substrate 10; compared with the first channel structure in the first embodiment, the first filling layer 511 is not disposed between the bottom of the first channel structure 61 and the substrate 10 in the second embodiment, so that the bottom of the first channel structure 61 is rapidly etched in the following step.

Referring to fig. 26, after forming the channel structure 60 in the channel hole 50 and before performing step S500', the method further includes: a gate slit 43 is formed through the stacked structure 40, and the gate slit 43 is used as an etching channel and a deposition channel to replace a sacrificial layer in the stacked structure 40 with a gate layer to form a stacked structure 40a, i.e., the first stacked structure 41 forms a first stacked structure 41a, and the second stacked structure 42 forms a second stacked structure 42 a. Further, after forming the stack structure 40a on the substrate 10, the gate gap 43 is filled with an insulating material to form an isolation structure 44, wherein one end of the isolation structure 44 extends to the etch stop layer 30, and the other end extends to the surface of the second stack structure 42a away from the substrate 10, and the structure formed in this step is as shown in fig. 27.

After forming the isolation structure 44 in the stack structure 40a and before performing step S500', the method further includes: forming a drain electrode 64 at an end portion of the second stack structure 42a away from the first stack structure 41a, wherein the drain electrode 64 is electrically connected to the second channel layer 62b of the second stack structure 42 a; the structure formed in this step is shown in fig. 28.

After forming the drain 64 in the second stack structure 40a and before performing the step S500', the method further includes: the peripheral circuit 80 is electrically connected to the end of the second channel structure 62 in the stacked structure 40 away from the substrate 10, and the structure formed in this step is as shown in fig. 29. Illustratively, an interconnect structure 70 is formed on a surface of the second stack structure 42a, the interconnect structure 70 is located on a side of the second stack structure 42a away from the substrate 10, the interconnect structure 70 is electrically connected to the drain 64, a peripheral circuit 80 is formed on a side of the interconnect structure 70 away from the second stack structure 42a, and the peripheral circuit 80 is electrically connected to the second channel structure 62 through the interconnect structure 70.

And, in some embodiments, after electrically connecting the peripheral circuit 80 with the second channel structure 62 and before performing the step S500', further comprising: thinning the back surface of the substrate 10 may expose or remove the first functional layer 61a and the first channel layer 61b at the bottom of the first channel structure 61, which facilitates subsequent etching of the first functional layer 61a on the sidewall of the first channel hole 51 and forms a portion of the first channel layer 61a protruding out of the first functional layer 61 a.

After thinning the substrate 10, step S500' is performed: a first through hole 12 penetrating through the substrate 10 is formed in the substrate 10, and the first through hole 12 is arranged opposite to one end, close to the substrate 10, of the first channel structure 61; the structure formed in this step is shown in fig. 30. Illustratively, etching is performed on the back surface of the substrate 10 opposite to the bottom of the first channel structure 61, and a first via 12 is formed through the substrate 10. For example, after the pre-etching position of the back surface of the substrate 10 is opposite to the bottom of each first channel structure 61, the substrate 10 may be etched by dry etching to form a plurality of first through holes 12 penetrating through the substrate 10.

After forming the first via 12 penetrating to the channel structure 60 on the substrate 10, step S600' is performed: a semiconductor plug 11 electrically connected to the channel layer 62 is formed in the first via hole 12, and the structure formed by this step is shown in fig. 31.

For example, after forming the first via hole 12 penetrating to the bottom of the first channel structure 61 on the substrate 10, the first functional layer 61a and the first channel layer 61b located at the bottom of the first channel structure 61 may be removed first; the first functional layer 61a on the sidewall of the first channel hole 51 is further partially etched such that the first channel layer 61b on the inner sidewall of the first channel hole 51 protrudes out of the first functional layer 61a, and the resulting structure is shown in fig. 30. Further, a conductive material is deposited in the first via hole 12 to form a semiconductor plug 11 electrically connected to a portion of the first channel layer 61b, and the structure formed by this step is as shown in fig. 31.

In some embodiments, after forming the semiconductor plug 11 between the substrate 10 and the channel structure 60, step 700' is performed: a first gate layer 25 and a semiconductor layer 26 wrapping the first gate layer are formed in the first passivation layer 20 to form a conductive channel for passing a read/write current. Illustratively, the following steps may be included:

a second through hole 13 is formed in the substrate 10, and the second through hole 13 is disposed to be offset from the first through hole 12, and the structure formed in this step is as shown in fig. 31. Illustratively, the substrate 10 includes a first doping well 14 and a second doping well 15, and accordingly, the first doping well 14 is a P-type doping region, the second doping well 15 is an N-type doping region, and the N-type doping region is located in the P-type doping region; the N-type doped region may be opened to form the second via hole 13 and the semiconductor plug 11 may be formed in the P-type doped region. The present embodiment may open the N-type doped region to form a second via 13 extending through the substrate 10 and to the surface of the first dielectric layer 21.

After forming the second via hole 13 on the substrate 10 to reach the surface of the first dielectric layer 21, etching a portion of the first protection layer 20 by using the second via hole 13 to form the first cavity 24, and the structure formed in this step is shown in fig. 32.

For example, one end of the second via 13 may extend to the surface of the second dielectric layer 23 and form an etching channel; the replacement layer 22 in the first protective layer 20 may be etched using the second via as an etching path to remove the replacement layer 22 and form a first cavity 24 in the first protective layer 20, i.e. the first cavity 24 is located between the first dielectric layer 21 and the second dielectric layer 23.

After the first protective layer 20 forms the first cavity 24, forming a semiconductor layer 26 insulated from the substrate 10 in the first cavity 24, wherein the first gate layer 25 is located in the semiconductor layer 26, and the semiconductor layer 26 is electrically connected to the channel layer 62; exemplary may include the steps of:

as shown in fig. 33, after the first protective layer 20 forms the first cavity 24, the first cavity 24 may be used as an etching channel, and an inner sidewall of the first channel structure 61 opposite to the first cavity 24 is etched to remove a portion of the first functional layer 61a on the sidewall of the first channel hole 51 to form a gap, and a portion of the first channel layer 61b is exposed in the gap.

As shown in fig. 34, after forming a notch on the first channel structure 61 opposite to the first cavity 24, polysilicon may be deposited on the back surface of the substrate 10 and in the first cavity 24 to form a semiconductor layer 26, and a portion of the semiconductor layer 26 is formed on the back surface of the substrate 10 and on the inner wall of the second via 13; a portion of the semiconductor layer 26 located in the first cavity 24 is formed on the surfaces of the first dielectric layer 21 and the second dielectric layer 23, a portion of the semiconductor layer formed on the first dielectric layer 21 is the first surface layer 243, a portion of the semiconductor layer 26 formed on the second dielectric layer 23 is the second surface layer 244, and both the first surface layer 243 and the second surface layer 244 extend into the notch and form a first extension portion, so that the semiconductor layer 26 is electrically connected to the first channel layer 61 b.

As shown in fig. 35, after forming the semiconductor layer 26 in the first cavity 24, a conductive material is continuously deposited in the first cavity 24 to form a first gate layer 25 attached to and electrically connected to the semiconductor layer 26; for example, tungsten may be deposited in the first cavity 24 and the first gate layer 25 may be formed between the first surface layer 243 and the second surface layer 244.

As shown in fig. 36, after forming the semiconductor layer 26 and the first gate layer 25 in the first cavity 24, partially etching the first gate layer 25 and the end of the semiconductor layer 26 close to the second via 13 to make the end portions thereof have a certain distance from the end of the first dielectric layer 21 close to the second via 13, so as to prevent the end of the first gate layer 25 and the end of the semiconductor layer 26 close to the second via 13 from being electrically connected to the substrate 10; simultaneously, removing the polysilicon layer on the back side of the substrate 10 and the inner wall of the second through hole 13; so as to insulate the first gate layer 25 and the semiconductor layer 25 from the substrate 10.

As shown in fig. 37, in order to insulate the first gate layer 242 and the semiconductor layer 26 from the substrate 10, an insulating material may be filled in the first cavity 24 at the second through hole 13 to form a second isolation layer 245. According to the arrangement of the first gate layer 242 and the semiconductor layer 26 near the second through hole 13, the second isolation layer 245 may be formed by filling the remaining cavity not filled with the conductive material with silicon oxide, and the second isolation layer 245 may fill the second through hole 13, and a side of the second isolation layer 245 away from the second dielectric layer 23 may be flush with the back surface of the substrate 10.

After the first cavity 24 is filled with the second isolation layer 245, the conductive element 16 may be formed on the back surface of the substrate 10, the conductive element 16 may be a conductive pad, and the conductive pad may be attached to the back surface of the substrate 10 and electrically connected to the semiconductor plug 11 located on the substrate 10, and the structure formed in this step is as shown in fig. 23.

EXAMPLE III

Fig. 38 is a schematic structural diagram of a three-dimensional memory according to a third embodiment of the present invention; as shown in fig. 38, the three-dimensional memory provided in this embodiment includes a substrate 10, and a first stack structure 41a and a second stack structure 42a sequentially disposed on the substrate 10, wherein the first stack structure 41a is disposed on the substrate 10, the second stack structure 42a is disposed on the first stack structure 41a, the first stack structure 41a is provided with a first channel structure 61 perpendicular thereto, one end of the first channel structure 61 close to the substrate 10 can extend to the surface of the substrate 10, and one end of the first channel structure 61 away from the substrate 10 is electrically connected to a second channel structure 62.

The structures of the first channel structure 61 and the second channel structure 62 are not repeated here, and it is understood that the first stack structure 41a and the second stack structure 42a further include the isolation structure 44 perpendicular thereto, and a drain 64 is disposed on a side of the second channel structure 62 away from the substrate 10, the drain 64 is disposed on the channel filling layer 63, and a portion of the drain 64 is electrically connected to the second channel layer 62b, and a side of the drain 64 facing the peripheral circuit 80 is electrically connected to the interconnect structure 70.

Further, the three-dimensional memory provided by the present embodiment further includes a peripheral circuit 80 and an interconnect structure 70 located between the peripheral circuit 80 and the second stack structure 62. Specifically, the interconnect structure 70 is disposed on a surface of the second stack structure 42a away from the substrate 10, a side of the interconnect structure 70 facing the second stack structure 42a is electrically connected to the drain 64, and a side of the interconnect structure 70 away from the second stack structure 42a is electrically connected to the peripheral circuit 80.

The interconnection structure 70 includes a plurality of interconnection layers, and two adjacent interconnection layers are electrically connected through a conductive plug; the peripheral circuit includes a substrate and a complementary metal oxide semiconductor (cmos) circuit formed on the substrate, and the peripheral circuit 80 is electrically connected to the second channel structure 42a through the interconnect structure 70 to implement logic control.

Referring to fig. 43, the three-dimensional memory provided in the present embodiment further includes a semiconductor layer 26, the semiconductor layer 26 passes through a gate layer closest to the substrate 10, and the semiconductor layer 26 may be in contact with the substrate 10, and the semiconductor layer 26 also passes through the first functional layer 61a in a direction parallel to the substrate 10 and is in contact with the first channel layer 61 b.

Specifically, the side of the first stacked-layer structure 41a close to the substrate 10 is provided with the etching stop layer 30, the semiconductor layer 26 and the gate layer (the first gate layer 25) located closest to the substrate are provided between the side of the etching stop layer 30 facing the substrate 10 and the substrate 10, and the semiconductor layer 26 wraps the first gate layer 25, and the first gate layer 25 is insulated from the semiconductor layer 26.

The semiconductor layer 26 is provided with an opening matched with the first channel structure 61, one end of the first channel structure 61 facing the substrate 10 can pass through the opening and extend to the surface of the substrate 10, and the bottom of the first channel structure 61 is in contact with the surface of the substrate 10; the semiconductor layer 26 may be in contact with the first channel layer 61b and the substrate 10, respectively, and may connect the first channel layer 61b and the substrate 10 together and form a loop.

In order to further improve the conductivity of the substrate 10, the embodiment is provided with the conductive plug 131 on the substrate 10, and the ohmic contact layer 132 is disposed between the conductive plug 131 and the substrate 10, so as to improve the electrical conduction efficiency between the conductive plug 131 and the substrate 10.

Specifically, with reference to fig. 48 and fig. 55, the substrate 10 includes a first doping well 14 and a second doping well 15, and accordingly, the first doping well 14 is a P-type doping region, the second doping well 15 is an N-type doping region, and the N-type doping region is located in the P-type doping region; the second via 13 is located in the N-type doped region of the substrate 10, a conductive block is disposed in the second via 13 to form the conductive plug 131, and the material for forming the conductive plug 131 includes, but is not limited to, tungsten.

In order to reduce the impedance between the N-type doped region of the substrate 10 and the conductive plug 131, an ohmic contact layer 132 may be disposed on a contact surface between the conductive plug 131 and the N-type doped region of the substrate 10, and a portion of the semiconductor layer 26 may be connected to the N-type doped region of the substrate 10, so that the semiconductor layer 26 is electrically connected to the conductive plug 131.

The semiconductor layer 252 is electrically connected not only to the conductive plug 131 but also to the first channel layer 61b of the first channel structure 61. The first channel structure 60 includes a first functional layer 61a disposed within the first channel hole 51 and a first channel layer 61b disposed within the first functional layer 61 a; a notch is provided in the first functional layer 61a near the opening so that the first channel layer 61b is partially exposed in the notch. The semiconductor layer 26 is provided with a first extending portion near the notch, the first extending portion can be embedded in the notch, and the first extending portion is electrically connected to the outer side surface of the first channel layer 61b, so as to electrically connect the conductive plug 131 and the first channel layer 61b together.

The three-dimensional memory provided in the present embodiment is provided with the second via hole 13 penetrating through the substrate 10 on the back surface of the substrate 10, and the conductive plug 131 is disposed in the second via hole 13, and meanwhile, the semiconductor layer 26 electrically connected to the first channel layer 61b of the first channel structure 61 is disposed on the side of the stack structure 40a close to the substrate 10, and the semiconductor layer 26 electrically connects the conductive plug 131 and the first channel layer 61b together and forms a loop; the phenomenon that the functional layer at the joint of the second channel hole and the first channel hole is damaged when the bottom of the channel structure is subjected to front etching by using the channel hole as an etching channel can be avoided, and the yield and the reliability of the storage function of the three-dimensional memory are improved.

On the basis of the above embodiment, the gate layer closest to the substrate 10 is further disposed in the semiconductor layer 26 to be insulated therefrom to form a bottom select gate, and for convenience of describing the present embodiment, the gate layer closest to the substrate is referred to as a first gate layer 25. Illustratively, the semiconductor layer 26 includes a first surface layer 243 and a second surface layer 244, wherein the first surface layer 243 is located between the first gate layer 25 and the substrate 10, and the second surface layer 244 is opposite to the first surface layer 243. An insulating isolation layer is provided between the semiconductor layer 26 and the first gate layer 25, and the insulating isolation layer includes a first insulating layer 246 and a second insulating layer 247; a first insulating layer 246 is located between the first surface layer 243 and the first gate layer 25, and a second insulating layer 247 is located between the second surface layer 244 and the first gate layer 25. The semiconductor layer 26 is made of a material including, but not limited to, polysilicon, and the first insulating layer 246 and the second insulating layer 247 are made of an insulating material including, but not limited to, silicon oxide.

The first gate layer 25 is disposed between the first insulating layer 246 and the second insulating layer 247, and the first gate layer 25 is insulated from the semiconductor layer 26, and the material of the first gate layer 25 includes, but is not limited to, tungsten. In this embodiment, the first channel structure 61 needs to pass through the semiconductor layer 26, the first insulating layer 246, the second insulating layer 247 and the first gate layer 25 and extend to the surface of the substrate 10, and the first insulating layer 246 and the second insulating layer 247 at the opening wrap the first gate layer 25 to insulate the first gate layer 25 from the semiconductor layer 26.

Further, in the process of forming the semiconductor layer 26 between the stacked structure 40 and the substrate 10 and forming the first gate layer 25 in the semiconductor layer 26, a cavity for accommodating the semiconductor layer 26 is formed between the stacked structure 40 and the substrate 10.

In order to prevent damage to a portion of the stacked structure 40 during formation of the cavity for accommodating the semiconductor layer 26, the stacked structure 40 of the present embodiment includes an etching stop layer 30, the etching stop layer 30 is located on a side of the first gate layer 25 away from the substrate 10, and a second surface layer 244 and a second insulating layer 247 are disposed between the first gate layer 25 and the etching stop layer 30 to insulate the first gate layer 25 from the etching stop layer 30.

The etching barrier layer 30 is made of materials including but not limited to aluminum oxide, a second dielectric layer 23 is arranged between the semiconductor layer 26 and the etching barrier layer 30, and the second dielectric layer 23 can be made of insulating materials including but not limited to silicon oxide; the second dielectric layer 23 is disposed between the semiconductor layer 26 and the etch stop layer 30 in this embodiment, so that the semiconductor layer 26 and the etch stop layer 30 are insulated from each other.

Fig. 39 is a schematic flow chart illustrating a method for manufacturing a three-dimensional memory according to a third embodiment of the present invention; fig. 40 to 55 are schematic diagrams illustrating stages of forming a three-dimensional memory according to a third embodiment.

As shown in fig. 39, an embodiment of the present invention further provides a manufacturing method for forming a three-dimensional memory according to a third embodiment, including the following steps:

After the first protection layer 20 and the etching stop layer 30 are formed on the substrate 10, step S300 ″ is performed: forming at least two stacked structures on the substrate 10, the two stacked structures being a first stacked structure 41 and a second stacked structure 42 formed on the first stacked structure 41, respectively; and forming a trench hole 50 penetrating the entire stacked structure 40, the implementation process of step S300 "is substantially the same as the implementation process of step S300 in the first embodiment, and step S300" of the same portion of the two is not repeated.

The implementation process of step S300 "is different from that of step S300 in the first embodiment, as shown in fig. 40: in the present embodiment, the first channel hole 51 formed in the first stacked structure 41 extends to the surface of the substrate 10, that is, one end of the first channel hole 51 near the substrate 10 penetrates through the first stacked structure 41, the etching stop layer 30 and the first protection layer 20 and extends to the surface of the substrate 10.

In addition, as shown in fig. 41: in this embodiment, before the first stacked structure 41 forms the second stacked structure 42, a sacrificial material may be deposited in the first channel hole 51 to form the first support layer 512, and a second support layer 513 is disposed between the first support layer 512 and the substrate 10, the second support layer 513 may be made of, but not limited to, tungsten, and the first support layer 512 may be made of, but not limited to, polysilicon.

In the embodiment of the present application, a second support layer 513 is disposed at the bottom of the first channel hole 51, and a first support layer 512 is formed on the second support layer 513; the stress generated by the direct contact of the first support layer 512 with the substrate 10 can be prevented from damaging the substrate 10. Accordingly, as shown in fig. 42: after the second stacked structure 42 is formed on the first stacked structure 41 and the second stacked structure 42 is formed with the second channel hole 52 penetrating therethrough, the first support layer 512 and the second support layer 513 may be respectively etched to re-form the first channel hole 51.

After forming the trench holes 50 penetrating the respective stacked structures 40 on the substrate 10, step S400 ″ is performed: a channel structure 60 is formed within channel hole 50 and the resulting structure is shown in fig. 43. The implementation process of step 400 ″ in this embodiment is the same as the implementation process of step S400 in the first embodiment, and is not repeated. It should be noted that: the channel structure 60 formed in the channel hole 50 in this embodiment may extend to the surface of the substrate 10, i.e., the bottom of the channel structure 60 is attached to the surface of the substrate 10.

In some embodiments, after forming the channel structure 60, further comprising: the sacrificial layer in each stacked structure 40 is replaced with a gate layer, and a stacked structure 40a is formed. For example, as shown in fig. 44, a gate slit 43 is formed through the stacked structure 40, and the gate slit 43 is used as an etching channel and a deposition channel to replace a sacrificial layer in the stacked structure 40 with a gate layer to form a stacked structure 40a, i.e., the first stacked structure 41 is formed into a first stacked structure 41a, and the second stacked structure 42 is formed into a second stacked structure 42 a.

Further, after forming the stack structure 40a on the substrate 10, the gate gap 43 is filled with an insulating material to form an isolation structure 44, wherein one end of the isolation structure 44 extends to the etch stop layer 30, and the other end extends to the surface of the second stack structure 42a away from the substrate 10, and the structure formed in this step is as shown in fig. 45.

After forming the isolation structure 44 in the stack structure 40a, the method further includes: a drain 44 is formed at an end of the second stack structure 42a remote from the first stack structure 41a, and the drain 44 is connected to the second channel layer 42b, and the structure formed in this step is as shown in fig. 46. And, after forming the drain 44 on the second stack structure 42a, further comprising: peripheral circuitry 80 may be electrically connected to an end of the second channel structure 62 remote from the substrate 10, the resulting structure being shown in fig. 47. The above steps can refer to the same steps in the first embodiment, and are not described herein again.

After the second channel structure 62 is electrically connected to the peripheral circuit 80 through the interconnect structure 70, step S500 ″ is performed: a second via 13 penetrating through the substrate 10 is formed on the substrate 10, and the second via 13 and one end of the channel structure 60 close to the substrate 10 are arranged in a staggered manner, and the structure formed in this step is as shown in fig. 48. Illustratively, the substrate 10 includes a first doping well 14 and a second doping well 15, and accordingly, the first doping well 14 is a P-type doping region, the second doping well 15 is an N-type doping region, and the N-type doping region is located in the P-type doping region; the N-type doped region may be opened to form the second via hole 13. For example, the N-type doped regions on both sides of the substrate 10 may be respectively etched to form the second via holes 13 penetrating through the substrate 10.

After forming the second via hole 13 penetrating the substrate 10 on the substrate 10, step S600 ″ is performed: a semiconductor layer 26 and a first gate layer 25 located in the semiconductor layer 26 are formed in the first protective layer 30, and the first gate layer 25 is insulated from the semiconductor layer 26.

Illustratively, a first cavity 24 is formed in the first protective layer 20 between the etch stopper 30 and the substrate 10, and then the first functional layer 61a opposite to the first cavity 24 is etched using the formed first cavity 24 as an etch path to form a notch in a region of the first functional layer 61a opposite to the first cavity 24 while the first channel layer 61b is exposed in the notch; subsequently, the semiconductor layer 26 is formed in the first cavity 24, one side of the semiconductor layer 26 is attached to the substrate 10, a portion of the semiconductor layer 26 close to the first channel structure 61 forms a first extension portion, and the first extension portion is in contact with the first channel layer 61 b.

For example, after forming the second through hole 13 penetrating the substrate 10, the first cavity 24 is formed in the first protection layer 20, and the structure formed by this step is as shown in fig. 49. Illustratively, after forming the second via hole 13 on the substrate 10, silicon oxide may be deposited on the back surface of the substrate 10 and the inner wall of the second via hole 13 to form a second insulating protection layer 248; after the second insulating protective layer 248 is formed; a portion of the first protection layer 20 is etched away using the second via hole 13 as an etching path to form a first cavity 24. For example, the embodiment may etch the first dielectric layer 21 and the replacement layer 22 in the first protection layer 20 to remove the first dielectric layer 21 and the replacement layer 22 and form the first cavity 24 in the first protection layer 20.

As shown in fig. 50, after the first cavity 24 is formed in the first protection layer 20, the first cavity 24 is used as an etching channel, and the first channel structure 61 is etched, so that a gap is formed in a region of the first channel structure 61 opposite to the first cavity 24, and a portion of the first channel layer 61b is exposed in the gap. It is understood that the second insulating protection layer 248 on the backside of the substrate 10 and the inner wall of the second via 13 may be removed after a portion of the first channel layer 61b is exposed in the opening and before the semiconductor layer 26 is formed in the second cavity 24.

After removing the second insulating protection layer 248 on the back surface of the substrate 10 and the inner wall of the second through hole 13, depositing polysilicon through the second through hole 13 to form the semiconductor layer 26 in the second cavity 24; the structure formed in this step is shown in fig. 51. Illustratively, a portion of polysilicon is formed on the back side of the substrate 10; a portion of polysilicon is formed on the inner surface of the first cavity 24, i.e., polysilicon is deposited on both the surface of the substrate 10 facing the stacked structure 40 and the side of the second dielectric layer 23 facing the substrate 10 and forms a semiconductor layer 26, and a portion of the semiconductor layer 26 extends into the gap to contact the first channel layer 61 b. The first surface layer 243 of the semiconductor layer 26 is in contact with the substrate 10, and the second surface layer 244 of the semiconductor layer 26 is attached to the second dielectric layer 23.

After the semiconductor layer 26 is formed in the first cavity 24, step S700 ″ is performed to continue forming the first gate layer 25 insulated from the semiconductor layer 26 in the semiconductor layer 26, where the first gate layer 25 is a bottom select gate, and the forming of the first gate layer 25 insulated from the semiconductor layer 26 in this embodiment specifically includes the following steps:

as shown in fig. 52: after forming the semiconductor layer 26 in the first cavity 24, an insulating material may be deposited in the first cavity 24 to form an insulating isolation layer, which includes a first insulating layer 246 and a second insulating layer 247, wherein the first insulating layer 246 is attached to the first surface layer 243, and the second insulating layer 247 is attached to the second surface layer 244; the insulating material forming the insulating isolation layer includes, but is not limited to, silicon oxide; the insulating isolation layer is attached to an inner surface of the semiconductor layer 26, so that the first gate layer 25 formed in the first cavity 24 is insulated from the semiconductor layer 26.

As shown in fig. 53: after forming the insulating isolation layer in the first cavity 24 and the first cavity 24, a conductive material is deposited in the first cavity 24 to form the first gate layer 25, wherein the conductive material forming the first gate layer 25 includes, but is not limited to, tungsten, i.e., the first gate layer 25 is a tungsten layer formed in the insulating isolation layer.

In some embodiments, after forming the insulating isolation layer in the first cavity 24, the following steps are further included: as shown in fig. 54: after the first gate layer 25 is formed in the first cavity 24, an insulating material may be filled in the first cavity 24 at the position of the second via 13 to form a third isolation layer 249, and in addition, according to the arrangement of the first gate layer 25 and the semiconductor layer 26 near the second via 13, the remaining first cavity 24 not filled with the conductive material may also be filled with silicon oxide to form the third isolation layer 249, and a side of the third isolation layer 249 away from the second dielectric layer 23 may be flush with an end of the second via 13 facing the first protection layer 20.

Further, before filling the first cavity 24 with silicon oxide to form the third isolation layer 249, the method further includes: after forming the first gate layer 25 and the semiconductor layer 26 in the first cavity 24, one end of the first gate layer 25 and the semiconductor layer 26 near the second via hole 13 is partially etched to have a certain distance from the conductive plug 131 in the second via hole 13, so that the first gate layer 25 and the semiconductor layer 26 are insulated from the conductive plug 131 in the substrate 10. In addition, polysilicon for forming a semiconductor layer is further laid on the back surface of the substrate 10 and the inner wall of the second via hole 13, and the polysilicon layer on the inner wall of the second via hole 13 and the back surface of the substrate 10 needs to be removed before the conductive plug 131 is formed in the second via hole 13.

After forming the third isolation layer 249 in the first cavity 24, step 700 ″ is performed to form the conductive plugs 131 electrically connected to the semiconductor layer 26 on the substrate 10, and the resulting structure is shown in fig. 55. For example, the ohmic contact layer 132 and the conductive plug 131 may be sequentially formed in the second via hole 13 of the substrate 10. For example, titanium nitride may be deposited on the inner wall of the second via hole 13 to form the ohmic contact layer 132, and tungsten may be deposited on the inner wall surface of the ohmic contact layer 132 to form the conductive plug 131. In this embodiment, the conductive plug 131 and the ohmic contact layer 132 between the conductive plug 131 and the substrate 10 are formed in the second via 13, so that the resistance between the conductive plug 131 and the substrate 10 can be reduced.

After forming the conductive plugs 131 on the substrate 10, a conductive pad is formed on the backside of the substrate 10, and the conductive pad is contacted with the conductive plugs 131, and the structure is formed as shown in fig. 38.

In the method for manufacturing a three-dimensional memory provided by the embodiment of the invention, the semiconductor layer 26 is formed at the position of the gate layer closest to the substrate 10, the semiconductor layer 26 penetrates through the gate layer closest to the substrate 10 and is in contact with the substrate 10, and meanwhile, in the direction parallel to the substrate 10, the semiconductor layer 26 penetrates through the functional layer and is electrically connected with the channel layer; so that the channel layer is in contact with the substrate 10 through the semiconductor plug 11 and forms an electrical connection. The present embodiment employs forming the semiconductor layer 26 electrically connected to the channel layer on the substrate 10, and does not need to etch the bottom of the channel structure by using front etching, so that the channel layer is exposed and electrically connected to the substrate 10; the functional layer at the joint of the second channel hole and the first channel hole can be prevented from being damaged, and the yield and the reliability of the storage function of the three-dimensional memory are improved.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A three-dimensional memory, comprising:

a substrate;

the stack structure is positioned on the substrate and comprises a plurality of layers of gate layers and insulating layers which are alternately arranged;

a channel structure passing through the stack structure and extending to the substrate, the channel structure comprising a channel layer and a functional layer surrounding the channel layer;

a semiconductor layer in contact with the substrate through a gate layer closest to the substrate, the semiconductor layer also in contact with the channel layer through the functional layer in a direction parallel to the substrate;

the substrate is provided with a second through hole penetrating through the substrate, the second through hole and one end, close to the substrate, of the channel structure are arranged in a staggered mode, the second through hole is used as an etching channel to form the semiconductor layer, and a conductive plunger electrically connected with the semiconductor layer is formed in the second through hole.

2. The three-dimensional memory according to claim 1, further comprising: peripheral circuitry located on the stack structure, the peripheral circuitry to implement logic control.

3. The three-dimensional memory according to claim 2, further comprising:

a drain on the channel structure, the drain in contact with the channel layer;

an interconnect structure between the drain and the peripheral circuitry, the interconnect structure being electrically connected to the drain and the peripheral circuitry, respectively.

4. The three-dimensional memory according to claim 1, further comprising: the isolation structure penetrates through the stack structure and extends along a set direction to divide the stack structure into a plurality of blocks.

5. The three-dimensional memory according to claim 4, wherein the isolation structures are insulating pillars.

6. The three-dimensional memory according to claim 4, wherein the stack structure comprises an etch stop layer between the gate layer closest to the substrate and the gate layer adjacent thereto, the channel structure passing through the etch stop layer.

7. The three-dimensional memory according to claim 6, further comprising: a bottom selection gate;

and the gate layer positioned between the etching barrier layer and the substrate is used as the bottom selection gate.

8. The three-dimensional memory according to claim 4, further comprising:

a first doped well within the substrate;

a second doped well located within the first doped well, the first doped well being of an opposite doping type to the second doped well;

the projection of the isolation structure in the direction perpendicular to the substrate is located in the second doped well.

9. The three-dimensional memory according to claim 8, wherein the second channel extends through the second doped well.

10. The three-dimensional memory according to claim 9, wherein an ohmic contact layer is disposed between the conductive plug and the second doping well;

the ohmic contact layer is located on the side wall of the conductive plunger and is in contact with the second doping well.

11. The three-dimensional memory according to claim 8, wherein the doping type of the first doping well is P-type, and the doping type of the second doping well is N-type.

12. The three-dimensional memory according to claim 1, wherein the stack structure comprises a first stack structure and a second stack structure located on the first stack structure;

the channel structure comprises a first channel structure and a second channel structure which are stacked;

the first channel structure passes through the first stack structure and the second channel structure passes through the second stack structure.

13. The three-dimensional memory according to claim 12, wherein the first channel structure protrudes radially beyond the second channel structure at a junction of the first channel structure and the second channel structure.

14. The three-dimensional memory according to claim 1, further comprising: a conductive member located on a back surface of the substrate and in contact with the substrate.

15. The three-dimensional memory according to any one of claims 1 to 14, wherein the semiconductor layer further comprises a first surface layer and a second surface layer surrounding a gate layer closest to the substrate;

the first surface layer is located on the side, facing the substrate, of the gate layer closest to the substrate, and the second surface layer is located on the side, facing away from the substrate, of the gate layer closest to the substrate.

16. The three-dimensional memory according to claim 15, wherein a first insulating layer is provided between a gate layer closest to the substrate and the first surface layer;

a second insulating layer is arranged between the gate layer closest to the substrate and the second surface layer.

17. The three-dimensional memory according to claim 14, wherein the material of the semiconductor layer comprises polysilicon.

18. The three-dimensional memory according to any one of claims 1 to 14, wherein a material of a gate layer closest to the substrate comprises tungsten.