JPH03156915A - Formation of pattern by multilayer resist method - Google Patents

Abstract

PURPOSE:To execute a patterning operation in a short time by increasing a processing speed and to increase a throughput by a method wherein an intermediate layer formed between a first resist layer and a second resist layer is formed of two layers whose etching rates are different. CONSTITUTION:In this pattern formation method, a first resist layer formed on a substrate to be etched and a second resist layer formed on it are used. When an intermediate layer 3 formed between the first and second resist layers 21, 22 is constituted of two layers 31, 32 whose etching rates are different, the second resist layer (an upper-layer resist layer) 22 can be removed by an ashing operation or the like before the first resist layer (a lower-layer resist layer) 21 is etched. Thereby, when the first resist layer is etched, it is not required to etch and remove the second resist layer simultaneously; an etching speed at an etching operation of the first resist layer can be speed-up.

Description

[Detailed description of the invention] The present invention will be explained in the following order.

Industrial application field Outline of the invention Conventional technology Problems to be solved by the invention Purpose of the invention Means for solving the problems and their effects Embodiments Example-1 (Figures 1 (a) to (e) ) Example-2 (Fig. 2 (a) to (e)) Example-3 (Fig. 3 (a) to (C), Fig. 4) Example-4 (Fig. 5 (a) to (b) )) Effects of the Invention [Field of Industrial Application] The present invention relates to a pattern forming method using a multilayer resist method. The present invention can be used, for example, as an etching technique for performing various types of microfabrication, and can be used, for example, in the field of manufacturing SRAMs and various other semiconductor devices having microstructures.

[Summary of the invention]

Each invention of the present application provides a pattern forming method using a multilayer resist structure having a first resist layer formed on a substrate to be etched and a second resist layer formed on the first resist layer. It is.

The invention of claim 1 of the present application provides the above pattern forming method, in which an intermediate layer is provided between the first and second resist layers, and the intermediate layer is composed of two layers having different etching rates. , prior to etching the first resist layer (lower resist layer), the second resist layer (upper resist layer) can be removed by ashing etc. This eliminates the need for simultaneous etching removal of the resist layer, thereby making it possible to speed up the etching process when etching the first resist layer.

The invention of claim 2 of the present application provides a configuration in which an intermediate layer is provided between the first and second resist layers, the second resist layer is made of a silicon-containing resist, and the intermediate layer is made of a conductive material. This facilitates the removal of the silicon-containing resist that has been converted into silicon dioxide and the SEM observation (observation using an electron microscope), thereby increasing the speed and ease of the entire etching process.

The invention according to claim 3 of the present application provides an intermediate layer between the first and second resist layers, the intermediate layer is made of silicon dioxide, and the intermediate layer and the first resist layer are connected to each other by bias ECR. By using an etching device to apply high frequency biases of different frequencies to perform etching, it is possible to achieve effective etching and increase the processing speed.

The invention according to claim 4 of the present application provides the steps of: forming the second resist layer from a silicon-containing resist; and etching the first resist layer using the second resist layer as a mask.
By carrying out an etching process under low pressure and high ion energy conditions and a subsequent low temperature etching process, etching can be achieved at high speed, stably, and at low cost.

[Conventional technology]

In recent years, with the miniaturization and higher density of semiconductor devices, especially VLSIs, highly accurate dry etching has been used for substrate processing, and it has also become necessary to form patterns on substrates with steps. For these reasons, pattern formation methods using multilayer resists are attracting attention.

Particularly, for example, in the field of excimer lithography technology, the need for multilayer resist processes is increasing with the development of technology in this field.

One of the reasons for this is that in order to achieve a resolution of 0.35 μm at the mass production level using exactimer lithography technology, it is inevitable to increase N and A, which would result in a shallow depth of focus and thick resist. Therefore, a multilayer resist structure has no choice but to be used. In this case, the multilayer resist method can provide an advantage in that a substantial selectivity can be obtained for the layer to be etched formed on the stepped portion of the thick object to be etched.

Another reason is that from the viewpoint of line width control, it is necessary to switch from conventional wet development to dry development, for example, for gate materials, isolation regions (I5Olation), and the first layer (lower layer).
Due to the necessity of insufficient dimensional accuracy in forming resist masks for forming contacts (i-con), etc.
One example is that a multilayer resist method is required.

The multilayer resist method generally involves forming a pattern on a lower first resist layer, and patterning the lower first resist using the upper layer pattern as a mask. According to this, it is possible to perform fine patterning that suppresses the effects of differences in the base level and reflections from the base.

For example, the two-layer resist method shown in FIG. 6 is a two-layer resist method in which a flat lower layer C is formed on a base b (such as a substrate) having a step a as shown in FIG. Form an organic film d with photoresist, then pattern the upper photoresist organic film d as shown in the figure (b), and then planarize using the organic film d as a mask as shown in the figure (c). Layer C is dry etched. (For the two-layer resist method, see "Electronic Materials J, April 1986 issue 4.
pp. 7-48, and rsemi for multilayer resist methods.
Conductor World J (Press Journal) May 1986, pp. 70-77, 1987
(See November 2015, pp. 101-105).

Furthermore, in the three-layer resist method as shown in FIG. 7, a base resist b° consisting of a photoresist that also functions as a flattening film is formed on a base such as a substrate.
(see FIG. 7(b)), on which an intermediate layer C such as SOG is formed by Sing or spin coating by CVD, and then an upper layer resist ld is formed (see FIG. 7(b)). After exposure and development, the image shown in Figure 7 (d
), and then the lower resist layer B' is patterned using the pattern of the intermediate layer C as a mask by RIE using oxygen gas or the like as an etching condition (see FIG. 7(e)).

Other multilayer resist techniques include the so-called PCM method.

The patterning of the lower layer in the multilayer resist method described above is usually performed by dry etching as described above, and in fact, it is performed by RIE method (reactive ion etching method) using an appropriate gas such as 02. ), it is possible to process the resist according to the mask pattern by setting the etching conditions to, for example, low pressure and high Vdc, and using Sing or a Si-containing resist as the lower layer etching mask.

[Problem that the invention seeks to solve]

However, the multilayer resist method has a number of problems that must be resolved.

The fundamentally important issues are from resist 1 to pattern formation.
This means that it is necessary to increase productivity by shortening the time required to form a pattern on a workpiece.

For example, even if one resist coating process is taken, in the case of a single-layer resist, it only needs to be done once, whereas in the case of a multi-layer resist, it is necessary at least twice, and if intermediate layers are included, it is necessary three times or more.

Therefore, the overall process time can be reduced by increasing the speed of etching, etc. when forming patterns on the workpiece, or by shortening the time required for various other processes as necessary. It is necessary to shorten the length and increase throughput.

Furthermore, it is desired that the above requirements can be implemented using a method that can form patterns as stably as possible, and at as low a cost as possible.

The following are specific problems that hinder the speeding up of machining.

First, in the three-layer resist method shown in FIG. 7, in order to pattern the lower resist layer "b", the pattern of the intermediate layer C must be changed to form the structures shown in FIGS. 7(d) to (e). It is sufficient to use a mask to etch the lower layer resist b'', but at this time too, there is an upper layer resist d on top of the intermediate layer C.
Since the pattern remains, the etchant is consumed not only in etching the lower resist b° but also in etching the upper resist d. As a result, the etching rate inevitably decreases and the overall processing time also increases. This problem is particularly problematic when using costly processes such as low-temperature etching to control linewidth and prevent redeposition (redeposition of etched material). It is considered wasteful to etch the entire surface, and it is also a problem in terms of cost.

This is the first specific problem.

A technique has also been proposed in which the upper resist layer is made of a silicon-containing resist without using an intermediate layer, and when etching the lower resist using this as a mask, the silicon-containing resist is made into SjO, which also serves as the intermediate layer.

However, this silicon-containing resist process also has specific problems such as the following.

Compared to the middle layer of the 03-layer resist, the silicon-containing resist turned into SiO□ is thicker, so the subsequent removal process takes more time.

■When patterning a silicon-containing resist on a lower resist, for example, when trying to measure line width using a CD-SEM, since both are insulators, they charge up and are difficult to see, making measurement extremely difficult. It is.

This is the second specific problem.

Furthermore, if you try to perform patterning using the multilayer resist method using an ECR radiation type etching device that has been attracting attention recently, such as a plasma-based etcher as shown in Figure 8 or a diverging magnetic field type etcher as shown in Figure 9, the following will occur. A third specific problem arises.

That is, these ECR discharge type etching apparatuses use ECR discharge, so they can generate high-density plasma at low pressure, and can provide sufficient throughput even when used as a single-wafer type etcher, which is necessary for high-precision processing.

■Ion energy can be controlled separately from discharge parameters.

■Electrodeless discharge produces fewer particles, and
Easy maintenance.

Despite these advantages, conventional devices can only apply a fixed RF frequency when applying an RF bias to control ion energy.

Therefore, when it is desired to perform etching continuously by changing the etching conditions, such as in a multilayer resist method, it cannot necessarily be said to be effectively applied.

Note that the symbols in FIG. 8 are the same as those shown in FIG. 4, which will be described later. Further, in FIG. 9, arrows 91 and 92 indicate microwaves and gas, respectively, 93 is cooling water, 94 is a magnet, 95 is plasma, 96 is a material to be processed, 97 is an RF generator, 98
indicates exhaust.

Furthermore, when attempting to perform patterning using the multilayer resist method, especially patterning using the above-mentioned two-layer resist technology using a silicon-containing resist, using low-temperature etching technology, which has also been attracting attention recently, the following fourth problem arises: A specific problem arises.

In other words, if low-temperature etching is used in an etching method in which the upper layer of silicon-containing resist is converted to SiO□ and also serves as an intermediate layer, because it is a low-temperature etching, radicals can be frozen, resulting in undercuts in the pattern shape obtained by etching. There is no.

■For this reason, the ion energy can be reduced.

Therefore, there is no redeposition.

(2) Also, on the ion-irradiated surface, a high -I can be maintained due to a reaction caused by ions, a so-called ion-assisted reaction.

You can get this advantage. However, when such low-temperature etching is used, there is a problem as to whether the silicon-containing resist can be successfully converted to 5iO7 when the lower resist layer is R18. As a result, it takes a long time to convert the silicon-containing resist into SiO□, which results in a problem that high speed cannot be achieved and the demand for improved throughput cannot be met.

[Purpose of the invention]

The inventions of this application are intended to solve the above-mentioned specific problems when patterning is performed using a multilayer resist method.

That is, the invention of claim 1 of the present application solves the first specific problem, and when etching the lower first resist layer using the intermediate layer as a mask in the three-layer resist method, the upper layer is etched. It is an object of the present invention to provide a pattern forming method that eliminates the need to perform etching of the first resist layer in the same manner, thereby preventing consumption of excess etchant and improving processing speed.

The invention of claim 2 of the present application solves the second specific problem, and in a multilayer resist method using a silicon-containing resist, it is possible to easily remove the silicon-containing resist that has become SiO It is an object of the present invention to provide a pattern forming method in which observation is easy and, for example, line width measurement can be quickly achieved, thereby improving the overall processing speed.

The invention of claim 3 of the present application is intended to solve the third specific problem mentioned above, and effectively applies this to the case where a multilayer resist method is implemented using an ECR etching apparatus. The aim is to perform high-speed machining with high throughput.

The invention of claim 4 of the present application is intended to solve the fourth specific problem, and even when performing a multilayer resist method using a silicon-containing resist using a low-temperature etching device, silicon The purpose is to make it possible to rapidly reduce the resist content to 5iOz, thereby allowing processing to be carried out in a short time.

[Means, Steps, and Their Effects for Solving the Problems 3 Each of the inventions of the present application provides the following in a pattern forming method using a multilayer resist structure in which two or more resist layers are provided on a substrate to be etched. Adopt a configuration like this.

The invention of claim 1 of the present application provides the pattern forming method, wherein the multilayer resist structure includes a first resist layer formed on the base, an intermediate layer formed on the first resist layer, and a first resist layer formed on the base. and a second resist layer formed on the intermediate layer, and the intermediate layer is characterized by comprising two layers having different etching rates.

As a result of the above configuration, the present invention is capable of patterning the upper intermediate layer using the second resist layer, which is the upper resist layer 6, as a mask, and then removing the remaining second resist layer by an appropriate means such as ashing. Processing can be performed in which the lower intermediate layer is patterned using the upper intermediate layer as a mask, and the first resist layer is patterned using the lower intermediate layer as a mask. The second resist layer can be removed by ashing etc. if the intermediate layer is etched at two different etching speeds.
This is because the structure has layers. Therefore, when patterning the lower first resist layer, the upper first resist layer is patterned.
It is not necessary to etch both resist layers at the same time. Therefore, it is not necessary to use extra etchant for etching the second resist layer, and the etching speed of the first resist layer can be improved.

Particularly, the present invention is suitable when etching the underlying first resist layer using an etching process such as low-temperature etching, which requires cost and requires improved speed.

The invention of claim 2 of the present application provides the above pattern forming method, wherein the multilayer resist structure includes a first resist layer formed on the substrate and an intermediate layer formed on the first resist layer. and a second resist layer formed on the intermediate layer, the second resist layer being made of a silicon-containing resist, and the intermediate layer being made of a conductive material.

Here, the conductive material constituting the intermediate layer means an electron-transparent material, and does not need to have high conductivity. For example, it may be amorphous silicon.

As a result of the above configuration, according to the present invention, after patterning a silicon-containing resist, if the intermediate layer is etched using this as a mask, the underlying intermediate layer is made of a conductive material such as amorphous silicon, so the pattern of the silicon-containing resist is etched. can be clearly observed as an SEM image. After that, the lower first resist layer is etched halfway, the SiO□ silicon-containing resist on the intermediate layer is removed, the first resist layer is further etched, and finally the intermediate layer is removed. It can be configured as follows.

The invention of claim 3 of the present application provides the pattern forming method, wherein the multilayer resist structure includes a first resist layer formed on the base, an intermediate layer formed on the first resist layer, and a first resist layer formed on the base. a second resist layer formed on the intermediate layer, and the intermediate layer is made of silicon dioxide;
The intermediate layer and the first resist layer are subjected to bias ECR.
This is characterized in that etching is performed by applying high frequency biases of different frequencies using an etching device.

When etching a multilayer film structure such as a multilayer resist structure, this invention can perform etching by appropriately selecting the frequency, so in addition to the advantages of the ECR etching apparatus,
Each layer of a multilayer resist can be etched at an appropriate frequency, and effective etching can be achieved. As a result,
High-speed machining is possible.

The invention according to claim 4 of the present application is the pattern forming method, in which the multilayer resist structure includes a first resist layer formed on the substrate and a second resist layer formed on the first resist layer. the second resist layer is made of a silicon-containing resist, and the first resist layer is etched using the second resist layer as a mask in an etching process under low pressure and high ion energy conditions. and a subsequent low-temperature etching step.

As a result of the above structure, the present invention is capable of etching the first resist layer, which is the lower resist layer, using the second resist layer, which is the upper resist layer, as a mask, in the first step under low pressure and high ion energy conditions. Since etching is performed in the same manner as in the conventional method, the silicon-containing resist can be stably converted into SiO□.

Furthermore, by performing low-temperature etching in a subsequent process, low-temperature etching does not need to be used for the entire structure, which provides a great cost advantage.

As a result, high-speed, stable and low-cost buttering can be performed.

〔Example〕

0 Below, one example of each invention of the present application is given below.
This will be explained with reference to the drawings. It should be noted that, as a matter of course, each invention is not limited to the embodiments described below, and can take various forms.

Example 1 This example embodies the invention of claim 1 of the present application, and is particularly applied to excimer lithography technology using a three-layer resist process to improve the throughput of pattern formation. It is something.

This embodiment will be explained with reference to FIG. In this embodiment, the present invention is applied to the formation of fine patterns of highly integrated semiconductor devices such as SRAMs.

In the pattern forming method of this embodiment, as shown in FIG. 1(a), two or more resist layers 2 are formed on a substrate 1 to be etched.
1. 3.22 A pattern forming method using a multilayer resist structure comprising:
It has an 11 2 resist layer 21 formed on the base 1, an intermediate layer 3 formed on the first resist layer, and a second resist layer 22 formed on the intermediate layer 3. However, the intermediate layer 3 consists of two layers 31 and 32 having different etching rates.

FIG. 1(a) shows the state after patterning the second resist layer 22, which is the upper resist layer. Second
The resist layer 22 had a thickness of approximately 5,000 layers.

In this embodiment, the intermediate layer 3 includes a first intermediate layer 31 that is a lower intermediate layer made of amorphous silicon, and a second intermediate layer 32 that is an upper intermediate layer made of silicon glass-based SOG.
(spin-on glass) to have a two-layer structure. The etching rate of SOG is higher than that of amorphous silicon. The second intermediate layer, 300 layers, is approximately 100
The amorphous silicon film serving as the first intermediate layer was formed to have a thickness of approximately 500 layers.

In this embodiment, using this structure, the second resist layer 22
Using the upper layer resist pattern consisting of as a mask, 300 layers of the upper second intermediate layer 32 are removed by etching to obtain a structure as shown in FIG. 1(b).

The etching conditions at this time may be, for example, the following specific conditions.

Reaction gas: CHF3 Flow rate: 30 SCCM atmospheric pressure: 50 mTorr Usage amount: 0.23 W/cmz After that, the upper resist pattern that is the remainder of the second resist layer 22 is removed to form a layer as shown in FIG. 1(C). Create a structure. In this example, it was removed by ashing. Since this is resist ashing, it has the advantage that a commonly used general asher can be used as is.

In this example, oxygen gas ashing was performed under the following conditions, particularly as a step for removing the second resist layer 22.

Gas used: 0□ Flow rate: 100 SCCM atmospheric pressure: 1. OTorr ashing power=600 and other appropriate ashing techniques can be used. Furthermore, appropriate removal means other than ashing may be used.

Next, using the 300 layer 32 which is the second intermediate layer 32 as a mask,
The amorphous silicon layer, which is the first intermediate layer 31, is etched to form a structure as shown in FIG. 1(d).

The etching conditions at this time were as follows.

Reaction gas: SF,/Freon 113 mixed gas flow rate:
SF, / Freon 113 = 6/703CCM Atmospheric pressure:
20 mTorr Usage amount: 0.23 W/cm2 Next, the first resist layer 31, which is the lower resist layer, is dry etched (FIG. 1(e)). At this time, the second resist layer 22, which is the upper resist layer, has been removed and no longer exists, so there is no reduction in the etching rate during etching of the lower resist layer due to the upper resist layer. Therefore, compared to conventional techniques in which the remainder of the upper resist layer (second resist layer) is etched at the same time as the lower resist layer (first resist layer) is etched, etching can be performed in a shorter time. . This method can be said to be particularly effective when etching the lower resist layer 4 becomes a rate-determining step in the entire process, or when expensive etching means (such as low-temperature etching) are employed.

In this example, the first resist layer 21 (lower resist layer) was etched using excimer low temperature etching means using microwaves under the following specific conditions.

Reaction gas = 02 Flow rate: 30 SCCM atmosphere pressure: 10 mTorr Wave used and electric crab microwave 1 kW Applied RF bias power 300 low Processing temperature 100°C This example has the above configuration, and patterning can be done in a short time. Furthermore, a so-called sub-half-micron fine pattern with a line width of 0.30 to 0.35 .mu.m can be achieved by low-temperature etching that has a good shape and prevents redevolution.

In this example, the sensitivity and resolution are particularly good, but as mentioned above, if the mask is thick, resolution cannot be achieved, so the mask must be made thicker, which causes the problem that the 5 6 selection ratio cannot be obtained. The excimer lithography technique is effective in using a multilayer resist process, and it is extremely effective when using a low-temperature etching method that prevents redevolution, in addition to requiring a fine pattern and thus having line width limitations.

In this embodiment, the first. Second resist layer 21°22
The resist material is arbitrary, such as a general-purpose acrylic resist or a polyimide resist. Further, the lower first resist layer 21 may not be made of an organic material.

Furthermore, in this embodiment, amorphous silicon was used as the material for the first intermediate layer 31 because it can be deposited at a low temperature and has a good selectivity with SOG used as the second intermediate layer 32. However, other materials such as polysilicon can also be used, and the material is not limited thereto. rain middle layer 3
As for 1.32, each material is arbitrary as long as the selection ratio can be maintained and a configuration in which the second resist layer 21 can be removed in advance is possible. For example, P-5iOz/a-Si,
A laminated film structure such as P-5iN/a-Si or Ti0N/aSi can be used. Since it is sufficient for these to have a selectivity ratio, either one may be the upper layer or the lower layer. In addition, P-3i (h is silicon dioxide produced by plasma CVD, P-3iN is silicon nitride, T
i0N represents titanium oxynitride, and a-5i represents amorphous silicon.

Furthermore, it goes without saying that this embodiment can be carried out in a continuous process in multiple chambers.

Note that the above configuration requires a deposition and etching process to provide two layers of the intermediate layer 3, but the intermediate layer 3 may generally be thinner than the first resist layer 21 (lower resist layer). Therefore, it is effective in improving overall throughput.

Example-2 Next, Example-2 will be explained. This embodiment embodies the invention of claim 2 of the present application.

In the pattern forming method of this embodiment, as shown in FIG. 2(a), two or more 7 8 resist layers 21. 3.22, the multilayer resist structure includes a first resist layer 21 formed on the substrate 1, and a first resist layer 21 formed on the first resist layer. a second resist layer 22 formed on the intermediate layer 3, wherein the second resist layer 22 is made of a silicon-containing resist, and the intermediate layer 3 is made of a conductive material. It is.

FIG. 2(a) shows the state after the silicon-containing second resist layer 22, which is the upper resist layer, has been patterned.

This embodiment solves at the same time the problems that it takes time to remove the SiO□ silicon-containing resist described above, and that it is difficult to observe line widths even when attempting to measure them by SEM observation. In this embodiment, a first resist layer 21 is a lower resist layer, and an upper second resist layer 2 is made of a silicon-containing resist.
A layer made of a conductive material is sandwiched between the conductive material 2 and the intermediate layer 3, and the intermediate layer 3 made of the conductive material has a function as an etching stopper layer for the 5i02 silicon-containing resist.

In this embodiment, the substrate 1 is a base made of SiO□.

The first resist layer 21, which is the lower resist layer, is as follows:
The same material as the first resist layer 1 in No. 1 can be used, and the film thickness was 1 μm. The intermediate layer 3 was formed from amorphous silicon and had a thickness of about 1000 layers. The upper second resist layer 22 can be formed from any silicon-containing resist, and has a film thickness of 0.5 μm. Examples of the silicon-containing resist that can be used include those containing a silicon-containing resin having a skeleton of phenol or cresol and diazoketones.

For example, a silicon-containing resin with a phenol skeleton,
A resist containing naphthoquinonediazide sulfonic acid ester, which is a diazoketone, as a photosensitizer can be used. An ordinary commercially available silicon-containing resist may be used, and any resist can be used as long as it is ultimately 5to2 and serves as a mask.

9 0 In this example, the amorphous silicon layer as the intermediate layer 3 is formed by applying it to the first resist layer 21 at room temperature using 5it (4 gas) by a method such as PECVD or photoCD. For example, in the case of PE-CVD, Sil14=500SCC
Conditions such as M, 0.1 Torr, and room temperature to 100°C can be used. The amorphous silicon layer may be doped with phosphorus, arsenic, boron, etc., but it is not necessary.

The patterning process of this example will be specifically explained below.

After patterning the second resist layer 21, which is a silicon-containing resist, into the structure shown in FIG. 2(a), the amorphous silicon layer which is the intermediate layer 3 is etched using this as a mask.

At this time, the intermediate layer 3 underlying the second resist layer 21 is a conductive amorphous silicon layer through which electrons can pass.
The resist layer 21 is made of a silicon-containing resist,
The pattern can be clearly captured as an SEM image. Therefore, it is easy to measure the line width through SEM observation using an electron microscope, and after the measurement is completed, the next step can be carried out without requiring much time.

The patterning of the intermediate layer 3 is carried out by ordinary RIE.
This can be done under the following conditions: That is, etching is performed under the following conditions: reaction gas and flow rate: CF4 = 50 SCCM atmospheric pressure: 5Q mTorr 0.2 W/cm".

As a result of the above, the structure shown in FIG. 2(b) is obtained.

Next, O, RIE is performed under the following conditions, for example. That is, reaction gas and flow rate 20□-103 CCM Atmospheric pressure: l
RIE is performed under the following conditions: Q mTorr Working voltage: 0.25 W/cn+2. At this time, the first resist layer 21, which is the lower resist layer, is etched, and
The silicon 1 -containing resist of the upper second resist layer 22 is converted into SiO□.

As shown in FIG. 2(c), the lower first resist layer 1-layer 21
After etching about 80-90% of the 5i
The n2-containing silicon-containing resist layer (second resist layer 22) is selectively removed from the intermediate layer 3 as follows.

That is, for example, RIEL under the following etching conditions.
, 5iOz silicon-containing resist is removed.

Reaction gas and flow rate: CHF 3 =50 SCCM atmospheric pressure: 50 mTorr Working voltage: 0.2 W/cm2 As a result, a structure as shown in FIG. 2(d) is obtained.

Next, the remaining first resist layer 21 is deposited without redepositing (
Etching is performed under the following conditions, such as microwave etching. That is, Reaction gas and flow rate: 0□-10SCCM Atmospheric pressure: 1
Etching is performed under conditions such as 0 mTorr 2 applied RF bias electric crab 100W and μ wave type crab 800W.

Finally, the invention of claim 2, characterized in that the amorphous silicon layer that constitutes the intermediate N3 is formed by the above-mentioned method, has a selectivity ratio with the silicon-containing resist that has been changed to Si0g, such as when the base is SiO□ as in this embodiment. It is very effective when there is no or it is difficult to take.

According to this embodiment, SEM observation becomes easier and in-process monitoring of line width control can be performed accurately (
This has the effect that the silicon-containing resist that has been converted into SiO□ can be easily removed.

In addition, in this example, as in Example-1, it is also possible to perform these processes continuously in a continuous process or in a multi-chamber, and the same can be used in the numerous variations described in Example-1. Needless to say, it can be applied to

Further, the intermediate layer 3 may be made of any material as long as it has conductivity and electron mobility that facilitates S and EM observation.

Example 3 Next, Example 3 will be described. This embodiment embodies the invention of claim 3 of the present application.

In the pattern forming method of this embodiment, as shown in FIG. 3(a), two or more resist layers 2 are formed on the substrate 1 to be etched.
1, 3 and 22, the multilayer resist structure includes a first resist layer 21 formed on a substrate 1, and a first resist layer 21 formed on the first resist layer. an intermediate layer 3 formed on the intermediate layer 3 and a second resist layer 22 formed on the intermediate layer 3; the intermediate layer 3 is made of silicon dioxide; A bias ECR etching device is used to apply high frequency biases of different frequencies to perform etching.

FIG. 3(a) shows a state in which the upper second resist layer 22 has been patterned.

The resist pattern in this example was formed using a frequency-switchable high-frequency bias application type etching apparatus as shown in FIG. In the figure, S is a frequency changeover switch. H is a high frequency generator, and L is a low frequency generator. In addition, 41 is a magnetron, 42 is a microwave, 43 is a plasma generation chamber capable of generating uniform high-density plasma under a wide range of pressure by the synergistic effect of microwaves and a magnetic field, 44 is a solenoid coil, and 45 is a target to be treated. The materials are shown, arrow 46 shows the introduction of etching gas, and 47 shows the exhaust for forming a high vacuum.

In this example, the first resist layers are the lower resist layer and the upper resist layer.
As the second resist layers 21 and 22, those similar to those in Example-1 can be used.

The intermediate layer 3 is also optional, but here it is a SiO□ film.

In this example, when removing 5iO7 of the intermediate layer 3 by etching, SiO□ is etched by ion-assisted etching, that is, etching is performed in which the contribution of etching is large depending on the ion species, so low frequency etching with good ion utilization efficiency is used. Microwave etching is performed by applying an RF bias of (for example, 2MH2).

5 6 For example, the etching conditions were as follows.

μ wave type crab aoow Reaction gas and flow rate: CHF3 = 30 SCCM atmosphere pressure: 2 Pa Applied RF bias electric crab 60 W When etching was performed under these conditions, intermediate layer 3 S:
O2 was etched at a higher etching rate than in conventional equipment that only had a high frequency RF bias application device. The obtained structure is shown in FIG. 3(b).

Next, the lower first resist layer 2I is etched. At this time, in order to avoid re-spatter of the base material and damage from ion bombardment, switch to high frequency for etching.

For example, etching is performed using a high frequency of 13.56 MHz. Other etching conditions can be set as follows, for example.

μ wave type crab 800W Reaction gas and flow rate: 0□-20SCCM Atmospheric pressure: IP
a Applied RF bias power j 300W obtained [', ho4゜Thus, according to the configuration of this embodiment, when etching a multilayer film structure, the frequency of the RF bias can be adjusted as appropriate. By selecting
Efficient etching can be performed and throughput can be increased.

Margin below 7 8 Example-4 Next, Example-4 will be described. This embodiment is a concrete example of the invention of claim 4 of the present application.

In the pattern forming method of this embodiment, as shown in FIG. 5(a), two or more resist layers 2 are formed on a substrate 1 to be etched.
1 and 22, the multilayer resist structure includes a substrate 1 and 22.
It has a first resist layer 21 formed thereon and a second resist layer 22 formed on the first resist layer,
The second resist layer 22 is made of a silicon-containing resist, and the first resist layer 21 is etched using the second resist layer 22 as a mask: an etching step under low pressure and high ion energy conditions; This was done in a process that included a subsequent low-temperature etching process.

FIG. 5(a) shows a state in which the second resist layer 22, which is the upper silicon-containing resist layer, has been patterned.

In this embodiment, in particular, 02 RIE and 0° low temperature etching are performed continuously.

In this example, patterning was performed in the following steps.

In this example, a second resist layer is formed using the resist containing resist as an upper layer, and a commercially available positive resist (for example, OF I-' R800) is used as a lower first resist layer, thereby forming a two-layer resist structure. (each film thickness 5000
human, 1 μm). The upper silicon-containing second resist layer 22 is exposed and patterned (FIG. 5(a)).
Using this as a mask, apply the lower first resist layer 2 under the following conditions.
1 was etched.

Reaction gas and flow rate: 02 = 10 SCCM atmospheric pressure: 5 mTorr Ion acceleration voltage: Vdc = 600 V At this time, under these conditions, the silicon-containing resist constituting the second resist layer 22 is sufficiently converted into SiO□ while the underlying layer is The first resist layer 21 is etched by ion-assisted etching, and thus maintains an anisotropic shape (note that converting the silicon-containing resist 90 to 5i02 is actually equivalent to etching and converting it to SiO□). (This is considered to be a repetition of the

Next, as shown in FIG. 5(b), when about 80 to 90% of the lower first resist layer 21 has been etched, low-temperature etching is performed under the following conditions.

Reaction gas and flow rate: 0□=10 SCCM atmosphere
Atmospheric pressure: 2 mTorrμ wave electric crab
800W Applied RF bias voltage = 100ν When the temperature is 70°, the SiO□-containing part of the upper silicon-containing second resist 22 still remains, and the ion energy is small during low-temperature etching. The SiO□ layer (layer 22 in FIG. 5(b)) serves as a sufficient mask, and the underlying first resist layer 21 is etched. In the case of the substrate 1 having a step, it is sufficient to switch to low-temperature etching in the same way when about 80 to 90% of the thickness of the first resist on the step has been etched.

The lower first resist layer 21 is removed by anisotropic etching without redeposition, taking advantage of low-temperature etching. In this embodiment, the above process may be performed continuously in the same chamber, or may be performed continuously in multiple chambers.

In addition to the above-mentioned specific conditions, various conditions can be effectively adopted in this embodiment.

For example, in the above example, it is possible to perform O□RIB by microwave etching, and in that case, the RF bias may be set to a large value.

As described above, in this embodiment, a multilayer resist structure in which a silicon-containing resist is used as the upper second resist layer 22 is used, and when etching the lower first resist layer 21 using the silicon-containing resist as a mask, Patterning is performed under low pressure, high Vdc, high ion energy conditions such as RIE up to
Since we performed low-temperature etching (at ~20%
A silicon-containing resist can be converted into SiO□ stably. and,
Since low-temperature etching is used only for the final etching of, for example, 10 to 20% of the lower resist layer, it has a large cost advantage.

〔Effect of the invention〕

As described above, according to the inventions of the present application, in patterning using a multilayer resist structure, it is possible to increase the processing speed and perform patterning in a short time, resulting in the effect that throughput can be increased.

■... Substrate to be etched, 21... First resist layer, 22... Second resist layer, 3... Intermediate layer, 3
1: first intermediate layer, 32: second intermediate layer.

Claims (1)

[Claims] 1. In a pattern forming method using a multilayer resist structure in which two or more resist layers are provided on a substrate to be etched, the multilayer resist structure includes a first resist layer formed on the substrate. a resist layer, an intermediate layer formed on the first resist layer, and a second resist layer formed on the intermediate layer, and the intermediate layer is composed of two layers having different etching rates. A pattern forming method using a multilayer resist method characterized by: 2. In a pattern forming method using a multilayer resist structure comprising two or more resist layers provided on a substrate to be etched, the multilayer resist structure includes a first resist layer formed on the substrate; an intermediate layer formed on the resist layer; and a second resist layer formed on the intermediate layer, and the second resist layer is made of a silicon-containing resist;
A pattern forming method using a multilayer resist method, characterized in that the intermediate layer is made of a conductive material. 3. In a pattern forming method using a multilayer resist structure in which two or more resist layers are provided on a substrate to be etched, the multilayer resist structure includes a first resist layer formed on the substrate; an intermediate layer formed on the resist layer; and a second resist layer formed on the intermediate layer; the intermediate layer is made of silicon dioxide; and the intermediate layer and the first resist layer Bias ECR
A method for forming a pattern using a multilayer resist structure, characterized in that etching is performed by applying high frequency biases of different frequencies using an etching device. 4. In a pattern forming method using a multilayer resist structure comprising two or more resist layers provided on a substrate to be etched, the multilayer resist structure includes a first resist layer formed on the substrate; a second resist layer formed on the resist layer, the second resist layer is made of a silicon-containing resist, and the first resist layer is etched using the second resist layer as a mask. 1. A pattern forming method using a multilayer resist method, characterized in that it is carried out in a step comprising an etching step under low pressure and high ion energy conditions, and a subsequent low temperature etching step.