JPH0684841A - Formation method of groove in silicon substrate - Google Patents

Formation method of groove in silicon substrate

Info

Publication number
JPH0684841A
JPH0684841A JP26077992A JP26077992A JPH0684841A JP H0684841 A JPH0684841 A JP H0684841A JP 26077992 A JP26077992 A JP 26077992A JP 26077992 A JP26077992 A JP 26077992A JP H0684841 A JPH0684841 A JP H0684841A
Authority
JP
Japan
Prior art keywords
mask
groove
silicon oxide
oxide film
silicon substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP26077992A
Other languages
Japanese (ja)
Other versions
JP3155085B2 (en
Inventor
Tsukasa Kuroda
司 黒田
Hiroaki Iwaguro
弘明 岩黒
Junichi Ono
純一 大野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shindengen Electric Manufacturing Co Ltd
Original Assignee
Shindengen Electric Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shindengen Electric Manufacturing Co Ltd filed Critical Shindengen Electric Manufacturing Co Ltd
Priority to JP26077992A priority Critical patent/JP3155085B2/en
Publication of JPH0684841A publication Critical patent/JPH0684841A/en
Application granted granted Critical
Publication of JP3155085B2 publication Critical patent/JP3155085B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Abstract

PURPOSE:To achieve that a deep groove in which the selective ratio of a silicon substrate with reference to a mask is high and whose aspect ratio is high is formed without any damaged part by a method wherein a plasma etching operation is performed by making use of a silicon oxide film as a mask and by using a gas composed mainly of heavy hydrogen. CONSTITUTION:In a method wherein a groove 3 is formed on the main surface of a silicon substrate 1 by a plasma etching operation, the etching operation is performed by making use of a silicon oxide film 2 as a mask and by using a gas composed mainly of heavy hydrogen. For example, a parallel plate-type RIE apparatus on which a permanent magnet has been set is used, a plasma etching operation is performed by using a silicon oxide mask 2 having a stripe shape at an opening width of 1mum and at a length of 1mm by using a single gas of D2, at an ion impinging energy of 110eV and at an operating pressure of 10mTorr with reference to a repeated pitch of 1000 lines at 2.6mum. As a result, it is possible to form a groove 3 having a depth of 4mum at a selective ratio of 100 in such a way that an undercut part 5 and a damaged part 4 are hardly recognized.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、半導体装置に用いるシ
リコン基板の主表面に溝を形成する方法に関するもので
ある。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a groove on the main surface of a silicon substrate used for a semiconductor device.

【0002】[0002]

【従来の技術】従来、シリコン単結晶基板を用いた個別
半導体デバイスや半導体集積回路の半導体装置は広く利
用されている。又、シリコン単結晶基板の主表面に溝を
井戸状、ストライブ状、包囲状などに形成し、その溝に
より、高耐圧構造、絶縁分離構造などとする半導体装置
も知られている。
2. Description of the Related Art Conventionally, individual semiconductor devices using a silicon single crystal substrate and semiconductor devices such as semiconductor integrated circuits have been widely used. There is also known a semiconductor device in which a groove is formed in a well shape, a stripe shape, a surrounding shape, or the like on a main surface of a silicon single crystal substrate, and the groove forms a high breakdown voltage structure, an insulation separation structure, or the like.

【0003】近年、半導体装置の製造におけるシリコン
基板への溝形成方法としては、ウェットエッチングに対
し、プラズマ放電による励起手段を用いたドライエッチ
ングが用いられるようになった。即ち、ドライエッチン
グは、アンダ−カットによる加工精度の低下がなく、加
工材料表面に垂直に入射するイオンの働きにより、加工
寸法がマスクに忠実である垂直な加工形状が得られるな
どの利点が上げられている。
In recent years, as a method of forming a groove in a silicon substrate in the manufacture of a semiconductor device, dry etching using an excitation means by plasma discharge has come to be used as opposed to wet etching. In other words, dry etching has the advantage that there is no reduction in processing accuracy due to undercutting, and the effect of ions that are vertically incident on the surface of the processing material makes it possible to obtain a vertical processing shape whose processing dimensions are faithful to the mask. Has been.

【0004】現在、半導体装置の製造に最も広く適用さ
れているドライエッチングの装置は、反応性イオンエッ
チング装置(RIE)である。通常、円板状の電極を (2) 真空容器内に平行に配置し、一方の電極に高周波電力を
印加して電極間にプラズマを発生させ、電極上に設置し
た半導体基板にプラズマ中のイオンを垂直に入射させ
る。又、改良型RIEとしても種々のものがあり、例え
ば、磁場を用いてプラズマ中の電子とガス分子の衝突回
数を増加させ、プラズマ密度を高めたものがある。
Currently, the most widely used dry etching apparatus for manufacturing semiconductor devices is a reactive ion etching apparatus (RIE). Usually, disk-shaped electrodes are arranged in parallel in a vacuum container, high-frequency power is applied to one of the electrodes to generate plasma between the electrodes, and ions in the plasma are generated on the semiconductor substrate installed on the electrodes. Incident vertically. There are various types of improved RIE, for example, there is one that increases the plasma density by increasing the number of collisions of electrons and gas molecules in plasma with a magnetic field.

【0005】又、RIEに用いる反応ガスも種々のもの
が開発されており、それらは、F系、Cl系などのハロ
ゲン元素を主成分とするガスであり、加工材料を揮発性
のハロゲン化合物にして除去するものである。実際のエ
ッチングでは、種々の添加ガスや反応ガスを混合するこ
とにより加工性能を制御している。
Various reaction gases used for RIE have also been developed. These are gases containing a halogen element such as F and Cl as a main component, and the processing material is made into a volatile halogen compound. To be removed. In actual etching, the processing performance is controlled by mixing various additive gases and reaction gases.

【0006】例えば、高耐圧化を主目的としたトレンチ
型ショットキバリアダイオ−ドの製造において、N型エ
ピタキシアル基板の主表面に公知のSF6ガスとC Cl
2F2ガスを使用したRIEにより、シリコン酸化膜をマ
スクとして幅1μm、深さ2μm、長さ3mmのストラ
イプ状溝を繰返しピッチ2.6μmで1000本形成し
たものがある。
For example, in the manufacture of a trench type Schottky barrier diode whose main purpose is to increase the breakdown voltage, a known SF6 gas and CCl are formed on the main surface of an N type epitaxial substrate.
There is a RIE using 2F2 gas in which 1000 stripe-shaped grooves having a width of 1 μm, a depth of 2 μm and a length of 3 mm are formed at a repeating pitch of 2.6 μm using a silicon oxide film as a mask.

【0007】[0007]

【発明が解決しようとする課題】解決しようとする課題
は、特に、選択性の向上、高アスペクト比(エッチング
するパタ−ンの深さとスペ−スの平面寸法との比)加
工、加工部へのダメ−ジの防止である。即ち、微細加工
技術の進歩及び半導体装置の性能向上に伴い、シリコン
基板の主表面への溝形成における高アスペクト比加工が
要求されている。しかし、シリコン酸化膜を含むマスク
と加工材料であるシリコン基板との選択性は例えば、1
0〜20程度であり、マスク材であるシリコン酸化膜に
もエッチングが同時に進行し、マスク効果を失い、高ア
スペクト比による深い溝形成は困難となる。又、従来の
反応ガスでは、大きな質量を持つイオンが基板に入射す
るため形成した溝の底部や内壁にダメ−ジが発生する。 (3)
The problems to be solved are, in particular, improvement of selectivity, high aspect ratio (ratio between the depth of the pattern to be etched and the plane size of the space) processing, and the processing part. Is the prevention of damage. That is, with the progress of fine processing technology and the improvement of the performance of semiconductor devices, high aspect ratio processing is required for forming grooves on the main surface of a silicon substrate. However, the selectivity between the mask including the silicon oxide film and the silicon substrate as the processing material is, for example, 1
It is about 0 to 20, and the silicon oxide film, which is a mask material, is simultaneously etched, the mask effect is lost, and it becomes difficult to form a deep groove with a high aspect ratio. Further, in the case of the conventional reaction gas, since ions having a large mass enter the substrate, a damage is generated at the bottom and inner wall of the groove formed. (3)

【0008】[0008]

【課題を解決するための手段】本発明は、シリコン基板
の主表面にプラズマエッチングにより溝を形成する方法
において、シリコン酸化膜をマスクとし、重水素を主成
分とするガスによりエッチングすることを特徴とする。
これにより、高アスペクト比によって溝形成した改良さ
れた個別半導体装置や半導体集積回路装置を得ることが
できる。
According to the present invention, in a method of forming a groove on a main surface of a silicon substrate by plasma etching, etching is performed with a gas containing deuterium as a main component using a silicon oxide film as a mask. And
As a result, it is possible to obtain an improved individual semiconductor device or semiconductor integrated circuit device in which grooves are formed with a high aspect ratio.

【0009】[0009]

【実施例】図1は、本発明の実施例を説明する断面構造
図である。1はエピタキシアル成長層から成るシリコン
基板、2はシリコン酸化膜のマスク、3は溝、4はダメ
−ジ部、5はアンダ−カット部であり、図1は、プラズ
マエッチングによる溝形成後の構造図を示している。
DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a sectional structural view for explaining an embodiment of the present invention. Reference numeral 1 is a silicon substrate made of an epitaxial growth layer, 2 is a mask of a silicon oxide film, 3 is a groove, 4 is a damage portion, 5 is an undercut portion, and FIG. 1 shows a groove after plasma etching. A structural drawing is shown.

【0010】本発明の特徴は、シリコン酸化膜のマスク
2の開口部から重水素を主成分とするガスによりエッチ
ングすることである。重水素は、質量数2の水素の同位
体で、ジュウテリウム、デュ−テリウムとも呼ばれ、D
2であらわす。
A feature of the present invention is that etching is performed with a gas containing deuterium as a main component from the opening of the mask 2 of the silicon oxide film. Deuterium is an isotope of hydrogen having a mass number of 2, and is also called deuterium or deuterium.
Expressed as 2.

【0011】次に、本発明の実施例について、さらに具
体的に説明する。使用した装置は、永久磁石を設置した
平行平板型RIEであり、シリコン酸化膜マスクの開口
幅1μm、長さ1mmのストライプ状で繰返しピッチ2.
6μm、1000本に対し、D2の単独ガス、イオン入
射エネルギ110eV、動作圧力10mTorrにより
プラズマエッチングをした。結果として、選択比10
0、アンダ−カット部5及びダメ−ジ部4は殆んど認め
られず、深さ4μmの溝を形成した。図1において、ア
ンダ−カット部5及びダメ−ジ部4は、説明のため、拡
大して示しているが、実施例では無視できる範囲であっ
た。なお、ダメ−ジ部4が大なる場合でも、通常、後工
程にソフトエッチングなどの除去処理が必要になるが、
この場合は500℃、 (4) 30分の熱処理で十分ダメ−ジ層は回復する。
Next, the embodiments of the present invention will be described more specifically. The equipment used was a parallel plate type RIE equipped with a permanent magnet, and the silicon oxide film mask had an opening width of 1 μm and a length of 1 mm, and had a repeating pitch of 2.
Plasma etching was performed on 1000 μm of 6 μm with a single gas of D 2, ion incident energy of 110 eV, and operating pressure of 10 mTorr. As a result, the selection ratio is 10
0, the undercut portion 5 and the damage portion 4 were hardly recognized, and a groove having a depth of 4 μm was formed. In FIG. 1, the undercut portion 5 and the damage portion 4 are shown in an enlarged manner for the sake of explanation, but they were in a negligible range in the embodiment. Even when the damage portion 4 is large, a removal process such as soft etching is usually required in a post process,
In this case, heat treatment at 500 ° C. (4) for 30 minutes sufficiently recovers the damage layer.

【0012】図2は、本発明に使用する重水素D2ガス
によるプラズマの有効性を実証するため、H2ガスによ
るプラズマと対比した実験デ−タにもとづく、シリコン
基板のエッチング速度のデ−タ図である。横軸はプラズ
マ照射中にシリコン基板に印加される自己バイアス電圧
であり、イオンの入射エネルギ−に相当している。縦軸
は、シリコンのエッチング速度である。自己印加電圧は
rfパワ−、プラズマガスの圧力に依存する。図2から
明らかなように、同じ自己印加電圧において、水素プラ
ズマでは、シリコンのエッチングはほとんど進行しな
い。一方、重水素プラズマでは、1分間に約70nm
(700オングストロ−ム)のシリコンがエッチング可
能になる。シリコン酸化膜のエッチング速度は、図2
に、載せてはいないが、水素プラズマと重水素プラズマ
の両方に対して、ほとんどゼロであった。したがって、シ
リコンエッチングを行うとき、マスクに用いるシリコン
酸化膜の厚さを極力薄くすることができる。すなわち、
マスクとして必要なシリコン酸化膜の厚さは、イオンの
入射エネルギ−(自己印加電圧)で決定される。入射し
たイオンがシリコン酸化膜を通過して下地基板に到達し
ない程度のシリコン酸化膜の厚さが必要になる。モンテ
カルロ法を用いた計算からすれば、200eVの入射エ
ネルギ−では、300オングストロ−ムのシリコン酸化
膜厚で十分である。したがって、重水素プラズマによる
シリコンのエッチングでは、マスクとして用いるシリコ
ン酸化膜の厚さは、従来の方法を用いた場合(従来では
1〜2μmのシリコン酸化膜がマスクとして使用されて
いる)よりも1オ−ダ近く薄くできる。このマスクの厚
さを薄くできることによって、微細加工制御がやりやす
くなる。
FIG. 2 is a data diagram of the etching rate of a silicon substrate based on experimental data in comparison with plasma using H2 gas in order to demonstrate the effectiveness of plasma using deuterium D2 gas used in the present invention. Is. The horizontal axis is the self-bias voltage applied to the silicon substrate during plasma irradiation, and corresponds to the incident energy of ions. The vertical axis represents the etching rate of silicon. The self-applied voltage depends on the rf power and the pressure of the plasma gas. As is clear from FIG. 2, with the same self-applied voltage, hydrogen plasma hardly etches silicon. On the other hand, with deuterium plasma, about 70 nm per minute
(700 Å) silicon can be etched. The etching rate of the silicon oxide film is shown in FIG.
Although not shown, it was almost zero for both hydrogen plasma and deuterium plasma. Therefore, when performing silicon etching, the thickness of the silicon oxide film used for the mask can be made as thin as possible. That is,
The thickness of the silicon oxide film required as a mask is determined by the incident energy of ions (self-applied voltage). The thickness of the silicon oxide film is required so that the incident ions do not pass through the silicon oxide film and reach the underlying substrate. From the calculation using the Monte Carlo method, at the incident energy of 200 eV, the silicon oxide film thickness of 300 angstrom is sufficient. Therefore, in the etching of silicon by deuterium plasma, the thickness of the silicon oxide film used as the mask is 1 as compared with the case where the conventional method is used (the silicon oxide film of 1 to 2 μm is conventionally used as the mask). It can be thin near the order. By making this mask thin, it becomes easy to perform fine processing control.

【0013】本発明の溝形成方法は、本発明の要旨の範
囲で前記実施例を種々に変形し得る。例えば、図1のシ
リコン酸化膜のマスク2の上にレジスト膜等を被着して
複合層マスクを形成する場合や反応ガス中の主成分であ
る重水素D2に他 (5) の添加ガス又は混合ガスにより加工性能を制御する反応
ガス設計をする場合を含んでいる。
The groove forming method of the present invention can be variously modified within the scope of the gist of the present invention. For example, in the case of forming a composite layer mask by depositing a resist film or the like on the mask 2 of silicon oxide film in FIG. 1, or in addition to deuterium D2 which is the main component in the reaction gas, other (5) additive gas or This includes the case of designing a reaction gas that controls the processing performance with a mixed gas.

【0014】[0014]

【発明の効果】以上、説明のとおり、シリコン酸化膜の
マスクに対し、シリコン基板の選択比が高く、高アスペ
クト比の深い溝をダメ−ジ部なく形成し得るので、半導
体装置の製造において、高精度微細化の溝形成による性
能向上、製造工程の容易化を実現でき、産業上の利用効
果、極めて大なるものである。
As described above, a deep groove having a high selection ratio of a silicon substrate and a high aspect ratio with respect to a mask of a silicon oxide film can be formed without damaging portions. It is possible to realize the performance improvement and the simplification of the manufacturing process by forming the groove with high precision and miniaturization, and the industrial application effect is extremely large.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の実施例の説明断面構造図である。FIG. 1 is an explanatory cross-sectional structural diagram of an embodiment of the present invention.

【図2】シリコン基板のエッチング速度のデ−タ図であ
る。
FIG. 2 is a data diagram of an etching rate of a silicon substrate.

【符号の説明】[Explanation of symbols]

1 シリコン基板 2 シリコン酸化膜 3 溝 4 ダメ−ジ部 5 アンダ−カット部 1 Silicon substrate 2 Silicon oxide film 3 Groove 4 Damage part 5 Undercut part

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 シリコン基板の主表面にプラズマエッチ
ングにより溝を形成する方法において、シリコン酸化膜
をマスクとし、重水素を主成分とするガスによりエッチ
ングすることを特徴とするシリコン基板の溝形成方法。
1. A method for forming a groove on a main surface of a silicon substrate by plasma etching, which comprises etching with a gas containing deuterium as a main component using a silicon oxide film as a mask. .
JP26077992A 1992-09-03 1992-09-03 Silicon substrate groove forming method Expired - Fee Related JP3155085B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP26077992A JP3155085B2 (en) 1992-09-03 1992-09-03 Silicon substrate groove forming method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP26077992A JP3155085B2 (en) 1992-09-03 1992-09-03 Silicon substrate groove forming method

Publications (2)

Publication Number Publication Date
JPH0684841A true JPH0684841A (en) 1994-03-25
JP3155085B2 JP3155085B2 (en) 2001-04-09

Family

ID=17352614

Family Applications (1)

Application Number Title Priority Date Filing Date
JP26077992A Expired - Fee Related JP3155085B2 (en) 1992-09-03 1992-09-03 Silicon substrate groove forming method

Country Status (1)

Country Link
JP (1) JP3155085B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007173085A (en) * 2005-12-22 2007-07-05 Canon Inc Patterning method, and method of manufacturing electrooptical device, color filter, light emitter and thin-film transistor
US7658859B2 (en) 2005-02-08 2010-02-09 Kabushiki Kaisha Toshiba Method of processing organic film using plasma etching and method of manufacturing semiconductor device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7658859B2 (en) 2005-02-08 2010-02-09 Kabushiki Kaisha Toshiba Method of processing organic film using plasma etching and method of manufacturing semiconductor device
JP2007173085A (en) * 2005-12-22 2007-07-05 Canon Inc Patterning method, and method of manufacturing electrooptical device, color filter, light emitter and thin-film transistor
JP4708998B2 (en) * 2005-12-22 2011-06-22 キヤノン株式会社 Patterning method, electro-optical device manufacturing method, color filter manufacturing method, luminous body manufacturing method, and thin film transistor manufacturing method

Also Published As

Publication number Publication date
JP3155085B2 (en) 2001-04-09

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