JP4316322B2 - Interlayer dielectric film dry etching method - Google Patents

Interlayer dielectric film dry etching method Download PDF

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JP4316322B2
JP4316322B2 JP2003288169A JP2003288169A JP4316322B2 JP 4316322 B2 JP4316322 B2 JP 4316322B2 JP 2003288169 A JP2003288169 A JP 2003288169A JP 2003288169 A JP2003288169 A JP 2003288169A JP 4316322 B2 JP4316322 B2 JP 4316322B2
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insulating film
interlayer insulating
etching
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dry etching
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JP2005057141A (en
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泰宏 森川
俊雄 林
紅コウ 鄒
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Ulvac Inc
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Description

本発明は、層間絶縁膜をドライエッチングする方法に関し、特に、比誘電率が低い層間絶縁膜をドライエッチングする方法に関する。   The present invention relates to a method for dry etching an interlayer insulating film, and more particularly to a method for dry etching an interlayer insulating film having a low relative dielectric constant.

一般に、例えば層間絶縁膜を構成するSiO2を異方性エッチングするには、イオンの注入エネルギが必要となる。このため、第1高周波電源を介して主放電用の電力を供給すると共に、第2高周波電源を介して主放電により生成されたイオン種を基板へ入射させる基板バイアス用の電力を供給するようにした装置が利用される(特許文献1)。この場合、層間絶縁膜へのイオン入射エネルギが高いと、エッチングによってトレンチ底面にはマイクロトレンチが発生する。このマイクロトレンチの発生はオーバーエッチングを行うことで解消できるものの、トレンチとビアとの間の中間層を有しないデュアルダマシン構造の場合、トレンチをエッチングするとき層間絶縁膜の途中でエッチングを止める必要がある。このため、マイクロトレンチを伴うエッチングでは、バリメタ成膜や電気特性に大きな影響が生じ得る。他方で、一旦マイクロトレンチが発生すると、深さ方向にエッチングを行っても解消は困難である。   In general, for example, in order to anisotropically etch SiO2 constituting an interlayer insulating film, ion implantation energy is required. For this reason, power for main discharge is supplied via the first high-frequency power source, and power for substrate bias for supplying the ion species generated by the main discharge to the substrate is supplied via the second high-frequency power source. The device is used (Patent Document 1). In this case, when the ion incident energy to the interlayer insulating film is high, a micro trench is generated on the bottom surface of the trench by etching. Although this micro-trench generation can be eliminated by over-etching, in the case of a dual damascene structure that does not have an intermediate layer between the trench and the via, it is necessary to stop etching in the middle of the interlayer insulating film when etching the trench. is there. For this reason, etching involving micro-trenching can have a significant effect on varimeta film formation and electrical characteristics. On the other hand, once the micro-trench is generated, it is difficult to eliminate it even if etching is performed in the depth direction.

このような問題を解決する目的で、エッチングプロセス実行時の作動圧力を高めてプラズマ密度を高めることによって、実行的なイオン入射エネルギを下げる方法や、第2高周波電源を介して供給される基板バイアスに供給される電力を低くしてマイクロトレンチの発生を抑制する方法が考えられる。   In order to solve such problems, a method of reducing the effective ion incident energy by increasing the operating pressure during the execution of the etching process to increase the plasma density, or a substrate bias supplied via the second high frequency power source. A method of suppressing the generation of micro-trench by reducing the power supplied to the substrate is conceivable.

特開2003−109947号公報(例えば,図1参照)。JP2003-109947A (for example, refer to FIG. 1).

しかしながら、上記のように、エッチングプロセス実行時の作動圧力を高めると、プロセス雰囲気が変化することによって、電気特性などのエッチング特性が変化することが考えられる。その上、低誘電率の層間絶縁膜(Low-K)をエッチングする場合、トレンチのサイドウォールへの反応原子や分子の衝突確立が高くなるためにサイドウォールがダメージを受ける場合がある。他方で、バイアス用の電力を小さくしたのでは、エッチング速度が大幅に低下してエッチング処理時間が長くなり、場合によっては完全にトレンチをエッチングできない場合が生じる。   However, as described above, when the operating pressure at the time of executing the etching process is increased, it is considered that the etching characteristics such as electrical characteristics change due to the change in the process atmosphere. In addition, when etching a low dielectric constant interlayer insulating film (Low-K), the side walls may be damaged because the collision of reactive atoms and molecules to the side walls of the trench becomes higher. On the other hand, if the bias power is reduced, the etching rate is greatly reduced and the etching process time is increased, and in some cases, the trench cannot be completely etched.

そこで、本発明は、上記点に鑑み、層間絶縁膜をドライエッチングする場合に、エッチング特性が変化することなく高いエッチングレートが得られ、層間絶縁膜にダメージを与えることがないようにした層間絶縁膜のドライエッチング方法を提供することを課題とするものである。   Therefore, in view of the above points, the present invention provides an interlayer insulating film in which when an interlayer insulating film is dry-etched, a high etching rate is obtained without changing etching characteristics and the interlayer insulating film is not damaged. It is an object of the present invention to provide a dry etching method for a film.

上記課題を解決するために、本発明の層間絶縁膜のドライエッチング方法は、第1高周波電源を介して主放電用の電力を供給し、第2高周波電源を介して主放電により生成されたイオン種を基板へ入射させる基板バイアス用の電力を供給すると共に、エッチングガスを導入して層間絶縁膜をドライエッチングし、配線用のホール、トレンチを微細加工する層間絶縁膜のドライエッチング方法であって、前記第2高周波電源の周波数を3MHzから6MHzの範囲内の所定値に設定して前記ドライエッチングを行うようにしたものにおいて、前記第2高周波電源の周波数を所定周波数に設定して層間絶縁膜を一旦エッチングし、マイクロトレンチの発生を抑制するのに最適な層間絶縁膜へのイオン入射エネルギ分布となるエッチング条件を見出し、このエッチング条件で、前記第2高周波電源の周波数を前記所定値に変更することを特徴とする。 In order to solve the above-described problem, the method for dry etching an interlayer insulating film according to the present invention supplies power for main discharge through a first high frequency power supply and ions generated by main discharge through the second high frequency power supply. A method for dry-etching an interlayer insulating film that supplies substrate bias power for making seeds incident on the substrate, introduces an etching gas to dry-etch the interlayer insulating film, and finely processes wiring holes and trenches. The dry etching is performed by setting the frequency of the second high-frequency power source to a predetermined value within a range of 3 MHz to 6 MHz, and the frequency of the second high-frequency power source is set to a predetermined frequency and the interlayer insulating film Once etching is performed, the optimum etching conditions for the ion incident energy distribution on the interlayer insulating film are found to suppress the generation of micro-trench. In this etching condition, and changing the frequency of the second high frequency power source to the predetermined value.

本発明によれば、前記第2高周波電源の周波数を3MHzから6MHzの範囲内の所定値に設定することで、基板上でのプラズマ生成に寄与する割合を大きくなってエッチャントがより多く生成されることで、エッチング特性を変化させることなく、エッチング速度を高めることができる。尚、前記第2高周波電源の周波数が3MHzより低いか、または6MHzより高いと、従来のものと比較して高いエッチングレート及び高度な形状制御性が得られない。   According to the present invention, by setting the frequency of the second high-frequency power source to a predetermined value within the range of 3 MHz to 6 MHz, the ratio that contributes to plasma generation on the substrate is increased and more etchants are generated. Thus, the etching rate can be increased without changing the etching characteristics. When the frequency of the second high frequency power source is lower than 3 MHz or higher than 6 MHz, a high etching rate and high shape controllability cannot be obtained as compared with the conventional one.

また、前記ドライエッチングを1.5Pa以下の作動圧力下で行うようにすれば、ラジカル反応が抑制されて層間絶縁膜にダメージを与えることが防止できる。   If the dry etching is performed under an operating pressure of 1.5 Pa or less, radical reaction can be suppressed and damage to the interlayer insulating film can be prevented.

尚、前記層間絶縁膜には、比誘電率の低い低誘電率層間絶縁膜を含まれる。   The interlayer insulating film includes a low dielectric constant interlayer insulating film having a low relative dielectric constant.

これにより、本発明の層間絶縁膜のエッチング方法は、、層間絶縁膜をドライエッチングする場合に、エッチング特性が変化することなく高いエッチングレートが得られ、層間絶縁膜にダメージを与えることがないという効果を奏する。   As a result, according to the method for etching an interlayer insulating film of the present invention, when the interlayer insulating film is dry-etched, a high etching rate is obtained without changing the etching characteristics, and the interlayer insulating film is not damaged. There is an effect.

図1を参照して、1は、本発明の低誘電率層間絶縁膜をドライエッチングして配線用のホール、トレンチの微細加工を実行するエッチング装置を示す。このエッチング装置1は、低温、高密度プラズマによるエッチングが可能なものであり、ターボ分子ポンプなどの真空排気手段11aを備えた真空チャンバー11を有する。その上部には、誘電体円筒状壁により形成されたプラズマ発生部12が、その下部には基板電極部13が設けられている。プラズマ発生部12を区画する壁(誘電体側壁)14の外側には、三つの磁場コイル15、16、17が設けられ、この磁場コイル15,16、17によって、プラズマ発生部12内に環状磁気中性線(図示せず)が形成される。中間の磁場コイル16と誘電体側壁14の外側との間にはプラズマ発生用高周波アンテナコイル19が配置され、この高周波アンテナコイル18は、第1高周波電源19に接続され、三つの磁場コイル15、16、17によって形成された磁気中性線に沿って交番電場を加えてこの磁気中性線に放電プラズマを発生するように構成されている。   Referring to FIG. 1, reference numeral 1 denotes an etching apparatus for performing fine etching of wiring holes and trenches by dry etching the low dielectric constant interlayer insulating film of the present invention. This etching apparatus 1 is capable of etching by low-temperature and high-density plasma, and has a vacuum chamber 11 provided with a vacuum exhaust means 11a such as a turbo molecular pump. A plasma generator 12 formed of a dielectric cylindrical wall is provided at the upper part, and a substrate electrode part 13 is provided at the lower part. Three magnetic field coils 15, 16, and 17 are provided outside the wall (dielectric side wall) 14 that partitions the plasma generation unit 12, and the magnetic field coils 15, 16, and 17 provide an annular magnetism in the plasma generation unit 12. A neutral line (not shown) is formed. A high frequency antenna coil 19 for plasma generation is disposed between the intermediate magnetic field coil 16 and the outside of the dielectric sidewall 14, and this high frequency antenna coil 18 is connected to a first high frequency power source 19, and includes three magnetic field coils 15, 15, An alternating electric field is applied along the magnetic neutral line formed by 16 and 17 to generate discharge plasma in the magnetic neutral line.

磁気中性線の作る面と対向させて基板電極部13内には、処理基板Sが載置される基板電極20が絶縁体20aを介して設けられている。この基板電極20は、コンデンサー21を介して第2高周波電源22に接続され、電位的に浮遊電極となって負のバイアス電位となる。また、プラズマ発生部12の天板23は、誘電体側壁14の上部フランジに密封固着され、電位的に浮遊状態とし対向電極を形成する。この天板23の内面には、真空チャンバ11内にエッチングガスを導入するガス導入ノズル24が設けられ、このガス導入ノズル24が、ガス流量制御手段(図示せず)を介してガス源に接続されている。   A substrate electrode 20 on which the processing substrate S is placed is provided via an insulator 20a in the substrate electrode portion 13 so as to face the surface formed by the magnetic neutral line. The substrate electrode 20 is connected to the second high-frequency power source 22 via the capacitor 21 and becomes a floating electrode in terms of potential and has a negative bias potential. The top plate 23 of the plasma generator 12 is hermetically fixed to the upper flange of the dielectric side wall 14 and is in a floating state in potential to form a counter electrode. A gas introduction nozzle 24 for introducing an etching gas into the vacuum chamber 11 is provided on the inner surface of the top plate 23, and this gas introduction nozzle 24 is connected to a gas source via a gas flow rate control means (not shown). Has been.

上記エッチング装置を用いて、処理基板S上に形成され、トレンチの微細加工される低誘電率層間絶縁膜としては、スピンコートによって形成されたHSQやMSQのようなSiOCH系材料、或いはCVDによって形成されるSiOC系材料で比誘電率2.0〜3.0のLowーk材料であり、多孔質材料であってもよい。塗布系であってSiOCH系材料としては、例えば、商品名NCS/触媒化成工業社製、商品名LKD5109r5/JSR社製、商品名HSG−7000/日立化成社製、商品名HOSP/Honeywell Electric Materials社製、商品名Nanoglass/Honeywell Electric Materials社製、商品名OCD T−12/東京応化社製、商品名OCD T−32/東京応化社製、商品名IPS2.4/触媒化成工業社製、商品名IPS2.2/触媒化成工業社製、商品名ALCAP−S5100/旭化成社製、商品名ISM/ULVAC社製がある。   As the low dielectric constant interlayer insulating film formed on the processing substrate S and finely processed in the trench using the etching apparatus, a SiOCH material such as HSQ or MSQ formed by spin coating, or CVD is used. It is a low-k material having a relative dielectric constant of 2.0 to 3.0, and may be a porous material. Examples of the coating system and SiOCH-based material include, for example, trade name NCS / catalyst chemical industry, trade name LKD5109r5 / JSR, trade name HSG-7000 / Hitachi Chemical, trade name HOSP / Honeywell Electric Materials Product name: Nanoglass / Honeywell Electric Materials, trade name: OCD T-12 / Tokyo Ohkasha, trade name: OCD T-32 / Tokyo Ohkasha, trade name: IPS 2.4 / Catalyst Chemical Industries, trade name There are IPS2.2 / catalyst chemical industry, trade name ALCAP-S5100 / Asahi Kasei, trade name ISM / ULVAC.

SiOC系材料としては、例えば、商品名Aurola2.7/日本ASM社製、商品名Aurola2.4/日本ASM社製、商品名Orion2.7/TRIKON社製、商品名Coral/Novellf社製、商品名Black Diamond/AMAT社製がある。また、商品名SiLK/Dow Chemical社製、商品名Porous-SiLK/Dow Chemical社製、商品名FLARE/Honeywell Electric Materials社製、商品名 Porous FLARE/Honeywell Electric Materials社製、商品名 GX‐3P/Honeywell Electric Materials社製などの有機系の低誘電率層間絶縁膜でもでもよい。尚、低誘電率層間絶縁膜上には、レジストを塗布した後、フォトリソグラフ法で所定のパターンが形成される。レジストとしては、公知のものが用いられる。   Examples of the SiOC material include trade name Aurola 2.7 / manufactured by ASM Japan, trade name Aurola 2.4 / made by ASM Japan, trade name Orion 2.7 / TRIKON, trade name Coral / Novellf, trade name Available from Black Diamond / AMAT. Also, trade name SiLK / Dow Chemical, trade name Porous-SiLK / Dow Chemical, trade name FLARE / Honeywell Electric Materials, trade name Porous FLARE / Honeywell Electric Materials, trade name GX-3P / Honeywell An organic low dielectric constant interlayer insulating film such as that manufactured by Electric Materials may also be used. A predetermined pattern is formed on the low dielectric constant interlayer insulating film by photolithography after applying a resist. A known resist is used as the resist.

ドライエッチングプロセスに用いるエッチングガスとしては、フッ化炭素ガスをエッチングガスとし、このフッ化炭素ガスに希ガスを添加した混合ガスを用いる。この場合、フッ化炭素ガスとして、CF、C、C、C、C、CFI、CIなどを用い、希ガスとして、Ar、Kr、Xeなどを用いる。また、エッチングする場合の作動圧力は、ラジカル反応を抑制するため1.5Pa以下に設定する。 As an etching gas used in the dry etching process, a mixed gas obtained by using a fluorocarbon gas as an etching gas and adding a rare gas to the fluorocarbon gas is used. In this case, CF 4 , C 2 F 6 , C 3 F 8 , C 4 F 8 , C 5 F 8 , CF 3 I, C 3 F 7 I, or the like is used as the fluorocarbon gas, and Ar is used as the rare gas. , Kr, Xe, etc. are used. Moreover, the operating pressure in the case of etching is set to 1.5 Pa or less in order to suppress radical reaction.

そして、第1高周波電源19を介して主放電用の電力を供給し、第2高周波電源22を介して主放電により生成されたイオン種を処理基板Sへ入射させる基板バイアス用の電力を供給すると共に、エッチングガスを導入して層間絶縁膜のドライエッチングを行う。第2高周波電源22の周波数は、3MHzから6MHzの範囲内の所定値、好ましくは4MHzに設定する。この場合、第2高周波電源22の周波数を従来のエッチング処理で使用されていた周波数(例えば、2MHz)に設定して層間絶縁膜を一旦エッチングし、その際、マイクロトレンチの発生を抑制するのに最適な層間絶縁膜へのイオン入射エネルギ分布となるように、例えば第2高周波電源22の投入電力などを変化させてSiOまたはLow−K材料の異方性エッチング条件を見出す。次に、処理基板S上でのプラズマ生成に寄与する割合を大きくしてエッチャントが多く生成されるように、上記範囲で第2高周波電源22の周波数を変更し、同じエッチング条件の下で層間絶縁膜をエッチングする。これにより、マイクロトレンチの発生及びエッチング特性の変化が防止されると共に、高いエッチングレートが得られる。 Then, power for main discharge is supplied via the first high-frequency power source 19, and power for substrate bias that causes the ion species generated by the main discharge to enter the processing substrate S is supplied via the second high-frequency power source 22. At the same time, an etching gas is introduced to dry-etch the interlayer insulating film. The frequency of the second high-frequency power source 22 is set to a predetermined value within the range of 3 MHz to 6 MHz, preferably 4 MHz. In this case, the frequency of the second high-frequency power source 22 is set to the frequency used in the conventional etching process (for example, 2 MHz), and the interlayer insulating film is once etched to suppress the generation of the microtrench. For example, the anisotropic etching conditions of the SiO 2 or Low-K material are found by changing the input power of the second high-frequency power supply 22 so as to obtain an optimum ion incident energy distribution on the interlayer insulating film. Next, the frequency of the second high-frequency power source 22 is changed within the above range so that a large proportion of the etchant is generated by increasing the ratio that contributes to plasma generation on the processing substrate S, and interlayer insulation is performed under the same etching conditions. Etch the film. As a result, generation of micro-trench and change in etching characteristics are prevented, and a high etching rate is obtained.

本実施例では、SiOCH系材料として、比誘電率(k)2.5のMSQを用い、スピンコータを使用して処理基板S上に、500nmの膜厚で低誘電率層間絶縁膜を形成した。そして、この低誘電率層間絶縁膜上に、スピンコータによりレジストを塗布し、フォトリソグラフ法で所定のパターンを形成した。この場合、レジストとしては、例えばUV−IIを使用し、レジスト層の厚さを500nmとした。   In this example, MSQ having a relative dielectric constant (k) of 2.5 was used as the SiOCH material, and a low dielectric constant interlayer insulating film having a thickness of 500 nm was formed on the processing substrate S using a spin coater. Then, a resist was applied on the low dielectric constant interlayer insulating film by a spin coater, and a predetermined pattern was formed by photolithography. In this case, for example, UV-II was used as the resist, and the thickness of the resist layer was 500 nm.

次に、図1に示すエッチング装置1を用いて、CFをエッチングガスとし、CFにアルゴンを添加した混合ガスを真空チャンバ11内に導入して低誘電率層間絶縁膜をエッチングした。この場合、CFとアルゴンとの混合ガスのガス流量を400sccmとした。また、プラズマ発生用高周波アンテナコイル18に接続した高周波電源19の出力を1.2KW(周波数13.56MHz)、基板電極21に接続した基板バイアス用の高周波電源22の出力を80W、基板温度0℃、真空チャンバ11の圧力を0.7Paに設定して行った。尚、基板バイアス用の第2高周波電源22の周波数について2MHz、4MHz、13.56MHz及び27MHzにそれぞれ設定してエッチングを行った。 Next, using the etching apparatus 1 shown in FIG. 1, a low dielectric constant interlayer insulating film was etched by introducing a mixed gas in which CF 4 was used as an etching gas and argon was added to CF 4 into the vacuum chamber 11. In this case, the gas flow rate of the mixed gas of CF 4 and argon was set to 400 sccm. Further, the output of the high frequency power source 19 connected to the plasma generating high frequency antenna coil 18 is 1.2 kW (frequency 13.56 MHz), the output of the high frequency power source 22 for substrate bias connected to the substrate electrode 21 is 80 W, and the substrate temperature is 0 ° C. The pressure in the vacuum chamber 11 was set to 0.7 Pa. Etching was performed by setting the frequency of the second high frequency power supply 22 for substrate bias to 2 MHz, 4 MHz, 13.56 MHz, and 27 MHz, respectively.

図2は、上記条件での各トレンチパターンサイズに対するエッチング深さを示し、図3は、そのときの各周波数でエッチングした場合のエッチングレートを示す。図4は、上記条件で低誘電率層間絶縁膜及びレジストマスクをエッチングしたときのSEM写真である。これによれば、2MHz及び4MHzでは、入射イオンエネルギの分布が適切になってそれぞれマイクロトレンチの発生が抑制されていることが判る(図4参照)。また、第2高周波電源22の周波数を4MHzに設定すると、2MHzに設定したときより、エッチングレートが約30%向上している。これは、処理基板S上でのプラズマ生成に寄与する割合が最適になることでエッチャントがより多く生成されるためである。尚、第2高周波電源22の周波数を13.56MHz及び27MHzに設定すれば、2MHzに設定した場合と比較してエッチングレートが低下し、実用的でなく、また、マイクロローディングが発生した。   FIG. 2 shows the etching depth for each trench pattern size under the above conditions, and FIG. 3 shows the etching rate when etching is performed at each frequency at that time. FIG. 4 is an SEM photograph when the low dielectric constant interlayer insulating film and the resist mask are etched under the above conditions. According to this, it can be seen that at 2 MHz and 4 MHz, the distribution of incident ion energy is appropriate and the generation of micro-trench is suppressed (see FIG. 4). Further, when the frequency of the second high-frequency power source 22 is set to 4 MHz, the etching rate is improved by about 30% compared to when the frequency is set to 2 MHz. This is because more etchant is generated by optimizing the ratio that contributes to plasma generation on the processing substrate S. If the frequency of the second high-frequency power source 22 was set to 13.56 MHz and 27 MHz, the etching rate decreased compared to the case where it was set to 2 MHz, which was not practical and microloading occurred.

本発明の低誘電率の層間絶縁膜のエッチング方法を実施するエッチング装置を概略的に示す図。The figure which shows schematically the etching apparatus which enforces the etching method of the low dielectric constant interlayer insulation film of this invention. バイアス用の高周波電源の周波数を変えて層間絶縁膜をエッチングをした場合の各トレンチパターンサイズに対するエッチング深さを示すグラフ。The graph which shows the etching depth with respect to each trench pattern size at the time of etching an interlayer insulation film by changing the frequency of the high frequency power supply for bias. バイアス用の高周波電源の周波数を変えて層間絶縁膜をエッチングをした場合のエッチングレートを示すグラフ。The graph which shows the etching rate at the time of etching an interlayer insulation film by changing the frequency of the high frequency power supply for bias. (a)及び(b)は、バイアス用の高周波電源の周波数を変えて層間絶縁膜をエッチングをした場合のSEM写真。(A) And (b) is the SEM photograph at the time of changing the frequency of the high frequency power supply for bias, and etching the interlayer insulation film.

符号の説明Explanation of symbols

1 エッチング装置
11 真空チャンバ
12 プラズマ発生部
13 基板電極部
S 処理基板
DESCRIPTION OF SYMBOLS 1 Etching apparatus 11 Vacuum chamber 12 Plasma generating part 13 Substrate electrode part S Processing substrate

Claims (3)

第1高周波電源を介して主放電用の電力を供給し、第2高周波電源を介して主放電により生成されたイオン種を基板へ入射させる基板バイアス用の電力を供給すると共に、エッチングガスを導入して層間絶縁膜をドライエッチングし、配線用のホール、トレンチを微細加工する層間絶縁膜のドライエッチング方法であって、前記第2高周波電源の周波数を3MHzから6MHzの範囲内の所定値に設定して前記ドライエッチングを行うようにしたものにおいて、
前記第2高周波電源の周波数を所定周波数に設定して層間絶縁膜を一旦エッチングし、マイクロトレンチの発生を抑制するのに最適な層間絶縁膜へのイオン入射エネルギ分布となるエッチング条件を見出し、このエッチング条件で、前記第2高周波電源の周波数を前記所定値に変更することを特徴とする層間絶縁膜のドライエッチング方法。
The main discharge power is supplied via the first high-frequency power supply, and the substrate bias power for causing the ion species generated by the main discharge to enter the substrate is supplied via the second high-frequency power supply, and the etching gas is introduced. In this method, the interlayer insulating film is dry etched, and the wiring holes and trenches are finely processed. The method of dry etching the interlayer insulating film sets the frequency of the second high frequency power source to a predetermined value within a range of 3 MHz to 6 MHz. Then, in what is to perform the dry etching,
The frequency of the second high frequency power supply is set to a predetermined frequency, the interlayer insulating film is once etched, and an etching condition that provides an ion incident energy distribution to the interlayer insulating film optimal for suppressing the generation of the microtrench is found. A dry etching method for an interlayer insulating film, wherein the frequency of the second high-frequency power source is changed to the predetermined value under etching conditions .
前記ドライエッチングを1.5Pa以下の作動圧力下で行うことを特徴とする請求項1記載の層間絶縁膜のドライエッチング方法。 2. The method of dry etching an interlayer insulating film according to claim 1, wherein the dry etching is performed under an operating pressure of 1.5 Pa or less. 前記層間絶縁膜が、SiOまたは比誘電率の低い層間絶縁膜を含むことを特徴とする請求項1または請求項2記載の層間絶縁膜のドライエッチング方法。 3. The method of dry etching an interlayer insulating film according to claim 1, wherein the interlayer insulating film includes SiO 2 or an interlayer insulating film having a low relative dielectric constant.
JP2003288169A 2003-08-06 2003-08-06 Interlayer dielectric film dry etching method Expired - Fee Related JP4316322B2 (en)

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