CN115117056A - Semiconductor structure and forming method thereof - Google Patents

Semiconductor structure and forming method thereof Download PDF

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Publication number
CN115117056A
CN115117056A CN202110307236.XA CN202110307236A CN115117056A CN 115117056 A CN115117056 A CN 115117056A CN 202110307236 A CN202110307236 A CN 202110307236A CN 115117056 A CN115117056 A CN 115117056A
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China
Prior art keywords
layer
source
forming
drain plug
side wall
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CN202110307236.XA
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Chinese (zh)
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陈卓凡
金吉松
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Priority to CN202110307236.XA priority Critical patent/CN115117056A/en
Publication of CN115117056A publication Critical patent/CN115117056A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/0886—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823468—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects

Abstract

A semiconductor structure and a method of forming the same, the method comprising: providing a substrate, forming a grid structure on the substrate, forming active drain doping layers in the substrate on two sides of the grid structure, and forming an interlayer dielectric layer on the top of the substrate exposed by the grid structure; removing the interlayer dielectric layer between the adjacent gate structures to form a first opening exposing the top of the source-drain doping layer; forming a first sacrificial layer on the side wall of the first opening; forming a source drain plug at the top of the source drain doping layer, wherein the source drain plug covers the side wall of the first sacrificial layer; removing the first sacrificial layer to form a groove surrounded by the side wall of the side wall, the top of the substrate and the side wall of the source drain plug; and forming a sealing layer covering the top of the gate structure and the side wall of the source drain plug, wherein the sealing layer also seals the top of the groove to form an air side wall surrounded by the side wall, the source drain doping layer, the substrate and the sealing layer. The air side wall has a low dielectric constant, so that the capacitance between the grid structure and the source-drain plug can be reduced, and the performance of the semiconductor can be improved.

Description

Semiconductor structure and forming method thereof
Technical Field
Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular, to a semiconductor structure and a method for forming the same.
Background
As the integration degree of integrated circuits is higher and higher, the technical nodes of the semiconductor process are smaller and smaller, so that the distance between adjacent devices is smaller and smaller. On the same chip, the distance between the gate structures of different transistors is smaller and smaller, which results in that the interlayer capacitance between the metal gate structure (MG) and the Contact hole (Contact or M0) is larger and larger, and the dynamic performance of the device is significantly affected by the excessively large interlayer capacitance, so that the energy consumption is increased, the resistance-capacitance (RC) time constant is increased, the operation speed of the chip is affected, and the reliability of the device on the chip is seriously affected.
In the prior art, a sidewall is usually formed on a sidewall surface of a gate structure by using a low-K material, so as to reduce interlayer capacitance between a Metal Gate (MG) and a Contact hole (Contact or M0), thereby improving performance of a transistor.
With the further reduction of the space between the gate structures, the difficulty of forming low-K side walls on the two sides of the gate structures in the prior art is gradually increased, and meanwhile, the side walls formed by the traditional low-K materials cannot further reduce the dielectric constant.
Disclosure of Invention
The embodiment of the invention provides a semiconductor structure and a forming method thereof, which are beneficial to further reducing the capacitance between a grid structure and a source drain plug.
To solve the above problems, an embodiment of the present invention provides a semiconductor structure, including: a substrate; the grid structure is positioned on the substrate; the source-drain doping layer is positioned in the substrates at two sides of the grid structure; the source drain plug is positioned at the top of the source drain doping layer and is electrically connected with the source drain doping layer; the sealing layer is positioned at the top of the grid structure and seals the top of a groove formed by the side wall of the grid structure, the top of the source-drain doping layer and the side wall of the source-drain plug in a surrounding mode; air gaps are enclosed by the grid structure, the source-drain doping layer, the source-drain plug and the sealing layer, and the air gaps serve as air side walls; and the side wall covers the side wall of the grid structure exposed by the air side wall.
Correspondingly, an embodiment of the present invention further provides a method for forming a semiconductor structure, including: providing a substrate, wherein a gate structure is formed on the substrate, side walls of the gate structure are formed with side walls, active drain doping layers are formed in the substrate on two sides of the gate structure, an interlayer dielectric layer is formed on the top of the substrate exposed by the gate structure, and the interlayer dielectric layer also covers the top of the gate structure; removing the interlayer dielectric layer between the adjacent grid electrode structures to form a first opening exposing the top of the source drain doping layer, wherein the first opening is formed by surrounding the side wall of the side wall, the side wall of the interlayer dielectric layer and the substrate; forming a first sacrificial layer on the side wall of the first opening, wherein the first sacrificial layer covers the side wall of the side wall; forming a source drain plug at the top of the source drain doping layer after the first sacrificial layer is formed, wherein the source drain plug covers the side wall of the first sacrificial layer and is electrically connected with the source drain doping layer; removing the first sacrificial layer to form a groove surrounded by the side wall, the top of the substrate and the side wall of the source drain plug; and forming a sealing layer covering the top of the gate structure and the side wall of the source drain plug, wherein the sealing layer also seals the top of the groove to form an air side wall surrounded by the gate structure, the source drain doping layer, the substrate and the sealing layer.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:
the embodiment of the invention provides a semiconductor structure, comprising a substrate; the grid structure is positioned on the substrate; the side wall covers the side wall of the grid structure; the source-drain doped layers are positioned in the substrates at two sides of the grid structure; the source drain plug is positioned at the top of the source drain doping layer and is electrically connected with the source drain doping layer; the sealing layer is positioned at the top of the grid structure and seals the top of a groove formed by the side wall, the top of the source-drain doping layer and the side wall of the source-drain plug in a surrounding mode; and the side wall, the source-drain doping layer, the source-drain plug and the sealing layer enclose an air gap, and the air gap is used as an air side wall. Compared with the existing dielectric layer with a larger dielectric constant between the gate structure and the source drain plug, the embodiment of the invention arranges the air side wall between the side wall of the side wall and the side wall of the source drain plug, and because the dielectric constant (k value) of the air side wall is lower than that of the existing dielectric layer, the capacitance between the gate structure and the source drain plug can be reduced, thereby being beneficial to improving the performance of a semiconductor.
In an alternative aspect, the semiconductor structure further comprises: the protective layer covers the side wall of the source drain plug exposed out of the air side wall; in the forming process of the semiconductor structure, a sacrificial layer is usually formed between the side wall of the side wall and the side wall of the source drain plug to occupy the position of the air side wall, and the sacrificial layer is correspondingly removed; in summary, the embodiment of the invention can reduce the capacitance between the gate structure and the source/drain plug, and ensure the quality of the source/drain plug, thereby being beneficial to improving the performance of the semiconductor.
Correspondingly, the embodiment of the invention also provides a method for forming the semiconductor structure, the interlayer dielectric layer between the adjacent gate structures is removed, and a first opening exposing the top of the source-drain doping layer is formed, wherein the first opening is defined by the side wall of the side wall, the side wall of the interlayer dielectric layer and the substrate; forming a first sacrificial layer on the side wall of the first opening, wherein the first sacrificial layer covers the side wall of the side wall; forming a source drain plug at the top of the source drain doping layer after the first sacrificial layer is formed, wherein the source drain plug covers the side wall of the first sacrificial layer and is electrically connected with the source drain doping layer; removing the first sacrificial layer to form a groove surrounded by the side wall, the top of the substrate and the side wall of the source drain plug; and forming a sealing layer covering the top of the gate structure and the side wall of the source-drain plug, wherein the sealing layer also seals the top of the groove to form the air side wall surrounded by the side wall, the source-drain doping layer, the substrate and the sealing layer. In the embodiment of the invention, the air side wall is arranged between the side wall of the side wall and the side wall of the source drain plug, and the dielectric constant (k value) of the air side wall is lower than that of the current dielectric layer, so that the capacitance between the grid structure and the source drain plug can be reduced, and the performance of a semiconductor can be improved.
In an alternative, the method for forming the semiconductor structure further comprises the following steps: forming a protective layer covering the side wall of the first sacrificial layer in the first opening; in the forming process of the semiconductor structure, a sacrificial layer is usually formed between the side wall of the side wall and the side wall of the source drain plug to occupy the position of the air side wall, and the sacrificial layer is correspondingly removed; in summary, the embodiment of the invention can reduce the capacitance between the gate structure and the source/drain plug, and ensure the quality of the source/drain plug, thereby being beneficial to improving the performance of the semiconductor.
Drawings
FIG. 1 is a schematic diagram of a semiconductor structure according to an embodiment of the present invention;
fig. 2 to fig. 22 are schematic structural diagrams corresponding to steps of a method for forming a semiconductor structure according to an embodiment of the present invention.
Detailed Description
In the current trend, the increase of device density brings many problems. Specifically, the interlayer capacitance rapidly increased between the metal gate structure and the source-drain plug is one of the two, and the performance of the semiconductor structure is affected by the overlarge interlayer capacitance, so that the effect required by the process cannot be achieved.
In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, wherein a gate structure is formed on the substrate, active drain doping layers are formed in the substrate on two sides of the gate structure, an interlayer dielectric layer is formed on the top of the substrate exposed by the gate structure, and the interlayer dielectric layer also covers the top of the gate structure; removing the interlayer dielectric layer between the adjacent grid electrode structures to form a first opening exposing the top of the source drain doping layer, wherein the first opening is formed by surrounding the side wall of the grid electrode structure, the side wall of the interlayer dielectric layer and the substrate; forming a first sacrificial layer on the side wall of the first opening, wherein the first sacrificial layer covers the side wall of the grid structure; forming a source drain plug on the top of the source drain doping layer after the first sacrificial layer is formed, wherein the source drain plug covers the side wall of the first sacrificial layer and is electrically connected with the source drain doping layer; removing the first sacrificial layer to form a groove surrounded by the side wall of the grid structure, the top of the substrate and the side wall of the source drain plug; and forming a sealing layer covering the top of the gate structure and the side wall of the source drain plug, wherein the sealing layer also seals the top of the groove to form an air side wall surrounded by the gate structure, the source drain doping layer, the substrate and the sealing layer.
In the forming method provided by the embodiment of the invention, the interlayer dielectric layer between the adjacent gate structures is removed, and a first opening exposing the top of the source-drain doping layer is formed, wherein the first opening is surrounded by the side wall of the gate structure, the side wall of the interlayer dielectric layer and the substrate; forming a first sacrificial layer on the side wall of the first opening, wherein the first sacrificial layer covers the side wall of the grid structure; forming a source drain plug at the top of the source drain doping layer after the first sacrificial layer is formed, wherein the source drain plug covers the side wall of the first sacrificial layer and is electrically connected with the source drain doping layer; removing the first sacrificial layer to form a groove surrounded by the side wall of the grid structure, the top of the substrate and the side wall of the source drain plug; and forming a sealing layer covering the top of the gate structure and the side wall of the source drain plug, wherein the sealing layer also seals the top of the groove to form an air side wall surrounded by the gate structure, the source drain doping layer, the substrate and the sealing layer. In the embodiment of the invention, the air side wall is arranged between the side wall of the side wall and the side wall of the source drain plug, and the dielectric constant (k value) of the air side wall is lower than that of the current dielectric layer, so that the capacitance between the grid structure and the source drain plug can be reduced, and the performance of a semiconductor can be improved.
In an alternative, the method for forming the semiconductor structure further comprises the following steps: forming a protective layer covering the side wall of the first sacrificial layer in the first opening; in the forming process of the semiconductor structure, a sacrificial layer is usually formed between the side wall of the side wall and the side wall of the source drain plug to occupy the position of the air side wall, and the sacrificial layer is correspondingly removed; in summary, the embodiment of the invention can reduce the capacitance between the gate structure and the source/drain plug, and ensure the quality of the source/drain plug, thereby being beneficial to improving the performance of the semiconductor.
In order to make the aforementioned objects, features and advantages of the embodiments of the present invention comprehensible, specific embodiments accompanied with figures are described in detail below.
FIG. 1 is a schematic structural diagram of a semiconductor structure according to an embodiment of the present invention.
The semiconductor structure includes: a substrate; a gate structure 204 on the substrate; a sidewall spacer 203 covering the sidewall of the gate structure 204; the source-drain doping layer 207 is positioned in the substrate at two sides of the gate structure 204; a source-drain plug 226 located on the top of the source-drain doping layer 208, wherein the source-drain plug 226 is electrically connected to the source-drain doping layer 208; the sealing layer 228 is positioned at the top of the gate structure 204, and the sealing layer 228 seals the top of a trench surrounded by the side wall 203, the top of the source-drain doping layer 208 and the side wall of the source-drain plug 226; and air gaps are enclosed by the side walls 203, the source-drain doping layers 208, the source-drain plugs 226 and the sealing layers 228, and serve as air side walls 227.
In this embodiment, the air sidewall 227 is disposed between the sidewall of the sidewall 203 and the sidewall of the source/drain plug 226, and since the dielectric constant (k value) of the air sidewall 227 is lower than that of the current dielectric layer, the capacitance between the gate structure 204 and the source/drain plug 226 can be reduced, which is beneficial to improving the performance of the semiconductor.
In an alternative aspect, the semiconductor structure further comprises: the protective layer 211 covers the sidewall of the source/drain plug 226 exposed by the air sidewall 227; in the forming process of the semiconductor structure, a sacrificial layer (not shown) is usually formed between the sidewall of the gate structure 204 and the sidewall of the source/drain plug 226 to occupy the position of the air sidewall 227, and accordingly the sacrificial layer needs to be removed, because the sidewall of the source/drain plug 226 exposed by the air sidewall 227 is covered with the protective layer 211, the protective layer 211 can protect the sidewall of the source/drain plug 226 in the process of removing the sacrificial layer, thereby reducing the probability of damage to the source/drain plug 226, i.e., facilitating the improvement of the quality of the source/drain plug 226; in summary, the embodiment of the present invention can reduce the capacitance between the gate structure 204 and the source/drain plug 226, and ensure the quality of the source/drain plug 226, thereby improving the performance of the semiconductor.
The substrate is used for providing a process platform for subsequent process procedures.
In this embodiment, the substrate is used to form a fin field effect transistor (FinFET). The base includes a substrate 200 and a fin 202 protruding from the substrate 200. In other embodiments, when the base is used to form a planar field effect transistor, the base is correspondingly a planar substrate.
In this embodiment, the fin 202 is made of the same material as the substrate 200 and is made of silicon. In other embodiments, the material of the substrate can also be germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate can also be a silicon-on-insulator substrate or a germanium-on-insulator substrate.
In this embodiment, the semiconductor structure further includes: and the isolation layer 201 is located on the substrate 200 where the fin portion 202 is exposed, and the isolation layer 201 covers part of the sidewall of the fin portion 202.
The isolation layer 201 is used to isolate adjacent devices. The material of the isolation layer 201 may be silicon oxide, silicon nitride, or silicon oxynitride. In this embodiment, the isolation layer 201 is made of silicon oxide.
The gate structure 204 is used to control the conduction channel to be turned on or off during device operation.
In this embodiment, the gate structure 204 is located on the substrate 200, and the gate structure 204 crosses over the fin 202 and covers a portion of the top and a portion of the sidewall of the fin 202.
In this embodiment, the gate structure 204 is a metal gate structure, and the gate structure 204 includes a high-k gate dielectric layer, a work function layer on the high-k gate dielectric layer, and a gate electrode layer on the work function layer.
Specifically, the material of the high-k gate dielectric layer is a high-k dielectric material. Wherein, the high-k dielectric material is a dielectric material with a relative dielectric constant larger than that of silicon oxide. In this embodiment, the material of the high-k gate dielectric layer is HfO 2 . In other embodiments, the material of the high-k gate dielectric layer may also be selected from ZrO 2 HfSiO, HfSiON, HfTaO, HfTiO, HfZrO or Al 2 O 3 And so on.
The work function layer is used to adjust the threshold voltage of the formed transistor. When forming PMOS, the work function layer is P-type work function layer, and the material of P-type work function layer includes one or more of TiN, TaN, TaSiN, TaAlN and TiAlN. When formed as an NMOS, the work function layer is an N-type work function layer, and the material of the N-type work function layer includes one or more of TiAl, Mo, MoN, AlN, and TiAlC.
The gate electrode layer is used for subsequent electrical connection with an external structure. In this embodiment, the material of the gate electrode layer includes W. In other embodiments, the gate electrode layer may be made of Al, Cu, Ag, Au, Pt, Ni, or Ti.
In this embodiment, the source-drain doping layer 208 is located in the fin portion 202 at two sides of the gate structure 204.
When an NMOS transistor is formed, the source-drain doping layer 208 comprises a stress layer doped with N-type ions, the material of the stress layer is Si or SiC, the stress layer provides a tensile stress effect for a channel region of the NMOS transistor, and therefore carrier mobility of the NMOS transistor is improved, wherein the N-type ions are P ions, As ions or Sb ions; when a PMOS transistor is formed, the source-drain doping layer 208 includes a stress layer doped with P-type ions, the stress layer is made of Si or SiGe, and the stress layer provides a compressive stress effect for a channel region of the PMOS transistor, so as to improve carrier mobility of the PMOS transistor, wherein the P-type ions are B ions, Ga ions, or In ions.
In this embodiment, the sidewall spacers 203 cover the sidewalls of the gate structures 204.
The sidewall spacers 203 are used for defining a formation region of the source-drain doping layer 208, and the sidewall spacers 203 are also used for protecting the sidewalls of the gate structure 204. The sidewall 203 may be a single-layer structure or a stacked structure, and the material of the sidewall 203 includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, and boron carbonitride. In this embodiment, the sidewall spacers 203 have a single-layer structure, and the sidewall spacers 203 are made of silicon nitride.
In this embodiment, the semiconductor structure further includes: a gate capping layer 205 on top of the gate structure 204.
The gate capping layer 205 is used for protecting the top of the gate structure 204, so that the damage to the gate structure 204 and the short circuit between the top source drain plug and the gate structure 204 are reduced in the process of forming the top source drain plug.
The material of the gate cap layer 205 includes one or more of SiC, SiCO, SiN, and SiCN. In this embodiment, the gate capping layer 205 is made of SiN.
In this embodiment, the semiconductor structure further includes: and a metal silicide layer 213 positioned on the top surface of the source-drain doped layer 208.
The metal silicide layer 213 can reduce the contact resistance between the source drain plug 226 and the source drain doping layer 208.
In addition, in this embodiment, the etching rate of the metal silicide layer 213 is lower than the etching rate of the first sacrificial layer formed in the forming process, and in the manufacturing process of etching and removing the first sacrificial layer in the forming process, the metal silicide layer 213 can play a role in protecting the source/drain doping layer 208, so that the source/drain doping layer 208 is not easily damaged in the etching process.
In this embodiment, the material of the metal silicide layer 213 includes one or more of TiSi, NiSi, and CoSi.
The TiSi, NiSi, and CoSi have characteristics of high conductivity, high hardness, and the like, and can ensure a protective effect on the source-drain doping layer 208 while satisfying an electrical connection function between the source-drain plug 226 and the source-drain doping layer 208.
In this embodiment, the source-drain plug 226 is located at the top of the source-drain doping layer 208, and the source-drain plug 226 is electrically connected to the source-drain doping layer 208.
The source drain plugs 226 are used to electrically connect the source drain doped layer 208 to an external circuit or other interconnect structure.
In this embodiment, the source/drain plug 226 is located on the top of the metal silicide layer 213 and contacts the metal silicide layer 213.
Because the metal silicide layer 213 has good conductivity, the source drain plug 226 contacts with the metal silicide layer 213, and the process requirement of electrically connecting the source drain doping layer 208 with an external circuit or other interconnection structures can be still met.
In this embodiment, the source-drain plugs 226 include bottom source-drain plugs 215 and top source-drain plugs 225 located on top of the bottom source-drain plugs 215.
The bottom source drain plug 215 is electrically connected to the source drain doped layer 208 for electrically connecting the source drain doped layer 208 to an external circuit or other interconnect structure.
In this embodiment, the bottom source-drain plug 215 is made of tungsten. The resistivity of tungsten is low, which is beneficial to improving the signal delay of the rear-section RC and improving the processing speed of the chip, and is also beneficial to reducing the resistance of the bottom source drain plug 215, and correspondingly reduces the power consumption. In other embodiments, the material of the bottom source-drain plug may also be a conductive material such as cobalt or ruthenium.
The top source drain plug 225 is electrically connected with the source drain doping layer 208 through the bottom source drain plug 215, so that the electrical property of the source drain doping layer 208 is led out through the bottom source drain plug 215.
In this embodiment, the semiconductor structure further includes: and a source-drain capping layer (not shown) located on the top of the bottom source-drain plug 215 exposed by the top source-drain plug 225, wherein the top of the source-drain capping layer is flush with the top of the gate capping layer 205.
Note that fig. 1 is a cross-sectional view at a location on top of top source drain plug 225, and thus, the source drain cap layer is not shown.
The source drain capping layer protects the bottom source drain plug 215.
The source-drain cap layer is made of a material having etching selectivity with the gate cap layer 205, the protective layer 211 and the sidewall 203, so that the source-drain cap layer can protect the bottom source-drain plug 215.
Moreover, the top source-drain plug 225 is located at the top of the bottom source-drain plug 215, so that, in order to facilitate the mutual contact between the top source-drain plug 225 and the bottom source-drain plug 215, the source-drain cap layer needs to be etched, that is, the material of the source-drain cap layer is a material capable of being etched.
In this embodiment, the material of the source/drain cap layer includes SiO 2 One or more of SiC and SiCN. As an example, the source/drain cap layer material is SiO 2 。
In this embodiment, the top of the source/drain cap layer is flush with the top of the gate cap layer 205, which is beneficial to using the top of the gate cap layer 205 as a stop position in the planarization process for forming the source/drain cap layer, thereby reducing the process difficulty.
In this embodiment, the sealing layer 228 is located on the top of the gate structure 204, and seals the top of the trench surrounded by the sidewall 203, the top of the source-drain doping layer 208, and the sidewall of the source-drain plug 226; and air gaps are enclosed by the side walls 203, the source-drain doping layers 208, the source-drain plugs 226 and the sealing layers 228, and serve as air side walls 227.
The sealing layer 228 is used for sealing the top of an air gap enclosed by the sidewall of the gate structure 204, the top of the source-drain doping layer 208 and the sidewall of the source-drain plug 226, so that an air sidewall 227 can be formed. The bottom of the seal 228 serves as the top of the air sidewall 227.
In this embodiment, the sealing layer 228 is located on top of the gate capping layer 205.
In this embodiment, the material of the sealing layer 228 includes SiO 2 SiN and SiC.
SiN and SiO 2 And SiC has higher compactness, so that the sealing performance is better, smaller gaps are difficult to fill, and the sealing groove top is sealed, and meanwhile, the gate structure 204, the source-drain doping layer 208, the source-drain plug 226 and the sealing layer 228 are enabled to surround the air side wall 227 with larger height.
The air sidewall 227 has a lower dielectric constant, and compared with a dielectric layer having a larger dielectric constant formed between the gate structure 204 and the source-drain plug 226, the present embodiment is beneficial to reducing the capacitance between the gate structure 204 and the source-drain plug 226, thereby improving the performance of the semiconductor structure.
In this embodiment, the metal silicide layer 213 is exposed at the bottom of the air sidewall 227.
Specifically, in order to reduce the influence of the air side wall 227 on the source/drain doping layer 208 at the bottom of the metal silicide layer 213, the metal silicide layer 213 covers the bottom of the air side wall 227, so that the probability that the air side wall 227 is in direct contact with the source/drain doping layer 208 is reduced.
In this embodiment, the semiconductor structure further includes: and the protective layer 211 covers the sidewall of the source/drain plug 226 exposed by the air sidewall 227.
The protection layer 211 provides a protection effect for the sidewalls of the source/drain plugs 226, and reduces the probability of damage to the sidewalls of the source/drain plugs 226 in related process, thereby improving the performance of the semiconductor structure.
In this embodiment, the material of the protection layer 211 includes one or more of silicon oxide, and silicon oxynitride.
The silicon nitride, the silicon oxide and the silicon oxynitride have the characteristic of high material hardness, and under the influence of related process technologies, the probability of removing the protective layer 211 is low, so that the side wall of the source/drain plug 226 can be protected. As an embodiment, in the present embodiment, the material of the protection layer 211 is silicon nitride.
In this embodiment, the sidewall of the top source-drain plug 225 exposed by the protection layer 211 protrudes outward relative to the sidewall of the bottom source-drain plug 215, which is beneficial to ensuring that the bottom dimension of the top source-drain plug 225 is the same as the top dimension of the bottom source-drain plug 215 in a direction perpendicular to the extending direction of the gate structure 204, so that the contact area between the top source-drain plug 225 and the bottom source-drain plug 215 is increased, and a better electrical connection effect is obtained.
In this embodiment, the thickness of the protection layer 211 is 0.5 nm to 2 nm.
The thickness of the protective layer 211 is not too large, nor too small. If the thickness of the protection layer 211 is too large, the space region of the air sidewall 227 is easily occupied too much, and accordingly the space region of the air sidewall 227 is too small, which is difficult to meet the requirement of capacitance between the source-drain plug 226 and the gate structure 204, thereby affecting the performance of the semiconductor structure; if the thickness of the protection layer 211 is too small, the protection layer 211 is likely to have a good protection effect on the sidewall of the source/drain plug 226 in the process of forming the air sidewall 227, so that the sidewall of the source/drain plug 226 is likely to be damaged, and the performance of the source/drain plug 226 is affected, and the performance of the semiconductor structure is correspondingly affected. For this reason, in the present embodiment, the thickness of the protection layer 211 is 0.5 nm to 2 nm.
In this embodiment, the semiconductor structure further includes: and an etch stop layer 219 located between the sealing layer 228 and the top of the gate cap layer 205.
Specifically, in the forming process of the semiconductor structure, in the etching step of forming the opening for accommodating the top source-drain plug 225, the etching stop layer 219 on the top of the source-drain cap layer is firstly used as an etching stop position, and then the source-drain cap layer is etched at the same time, which is beneficial to improving the thickness consistency of the top source-drain plug 225.
Fig. 2 to fig. 22 are schematic structural diagrams corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.
Referring to fig. 2, a substrate is provided, a gate structure 104 is formed on the substrate, a sidewall 103 is formed on a sidewall of the gate structure 104, an active drain doping layer 108 is formed in the substrate on both sides of the gate structure 104, an interlayer dielectric layer 106 is formed on the top of the substrate exposed by the gate structure 104, and the interlayer dielectric layer 106 also covers the top of the gate structure 104.
The substrate is used for providing a process platform for subsequent process procedures.
In this embodiment, the substrate is used to form a fin field effect transistor (FinFET). The base includes a substrate 100 and a fin 102 protruding from the substrate 100. In other embodiments, when the base is used to form a planar field effect transistor, the base is correspondingly a planar substrate.
In this embodiment, the fin 102 is made of the same material as the substrate 100, and is made of silicon. In other embodiments, the material of the substrate can also be germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate can also be a silicon-on-insulator substrate or a germanium-on-insulator substrate.
In this embodiment, the method for forming the semiconductor structure further includes: after the fin portion 102 is formed, an isolation layer 101 is formed on the substrate 100 exposed by the fin portion 102, and the isolation layer 101 covers a portion of a sidewall of the fin portion 102.
The isolation layer 101 is used to isolate adjacent devices. The material of the isolation layer 101 may be silicon oxide, silicon nitride, or silicon oxynitride. In this embodiment, the material of the isolation layer 101 is silicon oxide.
The gate structure 104 is used to control the conduction channel to be turned on or off during device operation.
In this embodiment, the gate structure 104 is located on the substrate 100, and the gate structure 104 crosses over the fin 102 and covers a portion of the top and a portion of the sidewall of the fin 102.
In this embodiment, the gate structure 104 is a metal gate structure, and the gate structure 104 includes a high-k gate dielectric layer, a work function layer on the high-k gate dielectric layer, and a gate electrode layer on the work function layer.
In this embodiment, the source-drain doping layer 108 is located in the fin portion 102 at two sides of the gate structure 104.
It should be noted that, with reference to fig. 2, in this embodiment, a sidewall 103 is further formed on a sidewall of the gate structure 104. The sidewall spacers 103 are used for defining a formation region of the source-drain doping layer 108, and the sidewall spacers 103 are also used for protecting the sidewalls of the gate structure 104.
For specific description of the gate structure 104, the source-drain doping layer 108 and the sidewall spacer 103, reference may be made to corresponding description in the foregoing embodiments, and details are not repeated herein in this embodiment.
In this embodiment, in the step of providing the substrate, a gate capping layer 105 is formed on the top of the gate structure 104.
In order to save the chip Area, the forming method introduces a Contact Over Active Gate (COAG) process, so as to form a Gate plug above the Gate structure 104 of the Active Area (AA) subsequently. The gate capping layer 105 is used for protecting the top of the gate structure 104, so that the damage to the gate structure 104 and the short circuit between the top source drain plug and the gate structure 104 are reduced in the subsequent process of forming the top source drain plug.
The gate capping layer 105 is made of a material having an etching selectivity with the sidewall spacer 103 and a subsequently formed second sacrificial layer, so as to be beneficial to ensuring that the gate capping layer 105 can protect the gate structure 104.
The material of the gate cap layer 105 includes one or more of SiC, SiCO, SiN, and SiCN. In this embodiment, the gate capping layer 105 is made of SiN.
The interlayer dielectric layer 106 provides a space position for a source drain plug and a sealing layer which are formed subsequently.
In this embodiment, the interlayer dielectric layer 106 is made of an insulating material, and the material of the interlayer dielectric layer 106 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon oxycarbonitride. In this embodiment, the interlayer dielectric layer 106 is made of silicon oxide.
Referring to fig. 3, the interlayer dielectric layer 106 between adjacent gate structures 104 is removed, and a first opening 107 exposing the top of the source-drain doping layer 108 is formed, where the first opening 107 is surrounded by the sidewall of the sidewall spacer 103, the sidewall of the interlayer dielectric layer 106, and the substrate.
The first opening 107 provides a spatial location for the subsequent formation of a first sacrificial layer, a protective layer and a source drain plug.
In this embodiment, the step of forming the first opening 107 includes: and etching the interlayer dielectric layer 106 between the adjacent gate structures 104 by using the gate cap layer 105 as a self-alignment stop layer to expose the top of the source-drain doped layer 108.
The probability that the first opening 107 exposes the gate structure 104 is low under the effect of the gate capping layer 105, so that the self-aligned etching is realized during the etching process, and the position of the first opening 107 is limited between the adjacent gate structures 104.
In this embodiment, the sidewall of the first opening 107 exposes the sidewall 103, so that the dielectric material between the sidewalls 103 is completely removed, which is favorable for reducing the capacitance between the subsequent source/drain plug and the gate structure 104, and the sidewall 103 is retained, so that the sidewall 103 still protects the sidewall of the gate structure 104 in the subsequent process (for example, in the subsequent process of removing the first sacrificial layer).
In this embodiment, the process of removing the interlayer dielectric layer 106 between the adjacent gate structures 104 includes a dry etching process.
The dry etching process comprises an anisotropic dry etching process, and the anisotropic dry etching process has anisotropic etching characteristics. That is, the longitudinal etching rate is greater than the transverse etching rate, so that the shape and quality of the sidewall of the first opening 106 can be ensured while the interlayer dielectric layer 106 between the adjacent gate structures 104 is removed.
Referring to fig. 4, a first sacrificial layer 109 is formed on the sidewall of the first opening 107, and the first sacrificial layer 109 covers the sidewall of the sidewall 103.
The first sacrificial layer 109 occupies a space for forming an air sidewall between the gate structure 104 and the source-drain plug.
In this embodiment, in the step of forming the first sacrificial layer 109 on the sidewall of the first opening 107, the first sacrificial material layer 300 conformally covering the bottom and the sidewall of the first opening 107 and the top of the gate structure 104 is formed, wherein the first sacrificial material layer 300 on the sidewall of the first opening 107 serves as the first sacrificial layer 109.
A first sacrificial material layer 300 is covered on the top of the gate structure 104 and the bottom of the first opening 107, and a process preparation is performed in advance for converting the first sacrificial material layer on the top of the gate structure and the bottom of the first opening into a metal silicide layer for a subsequent silicide process.
In this embodiment, the process of forming the first sacrificial layer 109 includes an atomic layer deposition process.
The ald process includes multiple ald cycles, which is beneficial to improve the thickness uniformity of the first sacrificial layer 109, so that the first sacrificial layer 109 can cover the sidewall of the gate structure 104. In other embodiments, the first sacrificial layer may also be formed by a Chemical Vapor Deposition (CVD) process.
The material of the first sacrificial layer 109 (i.e. the first sacrificial material layer 300) is required to satisfy: the first sacrificial layer 109 is easy to remove later, and the process of removing the first sacrificial layer 109 has less damage to other film layers. Also, the material of the first sacrificial layer 109 is a material capable of silicide processing.
Therefore, in the present embodiment, the material of the first sacrificial layer 109 includes amorphous silicon. The amorphous silicon can react with metal, and the crystal orientation of the amorphous silicon is irregularly arranged and has the characteristic of instability, so that the amorphous silicon is easy to remove.
Referring to fig. 5 to 6, a protective layer 111 is formed in the first opening 107 to cover the sidewall of the first sacrificial layer 109.
The protective layer 111 provides a protective effect for a source-drain plug formed in a remaining space of the first opening 107, and reduces the probability that the sidewall of the source-drain plug is damaged in a related process, thereby improving the performance of the semiconductor structure.
Moreover, in the subsequent silicide processing process of the protective layer 111, the probability that a subsequently formed metal silicide layer penetrates into the side wall 103 of the side wall of the gate structure 104 can be reduced, and then the probability that the gate structure 104 and a subsequently formed source-drain plug are short-circuited is reduced, so that the performance of the semiconductor structure is improved.
In this embodiment, the step of forming the protective layer 111 includes: as shown in fig. 5, after the first sacrificial layer 109 is formed, a protective material layer 110 is formed to conformally cover the bottom and sidewalls of the first opening 107 and the top of the interlayer dielectric layer 106; as shown in fig. 6, the protective material layer 110 on the top of the interlayer dielectric layer 106 and at the bottom of the first opening 107 is removed, and the remaining protective material layer 110 serves as the protective layer 111.
In this embodiment, the process of forming the protective material layer 110 includes an atomic layer deposition process.
In this embodiment, the process of removing the protective material layer 110 on the top of the interlayer dielectric layer 106 and at the bottom of the first opening 107 includes a dry etching process, so that the protective material layer 110 on the sidewall of the first sacrificial layer 109 is retained by using the characteristic of anisotropic etching of the dry etching process.
The material of the protective layer 111 includes one or more of silicon nitride, silicon oxide, and silicon oxynitride.
The silicon nitride, the silicon oxide and the silicon oxynitride have the characteristic of high material hardness, and under the influence of related process technologies, the probability of removing the protective layer 111 is low, so that the protective layer can protect the side wall of a source-drain plug formed subsequently. As an embodiment, in the present embodiment, the material of the protection layer 111 is silicon nitride.
Referring to fig. 7 to 8, a silicide process is performed on the exposed first sacrificial material layer 110 of the protection layer 111 to convert the first sacrificial material layer 110 on the top of the gate structure 104 and at the bottom of the first opening 107 into a metal silicide layer 113, and the metal silicide layer 113 extends to the bottom of the first sacrificial layer 109 on the sidewall of the first opening 107.
In the subsequent process of removing the first sacrificial layer 109 on the top of the metal silicide layer 113, the etching rate of the metal silicide layer 113 is less than that of the first sacrificial layer 109, and when the first sacrificial layer 109 is removed by etching, the top of the metal silicide layer 113 can define the position where etching stops, so that the source-drain doping layer 108 can be protected, and therefore the source-drain doping layer 108 is not easily damaged by the etching process, and the contact resistance between a subsequently formed source-drain plug and the source-drain doping layer 108 can be reduced by the metal silicide layer 113, so that the metal silicide layer 113 does not need to be removed, process steps are reduced, and the efficiency of the semiconductor structure forming method is improved.
In this embodiment, the step of forming the metal silicide layer 113 includes: as shown in fig. 7, a selective deposition process is adopted to form a metal layer 112 on the surface of the first sacrificial material layer 300 exposed by the protective layer 111; as shown in fig. 8, annealing the metal layer 112 and the first sacrificial layer 300 is performed, so that the first sacrificial layer 300 reacts with the metal layer 112, and the metal silicide layer 113 located on the surface of the source-drain doping layer 108 and the top of the gate structure 104 is formed.
In this embodiment, the material of the metal layer 112 includes one or more of titanium, nickel, and platinum.
The titanium, the nickel and the platinum have the characteristics of conductivity, high hardness and the like, and can react with the first sacrificial layer 300 to form the metal silicide layer 113, so that the metal silicide layer 113 formed by the reaction can protect the source-drain doping layer 108 while the electrical connection performance between the source-drain plug and the source-drain doping layer 108 is met. Also, by using the above materials, it is convenient to form the metal layer 112 by means of selective deposition.
In this embodiment, the selective deposition process has characteristics of deposition flexibility, etc., and deposition rates of the selective deposition process on different materials are different, so as to meet the required process requirements, and the metal layer 112 is selectively formed on the surface of the first sacrificial material layer 300 exposed by the protection layer 111, but is difficult to be formed on the surface of the protection layer 111.
In this embodiment, the selective deposition process includes a pulsed plasma deposition process.
In the pulse plasma deposition process, a pulse power supply controls the reaction gas to generate the opening or closing of the plasma, and when the pulse power supply is in an opening state, the reaction gas forms the plasma, namely the plasma is opened; when the pulse power supply is in an off state, the reaction gas does not form a plasma. The plasma is alternately turned on or off, so that the deposition of the metal layer on the sidewall of the protection layer 111 is inhibited, and meanwhile, in the process of the pulsed plasma deposition process, the material selected for the protection layer 111 has the characteristic of difficult deposition, so that the deposition effect of the metal layer on the sidewall of the protection layer 111 is poor, and the process requirement of forming the metal layer 112 on the surface of the first sacrificial material layer 300 exposed out of the protection layer 111 is met.
Referring to fig. 9 to 20, after the first sacrificial layer 109 is formed, a source drain plug 126 (as shown in fig. 9) is formed on the top of the source drain doping layer 108, the source drain plug 126 covers the sidewall of the first sacrificial layer 114, and the source drain plug 126 is electrically connected to the source drain doping layer 108.
The source-drain plugs 126 are used for realizing the electrical connection between the source-drain doping layer 108 and an external circuit or other interconnection structures.
In this embodiment, a gate plug is formed by using a COAG process, and thus, the source and drain plugs 126 include a top source and drain plug 125 and a bottom source and drain plug 115 located at the top of the top source and drain plug 125.
The step of forming the source/drain plug 126 on top of the source/drain doped layer 108 will be described in detail below with reference to the accompanying drawings.
Referring to fig. 9, the metal silicide layer 113 on top of the gate structure 104 is removed.
Removing the metal silicide layer 113 on top of the gate structure 104 provides a spatial location for the subsequent formation of a gate plug on top of the gate structure 104.
With reference to fig. 9 to fig. 10, a bottom source drain plug 115 is formed in the remaining space of the first opening 107, the top of the bottom source drain plug 115 is flush with the top of the gate capping layer 105, and in the process of forming the bottom source drain plug 115, the interlayer dielectric layer 106 and the first sacrificial layer 109 higher than the top of the gate capping layer 105 are removed.
The bottom source drain plug 115 is in contact with the source drain doped layer 108, and is used for electrically connecting the source drain doped layer 108 with an external circuit or other interconnection structures.
And forming a top source-drain plug 125 which is in contact with the bottom source-drain plug 115 on the bottom source-drain plug 115, wherein the top source-drain plug 125 is electrically connected with the source-drain doping layer 108 through the bottom source-drain plug 115.
Specifically, the step of forming the bottom source drain plug 115 in the remaining space of the first opening 107 includes: forming a bottom source drain plug material (not shown) in the remaining space of the first opening 107, wherein the bottom source drain plug material also covers the top of the interlayer dielectric layer 106; and with the top of the gate cap layer 105 as a stop position, planarizing the bottom source-drain plug material, the interlayer dielectric layer 106 and the first sacrificial layer 109, and taking the rest of the planarized bottom source-drain plug material as a bottom source-drain plug 115.
In this embodiment, the bottom source/drain plug 115 is made of tungsten. The resistivity of tungsten is low, which is beneficial to improving the signal delay of the rear RC and improving the processing speed of the chip, and is also beneficial to reducing the resistance of the bottom source drain plug 115, and correspondingly reducing the power consumption. In other embodiments, the material of the bottom source-drain plug may also be a conductive material such as cobalt or ruthenium.
The bottom source/drain plug material is planarized to retain the bottom source/drain plug material (i.e., the bottom source/drain plug 115) in the first opening 107, and the top surface of the bottom source/drain plug 115 has a high flatness, so that the etching uniformity is improved when the bottom source/drain plug 115 having a certain thickness is etched back in the subsequent process. In addition, in the process of performing planarization treatment on the bottom source drain plug material, the interlayer dielectric layer 106 and the first sacrificial layer 109 are planarized, and accordingly, the metal silicide layer 113 on the top of the gate junction structure is also removed.
Referring to fig. 11 to fig. 12, etching back a part of the thickness of the bottom source drain plug 115 to form a second opening 116 (as shown in fig. 11) surrounded by the remaining bottom source drain plug 115, the first sacrificial layer 109 and the interlayer dielectric layer 106; and forming a source-drain capping layer 117 in the second opening 116 to cover the top of the bottom source-drain plug 115 (as shown in fig. 12).
The second opening 116 provides a spatial location for forming a source/drain capping layer 117, and the source/drain capping layer 117 protects the bottom source/drain plug 115.
The source-drain cap layer 117 is made of a material having etching selectivity with the gate cap layer 105, the protective layer 111, the sidewall 103, the first sacrificial layer 109 and a subsequently formed second sacrificial layer, so that the source-drain cap layer 117 can protect the bottom source-drain plug 115. Moreover, in the subsequent process of forming the top source-drain plug, not only the second sacrificial layer but also the source-drain cap layer 117 needs to be etched, so that the material of the source-drain cap layer 117 is a material capable of being etched.
In this embodiment, the source/drain capping layer 117 material includes SiO 2 One or more of SiC and SiCN. As an example, the source/drain capping layer 117 is made of SiO 2 。
In this embodiment, after the gate capping layer 105 is formed, the source and drain capping layer 117 is formed, so that the gate capping layer 105 can be used to define a stop position of the etch-back process in the process of forming the source and drain capping layer 117.
In this embodiment, the bottom source/drain plug 115 with a certain thickness is etched back by using a dry etching process, so as to accurately control the etching amount and improve the top surface flatness of the remaining bottom source/drain plug 115 after etching.
Referring to fig. 13, a second sacrificial layer 118 is formed atop the gate structure 104 and atop the source drain capping layer 108.
The second sacrificial layer provides a process basis for the subsequent formation of a top source drain plug and a gate plug.
In this embodiment, the material of the second sacrificial layer 118 is the same as the material of the first sacrificial layer 109. Facilitating subsequent removal of the material of the second sacrificial layer 118 and the first sacrificial layer 109 in the same etch process.
In this embodiment, the material of the second sacrificial layer 118 includes amorphous silicon.
In this embodiment, in the process of forming the source/drain plug 126, after forming the source/drain capping layer 117 and before removing the second sacrificial layer 118, the method further includes: and forming an etching stop layer 119 on the tops of the gate capping layer 105 and the source drain capping layer 117.
In the subsequent process of forming the third opening, in order to ensure that the etching depths of the adjacent third openings are consistent, the etching stop layer 119 at the top of the source/drain cap layer 117 is used as an etching stop position, and then the source/drain cap layer 117 is etched at the same time.
In this embodiment, the material of the etch stop layer 119 includes one or more of silicon nitride, silicon oxide, and silicon oxynitride.
Referring to fig. 14 to fig. 20, a top source drain plug 125 penetrating through the second sacrificial layer 118 and the source drain capping layer 117 on the top of the bottom source drain plug 115 and connected to the bottom source drain plug 115 is formed, and the top source drain plug 125 and the bottom source drain plug 115 form the source drain plug 126.
The top source drain plug 125 is electrically connected to the source drain doping layer through the bottom source drain plug 115, so as to lead out the electrical property of the source drain doping layer.
The step of forming the top source drain plug 125 includes: as shown in fig. 14 to fig. 16, etching the second sacrificial layer and the source-drain capping layer on the top of the bottom source-drain plug, and forming a third opening 120 (shown in fig. 16) penetrating through the second sacrificial layer 118 and the source-drain capping layer 117 on the top of the bottom source-drain plug 115, where the third opening 120 exposes the top of the bottom source-drain plug 115; as shown in fig. 20, a top source drain plug material layer (not shown) is filled in the third opening 120; and planarizing the top source drain plug material layer by taking the top of the second sacrificial layer 118 as a stop position, wherein the rest of the top source drain plug material layer in the third opening 120 is taken as a top source drain plug 125.
In this embodiment, in the step of forming the top source-drain plug 125, the top source-drain plug 125 further penetrates through the etching stop layer 119 on the top of the source-drain capping layer 117, and correspondingly, the third opening 120 penetrates through the second sacrificial layer 118, the etching stop layer 119, and the source-drain capping layer 117.
Referring to fig. 14, in the process of forming the third opening 120 in this embodiment, in the step of etching the second sacrificial layer 118 on the top of the bottom source/drain plug 115, the second sacrificial layer 118 also exposes the top of the first sacrificial layer 109.
By exposing the top of the first sacrificial layer 109 through the second sacrificial layer, it is beneficial to ensure that the top of the bottom source drain plug 115 can be completely exposed through the subsequent third opening 120 in the direction perpendicular to the extending direction of the gate structure 104, so as to increase the contact area between the subsequent top source drain plug and the top of the bottom source drain plug 115.
Accordingly, the isolated first sacrificial layer 109 and the isolated second sacrificial layer 118 are connected to each other through a subsequently formed third sacrificial layer, so that the first sacrificial layer 109, the second sacrificial layer 118 and the third sacrificial layer can be removed in the same step, and for this reason, the third opening 120 exposes the top of the first sacrificial layer 109, thereby providing a process basis for the subsequently formed third sacrificial layer.
Referring to fig. 15, after the etching of the second sacrificial layer and before the etching of the source drain cap layer, the method further includes: a third sacrificial layer 121 is formed on the sidewall of the second sacrificial layer 118, and the third sacrificial layer 121 covers the top of the first sacrificial layer 109 and contacts the first sacrificial layer 109.
In order to facilitate the subsequent removal of the first sacrificial layer 109, the second sacrificial layer 118 and the third sacrificial layer 121 simultaneously by an isotropic wet etching process, the third sacrificial layer 121 is formed on the sidewall of the second sacrificial layer 118, so that the first sacrificial layer 109 and the second sacrificial layer 118 are connected through the third sacrificial layer 121.
In this embodiment, the step of forming the third sacrificial layer 121 includes: forming a second sacrificial material layer (not shown) on the top and the sidewall of the second sacrificial layer 118, and on the bottom source drain plug 115 and the top of the first sacrificial layer 109; and removing the second sacrificial material layer on the top of the second sacrificial layer 118 and on the top of the bottom source drain plug 115, and using the remaining second sacrificial material layer as the third sacrificial layer 121.
In this embodiment, the third sacrificial layer 121 exposes the source/drain capping layer 117, so as to prepare for subsequent etching of the source/drain capping layer 117.
In this embodiment, the process of forming the second sacrificial material layer includes an atomic layer deposition process.
In this embodiment, the process of removing the second sacrificial material layer on the top of the second sacrificial layer 118 and the top of the bottom source drain plug 115 includes a dry etching process, so that the third sacrificial layer 121 covers the sidewall of the second sacrificial layer 118 by using the anisotropic etching characteristic of the dry etching process.
Referring to fig. 17 and fig. 20, after forming the top source drain plugs 125 and before removing the first sacrificial layer 109, the method further includes: a gate plug 124 is formed through the second sacrificial layer 118 on top of the gate structure 104, and the gate plug 124 is connected to the top of the gate structure 104.
The gate plug 124 is used to make electrical connection between the gate structure 104 and external circuitry or other interconnect structures.
In this embodiment, the step of forming the gate plug 124 includes: etching to remove the second sacrificial layer 118 and the gate capping layer 105 on the top of the gate structure 104, and forming a gate contact hole 123 on the top of the gate structure 104; forming a gate plug material layer (not shown) in the gate contact hole 123; taking the top of the second sacrificial layer 118 as a stop position, the gate plug material layer higher than the top of the second sacrificial layer 118 is removed, and the remaining gate plug material layer is used as the gate plug 124.
In this embodiment, in the same step, the top source drain plugs 125 are formed in the third opening 120, and the gate plugs 124 are formed in the gate contact holes 123, so that the top source drain plugs 125 and the gate plugs 124 are made of the same material.
Note that, referring to fig. 17, before forming the gate contact hole 123, the method further includes: an organic material layer 122 is formed on top of the second sacrificial layer 118, and the organic material layer 122 also fills the third opening 120.
In the process of forming the gate contact hole 123, the organic material layer 122 protects the top of the bottom source drain plug 115 exposed by the third opening 120.
Accordingly, as shown in fig. 19, after the gate contact hole 123 is formed, the method further includes: the organic material layer 122 is removed.
Referring to fig. 21, the first sacrificial layer 109 is removed, and a trench 127 surrounded by the sidewall 103, the top of the substrate, and the sidewall of the source/drain plug 126 is formed.
In this embodiment, the first sacrificial layer 109 is formed on the sidewall of the first opening 107, the source-drain plug 126 is formed in the remaining space of the first opening 107, that is, the first sacrificial layer 109 is formed between the source-drain plug 126 and the gate structure 104, and then the air sidewall surrounded by the gate structure 104, the source-drain doping layer 108, the source-drain plug 126 and the subsequently formed sealing layer is formed by removing the first sacrificial layer 109.
It should be noted that the trench 127 is formed to provide a spatial location for forming an air sidewall later.
It should be noted that the etching selectivity of the first sacrificial layer 109 to other film layers is relatively high, so as to improve the process flexibility of removing the first sacrificial layer 109.
Therefore, in this embodiment, the process of removing the first sacrificial layer 109 includes one or both of a wet etching process and an isotropic dry etching process.
In this embodiment, in the step of removing the first sacrificial layer 109, an etching selection ratio of the first sacrificial layer 109 to the metal silicide layer 113 is greater than 20: 1.
it should be noted that the etching selectivity of the first sacrificial layer 109 and the metal silicide layer 113 is not too small. If the etching selectivity of the first sacrificial layer 109 and the metal silicide layer 113 is too small, the exposed top of the metal silicide layer 113 is easily damaged to some extent, and the source/drain doped layer 108 at the bottom of the metal silicide layer 113 is further damaged. For this reason, in this embodiment, in the step of removing the first sacrificial layer 109, the etching selection ratio of the first sacrificial layer 109 to the metal silicide layer 113 is greater than 20: 1.
in this embodiment, the sidewall 103 covers the sidewalls of the gate structure 104 and the gate capping layer 105, so in the step of removing the first sacrificial layer 109, the trench 127 is a trench 127 surrounded by the sidewall 103, the top of the substrate, and the sidewalls of the source-drain plug 126.
In this embodiment, in the process of removing the first sacrificial layer 109, the sidewall 103 is used to protect the sidewall of the gate structure 104, and the protective layer 111 is used to protect the sidewall of the source/drain plug 126 opposite to the sidewall of the gate structure 104, so that damage to the gate structure 104 and the source/drain plug 126 is reduced.
With continuing reference to fig. 21, it should be further noted that, in this embodiment, before removing the first sacrificial layer 109, the forming method further includes: the first sacrificial layer 109 and the third sacrificial layer 119 are removed.
Specifically, the first sacrificial layer 109, the second sacrificial layer 118, and the third sacrificial layer 119 are simultaneously removed in one step.
In the same step, the first sacrificial layer 109, the second sacrificial layer 118, and the third sacrificial layer 119 are removed, and compared with a scheme of removing the first sacrificial layer 109, the second sacrificial layer, and the third sacrificial layer in multiple steps, the one-step etching process of this embodiment reduces damage to the source-drain plug 126 and the gate plug 124, and improves reliability of the semiconductor structure.
Referring to fig. 22, a sealing layer 128 is formed to cover the top of the gate structure 104 and the sidewalls of the source and drain plugs 126, the sealing layer 128 further seals the top of the trench 127, and an air sidewall 160 surrounded by the sidewall 103, the source and drain doping layer 108, the substrate, and the sealing layer 128 is formed.
The air side wall 160 has a lower dielectric constant, and compared with a dielectric layer having a larger dielectric constant formed between the side wall 103 and the source/drain plug 126, the embodiment is beneficial to reducing the capacitance between the side wall 103 and the source/drain plug 126, thereby improving the performance of the semiconductor structure.
In this embodiment, in the step of forming the sealing layer 128, the sealing layer 128 also covers the sidewall of the gate plug 124, which is beneficial to ensure that the top of the trench 127 is sealed, and provides a process foundation for forming the air sidewall. Moreover, the sealing layer 128 also covers the sidewalls of the gate plug 124, which is advantageous for protecting the sidewalls of the gate plug 124 in a subsequent process.
In this embodiment, the process of forming the sealing layer 128 includes a chemical vapor deposition process.
The filling capability of the chemical vapor deposition process is not too high, and the process stability is high, which is beneficial to sealing the top of the trench 127 and forming the air sidewall 160 meeting the process requirements. In other embodiments, the sealing layer may be formed by a furnace process.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (32)

1. A semiconductor structure, comprising:
a substrate;
the grid structure is positioned on the substrate;
the side wall covers the side wall of the grid structure;
the source-drain doping layer is positioned in the substrates at two sides of the grid structure;
the source-drain plug is positioned at the top of the source-drain doping layer and is electrically connected with the source-drain doping layer;
the sealing layer is positioned at the top of the grid structure and seals the top of a groove which is formed by the side wall, the top of the source-drain doping layer and the side wall of the source-drain plug in a surrounding mode; and the side wall, the source-drain doping layer, the source-drain plug and the sealing layer enclose an air gap, and the air gap is used as an air side wall.
2. The semiconductor structure of claim 1, further comprising: and the gate cap layer is positioned on the top of the gate structure, wherein the sealing layer is positioned on the top of the gate cap layer.
3. The semiconductor structure of claim 2, wherein the source drain plugs comprise bottom source drain plugs and top source drain plugs located at tops of the bottom source drain plugs;
the semiconductor structure further includes: and the source-drain cap layer is positioned at the top of the bottom source-drain plug exposed from the top source-drain plug, and the top of the source-drain cap layer is flush with the top of the grid cap layer.
4. The semiconductor structure of claim 3, further comprising: the protective layer covers the side wall of the source drain plug exposed out of the air side wall;
and the side wall of the top source drain plug exposed by the protective layer protrudes outwards relative to the side wall of the bottom source drain plug.
5. The semiconductor structure of claim 2, further comprising: and the etching stop layer is positioned between the sealing layer and the top of the grid electrode cap layer.
6. The semiconductor structure of claim 1, further comprising: the metal silicide layer is positioned on the top surface of the source-drain doping layer;
the source drain plug is positioned on the top of the metal silicide layer and is in contact with the metal silicide layer;
the metal silicide layer is exposed at the bottom of the air side wall.
7. The semiconductor structure of claim 4, wherein a material of the protective layer comprises one or more of silicon nitride, silicon oxide, and silicon oxynitride.
8. The semiconductor structure of claim 4, wherein the protective layer has a thickness of 0.5 nm to 2 nm.
9. The semiconductor structure of claim 5, wherein the material of the etch stop layer comprises one or both of SiN, SiC, and SiCN.
10. The semiconductor structure of claim 6, in which a material of the metal silicide layer comprises one or more of TiSi, NiSi, and CoSi.
11. The semiconductor structure of claim 1, in which a material of the encapsulation layer comprises SiO 2 And SiON.
12. A method of forming a semiconductor structure, comprising:
providing a substrate, wherein a gate structure is formed on the substrate, side walls of the gate structure are formed with side walls, active drain doping layers are formed in the substrate on two sides of the gate structure, an interlayer dielectric layer is formed on the top of the substrate exposed by the gate structure, and the interlayer dielectric layer also covers the top of the gate structure;
removing the interlayer dielectric layer between the adjacent grid electrode structures to form a first opening exposing the top of the source drain doping layer, wherein the first opening is formed by the side wall of the side wall, the side wall of the interlayer dielectric layer and the substrate in a surrounding mode;
forming a first sacrificial layer on the side wall of the first opening, wherein the first sacrificial layer covers the side wall of the side wall;
forming a source drain plug at the top of the source drain doping layer after the first sacrificial layer is formed, wherein the source drain plug covers the side wall of the first sacrificial layer and is electrically connected with the source drain doping layer;
removing the first sacrificial layer to form a groove surrounded by the side wall, the top of the substrate and the side wall of the source drain plug;
and forming a sealing layer covering the top of the gate structure and the side wall of the source drain plug, wherein the sealing layer also seals the top of the groove to form the air side wall surrounded by the side wall, the source drain doping layer, the substrate and the sealing layer.
13. The method for forming a semiconductor structure according to claim 12, wherein after forming the first sacrificial layer and before forming a source drain plug on top of the source drain doping layer, the method further comprises: and forming a protective layer covering the side wall of the first sacrificial layer in the first opening.
14. The method of forming a semiconductor structure of claim 13, wherein forming the protective layer comprises: after the first sacrificial layer is formed, forming a protective material layer which conformally covers the bottom and the side wall of the first opening and the top of the interlayer dielectric layer; and removing the protective material layer on the top of the interlayer dielectric layer and at the bottom of the first opening, wherein the residual protective material layer is used as the protective layer.
15. The method of forming a semiconductor structure of claim 13, wherein in the step of forming a first sacrificial layer on sidewalls of the first opening, a first sacrificial material layer is formed conformally covering a bottom and sidewalls of the first opening and a top of the gate structure, wherein the first sacrificial material layer on the sidewalls of the first opening serves as a first sacrificial layer;
after forming the protective layer, before forming the source drain plug, further comprising: and carrying out silicide treatment on the first sacrificial material layer exposed out of the protective layer, converting the first sacrificial material layer positioned at the top of the grid structure and the bottom of the first opening into a metal silicide layer, and extending the metal silicide layer to the bottom of the first sacrificial layer positioned on the side wall of the first opening.
16. The method of forming a semiconductor structure of claim 15, wherein forming the metal silicide layer comprises: forming a metal layer on the surface of the first sacrificial material layer exposed out of the protective layer by adopting a selective deposition process; annealing the metal layer and the first sacrificial layer to enable the first sacrificial layer to react with the metal layer to form a metal silicide layer located on the surface of the source drain doped layer and the top of the grid structure;
and removing the metal silicide layer positioned at the top of the gate structure in the process of forming the source-drain plug at the top of the source-drain doping layer.
17. The method for forming a semiconductor structure according to claim 12, wherein in the step of providing a substrate, a gate cap layer is formed on top of the gate structure;
the step of forming the first opening includes: and etching the interlayer dielectric layer between the adjacent gate structures by taking the gate cap layer as a self-alignment stop layer to expose the top of the source-drain doped layer.
18. The method for forming a semiconductor structure according to claim 17, wherein the step of forming a source drain plug on top of the source drain doping layer comprises: forming a bottom source drain plug in the residual space of the first opening, wherein the top of the bottom source drain plug is flush with the top of the grid cap layer, and removing the interlayer dielectric layer and the first sacrificial layer which are higher than the top of the grid cap layer in the process of forming the bottom source drain plug; back etching the bottom source drain plug with partial thickness to form a second opening surrounded by the rest of the bottom source drain plug, the first sacrificial layer and the interlayer dielectric layer; forming a source drain cap layer covering the top of the bottom source drain plug in the second opening; forming a second sacrificial layer on the top of the grid structure and the top of the source drain cap layer; forming a second sacrificial layer and a source-drain cap layer which penetrate through the top of the bottom source-drain plug, and a top source-drain plug which is connected with the bottom source-drain plug, wherein the top source-drain plug and the bottom source-drain plug form the source-drain plug;
before forming the sealing layer, the forming method further includes: and removing the second sacrificial layer.
19. The method for forming a semiconductor structure according to claim 18, wherein the step of forming a bottom source drain plug in a remaining space of the first opening comprises: forming a bottom source drain plug material in the residual space of the first opening, wherein the bottom source drain plug material also covers the top of the interlayer dielectric layer; and flattening the bottom source drain plug material, the interlayer dielectric layer and the first sacrificial layer by taking the top of the gate cap layer as a stop position, wherein the flattened residual bottom source drain plug material is used as a bottom source drain plug.
20. The method for forming a semiconductor structure according to claim 18, further comprising, after forming the top source drain plugs and before removing the first sacrificial layer: forming a grid electrode plug penetrating through the second sacrificial layer on the top of the grid electrode structure, wherein the grid electrode plug is connected with the top of the grid electrode structure;
in the step of forming the sealing layer, the sealing layer also covers sidewalls of the gate plug.
21. The method for forming a semiconductor structure according to claim 18, wherein in the process of forming the source and drain plugs, after forming the source and drain cap layers and before removing the second sacrificial layer, the method further comprises: forming an etching stop layer on the tops of the gate cap layer and the source drain cap layer;
in the step of forming the top source drain plug, the top source drain plug also penetrates through the etching stop layer at the top of the source drain cap layer.
22. The method for forming a semiconductor structure of claim 18, wherein the step of forming the top source drain plugs comprises: etching the second sacrificial layer and the source drain cap layer on the top of the bottom source drain plug, and forming a third opening penetrating through the second sacrificial layer and the source drain cap layer on the top of the bottom source drain plug, wherein the third opening exposes the top of the bottom source drain plug; filling a top source drain plug material layer in the third opening; and flattening the top source drain plug material layer by taking the top of the second sacrificial layer as a stop position, wherein the rest top source drain plug material layer in the third opening is used as a top source drain plug.
23. The method for forming a semiconductor structure according to claim 22, wherein in the step of etching the second sacrificial layer on top of the bottom source drain plug, the second sacrificial layer also exposes the top of the first sacrificial layer;
after the second sacrificial layer is etched and before the source drain cap layer is etched, the method further comprises the following steps: forming a third sacrificial layer on the side wall of the second sacrificial layer, wherein the third sacrificial layer covers the top of the first sacrificial layer and is in contact with the first sacrificial layer;
before forming the sealing layer, the forming method further includes: and removing the third sacrificial layer.
24. The method of forming a semiconductor structure according to claim 23, wherein the first sacrificial layer, the second sacrificial layer, and the third sacrificial layer are all the same material;
and removing the first sacrificial layer, the second sacrificial layer and the third sacrificial layer in the same step.
25. The method of forming a semiconductor structure of claim 24, wherein the step of forming the third sacrificial layer comprises: forming a second sacrificial material layer on the top and the side wall of the second sacrificial layer, the bottom source drain plug and the top of the first sacrificial layer; and removing the second sacrificial material layer on the top of the second sacrificial layer and at the bottom of the second opening, wherein the rest of the second sacrificial material layer is used as the third sacrificial layer.
26. The method of forming a semiconductor structure of claim 12, wherein the process of forming the first sacrificial layer comprises an atomic layer deposition process.
27. The method of forming a semiconductor structure of claim 12, wherein in the step of forming the first sacrificial layer, a material of the first sacrificial layer comprises amorphous silicon.
28. The method of forming a semiconductor structure of claim 12, wherein the process of removing the first sacrificial layer comprises one or both of a wet etching process and an isotropic dry etching process.
29. The method of forming a semiconductor structure of claim 15, wherein in the step of removing the first sacrificial layer, an etch selectivity ratio of the first sacrificial layer to the metal silicide layer is greater than 20: 1.
30. the method of forming a semiconductor structure of claim 16, wherein a material of the metal layer comprises one or more of titanium, nickel, and platinum.
31. The method of forming a semiconductor structure of claim 16, wherein said selective deposition process comprises a pulsed plasma deposition process.
32. The method of forming a semiconductor structure of claim 12, wherein the process of forming the sealing layer comprises a chemical vapor deposition process.
CN202110307236.XA 2021-03-23 2021-03-23 Semiconductor structure and forming method thereof Pending CN115117056A (en)

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