CN115084254A - 半导体装置及半导体装置的制造方法 - Google Patents
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 84
- 238000000034 method Methods 0.000 title claims abstract description 22
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 12
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims abstract description 36
- 229910052698 phosphorus Inorganic materials 0.000 claims abstract description 36
- 239000011574 phosphorus Substances 0.000 claims abstract description 36
- 238000009825 accumulation Methods 0.000 claims abstract description 25
- 239000010410 layer Substances 0.000 claims description 119
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 43
- 229920005591 polysilicon Polymers 0.000 claims description 43
- 239000000758 substrate Substances 0.000 claims description 39
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 12
- 229910052751 metal Inorganic materials 0.000 claims description 12
- 239000002184 metal Substances 0.000 claims description 12
- 238000005229 chemical vapour deposition Methods 0.000 claims description 11
- 239000012535 impurity Substances 0.000 claims description 8
- 239000002344 surface layer Substances 0.000 claims description 7
- 229910052757 nitrogen Inorganic materials 0.000 claims description 6
- 239000000463 material Substances 0.000 description 10
- 239000011229 interlayer Substances 0.000 description 7
- 238000005468 ion implantation Methods 0.000 description 4
- 238000005204 segregation Methods 0.000 description 4
- 230000004888 barrier function Effects 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 238000005530 etching Methods 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 229910000789 Aluminium-silicon alloy Inorganic materials 0.000 description 1
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910008484 TiSi Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 230000003213 activating effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
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Abstract
本发明涉及半导体装置及半导体装置的制造方法。针对在栅极沟槽电极的下方具有填埋电极的构造的半导体装置,减小栅极泄漏的滞后。半导体装置(100)具有形成于与发射极层(13)、基极层(15)及载流子积蓄层(2)接触而到达漂移层(1)的沟槽内的有源沟槽栅极(11)。有源沟槽栅极(11)具有:栅极沟槽绝缘膜(11b),其形成于沟槽的内壁;以及栅极沟槽电极(11a)及填埋电极(11c),它们在沟槽内形成于栅极沟槽绝缘膜(11b)之上,彼此绝缘,该填埋电极(11c)配置于栅极沟槽电极(11a)的下方。填埋电极(11c)的磷浓度比栅极沟槽电极(11a)的磷浓度低。
Description
技术领域
本发明涉及半导体装置及其制造方法。
背景技术
从节能的观点出发,在通用逆变器和AC伺服等领域,对进行3相电动机的可变速控制的功率模块使用IGBT(Insulated Gate Bipolar Transistor)、二极管。为了降低逆变器的损耗,要求这样的功率模块的IGBT、二极管的通断损耗及接通电压低。
具有在沟槽内形成的栅极电极(栅极沟槽电极)的沟槽栅型IGBT是通断损耗低的器件,特别地,作为栅极电容低的器件而知晓在栅极沟槽电极的下方设置有填埋电极的构造的IGBT(例如下述的专利文献1)。就具有栅极沟槽电极及填埋电极的IGBT而言,栅极沟槽电极与栅极电位连接,填埋电极与发射极电位连接。由此,栅极沟槽电极被填埋电极屏蔽,实现低的栅极电容。
专利文献1:日本特开2020-077727号公报
就具有栅极沟槽电极及填埋电极的IGBT而言,作为栅极沟槽电极及填埋电极的材料而通常使用添加了磷的掺杂多晶硅。但是,如果在栅极沟槽电极及填埋电极与设置于它们的表面的绝缘膜(栅极沟槽绝缘膜)之间的界面处磷发生偏析,则产生IGBT的栅极泄漏的滞后变大这一问题。
例如,在对栅极施加了正偏置时,电子容易被在填埋电极与栅极沟槽绝缘膜之间的界面处形成的磷的偏析部捕获,这成为使栅极泄漏(正侧栅极泄漏)的滞后变大的原因。另外,在对栅极施加了负偏置时,电子容易被在栅极沟槽电极与栅极沟槽绝缘膜之间的界面处形成的磷的偏析部捕获,这成为栅极泄漏(负侧栅极泄漏)的滞后变大的原因。
作为在填埋电极与栅极沟槽绝缘膜之间的界面处磷发生偏析的原因之一,想到在IGBT的制造工序中,由于在形成了填埋电极之后形成栅极沟槽绝缘膜,因而对填埋电极施加了大量的热处理。
发明内容
本发明就是为了解决以上这样的课题而提出的,其目的在于针对在栅极沟槽电极的下方具有填埋电极的构造的半导体装置,减小栅极泄漏的滞后。
本发明涉及的半导体装置具有:半导体衬底,其具有第1主面、第2主面及第1导电型的漂移层;所述第1导电型的载流子积蓄层,其在所述半导体衬底形成于比所述漂移层更靠所述第1主面侧处,与所述漂移层相比杂质的峰值浓度高;第2导电型的基极层,其在所述半导体衬底形成于比所述载流子积蓄层更靠所述第1主面侧处;所述第1导电型的发射极层及所述第2导电型的接触层,它们是在所述半导体衬底处与所述第1主面接触地形成的;以及有源沟槽栅极,其形成于与所述发射极层、所述基极层及所述载流子积蓄层接触而到达所述漂移层的沟槽内,所述有源沟槽栅极具有:栅极沟槽绝缘膜,其形成于所述沟槽的内壁;以及栅极沟槽电极及填埋电极,它们在所述沟槽内形成于所述栅极沟槽绝缘膜之上,彼此绝缘,该填埋电极配置于比所述栅极沟槽电极更靠所述第2主面侧处,所述填埋电极的磷浓度比所述栅极沟槽电极的磷浓度低。
发明的效果
根据本发明,针对在栅极沟槽电极的下方具有填埋电极的构造的半导体装置,能够减小栅极泄漏的滞后。
附图说明
图1是实施方式1涉及的半导体装置的俯视图。
图2是实施方式1涉及的半导体装置的剖视图。
图3是实施方式3涉及的半导体装置的剖视图。
图4是实施方式5涉及的半导体装置的剖视图。
图5是表示实施方式1~5涉及的半导体装置的制造方法的流程图。
具体实施方式
<实施方式1>
图1是实施方式1涉及的半导体装置100的俯视图。图2是该半导体装置100的剖视图,图2示出沿图1的A-A线的剖面。在本实施方式中,示出IGBT作为半导体装置100的元件构造。但是,本发明涉及的技术的应用不限于IGBT,能够广泛应用于MOSFET(Metal-Oxide-Semiconductor Field Effect Transistor)、RC-IGBT(Reverse-Conducting IGBT)等功率器件。
另外,半导体装置100的耐压等级、半导体衬底10所使用的半导体衬底的种类(例如,FZ(Floating Zone)衬底、MCZ(Magnetic field applied Czochralski)衬底、外延衬底等)没有特别限制。作为半导体衬底10的材料,除了硅(Si)以外,还可以使用碳化硅(SiC)、氮化镓(GaN)类材料、金刚石等宽带隙半导体。能够通过使用宽带隙半导体而实现高耐电压、低损耗及高耐热。
以下,关于半导体的导电型,将第1导电型设为n型、将第2导电型设为p型而进行说明,但也可以将第1导电型设为p型、将第2导电型设为n型。
半导体装置100是使用具有第1导电型(n型)的漂移层1的半导体衬底10而形成的。这里,将图1中的半导体衬底10的上表面定义为“第1主面”,将下表面定义为“第2主面”。
在半导体衬底10,在比漂移层1更靠第1主面侧处形成有与漂移层1相比杂质的峰值浓度高的第1导电型的载流子积蓄层2。另外,在比载流子积蓄层2更靠第1主面侧处形成有第2导电型(p型)的基极层15。并且,在比基极层15更靠第1主面侧处,第1导电型的发射极层13和与基极层15相比杂质的峰值浓度高的第2导电型的接触层14形成为各自与第1主面接触。
另外,在半导体衬底10的第1主面形成有贯通发射极层13、基极层15及载流子积蓄层2而到达漂移层1的沟槽。由此,沟槽与发射极层13、基极层15及载流子积蓄层2接触,其底部位于比漂移层1与载流子积蓄层2之间的边界更靠第2主面侧处。在各沟槽内形成有有源沟槽栅极11或哑沟槽栅极12。
有源沟槽栅极11具有在沟槽的内壁形成的栅极沟槽绝缘膜11b和在栅极沟槽绝缘膜11b之上形成的栅极沟槽电极11a及填埋电极11c。填埋电极11c配置于比栅极沟槽电极11a更靠第2主面侧处,在栅极沟槽电极11a与填埋电极11c之间存在栅极沟槽绝缘膜11b。即,栅极沟槽电极11a与填埋电极11c彼此绝缘。此外,栅极沟槽电极11a的底部位于比基极层15与载流子积蓄层2之间的边界更靠第2主面侧处。
哑沟槽栅极12由在沟槽的内壁形成的哑沟槽绝缘膜12b和在哑沟槽绝缘膜12b之上形成的哑沟槽电极12a构成。即,哑沟槽栅极12不具有填埋电极。此外,半导体装置100只要具有有源沟槽栅极11及哑沟槽栅极12中的至少有源沟槽栅极11即可,也可以省略哑沟槽栅极12。
在半导体衬底10的第1主面之上形成有将栅极沟槽电极11a及哑沟槽电极12a覆盖的层间绝缘膜4,在层间绝缘膜4之上形成有发射极(emitter)电极(electrode)6。发射极电极6通过在层间绝缘膜4形成的接触孔而与发射极层13及接触层14连接。另外,有源沟槽栅极11的填埋电极11c在未图示的区域与发射极电极6连接。由此,发射极电极6与有源沟槽栅极11电连接。
在本实施方式中,发射极电极6在其下表面设置有阻挡金属5。发射极电极6例如能够由Al或AlSi等金属构成。阻挡金属5例如能够由Ti或TiN、TiSi等构成。另外,发射极电极6也可以包含在接触孔内由W等构成的插塞。
另一方面,在半导体衬底10,在比漂移层1更靠第2主面侧处形成有与漂移层1相比杂质的峰值浓度高的缓冲层3。另外,在比缓冲层3更靠第2主面侧处,第2导电型的集电极层16形成为与第2主面接触。另外,在半导体衬底10的第2主面之上形成有与集电极层16连接的集电极(collector)电极(electrode)7。
这里,在实施方式1中,栅极沟槽电极11a及填埋电极11c由添加了磷的掺杂多晶硅形成。但是,填埋电极11c所包含的磷的浓度被设定为比栅极沟槽电极11a所包含的磷的浓度低。这样,通过降低填埋电极11c的磷浓度,从而能够使在填埋电极11c与栅极沟槽绝缘膜11b之间偏析的磷变少,能够减小正侧栅极泄漏的滞后。此外,哑沟槽电极12a的磷浓度也可以与填埋电极11c相同。
<实施方式2>
实施方式2涉及的半导体装置100的结构基本上与图1及图2相同。但是,在实施方式2中,对填埋电极11c使用不包含磷的材料。作为这样的填埋电极11c的材料,例如举出无掺杂多晶硅、金属、添加了氮的掺杂多晶硅等。与使用添加了磷的掺杂多晶硅作为填埋电极11c的材料的实施方式1相比,在使用无掺杂多晶硅的情况下,填埋电极11c的电阻变高,但在使用金属或添加了氮的掺杂多晶硅的情况下,能够降低填埋电极11c的电阻。
根据实施方式2,由于填埋电极11c不包含磷,因此,能够防止在填埋电极11c与栅极沟槽绝缘膜11b之间的界面处磷发生偏析,能够减小正侧栅极泄漏的滞后。此外,哑沟槽电极12a也可以由与填埋电极11c相同的材料构成。
<实施方式3>
图3是实施方式3涉及的半导体装置100的剖视图,与图2同样地,示出沿图1的A-A线的剖面。
在实施方式3中,填埋电极11c的表层部即与栅极沟槽绝缘膜11b接触的部分由无掺杂多晶硅形成,其内侧的部分由添加了磷的掺杂多晶硅形成。即,如图3所示,填埋电极11c由位于填埋电极11c的中心部且添加了磷的掺杂多晶硅层11c1、和位于掺杂多晶硅层11c1的外侧的无掺杂多晶硅层11c2构成。
根据实施方式3,由于填埋电极11c在表层部具有无掺杂多晶硅层11c2,因此,能够防止在填埋电极11c与栅极沟槽绝缘膜11b之间的界面处磷发生偏析,能够减小正侧栅极泄漏的滞后。另外,由于填埋电极11c的内部是掺杂多晶硅层11c1,因此防止了填埋电极11c的电阻变高。
此外,哑沟槽电极12a的结构也可以是与填埋电极11c相同的结构,即如下结构:与栅极沟槽绝缘膜11b接触的部分由无掺杂多晶硅形成,其内侧的部分由添加了磷的掺杂多晶硅形成。即,也可以如图3所示,哑沟槽电极12a由位于哑沟槽电极12a的中心部且添加了磷的掺杂多晶硅层12a1、和位于掺杂多晶硅层12a1的外侧的无掺杂多晶硅层12a2构成。
<实施方式4>
实施方式4涉及的半导体装置100的结构基本上与图1及图2相同。但是,在实施方式4中,对栅极沟槽电极11a使用不包含磷的材料(当然,与实施方式1不同,填埋电极11c所包含的磷的浓度也可以比栅极沟槽电极11a所包含的磷的浓度高)。作为这样的栅极沟槽电极11a的材料,例如举出无掺杂多晶硅、金属、添加了氮的掺杂多晶硅等。与使用添加了磷的掺杂多晶硅作为栅极沟槽电极11a的材料的实施方式1相比,在使用无掺杂多晶硅的情况下,栅极沟槽电极11a的电阻变高,但在使用金属或添加了氮的掺杂多晶硅的情况下,能够降低栅极沟槽电极11a的电阻。
根据实施方式4,由于栅极沟槽电极11a不包含磷,因此,能够防止在栅极沟槽电极11a与栅极沟槽绝缘膜11b之间的界面处磷发生偏析,能够减小负侧栅极泄漏的滞后。
<实施方式5>
图4是实施方式5涉及的半导体装置100的剖视图,与图2同样地,示出沿图1的A-A线的剖面。
在实施方式5中,栅极沟槽电极11a的表层部即与栅极沟槽绝缘膜11b接触的部分由无掺杂多晶硅形成,其内侧的部分由添加了磷的掺杂多晶硅形成。即,如图4所示,栅极沟槽电极11a由位于栅极沟槽电极11a的中心部且添加了磷的掺杂多晶硅层11a1、和位于掺杂多晶硅层11a1的外侧的无掺杂多晶硅层11a2构成。
根据实施方式5,由于栅极沟槽电极11a在表层部具有无掺杂多晶硅层11a2,因此,能够防止在栅极沟槽电极11a与栅极沟槽绝缘膜11b之间的界面处磷发生偏析,能够减小负侧栅极泄漏的滞后。另外,由于栅极沟槽电极11a的内部是掺杂多晶硅层11a1,防止了栅极沟槽电极11a的电阻变高。
<实施方式6>
在实施方式6中,对实施方式1~5涉及的半导体装置100的制造方法进行说明。图5是表示该制造方法的流程图。
首先,准备第1导电型的半导体衬底10(步骤S101),在IGBT等的元件形成区域的外侧的末端区域形成用于保持耐压的末端构造(例如,保护环、FLR(Field Limiting Ring)等)(步骤S102)。
接下来,通过在半导体衬底10的第1主面之上反复进行使用光刻技术而形成掩模的处理(掩模处理)和使用了该掩模的选择性离子注入,从而在半导体衬底10形成载流子积蓄层2及基极层15(步骤S103)。此时,在载流子积蓄层2之下残存的第1导电型的区域成为漂移层1。
接下来,通过对半导体衬底10的第1主面选择性地进行蚀刻,从而形成用于有源沟槽栅极11的沟槽(步骤S104)。然后,在该沟槽的内表面成膜出成为栅极沟槽绝缘膜11b的一部分的第1绝缘膜(步骤S105),在该沟槽内的第1绝缘膜之上形成填埋电极11c(步骤S106)。
接下来,通过以填埋电极11c为掩模的蚀刻,从而将沟槽内的第1绝缘膜中的在基极层15的侧壁形成的部分去除(步骤S107)。然后,通过氧化法或CVD(Chemical VaporDeposition:化学气相沉积)法或者它们的组合而在沟槽内的填埋电极11c之上及基极层15的侧壁成膜出成为栅极沟槽绝缘膜11b的一部分的第2绝缘膜(步骤S108)。然后,在沟槽内的第2绝缘膜之上形成栅极沟槽电极11a(步骤S109),由此,完成有源沟槽栅极11。
例如,在填埋电极11c是多晶硅的情况下,如果仅通过氧化法进行第2绝缘膜的形成,则在填埋电极11c之上形成的第2绝缘膜的厚度容易变得不均匀。另外,在填埋电极11c是金属的情况下,如果仅通过氧化法进行第2绝缘膜的形成,则无法在填埋电极11c之上形成氧化膜。因此,特别地,在填埋电极11c是多晶硅或金属的情况下,通过包含CVD法在内的方法而进行第2绝缘膜的形成,由此能够提高填埋电极11c与栅极沟槽电极11a之间的绝缘性。
此外,当在通过步骤S104形成的一部分的沟槽形成哑沟槽栅极12的情况下,能够在成膜出第1绝缘膜的步骤S105或成膜出第2绝缘膜的步骤S108中形成哑沟槽绝缘膜12b,在形成填埋电极11c的步骤S106或形成栅极沟槽电极11a的步骤S109中形成哑沟槽电极12a。由此,不增加制造工序数就能够导入哑沟槽栅极12。
在完成有源沟槽栅极11之后,通过反复进行掩模处理及离子注入而形成发射极层13及接触层14(步骤S110)。
然后,在半导体衬底10的第1主面之上形成层间绝缘膜4(步骤S111)。然后,当在层间绝缘膜4形成接触孔之后(步骤S112),在层间绝缘膜4之上形成发射极电极6(步骤S113)。
最后,在半导体衬底10的第2主面侧形成包含缓冲层3、集电极层16及集电极电极7在内的背面构造(步骤S114),由此完成半导体装置100。
用于将被离子注入的杂质激活的热处理可以在各自的离子注入工序之后进行,也可以在进行了多个离子注入工序之后集中进行。另外,各工序的顺序也可以适当调换。
此外,能够对各实施方式自由地进行组合,或对各实施方式适当地进行变形、省略。
标号的说明
100半导体装置,1漂移层,2载流子积蓄层,3缓冲层,4层间绝缘膜,5阻挡金属,6发射极电极,7集电极电极,10半导体衬底,11有源沟槽栅极,11a栅极沟槽电极,11b栅极沟槽绝缘膜,11c填埋电极,12哑沟槽栅极,12a哑沟槽电极,12b哑沟槽绝缘膜,13发射极层,14接触层,15基极层,16集电极层,11a1、11c1、12a1掺杂多晶硅层,11a2、11c2、12a2无掺杂多晶硅层。
Claims (14)
1.一种半导体装置,其具有:
半导体衬底,其具有第1主面、第2主面及第1导电型的漂移层;
所述第1导电型的载流子积蓄层,其在所述半导体衬底形成于比所述漂移层更靠所述第1主面侧处,与所述漂移层相比杂质的峰值浓度高;
第2导电型的基极层,其在所述半导体衬底形成于比所述载流子积蓄层更靠所述第1主面侧处;
所述第1导电型的发射极层及所述第2导电型的接触层,它们是在所述半导体衬底处与所述第1主面接触地形成的;以及
有源沟槽栅极,其形成于与所述发射极层、所述基极层及所述载流子积蓄层接触而到达所述漂移层的沟槽内,
所述有源沟槽栅极具有:
栅极沟槽绝缘膜,其形成于所述沟槽的内壁;以及
栅极沟槽电极及填埋电极,它们在所述沟槽内形成于所述栅极沟槽绝缘膜之上,彼此绝缘,该填埋电极配置于比所述栅极沟槽电极更靠所述第2主面侧处,
所述填埋电极的磷浓度比所述栅极沟槽电极的磷浓度低。
2.根据权利要求1所述的半导体装置,其中,
所述填埋电极不包含磷。
3.根据权利要求2所述的半导体装置,其中,
所述填埋电极由无掺杂多晶硅形成。
4.根据权利要求2所述的半导体装置,其中,
所述填埋电极由添加了氮的掺杂多晶硅形成。
5.根据权利要求2所述的半导体装置,其中,
所述填埋电极由金属形成。
6.一种半导体装置的制造方法,其是权利要求1至5中任一项所述的半导体装置的制造方法,其中,
形成所述有源沟槽栅极的工序包含以下工序:
工序(a),在所述半导体衬底的所述第1主面形成所述沟槽;
工序(b),在所述沟槽的内表面成膜出第1绝缘膜;
工序(c),在所述沟槽内的所述第1绝缘膜之上形成所述填埋电极;
工序(d),在所述工序(c)之后,将所述沟槽内的所述基极层的侧壁的所述第1绝缘膜去除;
工序(e),在所述工序(d)之后,通过包含CVD法在内的方法而在所述沟槽内的所述填埋电极之上及所述基极层的侧壁成膜出第2绝缘膜,其中,CVD是指化学气相沉积;以及
工序(f),在所述沟槽内的所述第2绝缘膜之上形成所述栅极沟槽电极。
7.一种半导体装置,其具有:
半导体衬底,其具有第1主面、第2主面及第1导电型的漂移层;
所述第1导电型的载流子积蓄层,其在所述半导体衬底形成于比所述漂移层更靠所述第1主面侧处,与所述漂移层相比杂质的峰值浓度高;
第2导电型的基极层,其在所述半导体衬底形成于比所述载流子积蓄层更靠所述第1主面侧处;
所述第1导电型的发射极层及所述第2导电型的接触层,它们是在所述半导体衬底处与所述第1主面接触地形成的;以及
有源沟槽栅极,其形成于与所述发射极层、所述基极层及所述载流子积蓄层接触而到达所述漂移层的沟槽内,
所述有源沟槽栅极具有:
栅极沟槽绝缘膜,其形成于所述沟槽的内壁;以及
栅极沟槽电极及填埋电极,它们在所述沟槽内形成于所述栅极沟槽绝缘膜之上,彼此绝缘,该填埋电极配置于比所述栅极沟槽电极更靠所述第2主面侧处,
所述填埋电极的表层部由无掺杂多晶硅形成,所述填埋电极的比所述表层部更靠内侧处由添加了磷的掺杂多晶硅形成。
8.一种半导体装置的制造方法,其是权利要求7所述的半导体装置的制造方法,
形成所述有源沟槽栅极的工序包含以下工序:
工序(a),在所述半导体衬底的所述第1主面形成所述沟槽;
工序(b),在所述沟槽的内表面成膜出第1绝缘膜;
工序(c),在所述沟槽内的所述第1绝缘膜之上形成所述填埋电极;
工序(d),在所述工序(c)之后,将所述沟槽内的所述基极层的侧壁的所述第1绝缘膜去除;
工序(e),在所述工序(d)之后,通过包含CVD法在内的方法而在所述沟槽内的所述填埋电极之上及所述基极层的侧壁成膜出第2绝缘膜,其中,CVD是指化学气相沉积;以及
工序(f),在所述沟槽内的所述第2绝缘膜之上形成所述栅极沟槽电极。
9.一种半导体装置,其具有:
半导体衬底,其具有第1主面、第2主面及第1导电型的漂移层;
所述第1导电型的载流子积蓄层,其在所述半导体衬底形成于比所述漂移层更靠所述第1主面侧处,与所述漂移层相比杂质的峰值浓度高;
第2导电型的基极层,其在所述半导体衬底形成于比所述载流子积蓄层更靠所述第1主面侧处;
所述第1导电型的发射极层及所述第2导电型的接触层,它们是在所述半导体衬底处与所述第1主面接触地形成的;以及
有源沟槽栅极,其形成于与所述发射极层、所述基极层及所述载流子积蓄层接触而到达所述漂移层的沟槽内,
所述有源沟槽栅极具有:
栅极沟槽绝缘膜,其形成于所述沟槽的内壁;以及
栅极沟槽电极及填埋电极,它们在所述沟槽内形成于所述栅极沟槽绝缘膜之上,彼此绝缘,该填埋电极配置于比所述栅极沟槽电极更靠所述第2主面侧处,
所述栅极沟槽电极的至少表层部不包含磷。
10.根据权利要求9所述的半导体装置,其中,
所述栅极沟槽电极由无掺杂多晶硅形成。
11.根据权利要求9所述的半导体装置,其中,
所述栅极沟槽电极由添加了氮的掺杂多晶硅形成。
12.根据权利要求9所述的半导体装置,其中,
所述栅极沟槽电极由金属形成。
13.根据权利要求9所述的半导体装置,其中,
所述栅极沟槽电极的所述表层部由无掺杂多晶硅形成,所述栅极沟槽电极的比所述表层部更靠内侧处由添加了磷的掺杂多晶硅形成。
14.一种半导体装置的制造方法,其是权利要求9至13中任一项所述的半导体装置的制造方法,
形成所述有源沟槽栅极的工序包含以下工序:
工序(a),在所述半导体衬底的所述第1主面形成所述沟槽;
工序(b),在所述沟槽的内表面成膜出第1绝缘膜;
工序(c),在所述沟槽内的所述第1绝缘膜之上形成所述填埋电极;
工序(d),在所述工序(c)之后,将所述沟槽内的所述基极层的侧壁的所述第1绝缘膜去除;
工序(e),在所述工序(d)之后,通过包含CVD法在内的方法而在所述沟槽内的所述填埋电极之上及所述基极层的侧壁成膜出第2绝缘膜,其中,CVD是指化学气相沉积;以及
工序(f),在所述沟槽内的所述第2绝缘膜之上形成所述栅极沟槽电极。
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