CN115064549A - Manufacturing method of semiconductor device and semiconductor device - Google Patents
Manufacturing method of semiconductor device and semiconductor device Download PDFInfo
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- CN115064549A CN115064549A CN202210642620.XA CN202210642620A CN115064549A CN 115064549 A CN115064549 A CN 115064549A CN 202210642620 A CN202210642620 A CN 202210642620A CN 115064549 A CN115064549 A CN 115064549A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 60
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 13
- 239000000758 substrate Substances 0.000 claims abstract description 71
- 238000000034 method Methods 0.000 claims abstract description 70
- 229910052751 metal Inorganic materials 0.000 claims description 35
- 239000002184 metal Substances 0.000 claims description 35
- 230000000149 penetrating effect Effects 0.000 claims description 19
- 238000003860 storage Methods 0.000 claims description 8
- 239000000463 material Substances 0.000 abstract description 35
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 9
- 229910052710 silicon Inorganic materials 0.000 description 8
- 239000010703 silicon Substances 0.000 description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 8
- 230000000903 blocking effect Effects 0.000 description 6
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 6
- 229910052721 tungsten Inorganic materials 0.000 description 6
- 239000010937 tungsten Substances 0.000 description 6
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 4
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 239000012212 insulator Substances 0.000 description 3
- 150000002739 metals Chemical class 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 2
- 238000010893 electron trap Methods 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 238000002248 hydride vapour-phase epitaxy Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 230000005641 tunneling Effects 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000005336 cracking Methods 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
- H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
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Abstract
The application provides a manufacturing method of a semiconductor device and the semiconductor device. The method comprises the following steps: forming a base structure, wherein the base structure comprises a substrate and a stacking structure, the stacking structure comprises a body structure, a gate line slit and a second virtual channel hole, the body structure comprises a first sacrificial layer and an insulating medium layer which are alternately arranged, the gate line slit comprises a first sub-gate line slit and a second sub-gate line slit, the first sub-gate line slit and the second sub-gate line slit are arranged at intervals, and the second virtual channel hole is located between the first sub-gate line slit and the second sub-gate line slit; forming a second sacrificial layer in the gate line slit; at least the first sacrificial layer and the second sacrificial layer are removed. In the method, the first sub-gate line slit and the second sub-gate line slit are separated by the second virtual channel hole, so that the material of the sacrificial layer at other positions is not increased, and the method for removing the sacrificial layer is simplified.
Description
Technical Field
The present disclosure relates to the field of semiconductors, and in particular, to a method for manufacturing a semiconductor device, a three-dimensional memory, and a storage system.
Background
With the continuous development of 3D NAND technology, the number of layers of the three-dimensional memory is increasing, and a high-order stacked structure from 24 layers, 32 layers and 64 layers to over 100 layers can greatly increase the storage density and reduce the price of a unit memory cell. However, as the number of layers is gradually increased, the process of removing the sacrificial layer in the stacked structure is relatively complicated. Therefore, a method for simplifying the removal of the sacrificial layer is needed.
Disclosure of Invention
The present application provides a method for fabricating a semiconductor device, a three-dimensional memory and a memory system, so as to solve the problem of lacking a method for simplifying the removal of a sacrificial layer in the technical solutions known to the inventors.
According to an aspect of the embodiments of the present invention, there is provided a method for manufacturing a semiconductor device, including: forming a base structure comprising a substrate structure and a stack structure, wherein the stack structure is located on the substrate structure, the stack structure includes a body structure, a plurality of channel holes in the body structure, a plurality of first virtual channel holes, a gate line slit, and a second virtual channel hole, one end of the body structure is provided with a step region, a plurality of first virtual channel holes are positioned in the step region, the body structure comprises first sacrificial layers and insulating medium layers which are alternately arranged, the gate line slits penetrate through the stacked structure and are positioned in part of the substrate structure, the gate line slits include a first sub-gate line slit and a second sub-gate line slit, the first sub-gate line slit and the second sub-gate line slit are disposed at an interval, and the second dummy channel hole is located between the first sub-gate line slit and the second sub-gate line slit; forming a second sacrificial layer in the gate line slit; removing at least the first sacrificial layer and the second sacrificial layer.
Optionally, forming a base structure comprising: providing the substrate structure, and forming the body structure on the surface of the substrate structure; forming a plurality of channel holes, a plurality of first virtual channel holes and a second virtual channel hole penetrating through the body structure, wherein the second virtual channel hole is located in a predetermined region, the predetermined region is a region which is located in a core region and a step region of the stacked structure at the same time and includes a boundary of the core region and the step region, and the core region is the stacked structure except for the step region; forming the gate line slits through the stacked structure and in a portion of the substrate structure.
Optionally, forming the second virtual channel hole through the body structure comprises at least one of: forming a second virtual channel hole of a first type penetrating through the body structure, wherein a filling structure of the second virtual channel hole of the first type is the same as that of the first virtual channel hole; and forming a second type of the second virtual channel hole penetrating through the body structure, wherein the filling structure of the second type of the second virtual channel hole is different from the filling structure of the first virtual channel hole.
Optionally, before forming the second sacrificial layer in the gate line slit, the method further comprises: forming a through hole penetrating through a part of the step region; and forming a first filling structure in the through hole to form a contact hole.
Optionally, forming a second sacrificial layer in the gate line slit includes: performing predetermined treatment on the surface of the gate line slit to form an insulating layer on the exposed surface of the substrate structure; and filling a second sacrificial layer in the gate line slit.
Optionally, after forming a second sacrificial layer in the gate line slit, before removing the first sacrificial layer and the second sacrificial layer, the method further comprises: and forming an insulating oxide layer on the exposed surface of the substrate structure after the second sacrificial layer is formed.
Optionally, removing at least the first sacrificial layer and the second sacrificial layer comprises: and removing the insulating oxide layer, the second sacrificial layer and the first sacrificial layer in sequence.
Optionally, removing at least the first sacrificial layer and the second sacrificial layer comprises: sequentially removing the insulating oxide layer, the second sacrificial layer and the first sacrificial layer in a core region, wherein the core region is the stacked structure except the step region; and sequentially removing the insulating oxide layer, the second sacrificial layer and the first sacrificial layer in the step area.
Optionally, after removing the first sacrificial layer and the second sacrificial layer, the method further comprises: filling metal on the exposed surface of the stacked structure with the first sacrificial layer removed to obtain a replaced stacked structure, wherein the replaced stacked structure comprises metal layers and insulating medium layers which are alternately arranged; removing the metal in the gate line slit; and forming a second filling structure in the gate line slit.
According to another aspect of the embodiments of the present invention, there is also provided a semiconductor device including: a base structure comprising a substrate structure and a stack structure, wherein the stack structure is located on the substrate structure, the stack structure includes a body structure, a plurality of channel holes in the body structure, a plurality of first virtual channel holes, a gate line slit, and a second virtual channel hole, one end of the body structure is provided with a step region, a plurality of first virtual channel holes are positioned in the step region, the body structure comprises metal layers and insulating medium layers which are alternately arranged, the gate line slits penetrate through the stacked structure and are positioned in part of the substrate structure, the gate line slits include a first sub-gate line slit and a second sub-gate line slit, the first sub-gate line slit and the second sub-gate line slit are disposed at intervals, and the second dummy channel hole is located between the first sub-gate line slit and the second sub-gate line slit.
Optionally, the semiconductor device further comprises: and a contact hole penetrating through a portion of the step region, the contact hole including a first filling structure.
According to another aspect of the embodiments of the present invention, there is also provided a three-dimensional memory including a semiconductor device obtained by any one of the methods or the semiconductor device.
According to yet another aspect of the embodiments of the present invention, there is also provided a storage system including a storage controller and the three-dimensional memory, the three-dimensional memory being configured to store data, the storage controller being coupled to the three-dimensional memory and configured to control the three-dimensional memory.
In an embodiment of the invention, first, a base structure is formed, the base structure includes a substrate structure and a stacked structure, the stacked structure includes a body structure, a gate line slit and a second dummy channel hole, the body structure includes first sacrificial layers and insulating dielectric layers which are alternately arranged, the gate line slit includes a first sub-gate line slit and a second sub-gate line slit, the first sub-gate line slit and the second sub-gate line slit are arranged at intervals, and the second dummy channel hole is located between the first sub-gate line slit and the second sub-gate line slit, then the second sacrificial layer is formed in the gate line slit, and finally, at least the first sacrificial layer and the second sacrificial layer are removed. In the method, a first sub-gate line slit and a second sub-gate line slit are arranged at intervals, a second virtual channel hole is positioned between the first sub-gate line slit and the second sub-gate line slit, i.e., the second dummy channel hole, separates the first sub-gate line slit and the second sub-gate line slit, so that when the second sacrificial layer in the gate line slit is removed, the second sacrificial layer in the first sub-gate line slit cannot flow to other positions from the slit due to the blockage of the second virtual channel hole, the second sacrificial layer in the second sub-gate line slit cannot flow to other positions from the slit due to the blockage of the second virtual channel hole, because the second sacrificial layer does not flow to other positions, the material of the sacrificial layer at other positions can not be increased, redundant materials do not need to be repeatedly removed when the sacrificial layer is subsequently removed, and therefore the method for removing the sacrificial layer is simplified.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this application, illustrate embodiments of the application and, together with the description, serve to explain the application and are not intended to limit the application. In the drawings:
fig. 1 shows a top view of a semiconductor device according to an embodiment of the present application;
fig. 2 illustrates a cross-sectional view of a semiconductor device according to an embodiment of the present application;
FIG. 3 shows a flow chart of a method of fabricating a semiconductor device according to an embodiment of the present application;
fig. 4 shows a top view of a semiconductor device according to an embodiment of the present application;
fig. 5 to 19 respectively show schematic structural diagrams obtained after respective process steps according to a method for manufacturing a semiconductor device of the present application.
Wherein the figures include the following reference numerals:
200. a gate line slit; 201. cracking; 202. a channel hole; 203. a first virtual channel hole; 204. a second virtual channel hole; 205. a substrate structure; 206. a stacked structure; 207. a step area; 208. a first sacrificial layer; 209. an insulating dielectric layer; 210. a substrate; 211. a first insulating oxide layer; 212. a first silicon layer; 213. a second insulating oxide layer; 214. a second silicon layer; 215. a second sacrificial layer; 216. an insulating layer; 217. an insulating oxide layer; 218. a metal layer; 219. a contact hole; 220. a first sub-gate line slit; 221. a second sub-gate line slit.
Detailed Description
It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict. The present application will be described in detail below with reference to the embodiments with reference to the attached drawings.
In order to make the technical solutions better understood by those skilled in the art, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only partial embodiments of the present application, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
It should be noted that the terms "first," "second," and the like in the description and claims of this application and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It should be understood that the data so used may be interchanged under appropriate circumstances such that embodiments of the application described herein may be used. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present. Also, in the specification and claims, when an element is described as being "connected" to another element, the element may be "directly connected" to the other element or "connected" to the other element through a third element.
At present, the process of removing the sacrificial layer is relatively complicated, and the inventors have studied and found that, as the number of layers of the 3D NAND increases, as shown in fig. 1 and 2, the gate line slit 200 is formed with a bow, so that a crack 201 may occur in the sacrificial layer in the gate line slit 200 when the gate line slit 200 is filled with the sacrificial layer. In order to completely remove the sacrificial layer, the sacrificial layer generally needs to be removed twice, but when the sacrificial layer is removed, the material of the sacrificial layer flows from the crack to other places due to the existence of the crack 201, and therefore, the subsequent process of removing the sacrificial layer is relatively complicated.
In order to solve the problem that the process of removing the sacrificial layer is complex, in an exemplary embodiment of the present disclosure, a method for manufacturing a semiconductor device, a three-dimensional memory and a memory system are provided.
According to an embodiment of the present application, a method of fabricating a semiconductor device is provided.
Fig. 3 is a flow chart of a method of fabricating a semiconductor device according to an embodiment of the present application. As shown in fig. 3, the method comprises the steps of:
step S101, as shown in fig. 4 and fig. 5 (it should be noted that fig. 5 and the following figures are cross-sectional views along the width direction of the gate line slit 200 and perpendicular to the gate line slit 200 and the channel hole 202 or the first virtual channel hole 203, so that the channel hole 202 and the first virtual channel hole 203 cannot appear simultaneously in the figures, and for convenience of illustration, the channel hole 202 and the first virtual channel hole 203 are shown in the same picture), forming a base structure, the base structure including a substrate structure 205 and a stacked structure 206, wherein the stacked structure 206 is located on the substrate structure 205, the stacked structure 206 includes a body structure, a plurality of channel holes 202 located in the body structure, a plurality of first virtual channel holes 203, a gate line slit 200 and a second virtual channel hole 204, one end of the body structure has a step region 207, and a plurality of the first virtual channel holes 203 are located in the step region 207, the body structure comprises first sacrificial layers 208 and insulating medium layers 209 which are alternately arranged, the gate line slits 200 penetrate through the stacked structure 206 and are positioned in a part of the substrate structure 205, the gate line slits 200 comprise first sub-gate line slits 220 and second sub-gate line slits 221, the first sub-gate line slits 220 and the second sub-gate line slits 221 are arranged at intervals, and the second dummy channel holes 204 are positioned between the first sub-gate line slits 220 and the second sub-gate line slits 221;
step S102, as shown in fig. 6, forming a second sacrificial layer 215 in the gate line slit 200;
in step S103, at least the first sacrificial layer 208 and the second sacrificial layer 215 are removed, thereby forming the structure shown in fig. 7.
In the method, firstly, a base structure is formed, the base structure comprises a substrate structure and a stacked structure, the stacked structure comprises a body structure, a gate line slit and a second virtual channel hole, the body structure comprises first sacrificial layers and insulating medium layers which are alternately arranged, the gate line slit comprises a first sub-gate line slit and a second sub-gate line slit, the first sub-gate line slit and the second sub-gate line slit are arranged at intervals, the second virtual channel hole is located between the first sub-gate line slit and the second sub-gate line slit, then the second sacrificial layer is formed in the gate line slit, and finally, at least the first sacrificial layer and the second sacrificial layer are removed. In the method, a first sub-gate line slit and a second sub-gate line slit are arranged at intervals, a second virtual channel hole is positioned between the first sub-gate line slit and the second sub-gate line slit, i.e., the second dummy channel hole, separates the first sub-gate line slit and the second sub-gate line slit, so that when the second sacrificial layer in the gate line slit is removed, the second sacrificial layer in the first sub-gate line slit cannot flow to other positions from the slit due to the blockage of the second virtual channel hole, the second sacrificial layer in the second sub-gate line slit cannot flow to other positions from the slit due to the blockage of the second virtual channel hole, because the second sacrificial layer does not flow to other positions, the material of the sacrificial layer at other positions can not be increased, redundant materials do not need to be repeatedly removed when the sacrificial layer is subsequently removed, and therefore the method for removing the sacrificial layer is simplified.
The second virtual channel hole may be rectangular or circular, and may be set by those skilled in the art according to actual situations. The length and width of the second virtual channel hole is in the range of 2-5 angstroms, and in this range, the material flow of the sacrificial layer can be blocked, and other parts in the semiconductor structure can not be affected. The filling structure in the second virtual channel hole may be the same as the filling structure in the first virtual channel hole, or may be different from the filling structure in the first virtual channel hole.
Specifically, as shown in fig. 4, there may be a plurality of gate line slits 200, and each gate line slit 200 includes sub-gate line slits arranged at intervals. For example, there are 3 gate line slits, where two gate line slits include a first sub-gate line slit, a second virtual channel hole, and a second sub-gate line slit, one gate line slit includes a plurality of sub-gate line slits arranged at intervals, two upper and lower gate line slits provided with the second virtual channel hole are gate line slits between different blocks, and a gate line slit in the two gate line slits is a gate line slit inside a block. When the gate line slits inside the block are set as the spaced sub-gate line slits, it is not necessary to provide the second virtual channel hole, which is also necessary if the gate line slits inside the block are the same shape as the gate line slits between different blocks.
The material of the first sacrificial layer may be silicon nitride, and the material of the second sacrificial layer may be polysilicon, but the material of the first sacrificial layer and the material of the second sacrificial layer are not limited thereto, and may be other materials, such as silicon oxide and monocrystalline silicon, and those skilled in the art may select a suitable material according to actual circumstances. The monocrystalline silicon has a compact structure, and other structures in the semiconductor can be prevented from being damaged. Although the polysilicon structure is less compact than the monocrystalline silicon structure, the cost of the polysilicon is lower than that of the monocrystalline silicon.
In a specific embodiment, the channel hole includes a charge blocking layer, an electron trapping layer, a tunneling layer, and a channel layer, which are sequentially stacked along a sidewall direction, and the material of each structural layer may also be any feasible material, for example, the material of the charge blocking layer may be silicon dioxide, the material of the electron trapping layer may be silicon nitride, the material of the tunneling layer may be silicon dioxide, and the material of the channel layer may be polysilicon.
These structural layers described above may be formed via one or more of Molecular Beam Epitaxy (MBE), Metal Organic Chemical Vapor Deposition (MOCVD), Metal Organic Vapor Phase Epitaxy (MOVPE), Hydride Vapor Phase Epitaxy (HVPE), and/or other well-known crystal growth processes.
In a specific application, the first dummy trench hole may include an oxide layer, and in an actual application, the first dummy trench hole may also include other filling structures.
In one embodiment of the present application, as shown in fig. 4 and 5, a base structure is formed comprising: providing the substrate structure 205, and forming the body structure on the surface of the substrate structure 205; forming a plurality of the channel holes 202, a plurality of the first dummy channel holes 203, and a plurality of the second dummy channel holes 204 penetrating the body structure, the second dummy channel holes 204 being located in a predetermined region, the predetermined region being a region of the stacked structure 206 located in both a core region and the step region 207 and including a boundary of the core region and the step region 207, the core region being the stacked structure 206 except for the step region 207; the gate line slit 200 is formed through the stacked structure 206 and in a portion of the substrate structure 205. In this embodiment, before the gate line slit is formed, the second virtual channel hole is formed, and the second virtual channel hole and the first virtual channel hole are formed at the same time, so that an additional step is not required to form the second virtual channel hole, the forming process of the second virtual channel hole is simpler, and the method for removing the sacrificial layer is further simplified.
In a specific embodiment of the present application, the second dummy trench hole may be formed after the first dummy trench hole is formed: etching the predetermined area to form a groove; and filling a structure in the groove to form the second virtual channel hole.
In a specific application, as shown in fig. 5, the substrate structure 205 includes a substrate 210, a first insulating oxide layer 211, a first silicon layer 212, a second insulating oxide layer 213 and a second silicon layer 214, which are stacked in sequence. With the substrate having the above structure, the performance of the channel hole can be improved.
It should be noted that, each step in the above-mentioned embodiment of forming the substrate can be implemented in a feasible manner in the prior art. The substrate may be selected according to actual requirements of the device, and may include a Silicon substrate, a germanium substrate, a Silicon germanium (sige) substrate, an SOI (Silicon On Insulator) substrate, or a GOI (germanium On Insulator) substrate. In other embodiments, the substrate may also be a substrate including other element semiconductors or compound semiconductors, such as GaAs, InP, SiC, or the like, may also be a stacked structure, such as Si/SiGe, or the like, and may also be another epitaxial structure, such as SGOI (silicon germanium on insulator) or the like. Of course, it may also be other substrates feasible in the art.
In another embodiment of the present application, the forming of the second virtual channel hole penetrating through the body structure includes at least one of: forming a second dummy channel hole of a first type penetrating the body structure, a filling structure of the second dummy channel hole of the first type being the same as a filling structure of the first dummy channel hole; forming a second type of the second virtual channel hole penetrating the body structure, wherein a filling structure of the second type of the second virtual channel hole is different from a filling structure of the first virtual channel hole. If the filling structure in the second virtual channel hole is the same as the filling structure in the first virtual channel hole, a second virtual channel hole may be formed at the same time as the first virtual channel hole, and if the filling structure in the second virtual channel hole is different from the filling structure in the first virtual channel hole, a separate step is required to form the second virtual channel hole.
For example, the filling structures in the first and second virtual channel holes may be both silicon oxide layers, or the filling structure in the first virtual channel hole may be a silicon oxide layer and the filling structure in the second virtual channel hole may be a silicon nitride layer.
In order to ensure better electrical performance of the semiconductor device, in another embodiment of the present application, before forming the second sacrificial layer in the gate line slit, the method further includes: forming a through hole penetrating through part of the step region; and forming a first filling structure in the through hole to form a contact hole. In an actual application process, in order to ensure that the contact holes can stop on the surface of the corresponding sacrificial layer or in the sacrificial layer, in the body structure, the thickness of each insulating medium layer is smaller than that of each sacrificial layer.
The first filling structure is a metal layer, the metal may be tungsten, in practical applications, the metal may also be other metals, and a person skilled in the art may select a suitable metal according to practical situations.
Specifically, the through hole may be completely filled with metal tungsten to form a metal tungsten layer, which may improve the conductivity of the contact hole.
In still another embodiment of the present application, forming the second sacrificial layer in the gate line slit includes: performing a predetermined process on the surface of the gate line slit 200 to form an insulating layer 216 on the exposed surface of the substrate structure 205, thereby forming the structure shown in fig. 8; as shown in fig. 6, the gate line slit 200 is filled with a second sacrificial layer 215. In this embodiment, the insulating layer is formed on the surface of the exposed substrate to isolate the substrate from the second sacrificial layer, so that the substrate is not adversely affected when the second sacrificial layer is filled, thereby further improving the performance of the semiconductor device.
The predetermined treatment may be an oxidation treatment, but in practical applications, the predetermined treatment is not limited to the oxidation treatment, and may be other processes, such as nitridation and the like.
In one embodiment, as shown in fig. 9, during the process of filling the gate line slits with the second sacrificial layer 215, the second sacrificial layer 215 is also formed on the surface of the stacked structure 206 away from the substrate structure 205, so that the second sacrificial layer 215 on the surface of the stacked structure 206 away from the substrate structure 205 is removed.
In another embodiment of the present application, as shown in fig. 10, after forming the second sacrificial layer in the gate line slit, before removing the first sacrificial layer and the second sacrificial layer, the method further includes: an insulating oxide layer 217 is formed on the exposed surface of the base structure after the second sacrificial layer 215 is formed. In this embodiment, before the sacrificial layer is removed, an insulating oxide layer is formed on the exposed surface of the substrate structure, and the insulating oxide layer may also be used to block the sacrificial layer from flowing to other places, so as to further ensure that the material of the sacrificial layer does not flow to other places, thereby further simplifying the method for removing the sacrificial layer.
In another embodiment of the present application, the removing at least the first sacrificial layer and the second sacrificial layer includes: and removing the insulating oxide layer, the second sacrificial layer and the first sacrificial layer in sequence. In the above method, the insulating oxide layer is formed on the exposed surface of the base structure, so that the insulating oxide layer is removed first, and then the second sacrificial layer in the gate line slit is removed, so as to remove the first sacrificial layer in the stacked structure.
In another embodiment of the present application, the removing at least the first sacrificial layer and the second sacrificial layer includes: as shown in fig. 11, the structure before removal is formed by sequentially removing the insulating oxide layer 217, the second sacrificial layer 215, and the first sacrificial layer 208 in the core region, which is the stacked structure 206 except for the step region, to form the structure shown in fig. 12; as shown in fig. 13, the insulating oxide layer 217, the second sacrificial layer 215, and the first sacrificial layer 208 in the step region are removed in this order to form the structure shown in fig. 14. In this embodiment, the second sacrificial layer in the gate line slit is removed twice, the sacrificial layer in the core region is removed first, and then the sacrificial layer in the step region is removed.
In practical applications, the insulating oxide layer, the second sacrificial layer and the first sacrificial layer in the step region may be removed first, and then the insulating oxide layer, the second sacrificial layer and the first sacrificial layer in the core region may be removed.
In a specific embodiment of the present invention, as shown in fig. 14, in order to further improve the performance of the semiconductor device, when the sacrificial layer in the step region is removed, the insulating oxide layer, the second sacrificial layer and a portion of the first sacrificial layer are sequentially removed.
In another embodiment of the present application, after removing the first sacrificial layer and the second sacrificial layer, the method further includes: filling metal on the exposed surface of the stacked structure 206 with the first sacrificial layer 208 removed to obtain a replaced stacked structure 206, wherein the replaced stacked structure 206 includes metal layers 218 and insulating dielectric layers 209 alternately arranged; removing the metal in the gate line slit 200; a second filling structure is formed in the gate line slit 200, so as to form the structure shown in fig. 15. In order to obtain the word line, in this embodiment, after removing the first sacrificial layer and the second sacrificial layer, the exposed surface of the stacked structure is filled with metal to obtain the word line, and then the metal in the gate line slit is removed, and a second filling structure is formed in the gate line slit to obtain the gate line.
The second filling structure may be an insulating oxide layer and a silicon layer, i.e., an insulating oxide layer is formed on the surface of the gate line slit, and then silicon is deposited into the gate line slit having the insulating oxide layer. Of course, in practical applications, the second filling structure is not limited to the above structure, and may have other structures.
Similarly, the metal may be tungsten, and may be other metals, not limited to tungsten.
According to an embodiment of the present application, there is also provided a semiconductor device, including a base structure, as shown in fig. 4 and 15, the base structure including a substrate structure 205 and a stacked structure 206, wherein the stacked structure 206 is located on the substrate structure 205, the stacked structure 206 includes a body structure, a plurality of channel holes 202 located in the body structure, a plurality of first dummy channel holes 203, a gate line slit 200 and a second dummy channel hole 204, one end of the body structure has a step region, the plurality of first dummy channel holes 203 are located in the step region, the body structure includes metal layers 218 and insulating dielectric layers 209 alternately arranged, the gate line slit 200 penetrates through the stacked structure 206 and is located in a part of the substrate structure 205, the gate line slit 200 includes a first sub-gate line slit 220 and a second sub-gate line slit 221, the first sub gate line slit 220 and the second sub gate line slit 221 are spaced apart from each other, and the second dummy channel hole 204 is located between the first sub gate line slit 220 and the second sub gate line slit 221.
The semiconductor device comprises a base structure, wherein the base structure comprises a substrate and a stacking structure, the stacking structure comprises a body structure, a gate line slit and a second virtual channel hole, the body structure comprises a first sacrificial layer and an insulating medium layer which are alternately arranged, the gate line slit comprises a first sub-gate line slit and a second sub-gate line slit, the first sub-gate line slit and the second sub-gate line slit are arranged at intervals, and the second virtual channel hole is located between the first sub-gate line slit and the second sub-gate line slit. In the semiconductor device, a first sub-gate line slit and a second sub-gate line slit are disposed at an interval, a second dummy channel hole is located between the first sub-gate line slit and the second sub-gate line slit, i.e., the second dummy channel hole, separates the first sub-gate line slit and the second sub-gate line slit, so that when the second sacrificial layer in the gate line slit is removed, the second sacrificial layer in the first sub-gate line slit cannot flow to other positions from the slit due to the blockage of the second virtual channel hole, the second sacrificial layer in the second sub-gate line slit cannot flow to other positions from the slit due to the blockage of the second virtual channel hole, because the second sacrificial layer does not flow to other positions, the material of the sacrificial layer at other positions can not be increased, therefore, redundant materials do not need to be repeatedly removed when the sacrificial layer is subsequently removed, and the method for removing the sacrificial layer is simplified.
In order to ensure better electrical performance of the semiconductor device, in an embodiment of the present application, as shown in fig. 15, the semiconductor device further includes: and a contact hole 219 penetrating a portion of the step region, the contact hole 219 including a first filling structure.
The first filling structure is a metal layer, the metal may be tungsten, in practical applications, the metal may also be other metals, and a person skilled in the art may select a suitable metal according to practical situations.
According to an embodiment of the present application, there is also provided a three-dimensional memory including a semiconductor device obtained by any one of the above-described methods or the above-described semiconductor device.
The three-dimensional memory device includes the semiconductor device, the semiconductor device structure is as shown in fig. 4 and 15, and includes a base structure, the base structure includes a substrate structure 205 and a stacked structure 206, wherein the stacked structure 206 is located on the substrate structure 205, the stacked structure 206 includes a body structure, a plurality of channel holes 202 located in the body structure, a plurality of first dummy channel holes 203, a gate line slit 200 and a second dummy channel hole 204, one end of the body structure has a step region, the plurality of first dummy channel holes 203 are located in the step region, the body structure includes metal layers 218 and insulating medium layers 209 alternately arranged, the gate line slit 200 penetrates through the stacked structure 206 and is located in a part of the substrate structure 205, the gate line slit 200 includes a first sub-gate line slit 220 and a second sub-gate line slit 221, the first sub gate line slit 220 and the second sub gate line slit 221 are spaced apart from each other, and the second dummy channel hole 204 is located between the first sub gate line slit 220 and the second sub gate line slit 221. Because redundant materials do not need to be removed repeatedly when the sacrificial layer of the semiconductor device is removed, the removal method is simple, and meanwhile, the sacrificial layer can be removed more cleanly, so that the electrical performance of the semiconductor device is better, and the electrical performance of the three-dimensional memory is better.
The three-dimensional memory comprises the semiconductor device obtained by any one of the above methods or the above semiconductor device, wherein the first sub-gate line slit and the second sub-gate line slit are arranged at intervals, and the second virtual channel hole is arranged between the first sub-gate line slit and the second sub-gate line slit, namely the second virtual channel hole separates the first sub-gate line slit from the second sub-gate line slit, so that when the second sacrificial layer in the gate line slit is removed, the second sacrificial layer in the first sub-gate line slit cannot flow to other positions from the slit due to the blockage of the second virtual channel hole, and the second sacrificial layer in the second sub-gate line slit cannot flow to other positions from the slit due to the blockage of the second virtual channel hole, and the material of the sacrificial layer at other positions cannot increase because the second sacrificial layer does not flow to other positions, redundant materials do not need to be repeatedly removed when the sacrificial layer is subsequently removed, and therefore the method for removing the sacrificial layer is simplified.
There is also provided, in accordance with an embodiment of the present application, a memory system, including a memory controller and the three-dimensional memory described above, the three-dimensional memory configured to store data, the memory controller coupled to the three-dimensional memory and configured to control the three-dimensional memory.
The above memory system, including a memory controller and the above three-dimensional memory, the above three-dimensional memory being configured to store data, the above memory controller being coupled to the above three-dimensional memory and being configured to control the above three-dimensional memory, a semiconductor device obtained by any of the above methods or the above semiconductor device, the above method, wherein the first sub-gate line slit and the second sub-gate line slit are disposed at an interval, and the second virtual channel hole is located between the first sub-gate line slit and the second sub-gate line slit, that is, the second virtual channel hole separates the first sub-gate line slit and the second sub-gate line slit, so that when the second sacrificial layer in the gate line slit is removed, the second sacrificial layer in the first sub-gate line slit does not flow from the slit to other positions due to the blocking of the second virtual channel hole, the second sacrificial layer in the second sub-gate line slit cannot flow to other positions from the crack due to the blocking of the second virtual channel hole, and the material of the sacrificial layer at other positions cannot be increased due to the fact that the second sacrificial layer does not flow to other positions, so that redundant material does not need to be removed repeatedly when the sacrificial layer is removed subsequently, and the method for removing the sacrificial layer is simplified.
In order to make the technical solutions of the present application more clearly understood, the following description is given with reference to specific embodiments:
examples
The manufacturing method of the semiconductor device comprises the following steps:
providing the substrate structure 205, and forming the body structure on the surface of the substrate structure 205; forming a plurality of the channel holes 202, a plurality of the first dummy channel holes 203, and a plurality of the second dummy channel holes 204 penetrating the body structure, wherein the second dummy channel holes 204 are located in a predetermined region, the predetermined region is a region of the stacked structure 206 that is located in both a core region and the step region 207 and includes a boundary between the core region and the step region 207, and the core region is the stacked structure 206 except for the step region 207; forming the gate line slit 200 penetrating the stacked structure 206 and being located in a portion of the substrate structure 205, and forming a semiconductor structure as shown in fig. 4 and 5; forming a through hole penetrating through part of the step region; forming a first filling structure in the through hole to form a contact hole 219 as shown in fig. 15;
as shown in fig. 8, the surface of the gate line slit 200 is oxidized to form an insulating layer 216 on the exposed surface of the substrate structure 205;
as shown in fig. 9, a second sacrificial layer 215 is filled in the gate line slit 200, and when the gate line slit 200 is filled, the second sacrificial layer 215 is also formed on the surface of the stacked structure 206 away from the substrate structure 205;
removing the second sacrificial layer 215 on the surface of the stacked structure 206 away from the substrate structure 205 to form the structure shown in fig. 6;
as shown in fig. 10, an insulating oxide layer 217 is formed on the exposed surface of the base structure after the second sacrificial layer 215 is formed, the semiconductor structure of the core region is shown in fig. 11, and the semiconductor structure of the step region is shown in fig. 13;
removing the insulating oxide layer 217 from the core region to form the structure shown in fig. 16, removing the second sacrificial layer 215 to form the structure shown in fig. 17, and removing the first sacrificial layer 208 to form the structure shown in fig. 12;
removing the insulating oxide layer 217 in the step region to form the structure shown in fig. 18, removing the second sacrificial layer 215 to form the structure shown in fig. 19, and removing the first sacrificial layer 208 to form the structure shown in fig. 14;
filling metal on the exposed surface of the stacked structure 206 with the first sacrificial layer 208 removed to obtain a replaced stacked structure 206, wherein the replaced stacked structure 206 includes metal layers 218 and insulating dielectric layers 209 alternately arranged; removing the metal in the gate line slit 200; a second filling structure is formed in the gate line slit 200, so as to form the structure shown in fig. 15.
From the above description, it can be seen that the above-described embodiments of the present application achieve the following technical effects:
1) the manufacturing method of the semiconductor device comprises the steps of firstly, forming a base structure, wherein the base structure comprises a substrate structure and a stacking structure, the stacking structure comprises a body structure, a gate line slit and a second virtual channel hole, the body structure comprises first sacrificial layers and insulating medium layers which are alternately arranged, the gate line slit comprises a first sub-gate line slit and a second sub-gate line slit, the first sub-gate line slit and the second sub-gate line slit are arranged at intervals, the second virtual channel hole is located between the first sub-gate line slit and the second sub-gate line slit, then, forming a second sacrificial layer in the gate line slit, and finally, at least removing the first sacrificial layer and the second sacrificial layer. In the method, a first sub-gate line slit and a second sub-gate line slit are arranged at intervals, a second virtual channel hole is positioned between the first sub-gate line slit and the second sub-gate line slit, i.e., the second dummy channel hole, separates the first sub-gate line slit and the second sub-gate line slit, so that when the second sacrificial layer in the gate line slit is removed, the second sacrificial layer in the first sub-gate line slit cannot flow to other positions from the slit due to the blockage of the second virtual channel hole, the second sacrificial layer in the second sub-gate line slit cannot flow to other positions from the slit due to the blockage of the second virtual channel hole, because the second sacrificial layer does not flow to other positions, the material of the sacrificial layer at other positions can not be increased, redundant materials do not need to be repeatedly removed when the sacrificial layer is subsequently removed, and therefore the method for removing the sacrificial layer is simplified.
2) The semiconductor device comprises a substrate structure, the substrate structure comprises a substrate structure and a stacking structure, the stacking structure comprises a body structure, a gate line slit and a second virtual channel hole, the body structure comprises a first sacrificial layer and an insulating medium layer which are alternately arranged, the gate line slit comprises a first sub-gate line slit and a second sub-gate line slit, the first sub-gate line slit and the second sub-gate line slit are arranged at intervals, and the second virtual channel hole is located between the first sub-gate line slit and the second sub-gate line slit. In the semiconductor device, a first sub-gate line slit and a second sub-gate line slit are disposed at an interval, a second dummy channel hole is located between the first sub-gate line slit and the second sub-gate line slit, i.e., the second dummy channel hole, separates the first sub-gate line slit and the second sub-gate line slit, so that when the second sacrificial layer in the gate line slit is removed, the second sacrificial layer in the first sub-gate line slit cannot flow to other positions from the slit due to the blockage of the second virtual channel hole, the second sacrificial layer in the second sub-gate line slit cannot flow to other positions from the slit due to the blockage of the second virtual channel hole, because the second sacrificial layer does not flow to other positions, the material of the sacrificial layer at other positions can not be increased, redundant materials do not need to be repeatedly removed when the sacrificial layer is subsequently removed, and therefore the method for removing the sacrificial layer is simplified.
3) The three-dimensional memory of the application comprises a semiconductor device obtained by adopting any one of the above methods or the above semiconductor device, wherein the first sub-gate line slit and the second sub-gate line slit are arranged at intervals, and the second virtual channel hole is positioned between the first sub-gate line slit and the second sub-gate line slit, namely the second virtual channel hole separates the first sub-gate line slit from the second sub-gate line slit, so that when the second sacrificial layer in the gate line slit is removed, the second sacrificial layer in the first sub-gate line slit cannot flow to other positions from the slit due to the blockage of the second virtual channel hole, the second sacrificial layer in the second sub-gate line slit cannot flow to other positions from the slit due to the blockage of the second virtual channel hole, and the second sacrificial layer cannot flow to other positions, so that the material of the sacrificial layer at other positions cannot increase, redundant materials do not need to be repeatedly removed when the sacrificial layer is subsequently removed, and therefore the method for removing the sacrificial layer is simplified.
4) The memory system of the present application includes a memory controller and the three-dimensional memory, the three-dimensional memory is configured to store data, the memory controller is coupled to the three-dimensional memory and configured to control the three-dimensional memory, the semiconductor device obtained by any one of the above methods or the semiconductor device, the method includes disposing the first sub-gate line slit and the second sub-gate line slit at an interval, and disposing the second dummy channel hole between the first sub-gate line slit and the second sub-gate line slit, that is, the second dummy channel hole separates the first sub-gate line slit and the second sub-gate line slit, so that when the second dummy layer in the gate line slit is removed, the second dummy layer in the first sub-gate line slit cannot flow from the slit to other positions due to the blocking of the second dummy channel hole, the second sacrificial layer in the second sub-gate line slit cannot flow to other positions from the crack due to the blocking of the second virtual channel hole, and the material of the sacrificial layer at other positions cannot be increased due to the fact that the second sacrificial layer does not flow to other positions, so that redundant material does not need to be removed repeatedly when the sacrificial layer is removed subsequently, and the method for removing the sacrificial layer is simplified.
The above description is only a preferred embodiment of the present application and is not intended to limit the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims (13)
1. A method for manufacturing a semiconductor device, comprising:
forming a base structure comprising a substrate structure and a stack structure, wherein the stack structure is located on the substrate structure, the stack structure includes a body structure, a plurality of channel holes in the body structure, a plurality of first virtual channel holes, a gate line slit, and a second virtual channel hole, one end of the body structure is provided with a step region, a plurality of first virtual channel holes are positioned in the step region, the body structure comprises first sacrificial layers and insulating medium layers which are alternately arranged, the gate line slits penetrate through the stacked structure and are positioned in part of the substrate structure, the gate line slits include a first sub-gate line slit and a second sub-gate line slit, the first sub-gate line slit and the second sub-gate line slit are disposed at an interval, and the second dummy channel hole is located between the first sub-gate line slit and the second sub-gate line slit;
forming a second sacrificial layer in the gate line slit;
removing at least the first sacrificial layer and the second sacrificial layer.
2. The method of claim 1, wherein forming a base structure comprises:
providing the substrate structure, and forming the body structure on the surface of the substrate structure;
forming a plurality of channel holes, a plurality of first virtual channel holes and a second virtual channel hole penetrating through the body structure, wherein the second virtual channel hole is located in a predetermined region, the predetermined region is a region which is located in a core region and a step region of the stacked structure at the same time and includes a boundary of the core region and the step region, and the core region is the stacked structure except for the step region;
forming the gate line slits through the stacked structure and in a portion of the substrate structure.
3. The method of claim 2, wherein forming the second virtual channel hole through the body structure comprises at least one of:
forming a second virtual channel hole of a first type penetrating through the body structure, wherein a filling structure of the second virtual channel hole of the first type is the same as that of the first virtual channel hole;
forming a second type of the second virtual channel hole penetrating the body structure, wherein a filling structure of the second type of the second virtual channel hole is different from a filling structure of the first virtual channel hole.
4. The method of claim 1, wherein before forming the second sacrificial layer in the gate line slit, the method further comprises:
forming a through hole penetrating through a part of the step region;
and forming a first filling structure in the through hole to form a contact hole.
5. The method of claim 1, wherein forming a second sacrificial layer in the gate line slit comprises:
performing predetermined treatment on the surface of the gate line slit to form an insulating layer on the exposed surface of the substrate structure;
and filling a second sacrificial layer in the gate line slit.
6. The method of claim 1, wherein after forming a second sacrificial layer in the gate line slit and before removing the first sacrificial layer and the second sacrificial layer, the method further comprises:
and forming an insulating oxide layer on the exposed surface of the substrate structure after the second sacrificial layer is formed.
7. The method of claim 6, wherein removing at least the first sacrificial layer and the second sacrificial layer comprises:
and removing the insulating oxide layer, the second sacrificial layer and the first sacrificial layer in sequence.
8. The method of claim 6, wherein removing at least the first sacrificial layer and the second sacrificial layer comprises:
sequentially removing the insulating oxide layer, the second sacrificial layer and the first sacrificial layer in a core region, wherein the core region is the stacked structure except the step region;
and sequentially removing the insulating oxide layer, the second sacrificial layer and the first sacrificial layer in the step area.
9. The method of claim 1, wherein after removing the first sacrificial layer and the second sacrificial layer, the method further comprises:
filling metal on the exposed surface of the stacked structure with the first sacrificial layer removed to obtain a replaced stacked structure, wherein the replaced stacked structure comprises metal layers and insulating medium layers which are alternately arranged;
removing the metal in the gate line slit;
and forming a second filling structure in the gate line slit.
10. A semiconductor device, comprising:
a base structure comprising a substrate structure and a stack structure, wherein the stack structure is located on the substrate structure, the stack structure includes a body structure, a plurality of channel holes in the body structure, a plurality of first virtual channel holes, a gate line slit, and a second virtual channel hole, one end of the body structure is provided with a step region, a plurality of first virtual channel holes are positioned in the step region, the body structure comprises metal layers and insulating medium layers which are alternately arranged, the gate line slits penetrate through the stacked structure and are positioned in part of the substrate structure, the gate line slits include a first sub-gate line slit and a second sub-gate line slit, the first sub-gate line slit and the second sub-gate line slit are disposed at intervals, and the second dummy channel hole is located between the first sub-gate line slit and the second sub-gate line slit.
11. The semiconductor device according to claim 10, further comprising:
and a contact hole penetrating through a portion of the step region, the contact hole including a first filling structure.
12. A three-dimensional memory comprising a semiconductor device obtained by the method of any one of claims 1 to 10 or the semiconductor device of claim 10 or 11.
13. A storage system comprising the three-dimensional memory of claim 12 and a storage controller, the three-dimensional memory configured to store data, the storage controller coupled to the three-dimensional memory and configured to control the three-dimensional memory.
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