CN114551459A - Semiconductor device, manufacturing method thereof and three-dimensional memory - Google Patents
Semiconductor device, manufacturing method thereof and three-dimensional memory Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 88
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 26
- 238000000034 method Methods 0.000 claims abstract description 92
- 239000000758 substrate Substances 0.000 claims abstract description 85
- 229910052751 metal Inorganic materials 0.000 claims abstract description 71
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- 238000002360 preparation method Methods 0.000 claims description 26
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 24
- 239000000463 material Substances 0.000 claims description 23
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 15
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- 238000003860 storage Methods 0.000 claims description 13
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 10
- 235000012239 silicon dioxide Nutrition 0.000 claims description 5
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
- H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
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Abstract
The application provides a semiconductor device, a manufacturing method thereof and a three-dimensional memory, wherein the semiconductor device comprises a substrate, a stack structure and a dielectric layer, the stack structure is positioned on the substrate, the stack structure comprises insulating dielectric layers and metal layers which are alternately overlapped along the direction far away from the substrate, one end of the stack structure is provided with a step area, the step area comprises a plurality of steps, the dielectric layer covers the stack structure and the surface, far away from the substrate, of the step area, the semiconductor device also comprises a groove, a virtual channel filling layer and a contact hole filling layer, and the groove penetrates through the dielectric layer and the stack structure to the substrate; the dummy channel filling layer and the contact hole filling layer are sequentially overlapped in the groove along the direction far away from the substrate, the metal layer on two sides of the groove, which is farthest away from the substrate, is a preset metal layer, the contact hole filling layer is in contact with the preset metal layer, and the contact hole filling layer is isolated from other metal layers through the dummy channel filling layer. The method and the device ensure that the process window of the contact hole and the virtual channel hole of the semiconductor device is larger.
Description
Technical Field
The present invention relates to the field of semiconductors, and in particular, to a semiconductor device, a method for manufacturing the semiconductor device, a three-dimensional memory, and a memory system.
Background
With the increasing number of layers of 3D NAND, the difficulty of stopping the CT (Contact) etching on the tungsten wire is greater and greater.
Meanwhile, the critical dimension of DCH (virtual channel Hole) affects the supporting effect of the step area and the process window (process window) of CT, and the critical dimension of DCH is small, which causes the supporting effect of DCH to the step area to be poor, but the critical dimension of DCH is large, which occupies the process window of CT.
Therefore, a method is needed to solve the problem that the prior art cannot ensure the better support effect of DCH and ensure the larger process window of CT.
The above information disclosed in this background section is only for enhancement of understanding of the background of the technology described herein and, therefore, certain information may be included in the background that does not form the prior art that is already known in this country to a person of ordinary skill in the art.
Disclosure of Invention
The present disclosure provides a semiconductor device, a method for manufacturing the semiconductor device, a three-dimensional memory and a storage system, so as to solve the problem that the process window of CT cannot be guaranteed to be large while the supporting function of DCH is guaranteed to be good in the prior art.
According to an aspect of the embodiments of the present invention, there is provided a semiconductor device, including a substrate, a stacked structure, and a dielectric layer, wherein the stacked structure is located on the substrate, the stacked structure includes insulating dielectric layers and metal layers that are alternately stacked in a direction away from the substrate, and one end of the stacked structure has a step region, the step region includes a plurality of steps, the dielectric layers cover the stacked structure and a surface of the step region away from the substrate, the semiconductor device further includes a groove, a dummy trench filling layer, and a contact hole filling layer, wherein the groove penetrates through the dielectric layer, the stacked structure, and the groove is located in the steps; the dummy channel filling layer and the contact hole filling layer are sequentially overlapped in the groove along the direction far away from the substrate, the metal layer on two sides of the groove, which is farthest away from the substrate, is a preset metal layer, the contact hole filling layer is in contact with the preset metal layer, and the contact hole filling layer is isolated from other metal layers through the dummy channel filling layer.
Optionally, the semiconductor device further includes a gate line in the dielectric layer and in the stacked structure and penetrating to the substrate.
Optionally, the semiconductor device further includes a channel hole located in the dielectric layer and in the stacked structure and penetrating to the substrate.
Optionally, the material of the dummy trench filling layer comprises silicon dioxide, and the material of the contact hole filling layer comprises tungsten.
According to another aspect of the embodiments of the present invention, there is also provided a method for manufacturing a semiconductor device, including: forming a preparation stacking structure and a dielectric layer on a substrate, wherein the preparation stacking structure comprises insulating dielectric layers and sacrificial layers which are alternately stacked along a direction far away from the substrate, one end of the preparation stacking structure is provided with a step area, the step area comprises a plurality of steps, and the dielectric layer covers the preparation stacking structure and exposed surfaces of the step area; forming a groove in the dielectric layer and the preparation stacking structure, wherein the groove penetrates through the substrate and is positioned in the step; forming a virtual channel filling layer in the groove to form a virtual channel hole, and forming a contact hole filling layer on the exposed surface of the virtual channel filling layer to form a contact hole, wherein the sacrificial layer at two sides of the groove, which is farthest away from the substrate, is a preset sacrificial layer, the contact hole filling layer is in contact with the preset sacrificial layer, and the contact hole filling layer is isolated from other sacrificial layers through the virtual channel filling layer; and replacing each sacrificial layer with a metal layer.
Optionally, forming a dummy trench filling layer in the groove to form a dummy trench hole includes: removing the exposed part of each insulating medium layer in the groove to form a plurality of spaced first sub-grooves in the groove; forming a polycrystalline silicon layer on the exposed surface of each first sub-groove; and oxidizing the polycrystalline silicon layer, forming an oxide layer on the exposed surface of the oxidized polycrystalline silicon layer to obtain the virtual channel hole, wherein the oxidized polycrystalline silicon layer and the oxide layer form the virtual channel filling layer.
Optionally, forming a polysilicon layer on an exposed surface of each of the first sub-grooves includes: forming a preliminary polysilicon layer in the groove in which the first sub-groove is formed; and removing part of the prepared polysilicon layer to expose the side walls of the dielectric layer and the sacrificial layers in the grooves, and forming the polysilicon layer by the residual prepared polysilicon layer.
Optionally, before forming the recess in the dielectric layer and the preliminary stacked structure, after forming the preliminary stacked structure and the dielectric layer on the substrate, the method further includes: forming a preparation channel hole in the dielectric layer and the preparation stacking structure; forming a charge blocking layer, an electron capturing layer, a tunneling layer and a channel layer on the bottom wall and the side wall of the preparation channel hole in sequence; and sequentially filling silicon oxide and polysilicon in the rest of the preparation channel holes to fill the preparation channel holes to obtain channel holes.
Optionally, replacing each sacrificial layer with a metal layer includes: forming a gate line slit in the dielectric layer and the preliminary stacked structure; removing the sacrificial layers through the gate line slits to obtain a plurality of second sub-grooves; sequentially filling titanium nitride and tungsten into the gate line slits and the second sub-grooves to form a plurality of metal layers; and removing the titanium nitride and the tungsten in the gate line slit.
Optionally, after each sacrificial layer is replaced by a metal layer, the method further includes: and sequentially filling silicon oxide and polysilicon into the gate line slits to obtain the gate lines.
According to still another aspect of the embodiments of the present invention, there is also provided a three-dimensional memory including any one of the semiconductor devices or a semiconductor device obtained by using any one of the methods.
There is also provided, in accordance with yet another aspect of an embodiment of the present invention, a memory system, including a memory controller and the three-dimensional memory, the three-dimensional memory being configured to store data, the memory controller being coupled to the three-dimensional memory and configured to control the three-dimensional memory.
In an embodiment of the present invention, the semiconductor device includes a substrate, a stack structure, a dielectric layer, a groove, a dummy trench filling layer, and a contact hole filling layer, wherein the stack structure includes an insulating dielectric layer and a metal layer stacked alternately, one end of the stack structure has a step region, the step region includes a plurality of steps, the groove penetrates through the dielectric layer and the corresponding steps to the substrate, the dummy trench filling layer and the contact hole layer are sequentially filled in the groove, the contact hole filling layer is in contact with a predetermined metal layer on both sides of the groove, the predetermined metal layer is farthest from the substrate, and the contact hole filling layer is isolated from other metal layers by the dummy trench filling layer. The semiconductor device of the application obtains the dummy trench hole by filling the dummy trench filling layer in the groove, then fills the contact hole filling layer in the rest groove, ensuring that the contact hole filling layer is only contacted with the preset metal layer and is not contacted with other metal layers to obtain a contact hole, that is, the dummy channel holes and the contact holes are formed in one groove, so that the contact holes and the dummy channel holes are not required to be formed on the step of the step region at intervals, which results in the failure to ensure the better supporting function of the DCH, the problem of ensuring a larger process window for CT, the semiconductor device of the present application ensures a larger process window for the contact hole and the dummy channel hole of the semiconductor device, therefore, the better supporting effect of the DCH is ensured, meanwhile, the larger process window of the CT is ensured, and the better performance of the device is further ensured. In addition, because the virtual channel hole and the contact hole are formed in the groove, compared with the prior art, a photomask and a corresponding manufacturing process are saved, the process of the semiconductor device is simpler, and the process cost is lower.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this application, illustrate embodiments of the application and, together with the description, serve to explain the application and are not intended to limit the application. In the drawings:
fig. 1 shows a schematic structural diagram of a semiconductor device according to an embodiment of the present application;
fig. 2 shows a flow diagram of a method of fabricating a semiconductor device according to an embodiment of the present application;
fig. 3 to 12 respectively show schematic structural diagrams obtained after each process step of a manufacturing method of a semiconductor device according to an embodiment of the present application.
Wherein the figures include the following reference numerals:
100. a substrate; 101. a dielectric layer; 102. an insulating dielectric layer; 103. a metal layer; 104. a sacrificial layer; 105. a step area; 106. a channel hole; 107. a gate line slit; 108. a gate line; 200. a groove; 201. a dummy trench fill layer; 202. a contact hole filling layer; 203. a first sub-groove; 300. a polysilicon layer; 301. a silicon oxide layer; 302. a polysilicon layer is prepared.
Detailed Description
It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict. The present application will be described in detail below with reference to the embodiments with reference to the attached drawings.
In order to make the technical solutions better understood by those skilled in the art, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only partial embodiments of the present application, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
It should be noted that the terms "first," "second," and the like in the description and claims of this application and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It should be understood that the data so used may be interchanged under appropriate circumstances such that embodiments of the application described herein may be used. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present. Also, in the specification and claims, when an element is described as being "connected" to another element, the element may be "directly connected" to the other element or "connected" to the other element through a third element.
As mentioned in the background art, the prior art cannot ensure that the process window of CT is large while ensuring the support function of DCH, and in order to solve the above problems, in an exemplary embodiment of the present application, a semiconductor device, a method for manufacturing the semiconductor device, a three-dimensional memory, and a memory system are provided.
According to an exemplary embodiment of the present application, there is provided a semiconductor device, as shown in fig. 1, the semiconductor device includes a substrate 100, a stacked structure and a dielectric layer 101, the stacked structure is located on the substrate 100, the stacked structure includes insulating dielectric layers 102 and metal layers 103 which are alternately stacked in a direction away from the substrate 100, and one end of the stacked structure has a step region, the step region includes a plurality of steps, the dielectric layer 101 covers the stacked structure and a surface of the step region away from the substrate 100, the semiconductor device further includes a groove, a dummy trench filling layer 201 and a contact hole filling layer 202, wherein the groove penetrates through the dielectric layer 101, the stacked structure and the substrate 100, and the groove is located in the steps; the dummy trench filling layer 201 and the contact hole filling layer 202 are sequentially stacked in the recess in a direction away from the substrate 100, the metal layer 103 located at both sides of the recess and farthest from the substrate 100 is a predetermined metal layer, the contact hole filling layer 202 is in contact with the predetermined metal layer, and the contact hole filling layer 202 is isolated from the other metal layers 103 by the dummy trench filling layer 201, that is, the contact hole filling layer 202 is not in contact with the other metal layers.
The semiconductor device comprises a substrate, a stacked structure, a dielectric layer, a groove, a virtual channel filling layer and a contact hole filling layer, wherein the stacked structure comprises insulating dielectric layers and metal layers which are alternately stacked, one end of the stacked structure is provided with a step area, the step area comprises a plurality of steps, the groove penetrates through the dielectric layers and the corresponding steps to the substrate, the virtual channel filling layer and the contact hole layer are sequentially filled in the groove, the contact hole filling layer is in contact with a preset metal layer which is arranged on two sides of the groove and is farthest away from the substrate, and the contact hole filling layer is isolated from other metal layers through the virtual channel filling layer. The semiconductor device of the present application obtains a dummy trench hole by filling the dummy trench filling layer in the groove, and then fills the contact hole filling layer in the remaining groove, ensuring that the contact hole filling layer is only contacted with the preset metal layer and is not contacted with other metal layers to obtain a contact hole, that is, the dummy channel holes and the contact holes are formed in one groove, so that the contact holes and the dummy channel holes are not required to be formed on the step of the step region at intervals, which results in the failure to ensure the better supporting function of the DCH, the problem of ensuring larger process window of CT, the semiconductor device of the present application ensures larger process window of the contact hole and the virtual channel hole of the semiconductor device, therefore, the better supporting effect of the DCH is ensured, meanwhile, the larger process window of the CT is ensured, and the better performance of the device is further ensured. In addition, because the virtual channel hole and the contact hole are formed in the groove, compared with the prior art, a photomask and a corresponding manufacturing process are saved, the process of the semiconductor device is simpler, and the process cost is lower.
In the above embodiment, a surface of the dummy trench filling layer away from the substrate may be flush with a surface of the predetermined metal layer close to the substrate, a surface of the dummy trench filling layer away from the substrate may be higher than the surface of the predetermined metal layer close to the substrate and lower than the surface of the predetermined metal layer away from the substrate, and a surface of the dummy trench filling layer away from the substrate may be lower than the surface of the predetermined metal layer close to the substrate and higher than surfaces of other metal layers away from the substrate. In a specific embodiment of the present application, as shown in fig. 1, a surface of the dummy trench filling layer away from the substrate may be flush with a surface of the predetermined metal layer close to the substrate.
It should be noted that, in fig. 1 and fig. 3 to fig. 12, X-cut refers to a structural diagram obtained by cutting the semiconductor device along an X direction, and Y-cut refers to a structural diagram obtained by cutting the semiconductor device along a Y square, where the X direction is perpendicular to the Y direction, that is, fig. 1 and fig. 3 to fig. 12 are respectively obtained by splicing cross-sectional views along two directions, a splicing position is marked by a dotted line, for example, the X direction may be an extending direction of a gate line slit, and the Y direction may be an arrangement direction of the gate line slit.
According to a specific embodiment of the present application, as shown in fig. 1, there are a plurality of the grooves, a plurality of the dummy trench filling layers and a plurality of the contact hole filling layers, the grooves are located in the steps in a one-to-one correspondence, and the dummy trench filling layers and the contact hole filling layers are located in the grooves in a one-to-one correspondence.
In one embodiment, as shown in fig. 1, the semiconductor device further includes a gate line 108, and the gate line 108 is located in the dielectric layer 101 and in the stacked structure and penetrates through the substrate 100. Replacement of the sacrificial layer to the metal layer in the stacked structure may be achieved through the gate line slit before the gate line is formed.
According to another specific embodiment of the present application, as shown in fig. 1, the semiconductor device further includes a channel hole 106, and the channel hole 106 is located in the dielectric layer 101 and the stacked structure and penetrates through the substrate 100.
Specifically, the number of the channel holes may be one or more.
In some embodiments, the material of the dummy trench filling layer comprises silicon dioxide, and the material of the contact hole filling layer comprises tungsten. In this embodiment, the dummy trench filling layer is made of silicon dioxide, and the contact hole filling layer is made of titanium nitride and tungsten. Of course, the material of the dummy trench filling layer and the material of the contact hole filling layer are not limited to the above materials, and those skilled in the art can flexibly select the constituent materials according to actual conditions.
In order to further ensure that the manufacturing process of the semiconductor device is simple and the resistance of the gate is reduced, as shown in fig. 1, in another specific embodiment of the present application, the thickness of the metal layer 103 is greater than the thickness of the insulating dielectric layer 102.
The sacrificial layer and the insulating dielectric layer may be made of materials conventional in the art. In another embodiment of the present application, the sacrificial layer is a silicon nitride layer, and the insulating dielectric layer is a silicon oxide layer. In addition, in some specific embodiments, the material of the dummy trench filling layer may be the same as that of the insulating dielectric layer, and in other specific embodiments, the material of the dummy trench filling layer may be different from that of the insulating dielectric layer.
According to another exemplary embodiment of the present application, a method of fabricating a semiconductor device is provided.
Fig. 2 is a flow chart of a method of fabricating a semiconductor device according to an embodiment of the present application. As shown in fig. 2, the method comprises the steps of:
step S101, as shown in fig. 3, forming a preliminary stacked structure and a dielectric layer 101 on a substrate 100, where the preliminary stacked structure includes insulating dielectric layers 102 and sacrificial layers 104 alternately stacked in a direction away from the substrate 100, one end of the preliminary stacked structure has a step region 105, the step region includes a plurality of steps, and the dielectric layer 101 covers exposed surfaces of the preliminary stacked structure and the step region 105;
step S102, as shown in fig. 4, forming a recess 200 in the dielectric layer and the preliminary stacked structure, wherein the recess 200 penetrates through the substrate 100 and is located in the step;
step S103, as shown in fig. 9, forming a dummy trench filling layer 201 in the groove 200 to form a dummy trench hole, as shown in fig. 10, and forming a contact hole filling layer 202 on an exposed surface of the dummy trench filling layer 201 to form a contact hole, wherein the sacrificial layer 104 on both sides of the groove, which is farthest from the substrate 100, is a predetermined sacrificial layer, the contact hole filling layer 202 is in contact with the predetermined sacrificial layer, and the contact hole filling layer 202 is isolated from the other sacrificial layers 104 by the dummy trench filling layer 201;
in step S104, as shown in fig. 11, 12 and 1, the sacrificial layers 104 are replaced with metal layers 103, and the semiconductor device shown in fig. 1 is obtained. In the manufacturing method of the semiconductor device, firstly, a preparation stacking structure and a dielectric layer are sequentially formed on a substrate, the preparation stacking structure comprises insulating dielectric layers and sacrificial layers which are alternately stacked, one end of the preparation stacking structure is also provided with a step area, and the step area comprises a plurality of steps; then, forming a plurality of grooves penetrating through the dielectric layer and the corresponding steps to the substrate; filling a dummy channel filling layer in each groove to form a dummy channel hole, and filling a contact hole filling layer in each remaining groove to form a contact hole, wherein the contact hole filling layer is in contact with a predetermined sacrificial layer and is isolated from other sacrificial layers by the dummy channel filling layer; and finally, replacing each sacrificial layer with a metal layer. In the method for manufacturing the semiconductor device, the dummy trench hole is obtained by filling the dummy trench filling layer in the groove, and then the contact hole filling layer is filled in the rest of the groove, ensuring that the contact hole filling layer is only contacted with the predetermined sacrificial layer and is not contacted with other sacrificial layers to obtain a contact hole, that is, the dummy channel holes and the contact holes are formed in one groove, so that the contact holes and the dummy channel holes are not required to be formed on the step of the step region at intervals, which results in the failure to ensure the better supporting function of the DCH, ensuring the larger process window of CT, ensuring the larger process window of the contact hole and the virtual channel hole of the semiconductor device, therefore, the better supporting effect of the DCH is ensured, meanwhile, the larger process window of the CT is ensured, and the better performance of the device is further ensured. In addition, because the virtual channel hole and the contact hole are formed in the groove, compared with the prior art, a photomask and a corresponding manufacturing process are saved, the process of the semiconductor device is simpler, and the process cost is lower.
It should be noted that, each step in the above-mentioned embodiment of forming the substrate can be implemented in a feasible manner in the prior art. The substrate may be selected according to actual requirements of the device, and may include a Silicon substrate, a germanium substrate, a Silicon germanium (sige) substrate, an SOI (Silicon On Insulator) substrate, or a GOI (germanium On Insulator) substrate. In other embodiments, the substrate may be a substrate including other element semiconductors or compound semiconductors, such as GaAs, InP, or SiC, a stacked structure, such as Si/SiGe, or another epitaxial structure. Of course, it may also be other substrates feasible in the art.
According to a specific embodiment of the present application, forming a dummy trench filling layer in the groove to form a dummy trench hole includes: as shown in fig. 5, removing the exposed portions of the insulating medium layers 102 in the grooves 200 to form a plurality of spaced first sub-grooves 203 in the grooves 200; forming a polysilicon layer 300 on the exposed surface of each of the first sub-grooves 203 to obtain the structure shown in fig. 7; as shown in fig. 8, the polysilicon layer 300 is oxidized to obtain a silicon oxide layer 301, and an oxide layer is formed on the exposed surface of the oxidized polysilicon layer 300 (i.e., the silicon oxide layer 301) to obtain the dummy trench hole as shown in fig. 9, and the oxidized polysilicon layer 300 and the oxide layer constitute the dummy trench filling layer 201. In this embodiment, the exposed portions of the insulating medium layers in the grooves are removed first, so that the insulating medium layers in the grooves retract to obtain a plurality of first sub-grooves, then a polysilicon layer is formed on the exposed surfaces of the first sub-grooves and oxidized, and the polysilicon layer expands after being oxidized, so that the oxidized silicon dioxide can better fill the first sub-grooves and form oxidized portions protruding out of the first sub-grooves, thereby avoiding the defect of incomplete filling and holes, and finally, an oxide layer is filled in the grooves, so that the oxide layer can be easily controlled to seal the lower surface of the predetermined sacrificial layer, further, the subsequently formed contact filling layer is in contact with the predetermined sacrificial layer and is not in contact with other sacrificial layers, even if the control contact hole stops on the corresponding predetermined sacrificial layer, the problem that the etching of the contact hole is difficult to control and the etching of the contact hole stops on the corresponding sacrificial layer in the prior art is further solved.
According to another specific embodiment of the present application, forming a polysilicon layer on the exposed surface of each of the first sub-grooves includes: as shown in fig. 5 and 6, a preliminary polysilicon layer 302 is formed in the groove 200 in which the first sub-groove 203 is formed; as shown in fig. 7, a portion of the preliminary polysilicon layer 302 is removed to expose at least the sidewalls of the dielectric layer 101 and the sacrificial layers 104 in the recess 200, and the remaining preliminary polysilicon layer 302 forms the polysilicon layer 300.
Specifically, removing part of the preliminary polysilicon layer to expose at least the sidewalls of the dielectric layer and the sacrificial layers in the groove includes: and removing part of the preliminary polysilicon layer to expose the surface of the substrate, the side wall of the dielectric layer and the side wall of each sacrificial layer 104 in the groove, namely only remaining the polysilicon layer in each first sub-groove.
Of course, the method for forming the dummy trench filling layer is not limited to the above method, and those skilled in the art may also use any other feasible method to form the dummy trench filling layer. In a specific embodiment, after removing the exposed portion of each of the insulating medium layers in the groove to form a plurality of spaced first sub-grooves in the groove, i.e. after forming the structure shown in fig. 5, the method further includes: silicon oxide is filled into the recess formed with the first sub-recess to form a dummy trench filling layer 201 in the recess 200, resulting in the structure shown in fig. 9.
In another specific embodiment of the present application, before forming the recess in the dielectric layer and the preliminary stacked structure, after forming the preliminary stacked structure and the dielectric layer on the substrate, the method further includes: forming a preliminary channel hole in the dielectric layer 101 and the preliminary stacked structure; forming a charge blocking layer, an electron capturing layer, a tunneling layer and a channel layer on the bottom wall and the side wall of the prepared channel hole in sequence; the remaining preliminary channel hole is filled with silicon oxide and polysilicon in this order to fill the preliminary channel hole, thereby obtaining a channel hole 106 as shown in fig. 2.
Specifically, a plurality of the preliminary channel holes may be provided, and the channel layer, the tunneling layer, the electron trapping layer, and the charge blocking layer may form a PONO stack structure, i.e., a poly-oxide-silicon nitride-oxide stack structure.
In an actual application process, replacing each sacrificial layer with a metal layer includes: as shown in fig. 11, a gate line slit 107 is formed in the dielectric layer 101 and the preliminary stacked structure; removing each sacrificial layer 104 through the gate line slits 107 to obtain a plurality of second sub-grooves; sequentially filling titanium nitride and tungsten into the gate line slits 107 and the second sub-grooves to form a plurality of metal layers 103 as shown in fig. 12; the titanium nitride and the tungsten in the gate line slit 107 are removed. And replacing the sacrificial layer with the metal layer through the gate line slit to obtain a plurality of word lines, and removing the titanium nitride and the tungsten in the gate line slit to avoid short circuit of each word line and ensure normal electrical property of the device.
In a specific embodiment, after each of the sacrificial layers is replaced by a metal layer, the method further includes: the gate line slit 107 is filled with silicon oxide and polysilicon in this order to obtain a gate line 108 as shown in fig. 1.
The step region can be formed by one-time stacking and one-time etching, and can also be formed by multiple-time stacking and multiple-time etching. The sacrificial layer and the insulating dielectric layer may be made of materials conventional in the art. In another embodiment of the present application, the sacrificial layer is a silicon nitride layer, the insulating dielectric layer is a silicon oxide layer, and the conductive layer is made of tungsten.
In practical applications, forming a preliminary channel hole in the dielectric layer and the preliminary stacked structure includes: providing a substrate; forming insulating medium layers and sacrificial layers which are alternately superposed on the exposed surface of the substrate, wherein the insulating medium layers and the sacrificial layers which are alternately superposed form a first sub-superposed structure; forming a first trench in the first sub-stack structure, and filling a sacrificial material in the first trench to form a bottom trench hole; forming alternately-stacked insulating dielectric layers and sacrificial layers on the first sub-stacked structure with the bottom channel hole, wherein the alternately-stacked insulating dielectric layers and the sacrificial layers form a second sub-stacked structure; forming a second trench in the first sub-stacked structure such that the bottom trench hole is exposed; and removing the sacrificial material in the bottom channel hole, wherein the first trench and the second trench form the preliminary channel hole.
Specifically, forming a contact hole filling layer on an exposed surface of the dummy trench filling layer to form a contact hole includes: depositing a titanium nitride material and a tungsten material on the exposed surface of the dummy trench filling layer and the exposed surface of the dielectric layer in sequence, wherein the titanium nitride material and the tungsten material form the contact hole filling material to fill the groove to obtain a first intermediate structure; and planarizing the first intermediate structure to remove at least the contact hole filling material on the surface of the dielectric layer, wherein the residual contact hole filling material forms the contact hole filling layer.
Forming a gate line slit in the dielectric layer and the preliminary stacked structure, including: depositing a dielectric material such as silicon oxide on the exposed surface of the dielectric layer to cover the contact hole; and forming a gate line slit in the deposited dielectric layer and the preliminary stacked structure.
These structural layers described above may be formed via one or more of Atomic Layer Deposition (ALD), Molecular Beam Epitaxy (MBE), Metal Organic Chemical Vapor Deposition (MOCVD), Metal Organic Vapor Phase Epitaxy (MOVPE), Hydride Vapor Phase Epitaxy (HVPE), and/or other well-known crystal growth processes.
In yet another exemplary embodiment of the present application, there is also provided a three-dimensional memory including any one of the above semiconductor devices or a semiconductor device obtained by any one of the above methods.
The three-dimensional memory comprises any one of the semiconductor devices or the semiconductor device obtained by any one of the methods, the semiconductor device obtains a virtual channel hole by filling the virtual channel filling layer in the groove, and then fills the contact hole filling layer in the rest groove to ensure that the contact hole filling layer is only contacted with the preset metal layer and is not contacted with other metal layers to obtain a contact hole, namely the virtual channel hole and the contact hole are formed in one groove, so that the contact hole and the virtual channel hole which are arranged at intervals are not required to be formed on the step of the step region, the problem that the process window of CT is large cannot be ensured while the supporting function of DCH is ensured is good is solved, the semiconductor device ensures that the process window of the contact hole and the virtual channel hole of the semiconductor device is large, so that the supporting function of DCH is good, the process window of the CT is ensured to be larger, and the performance of the three-dimensional memory is ensured to be better. In addition, because the virtual channel hole and the contact hole are formed in the groove, compared with the prior art, a photomask and a corresponding manufacturing process are saved, the process of the semiconductor device is simpler, the process cost is lower, and the process cost of the three-dimensional memory is lower.
There is also provided, in accordance with yet another exemplary embodiment of the present application, a memory system, including a memory controller and the three-dimensional memory, the three-dimensional memory being configured to store data, the memory controller being coupled to the three-dimensional memory and being configured to control the three-dimensional memory.
The storage system comprises a storage controller and the three-dimensional memory, wherein in the three-dimensional memory, the semiconductor device fills the groove with the dummy channel filling layer to obtain a dummy channel hole, and then fills the contact hole filling layer in the rest groove to ensure that the contact hole filling layer is only contacted with the preset metal layer and is not contacted with other metal layers to obtain a contact hole, namely the dummy channel hole and the contact hole are formed in one groove, so that the contact hole and the dummy channel hole which are arranged at intervals are not required to be formed on the step of the step region, the problem that the process window of CT is large cannot be ensured while the better supporting effect of DCH is ensured is solved, the semiconductor device ensures that the process window of the contact hole and the dummy channel hole of the semiconductor device is large, so that the better supporting effect of DCH is ensured, the process window of the CT is ensured to be larger, and the performance of the storage system is ensured to be better. In addition, because the virtual channel hole and the contact hole are formed in the groove, compared with the prior art, a photomask and a corresponding manufacturing process are saved, the process of the semiconductor device is simpler, and the process cost of the storage system is lower.
In the above embodiments of the present invention, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.
In the embodiments provided in the present application, it should be understood that the disclosed technology can be implemented in other ways. The above-described embodiments of the apparatus are merely illustrative, and for example, the above-described division of the units may be a logical division, and in actual implementation, there may be another division, for example, multiple units or components may be combined or may be integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, units or modules, and may be in an electrical or other form.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In addition, functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.
The integrated unit may be stored in a computer-readable storage medium if it is implemented in the form of a software functional unit and sold or used as a separate product. Based on such understanding, the technical solution of the present invention may be embodied in the form of a software product, which is stored in a storage medium and includes instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the above methods according to the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a removable hard disk, a magnetic or optical disk, and other various media capable of storing program codes.
From the above description, it can be seen that the above-described embodiments of the present application achieve the following technical effects:
1) the semiconductor device comprises a substrate, a stacked structure, dielectric layers, a groove, a virtual channel filling layer and a contact hole filling layer, wherein the stacked structure comprises insulating dielectric layers and metal layers which are alternately stacked, one end of the stacked structure is provided with a step area, the step area comprises a plurality of steps, the groove penetrates through the dielectric layers and the corresponding steps to the substrate, the virtual channel filling layer and the contact hole layer are sequentially filled in the groove, the contact hole filling layer is in contact with a preset metal layer which is farthest away from the substrate and arranged on two sides of the groove, and the contact hole filling layer is isolated from other metal layers through the virtual channel filling layer. The semiconductor device of the present application obtains a dummy trench hole by filling the dummy trench filling layer in the groove, and then fills the contact hole filling layer in the remaining groove, ensuring that the contact hole filling layer is only contacted with the preset metal layer and is not contacted with other metal layers to obtain a contact hole, that is, the dummy channel holes and the contact holes are formed in one groove, so that the contact holes and the dummy channel holes are not required to be formed on the step of the step region at intervals, which results in the failure to ensure the better supporting function of the DCH, the problem of ensuring larger process window of CT, the semiconductor device of the present application ensures larger process window of the contact hole and the virtual channel hole of the semiconductor device, therefore, the better supporting effect of the DCH is ensured, meanwhile, the larger process window of the CT is ensured, and the better performance of the device is further ensured. In addition, because the virtual channel hole and the contact hole are formed in the groove, compared with the prior art, a photomask and a corresponding manufacturing process are saved, the process of the semiconductor device is simpler, and the process cost is lower.
2) In the manufacturing method of the semiconductor device, firstly, a preparation stacking structure and a dielectric layer are sequentially formed on a substrate, the preparation stacking structure comprises insulating dielectric layers and sacrificial layers which are alternately stacked, one end of the preparation stacking structure is provided with a step area, and the step area comprises a plurality of steps; then, forming a plurality of grooves penetrating through the dielectric layer and the corresponding steps to the substrate; filling a dummy channel filling layer in each groove to form a dummy channel hole, and filling a contact hole filling layer in each remaining groove to form a contact hole, wherein the contact hole filling layer is in contact with a predetermined sacrificial layer and is isolated from other sacrificial layers by the dummy channel filling layer; and finally, replacing each sacrificial layer with a metal layer. In the method for manufacturing the semiconductor device, the dummy trench hole is obtained by filling the dummy trench filling layer in the groove, and then the contact hole filling layer is filled in the rest of the groove, ensuring that the contact hole filling layer is only contacted with the predetermined sacrificial layer and is not contacted with other sacrificial layers to obtain a contact hole, that is, the dummy channel holes and the contact holes are formed in one groove, so that the contact holes and the dummy channel holes are not required to be formed on the step of the step region at intervals, which results in the failure to ensure the better supporting function of the DCH, ensuring the larger process window of CT, ensuring the larger process window of the contact hole and the virtual channel hole of the semiconductor device, therefore, the better supporting effect of the DCH is ensured, meanwhile, the larger process window of the CT is ensured, and the better performance of the device is further ensured. In addition, because the virtual channel hole and the contact hole are formed in the groove, compared with the prior art, a photomask and a corresponding manufacturing process are saved, the process of the semiconductor device is simpler, and the process cost is lower.
3) The three-dimensional memory of the present application includes any one of the semiconductor devices or the semiconductor device obtained by any one of the methods described above, and the semiconductor device obtains a dummy trench hole by filling the dummy trench filling layer in the groove, and then fills the contact hole filling layer in the remaining groove, so as to ensure that the contact hole filling layer is only in contact with the predetermined metal layer and is not in contact with other metal layers, and thus obtains a contact hole, i.e., the dummy trench hole and the contact hole are formed in one groove, so that there is no need to form contact holes and dummy trench holes arranged at intervals on a step of a step region, which causes a problem that a process window of CT cannot be ensured to be large while a supporting effect of DCH is ensured to be good, and the semiconductor device of the present application ensures that a process window of the contact hole and the dummy trench hole of the semiconductor device is large, therefore, the better supporting effect of the DCH is ensured, the larger process window of the CT is ensured, and the better performance of the three-dimensional memory is ensured. In addition, because the virtual channel hole and the contact hole are formed in the groove, compared with the prior art, a photomask and a corresponding manufacturing process are saved, the process of the semiconductor device is simpler, the process cost is lower, and the process cost of the three-dimensional memory is lower.
4) The memory system comprises a memory controller and the three-dimensional memory, wherein in the three-dimensional memory, the semiconductor device is filled with a virtual channel filling layer in the groove to obtain a virtual channel hole, and then the contact hole filling layer is filled in the rest groove to ensure that the contact hole filling layer is only contacted with the preset metal layer and is not contacted with other metal layers to obtain a contact hole, namely the virtual channel hole and the contact hole are formed in one groove, so that the contact holes and the virtual channel holes which are arranged at intervals are not required to be formed on the step of the step area, the problem that the process window of CT cannot be ensured to be larger while the supporting function of DCH is ensured is solved, the semiconductor device ensures that the process window of the contact hole and the virtual channel hole of the semiconductor device is larger, thereby ensuring the supporting function of DCH is better, the process window of the CT is ensured to be larger, and the performance of the storage system is ensured to be better. In addition, because the virtual channel hole and the contact hole are formed in the groove, compared with the prior art, a photomask and a corresponding manufacturing process are saved, the process of the semiconductor device is simpler, and the process cost of the storage system is lower.
The above description is only a preferred embodiment of the present application and is not intended to limit the present application, and various modifications and changes may be made to the present application by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims (12)
1. A semiconductor device comprising a substrate, a stack structure and dielectric layers, wherein the stack structure is located on the substrate, the stack structure comprises insulating dielectric layers and metal layers which are alternately stacked along a direction far away from the substrate, one end of the stack structure is provided with a step region, the step region comprises a plurality of steps, the dielectric layers cover the stack structure and the surface of the step region far away from the substrate, and the semiconductor device further comprises:
the groove penetrates through the dielectric layer and the stacked structure to the substrate, and is positioned in the step;
the metal layer on two sides of the groove, which is farthest away from the substrate, is a preset metal layer, the contact hole filling layer is in contact with the preset metal layer, and the contact hole filling layer is isolated from other metal layers through the virtual channel filling layer.
2. The semiconductor device according to claim 1, further comprising:
and the gate line is positioned in the dielectric layer and the stacked structure and penetrates through the substrate.
3. The semiconductor device according to claim 1, further comprising:
and the channel hole is positioned in the dielectric layer and the stacked structure and penetrates through the substrate.
4. The semiconductor device according to any one of claims 1 to 3, wherein a material of the dummy trench filling layer comprises silicon dioxide, and a material of the contact hole filling layer comprises tungsten.
5. A method for manufacturing a semiconductor device, comprising:
forming a preparation stacking structure and a dielectric layer on a substrate, wherein the preparation stacking structure comprises insulating dielectric layers and sacrificial layers which are alternately stacked along a direction far away from the substrate, one end of the preparation stacking structure is provided with a step area, the step area comprises a plurality of steps, and the dielectric layer covers the preparation stacking structure and exposed surfaces of the step area;
forming a groove in the dielectric layer and the preparation stacking structure, wherein the groove penetrates through the substrate and is positioned in the step;
forming a virtual channel filling layer in the groove to form a virtual channel hole, and forming a contact hole filling layer on the exposed surface of the virtual channel filling layer to form a contact hole, wherein the sacrificial layer at two sides of the groove, which is farthest away from the substrate, is a preset sacrificial layer, the contact hole filling layer is in contact with the preset sacrificial layer, and the contact hole filling layer is isolated from other sacrificial layers through the virtual channel filling layer;
and replacing each sacrificial layer with a metal layer.
6. The method of claim 5, wherein forming a dummy trench fill layer in the recess to form a dummy trench hole comprises:
removing the exposed part of each insulating medium layer in the groove to form a plurality of spaced first sub-grooves in the groove;
forming a polycrystalline silicon layer on the exposed surface of each first sub-groove;
and oxidizing the polycrystalline silicon layer, forming an oxide layer on the exposed surface of the oxidized polycrystalline silicon layer to obtain the virtual channel hole, wherein the oxidized polycrystalline silicon layer and the oxide layer form the virtual channel filling layer.
7. The method of claim 6, wherein forming a polysilicon layer on exposed surfaces of each of the first sub-recesses comprises:
forming a preliminary polysilicon layer in the groove in which the first sub-groove is formed;
and removing part of the prepared polysilicon layer to expose the side walls of the dielectric layer and the sacrificial layers in the grooves, and forming the polysilicon layer by the residual prepared polysilicon layer.
8. The method of any of claims 5 to 7, wherein after forming a preliminary stack structure and a dielectric layer on a substrate prior to forming a recess in the dielectric layer and the preliminary stack structure, the method further comprises:
forming a preparation channel hole in the dielectric layer and the preparation stacking structure;
forming a charge blocking layer, an electron capturing layer, a tunneling layer and a channel layer on the bottom wall and the side wall of the preparation channel hole in sequence;
and sequentially filling silicon oxide and polysilicon in the rest of the preparation channel holes to fill the preparation channel holes to obtain channel holes.
9. The method of any of claims 5 to 7, wherein replacing each sacrificial layer with a metal layer comprises:
forming a gate line slit in the dielectric layer and the preliminary stacked structure;
removing the sacrificial layers through the gate line slits to obtain a plurality of second sub-grooves;
sequentially filling titanium nitride and tungsten into the gate line slits and the second sub-grooves to form a plurality of metal layers;
and removing the titanium nitride and the tungsten in the gate line slit.
10. The method of claim 9, wherein after replacing each sacrificial layer with a metal layer, the method further comprises:
and sequentially filling silicon oxide and polysilicon into the gate line slits to obtain the gate lines.
11. A three-dimensional memory comprising the semiconductor device of any one of claims 1 to 4 or obtained by the method of any one of claims 5 to 10.
12. A storage system comprising the three-dimensional memory of claim 11 and a storage controller, the three-dimensional memory configured to store data, the storage controller coupled to the three-dimensional memory and configured to control the three-dimensional memory.
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