CN114628401A - Method for manufacturing semiconductor device and semiconductor device - Google Patents

Abstract

The application provides a manufacturing method of a semiconductor device and the semiconductor device. The method comprises the following steps: providing an initial bonding structure with a memory array and a CMOS structure, wherein the memory array comprises a substrate, a stacking structure and a plurality of contact structures, and the contact structures penetrate through the stacking structure; removing the substrate to form a plurality of virtual channel holes and gate line slits which penetrate through the exposed stacked structure; the sacrificial layer in the gate line slit is replaced with a metal layer. The method does not need to consider a process window of the virtual channel hole when manufacturing the contact structure, and also does not need to consider the problem that the contact structure is contacted with the virtual channel hole due to the problems of inclination, bending and the like of the virtual channel hole, thereby ensuring that the process window of the contact structure is larger, and simultaneously ensuring that the virtual channel hole can better support the stacked structure.

Description

Method for manufacturing semiconductor device and semiconductor device

Technical Field

The present disclosure relates to the field of semiconductors, and in particular, to a method for manufacturing a semiconductor device and a semiconductor device.

Background

With the increasing number of layers of the 3D NAND, the tilting (tilting) problem and the bending (shift) problem of the virtual channel Hole (Dummy channel Hole) and the contact structure (contin contact structure) become more and more serious. In order to ensure that a process window (process window) of the contact structure is large, the critical dimension of the virtual channel hole needs to be shrunk, a large Margin (Margin) is reserved for the process window of the contact structure, and short circuit between WLs (word lines) caused by contact between the contact structure and the virtual channel hole when the contact structure is formed by etching is avoided. However, the shrinkage of the virtual channel hole can cause insufficient support of WL (Word Line), and a WL Bending (Bending) problem occurs, which affects the electrical performance of the device.

The above information disclosed in this background section is only for enhancement of understanding of the background of the technology described herein and, therefore, certain information may be included in the background that does not form the prior art that is already known in this country to a person of ordinary skill in the art.

Disclosure of Invention

The present application mainly aims to provide a method for manufacturing a semiconductor device and a semiconductor device, so as to solve the problem that the prior art cannot ensure a larger process window of a contact structure while ensuring a better supporting effect of a virtual channel hole.

According to an aspect of the embodiments of the present invention, there is provided a method for manufacturing a semiconductor device, including: providing an initial bonding structure, wherein the initial bonding structure comprises a storage array structure and a CMOS structure which are bonded and connected, the storage array structure comprises a substrate, a stacking structure and a plurality of contact structures, the stacking structure is positioned on the surface of the substrate close to the CMOS structure, the stacking structure comprises insulating medium layers and sacrificial layers which are alternately stacked, and the contact structures penetrate through part of the stacking structure and are in one-to-one correspondence with the sacrificial layers; removing the substrate to expose the stacked structure; sequentially forming a plurality of virtual channel holes and gate line slits, which penetrate through the exposed stacked structure, wherein the virtual channel holes and the contact structure are alternately arranged, and the gate line slits are positioned at one side of the virtual channel holes and the contact structure; and replacing the sacrificial layer with a metal layer through the gate line slit.

Optionally, providing an initial bonding structure comprising: providing the CMOS structure; providing the storage array structure, wherein the storage array structure further comprises a dielectric layer, a virtual gate line slit and a sacrificial material, the dielectric layer is located on the surface, far away from the substrate, of the stacking structure, each contact structure penetrates through the dielectric layer to be in contact with the corresponding sacrificial layer, the virtual gate line slit penetrates through the dielectric layer to the substrate, and the sacrificial material is filled in the virtual gate line slit; and bonding the CMOS structure and the memory array structure to obtain the initial bonding structure.

Optionally, removing the substrate to expose the stacked structure comprises: removing the substrate to expose the stacked structure and the sacrificial material, and sequentially forming a plurality of virtual channel holes and gate line slits through the exposed stacked structure, including: forming each of the dummy channel holes through the exposed stack structure to the dielectric layer; and removing the sacrificial material to obtain the gate line slit.

Optionally, providing the memory array structure comprises: providing the substrate, and sequentially arranging the stacking structure and the dielectric layer on the exposed surface of the substrate; forming the dummy gate line slit penetrating the dielectric layer, the stacked structure and into the substrate; filling the dummy gate line slits with the sacrificial material; and forming the contact structure penetrating through the dielectric layer to the surface of each sacrificial layer on one side of the virtual gate line slit to obtain the storage array structure.

Optionally, forming the dummy gate line slit through the dielectric layer, the stacked structure and into the substrate includes: sequentially etching the dielectric layer, the stacked structure and the substrate to form a groove; and carrying out wet oxidation on the groove to obtain the virtual gate line slit.

Optionally, providing the substrate, the stacked structure, and the dielectric layer in sequence includes: providing the substrate; forming the stacked structure on an exposed surface of the substrate; removing a portion of the stacked structure to form a plurality of continuous step structures; and forming the dielectric layer on the exposed surface of the stacked structure with the step structure.

Optionally, the sacrificial material comprises carbon.

Optionally, the storage array structure further includes a plurality of channel holes and a filling structure located in the channel holes, the channel holes penetrate through the stacked structure to the substrate, and the filling structure includes a high-K dielectric layer, a charge blocking layer, an electron trapping layer, a tunneling layer, and a channel layer sequentially arranged in a direction away from a sidewall of the channel holes.

Optionally, the high-K dielectric layer includes aluminum oxide.

According to another aspect of the embodiments of the present invention, there is also provided a semiconductor device manufactured by any one of the methods.

In an embodiment of the present invention, an initial bonding structure having a memory array structure and a CMOS structure is first provided, the memory array structure includes a substrate, a stacked structure, and a plurality of contact structures, the contact structures penetrate through the stacked structure, the substrate is then removed, a plurality of dummy channel holes and gate line slits penetrating through the exposed stacked structure are formed, and finally, the sacrificial layer is replaced with a metal layer through the gate line slits. In the method, a storage array structure in an initial bonding structure comprises a contact structure, namely the contact structure is formed, then the substrate is removed to expose the stacked structure, and a plurality of virtual channel holes and gate line slits are formed from the side of the exposed stacked structure (namely from the back of the storage array structure), so that a process window of the virtual channel holes does not need to be considered when the contact structure is manufactured, the problem that the contact structure is contacted with the virtual channel holes due to the problems of inclination, bending and the like of the virtual channel holes does not need to be considered, and the process window of the contact structure is ensured to be larger; compared with the method of forming the virtual channel hole from the front side, due to practical process limitation, the aperture of one end of the virtual channel hole far away from the CMOS structure is smaller than the aperture of one end of the virtual channel hole close to the CMOS structure, and bending or tilting generally occurs at one end of the virtual channel hole far away from the CMOS structure, so that the supporting effect of the virtual channel hole on the stacked structure is poor. The performance of the bonding structure is better, and the stacking structure with higher layers of the bonding structure is ensured.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this application, are included to provide a further understanding of the application, and the description of the exemplary embodiments and illustrations of the application are intended to explain the application and are not intended to limit the application. In the drawings:

fig. 1 shows a flow chart of a method of fabricating a semiconductor device according to an embodiment of the present application;

fig. 2 to 25 respectively show schematic structural diagrams obtained after respective process steps of a manufacturing method of a semiconductor device according to the present application.

Wherein the figures include the following reference numerals:

10. a storage array structure; 20. a CMOS structure; 100. a substrate; 101. a stacked structure; 102. a contact structure; 103. an insulating dielectric layer; 104. a sacrificial layer; 105. a metal layer; 106. a virtual channel hole; 107. a gate line slit; 108. a dielectric layer; 109. a sacrificial material; 110. filling the structure; 111. a channel hole; 112. a step structure; 113. a third groove; 114. an insulating section; 115. a high-K dielectric layer; 116. a charge blocking layer; 117. an electron trapping layer; 118. a tunneling layer; 119. a channel layer; 120. a third layer of insulating material; 121. a first layer of insulating material; 122. a metal transition layer; 123. a layer of metallic material; 124. a second layer of insulating material; 125. an outgoing line; 126. a fourth groove; 127. a fourth layer of insulating material; 128. a metal material; 129. a fifth insulating material layer; 130. a polysilicon layer; 131. a second substrate; 132. and a fifth groove.

Detailed Description

It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict. The present application will be described in detail below with reference to the embodiments with reference to the attached drawings.

In order to make the technical solutions better understood by those skilled in the art, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only partial embodiments of the present application, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

It should be noted that the terms "first," "second," and the like in the description and claims of this application and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It should be understood that the data so used may be interchanged under appropriate circumstances such that embodiments of the application described herein may be used. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present. Also, in the specification and claims, when an element is described as being "connected" to another element, the element may be "directly connected" to the other element or "connected" to the other element through a third element.

As mentioned in the background art, the prior art cannot ensure a good supporting effect of the virtual channel hole and a large process window of the contact structure, and in order to solve the above problems, in an exemplary embodiment of the present invention, a method for manufacturing a semiconductor device and a semiconductor device are provided.

According to an embodiment of the present application, a method of fabricating a semiconductor device is provided.

Fig. 1 is a flow chart of a method of fabricating a semiconductor device according to an embodiment of the present application. As shown in fig. 1, the method comprises the steps of:

step S101, providing an initial bonding structure as shown in fig. 10 or fig. 22, where the initial bonding structure includes a memory array structure 10 and a CMOS structure 20 that are bonded and connected, the memory array structure 10 includes a substrate 100, a stack structure 101, and a plurality of contact structures 102, the stack structure 101 is located on a surface of the substrate 100 close to the CMOS structure 20, the stack structure 101 includes insulating dielectric layers 103 and sacrificial layers 104 that are alternately stacked, and the contact structures 102 penetrate through a portion of the stack structure 101 and are in contact with the sacrificial layers 104 in a one-to-one correspondence manner;

step S102, removing the substrate 100 to expose the stacked structure 101, so as to obtain the structure shown in fig. 11;

step S103, as shown in fig. 14 or fig. 24, sequentially forming a plurality of dummy channel holes 106 and gate line slits 107 penetrating the exposed stacked structure, wherein the dummy channel holes 106 and the contact structures 102 are alternately disposed, and the gate line slits 107 are located at one side of the dummy channel holes 106 and the contact structures 102;

in step S104, the sacrificial layer 104 is replaced with a metal layer 105 through the gate line slit 107, thereby obtaining the structure shown in fig. 16 or 25.

In the method, an initial bonding structure with a memory array structure and a CMOS structure is provided, the memory array structure includes a substrate, a stacked structure, and a plurality of contact structures, the contact structures penetrate the stacked structure, the substrate is removed to form a plurality of virtual channel holes and gate line slits penetrating the exposed stacked structure, and the sacrificial layer is replaced with a metal layer through the gate line slits. In the method, a storage array structure in an initial bonding structure comprises a contact structure, namely the contact structure is formed, then the substrate is removed to expose the stacked structure, and a plurality of virtual channel holes and gate line slits are formed from the side of the exposed stacked structure (namely from the back of the storage array structure), so that a process window of the virtual channel holes does not need to be considered when the contact structure is manufactured, the problem that the contact structure is contacted with the virtual channel holes due to the problems of inclination, bending and the like of the virtual channel holes does not need to be considered, and the process window of the contact structure is ensured to be larger; compared with the method of forming the virtual channel hole from the front side, due to practical process limitation, the aperture of one end of the virtual channel hole far away from the CMOS structure is smaller than the aperture of one end of the virtual channel hole close to the CMOS structure, and bending or tilting generally occurs at one end of the virtual channel hole far away from the CMOS structure, so that the supporting effect of the virtual channel hole on the stacked structure is poor. The performance of the bonding structure is better, and the stacking structure with higher layers of the bonding structure is ensured.

In a specific embodiment of the present application, an initial bonding structure is provided, comprising: as shown in fig. 10 or fig. 22, the above-described CMOS structure 20 is provided; providing the memory array structure 10 shown in fig. 8 or fig. 21, wherein the memory array structure further includes a dielectric layer 108, a dummy gate line slit, and a sacrificial material 109, the dielectric layer 108 is located on a surface of the stacked structure 101 away from the substrate 100, each of the contact structures 102 penetrates through the dielectric layer 108 and contacts with the corresponding sacrificial layer 104, the dummy gate line slit penetrates through the dielectric layer 108 into the substrate 100, and the sacrificial material 109 is filled in the dummy gate line slit; the CMOS structure 20 and the memory array structure 10 are bonded to obtain the initial bonding structure shown in fig. 10 or 22. In the embodiment, the contact structure and the virtual gate line slit are formed on the front surface of the storage array structure, the sacrificial material is filled in the virtual gate line slit, and then bonding is performed, so that when the gate line slit is manufactured on the back surface of the storage array structure subsequently, the gate line slit can be obtained only by removing the sacrificial material, the problem that the bonded storage array structure is bent or deformed to further influence the bonding effect due to the fact that the gate line slit is formed on the back surface through a high-temperature process is solved, and the good performance of the bonding structure is further ensured.

In order to further ensure that the process of forming the dummy trench holes and the gate line slits in the memory array structure is simple, in another embodiment of the present invention, as shown in fig. 10 and 11 or fig. 22 and 23, the removing the substrate to expose the stacked structure includes: removing the substrate 100 to expose the stacked structure 101 and the sacrificial material 109, as shown in fig. 12 to 14, or as shown in fig. 23 and 24, sequentially forming a plurality of dummy channel holes and gate line slits through the exposed stacked structure, including: forming each of the dummy channel holes 106 through the exposed stacked structure 101 to the dielectric layer; the sacrificial material 109 is removed to obtain the gate line slit 107. Because the dummy gate line slits are formed and the dummy gate line slits are filled with the sacrificial material before the bonding of the storage array structure and the CMOS structure, when the gate line slits are manufactured on the back surface of the bonded storage array structure, the sacrificial material is only required to be removed to obtain the gate line slits meeting the requirements, the bonded storage array structure is not affected, the problem that the bonded storage array structure is bent or expanded is further avoided, and the electrical property of the semiconductor device is further ensured to be good.

According to another specific embodiment of the present application, as shown in fig. 2 to 8, or as shown in fig. 19 to 21, there is provided the above memory array structure, including: providing the substrate 100, and sequentially disposing the stacked structure 101 and the dielectric layer 108 on an exposed surface of the substrate 100, so as to obtain a structure as shown in fig. 2 or fig. 19; forming the dummy gate line slit penetrating the dielectric layer 108, the stacked structure 101 and the substrate 100; filling the dummy gate line slits with the sacrificial material 109 to obtain the structure shown in fig. 7 or fig. 20; as shown in fig. 8 or 21, the contact structure 102 is formed on one side of the dummy gate line slit, and penetrates through the dielectric layer 108 to the surface of each sacrificial layer 104, so as to obtain the memory array structure 10. The contact structure is formed on the front surface of the storage array structure, then bonding is carried out, and the subsequent virtual channel hole is formed, so that the problem that the contact structure is contacted with the virtual channel hole due to the consideration of the process window of the virtual channel hole, the inclination and the bending of the virtual channel hole and the like during the formation of the contact structure is further avoided, and the process window of the contact structure is further ensured to be larger.

In another specific embodiment of the present application, the forming the dummy gate line slit penetrating through the dielectric layer and the stacked structure into the substrate includes: etching the dielectric layer, the stacked structure and the substrate in sequence to form a groove; and carrying out wet oxidation on the groove to obtain the virtual gate line slit. In order to obtain the dummy gate line slit, in this embodiment, the dielectric layer, the stacked structure, and the substrate are sequentially etched to form a groove of the gate line slit, and then the groove is wet-oxidized to obtain the dummy gate line slit. Of course, the process of obtaining the dummy gate line slit is not limited to the wet oxidation, and may be any other process that is feasible in the prior art. Note that, in order to distinguish from other grooves described below, the groove described above is referred to as a first groove in the following description.

In order to ensure that the manufacturing process of the contact structure is simple and easy, in another specific embodiment of the present application, as shown in fig. 19, providing the substrate, the stacked structure, and the dielectric layer in sequence includes: providing the substrate 100; forming a stacked structure 101 on an exposed surface of the substrate, wherein the stacked structure 101 includes the insulating dielectric layers 103 and the sacrificial layers 104 alternately stacked; removing part of the stacked structure 101 to form a plurality of continuous step structures 112; the dielectric layer 108 is formed on the exposed surface of the stacked structure 101 on which the step structure 112 is formed. Each step structure is composed of a sacrificial layer and an insulating medium layer which are sequentially arranged along the direction far away from the substrate, and then the contact structure is formed and penetrates through the insulating medium layer of the corresponding step structure to reach the surface of the sacrificial layer or the sacrificial layer. In an actual application process, in order to ensure that the contact structure can stop on the surface of the corresponding sacrificial layer or in the sacrificial layer, the thickness of each insulating dielectric layer in the preliminary stacked structure is smaller than that of each sacrificial layer.

Of course, in order to simplify the process, the step structure may not be formed, and in another specific embodiment of the present application, as shown in fig. 2, the substrate, the stacked structure, and the dielectric layer are provided in sequence, and include: providing the substrate 100; forming the stacked structure 101 on an exposed surface of the substrate 100, wherein the stacked structure 101 includes the insulating dielectric layers 103 and the sacrificial layers 104 alternately stacked; the dielectric layer 108 is formed on the exposed surface of the stacked structure 101, resulting in the structure shown in fig. 2. Then, by setting the critical dimension of each contact structure and the corresponding etching parameters, a plurality of contact structures 102 penetrating through the surface of the corresponding sacrificial layer 104 or in the sacrificial layer are formed, so as to obtain the memory array structure 10 shown in fig. 8. Specifically, as shown in fig. 9, a second groove is formed first, then a first insulating material layer 121 is formed on the sidewall of the second groove, a metal transition layer 122 is formed on the surface of the first insulating material layer 121 away from the sidewall and the bottom and top of the groove, a metal material layer 123 is formed on the surface of the metal transition layer away from the first insulating material layer 121, and a second insulating material layer 124 is formed on the surface of the metal material layer 123 away from the metal transition layer 122, so as to obtain the contact structure. After forming the plurality of contact structures 102, bonding is performed with the CMOS structure 20 resulting in an initial bonded structure as shown in fig. 10 or as shown in fig. 23.

In practical applications, the insulating dielectric layer may include silicon oxide, the sacrificial layer may include silicon nitride, and the dielectric layer may include silicon oxide. In a specific embodiment, the insulating dielectric layer is made of silicon dioxide, the sacrificial layer is made of silicon nitride, and the dielectric layer is made of silicon dioxide. Of course, the materials of the insulating dielectric layer, the sacrificial layer and the dielectric layer are not limited to the above materials, and those skilled in the art can select suitable materials for the insulating dielectric layer, the sacrificial layer and the dielectric layer.

It should be noted that, each step in the above-mentioned embodiment of forming the substrate can be implemented in a feasible manner in the prior art. The substrate may be selected according to actual requirements of the device, and may include a Silicon substrate, a germanium substrate, a Silicon germanium (sige) substrate, an SOI (Silicon On Insulator) substrate, or a GOI (germanium On Insulator) substrate. In other embodiments, the substrate may also be a substrate including other element semiconductors or compound semiconductors, such as GaAs, InP, SiC, or the like, may also be a stacked structure, such as Si/SiGe, or the like, and may also be another epitaxial structure, such as SGOI (silicon germanium on insulator) or the like. Of course, it may also be other substrates feasible in the art.

In yet another embodiment of the present application, the sacrificial material comprises carbon. In practical applications, the sacrificial material may be other materials, and those skilled in the art may select the material according to practical situations.

In another embodiment of the present invention, as shown in fig. 8 or 21, the memory array structure further includes a plurality of channel holes 111, the channel holes 111 penetrate through the stacked structure 101 onto the surface of the substrate 100, as shown in fig. 6, the channel holes are formed by forming a third recess, and then sequentially depositing a high-K dielectric layer 115, a charge blocking layer 116, an electron trapping layer 117, a tunneling layer 118, a channel layer 119, and a third insulating material layer 120 on sidewalls of the third recess to obtain the channel holes, the channel holes further include a filling structure 110, the filling structure 110 is filled in the remaining third recess, and the filling structure is in contact with a portion of the tunneling layer 118, a portion of the channel layer 119, and a portion of the third insulating material layer 120. In this embodiment, a channel hole is formed before bonding, that is, the channel hole including a high-K dielectric layer is formed from the front side of the memory array structure, so that the problem that the high-K dielectric layer is formed at a high temperature on the back side of the memory array structure after bonding, and a high-temperature process may have a negative effect on the structure after bonding is solved, and the structure after bonding is further ensured to have good performance.

In a specific embodiment, during the etching process to form the channel hole, the sacrificial layer and the insulating dielectric layer have a dry etching selection ratio of almost 1:1, and when the sacrificial layer parallel to the substrate direction is replaced by a conductive layer, the sacrificial layer and the insulating dielectric layer have a high wet etching selection ratio, which may be 30:1 or even higher, for example, and the number of layers of the stacked structure may be determined according to specific needs.

The material of each structural layer may also be any feasible material in the prior art, for example, the material of the charge blocking layer may be silicon dioxide, the material of the electron trapping layer may be silicon nitride, the material of the tunneling layer may be silicon dioxide, the material of the channel layer may be polysilicon, the material of the filling structure may be polysilicon, and the third insulating material layer may be silicon dioxide.

These structural layers described above may be formed via one or more of Molecular Beam Epitaxy (MBE), Metal Organic Chemical Vapor Deposition (MOCVD), Metal Organic Vapor Phase Epitaxy (MOVPE), Hydride Vapor Phase Epitaxy (HVPE), and/or other well-known crystal growth processes.

In yet another embodiment of the present application, the high-K dielectric layer includes aluminum oxide. In practical application, the high-K dielectric layer may be aluminum oxide, or may be other materials.

According to another aspect of the embodiments of the present invention, there is also provided a semiconductor device manufactured by any one of the above methods.

The semiconductor device described above, which is manufactured by any of the above-described methods. In the method, a storage array structure in an initial bonding structure comprises a contact structure, namely the contact structure is formed, then the substrate is removed to expose the stacked structure, and a plurality of virtual channel holes and gate line slits are formed from the side of the exposed stacked structure (namely from the back of the storage array structure), so that a process window of the virtual channel holes does not need to be considered when the contact structure is manufactured, the problem that the contact structure is contacted with the virtual channel holes due to the problems of inclination, bending and the like of the virtual channel holes does not need to be considered, and the process window of the contact structure is ensured to be larger; compared with the method of forming the virtual channel hole from the front side, due to practical process limitation, the aperture of one end of the virtual channel hole far away from the CMOS structure is smaller than the aperture of one end of the virtual channel hole close to the CMOS structure, and bending or tilting generally occurs at one end of the virtual channel hole far away from the CMOS structure, so that the supporting effect of the virtual channel hole on the stacked structure is poor. The performance of the semiconductor device is better, and the semiconductor device can be guaranteed to have a stacked structure with a higher layer number.

In order to make the technical solutions of the present application clearly understood by those skilled in the art, the following description will be made with reference to the embodiments.

Example 1

A method for manufacturing a semiconductor device comprises the following steps:

providing a substrate 100, a stacked structure 101 and a dielectric layer 108 stacked in sequence, wherein the stacked structure 101 is formed by alternately stacking an insulating dielectric layer 103 and a sacrificial layer 104, so as to obtain a structure as shown in fig. 2, it should be noted that, for convenience of description and distinction, the substrate 100 is referred to as a first substrate in the following description;

as shown in fig. 2 and fig. 3, forming a third recess 113 in the dielectric layer 108 and the stacked structure 101 to obtain the structure shown in fig. 3;

as shown in fig. 4, removing the exposed portion of the sacrificial layer 104 in the third groove to form a sub-groove in the third groove, and then forming an insulating portion 114 in the sub-groove, wherein the insulating portion may be made of silicon dioxide;

as shown in fig. 5 and 6, a high-K dielectric layer 115, a charge blocking layer 116, an electron trapping layer 117, a tunneling layer 118, and a channel layer 119 are sequentially formed on the sidewall of the third recess where the insulating portion 114 is formed, and then a third insulating material layer 120 and a filling structure 110 are sequentially filled in the remaining third recess to fill the third recess, so as to obtain the channel hole 111;

forming a dummy gate line slit penetrating the dielectric layer 108, the stacked structure 101 and the first substrate on one side of the channel hole 111, and filling a sacrificial material 109 in the dummy gate line slit to obtain the structure shown in fig. 7;

as shown in fig. 8, forming a plurality of contact structures 102 on one side of the channel holes and the sacrificial material 109, where the contact structures 102 pass through the dielectric layer 108, penetrate through part of the stacked structures 101, and contact with the sacrificial layers 104 in a one-to-one correspondence manner, so as to obtain the memory array structure 10; as shown in fig. 8 and 9, the contact structure 102 is formed by forming a second groove in the dielectric layer 108 and the stacked structure 101, forming a first insulating material layer 121 on the sidewall of the second groove, forming a metal transition layer 122 on the surface of the first insulating material layer 121 away from the sidewall and on the bottom and top of the groove, forming a metal material layer 123 on the surface of the metal transition layer away from the first insulating material layer 121, and forming a second insulating material layer 124 on the surface of the metal material layer 123 away from the metal transition layer 122 to fill up the second groove, so as to obtain the contact structure 102. In fig. 8, lead lines 125 are provided on the surfaces of the contact structure 102, the channel hole 111, and the sacrificial material 109, which are away from the first substrate, and the lead lines 125 may be made of a metal material;

as shown in fig. 10, providing a CMOS structure 20, and bonding the CMOS structure 20 and the memory array structure 10 to obtain an initial bonding structure;

removing the first substrate in the initial bonding structure to expose the stacked structure 101, so as to obtain the structure shown in fig. 11;

forming a fourth recess 126 penetrating the stacked structure 101 to the dielectric layer 108, as shown in fig. 12;

as shown in fig. 12 and 13, depositing a fourth insulating material layer 127 in the fourth recess 126 and on the surface of the stacked structure 101 away from the CMOS structure 20, forming a dummy channel hole 106 in the filled fourth recess, and removing the sacrificial material in the dummy gate line slit to obtain a gate line slit 107, thereby obtaining the structure shown in fig. 14;

as shown in fig. 14, 15 and 16, the sacrificial layers are removed through the gate line slits 107 to form a plurality of fifth grooves 132, and then the fifth grooves 132 are filled with a metal material 128 through the gate line slits 107 to form a metal layer 105, specifically, the metal layer is composed of a titanium nitride layer and a tungsten layer;

removing the metal material 128 on the surface of the fourth insulating material layer 127 and the metal material 128 in the gate line slit 107 shown in fig. 16, and sequentially depositing a fifth insulating material layer 129 and a polysilicon layer 130 in the gate line slit 107 to form a gate line, thereby obtaining the structure shown in fig. 17;

as shown in fig. 17 and 18, the fourth insulating material layer 127 and the insulating dielectric layer 103 in contact with the fourth insulating material layer 127 are removed, and then a substrate material is deposited to form a second substrate 131.

Example 2

A method for manufacturing a semiconductor device comprises the following steps:

as shown in fig. 19, a substrate 100, a stacked structure 101 and a dielectric layer 108 are provided, which are stacked in sequence, the stacked structure 101 is formed by alternately stacking an insulating dielectric layer 103 and a sacrificial layer 104, one end of the stacked structure 101 has a step structure 112, it should be noted that, for convenience of description and distinction, the substrate 100 is referred to as a first substrate in the following description;

forming a channel hole 111 and a dummy gate line slit in the dielectric layer 108 and the stacked structure 101, and a sacrificial material 109 in the dummy gate line slit to obtain a structure as shown in fig. 20, where a specific structure of the channel hole 111 is shown in fig. 6 and is not described herein again;

as shown in fig. 21, forming a plurality of contact structures 102 on one side of the channel hole and the sacrificial material 109, where the contact structures 102 pass through the dielectric layer 108, penetrate through the partial stacked structures 101, and contact with the sacrificial layers 104 in a one-to-one correspondence manner, so as to obtain a memory array structure 10; the specific structure of the contact structure 102 is shown in fig. 9. In fig. 21, lead lines 125 are provided on the surfaces of the contact structure 102, the channel hole 111, and the sacrificial material 109, which are away from the first substrate, and the lead lines 125 may be made of a metal material;

as shown in fig. 22, providing a CMOS structure 20, and bonding the CMOS structure 20 and the memory array structure 10 to obtain an initial bonding structure;

removing the first substrate in the initial bonding structure to expose the stacked structure 101 and form a plurality of dummy channel holes 106 penetrating the stacked structure 101 to the dielectric layer 108, so as to obtain the structure shown in fig. 23;

removing the sacrificial material 109 in the dummy gate line slits shown in fig. 23 to obtain gate line slits 107, as shown in fig. 24;

as shown in fig. 24 and 25, each of the sacrificial layers is replaced with a metal layer 105 through the gate line slit 107, and specifically, the metal layer is composed of a titanium nitride layer and a tungsten layer;

the subsequent manufacturing process is the same as that of embodiment 1, and is not described herein again.

From the above description, it can be seen that the above-mentioned embodiments of the present application achieve the following technical effects:

1) the manufacturing method of the semiconductor device comprises the steps of firstly providing an initial bonding structure with a storage array structure and a CMOS structure, wherein the storage array structure comprises a substrate, a stacking structure and a plurality of contact structures, the contact structures penetrate through the stacking structure, then removing the substrate to form a plurality of virtual channel holes and gate line slits, which penetrate through the exposed stacking structure, and finally replacing a sacrificial layer with a metal layer through the gate line slits. In the method, a storage array structure in an initial bonding structure comprises a contact structure, namely the contact structure is formed, then the substrate is removed to expose the stacked structure, and a plurality of virtual channel holes and gate line slits are formed from the side of the exposed stacked structure (namely from the back of the storage array structure), so that a process window of the virtual channel holes does not need to be considered when the contact structure is manufactured, the problem that the contact structure is contacted with the virtual channel holes due to the problems of inclination, bending and the like of the virtual channel holes does not need to be considered, and the process window of the contact structure is ensured to be larger; compared with the method of forming the virtual channel hole from the front side, due to practical process limitation, the aperture of one end of the virtual channel hole far away from the CMOS structure is smaller than the aperture of one end of the virtual channel hole close to the CMOS structure, and bending or tilting generally occurs at one end of the virtual channel hole far away from the CMOS structure, so that the supporting effect of the virtual channel hole on the stacked structure is poor. The performance of the bonding structure is better, and the stacking structure with higher layer number of the bonding structure is ensured.

2) The semiconductor device of the present application is manufactured by any one of the above methods. In the method, a storage array structure in an initial bonding structure comprises a contact structure, namely the contact structure is formed, then the substrate is removed to expose the stacked structure, and a plurality of virtual channel holes and gate line slits are formed from the side of the exposed stacked structure (namely from the back of the storage array structure), so that a process window of the virtual channel holes does not need to be considered when the contact structure is manufactured, the problem that the contact structure is contacted with the virtual channel holes due to the problems of inclination, bending and the like of the virtual channel holes does not need to be considered, and the process window of the contact structure is ensured to be larger; compared with the method of forming the virtual channel hole from the front side, due to practical process limitation, the aperture of one end of the virtual channel hole far away from the CMOS structure is smaller than the aperture of one end of the virtual channel hole close to the CMOS structure, and bending or tilting generally occurs at one end of the virtual channel hole far away from the CMOS structure, so that the supporting effect of the virtual channel hole on the stacked structure is poor. The semiconductor device is guaranteed to have good performance, and the semiconductor device can be guaranteed to have a stacked structure with a high layer number.

The above description is only a preferred embodiment of the present application and is not intended to limit the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims (10)

1. A method for manufacturing a semiconductor device, comprising:

providing an initial bonding structure, wherein the initial bonding structure comprises a storage array structure and a CMOS structure which are bonded and connected, the storage array structure comprises a substrate, a stacking structure and a plurality of contact structures, the stacking structure is positioned on the surface of the substrate close to the CMOS structure, the stacking structure comprises insulating medium layers and sacrificial layers which are alternately stacked, and the contact structures penetrate through part of the stacking structure and are in one-to-one correspondence with the sacrificial layers;

removing the substrate to expose the stacked structure;

sequentially forming a plurality of virtual channel holes and gate line slits which penetrate through the exposed stacked structure, wherein the virtual channel holes and the contact structure are alternately arranged, and the gate line slits are positioned at one sides of the virtual channel holes and the contact structure;

and replacing the sacrificial layer with a metal layer through the gate line slit.

2. The method of claim 1, wherein providing an initial bonded structure comprises:

providing the CMOS structure;

providing the storage array structure, wherein the storage array structure further comprises a dielectric layer, a virtual gate line slit and a sacrificial material, the dielectric layer is located on the surface, far away from the substrate, of the stacking structure, each contact structure penetrates through the dielectric layer to be in contact with the corresponding sacrificial layer, the virtual gate line slit penetrates through the dielectric layer to the substrate, and the sacrificial material is filled in the virtual gate line slit;

and bonding the CMOS structure and the storage array structure to obtain the initial bonding structure.

3. The method of claim 2,

removing the substrate to expose the stacked structure, comprising:

removing the substrate to expose the stacked structure and the sacrificial material,

sequentially forming a plurality of virtual channel holes and gate line slits through the exposed stack structure, including:

forming each dummy channel hole penetrating the exposed stacked structure into the dielectric layer;

and removing the sacrificial material to obtain the gate line slit.

4. The method of claim 2, wherein providing the storage array structure comprises:

providing the substrate, and sequentially arranging the stacking structure and the dielectric layer on the exposed surface of the substrate;

forming the dummy gate line slit penetrating the dielectric layer, the stacked structure and into the substrate;

filling the dummy gate line slits with the sacrificial material;

and forming the contact structure penetrating through the dielectric layer to the surface of each sacrificial layer on one side of the virtual gate line slit to obtain the storage array structure.

5. The method of claim 4, wherein forming the dummy gate line slit through the dielectric layer, the stacked structure, and into the substrate comprises:

sequentially etching the dielectric layer, the stacked structure and the substrate to form a groove;

and carrying out wet oxidation on the groove to obtain the virtual gate line slit.

6. The method of claim 4, wherein providing the substrate, the stacked structure, and the dielectric layer in a sequential arrangement comprises:

providing the substrate;

forming the stacked structure on an exposed surface of the substrate;

removing a portion of the stacked structure to form a plurality of continuous step structures;

and forming the dielectric layer on the exposed surface of the stacked structure with the step structure.

7. The method of claim 4, wherein the sacrificial material comprises carbon.

8. The method of any of claims 1 to 6, wherein the memory array structure further comprises a plurality of channel holes penetrating the stacked structure into the substrate, wherein a high-K dielectric layer, a charge blocking layer, an electron trapping layer, a tunneling layer, and a channel layer are sequentially disposed in the channel holes along a direction away from the sidewalls.

9. The method of claim 8, wherein the high-K dielectric layer comprises aluminum oxide.

10. A semiconductor device manufactured by the method according to any one of claims 1 to 9.

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