CN114335001A - Manufacturing method of semiconductor device and semiconductor device - Google Patents

Abstract

The application provides a manufacturing method of a semiconductor device and the semiconductor device. The method comprises the following steps: forming a base structure comprising a substrate structure and a stacked structure, wherein the stacked structure comprises a plurality of insulating medium layers and gate line slits which are arranged at intervals; filling preset metal in the space between two adjacent insulating medium layers, forming a first metal layer between any two adjacent insulating medium layers, wherein the first metal layer is a word line, and forming a second metal layer on the surface of the gate line slit; injecting preset ions into the second metal layer filled with the preset metal; and removing the second metal layer. According to the method, the preset ions are injected into the second metal layer filled with the preset metal, and the preset ions can introduce vacancy type defects into the metal layer, so that the second metal layer in the gate line slit is more easily and completely removed, and the problem of electric leakage caused by the fact that the filling material in the gate line cannot be completely removed in the prior art is solved.

Description

Manufacturing method of semiconductor device and semiconductor device

Technical Field

The present disclosure relates to the field of semiconductors, and in particular, to a method for manufacturing a semiconductor device, a three-dimensional memory, and a storage system.

Background

With the continuous development of 3D NAND technology, the three-dimensional memory can be stacked vertically with more and more layers, from 24 layers, 32 layers and 64 layers to a high-level stack structure with more than 100 layers, which can greatly increase the storage density and reduce the price of a unit memory cell. But as the number of layers is gradually increased, the problem of leakage between word lines becomes more and more significant. Therefore, a method for solving the leakage problem between word lines is needed.

Disclosure of Invention

The present application provides a method for manufacturing a semiconductor device, a three-dimensional memory and a memory system, so as to solve the problem of leakage between word lines in the technical solution known by the inventors.

According to an aspect of the embodiments of the present invention, there is provided a method for manufacturing a semiconductor device, including: forming a base structure, wherein the base structure comprises a substrate structure and a stacked structure, the stacked structure is positioned on the substrate structure and comprises a body structure, a plurality of virtual channel holes and gate line slits, the virtual channel holes and the gate line slits are positioned in the body structure, the body structure comprises a plurality of insulating medium layers which are arranged at intervals, and the gate line slits penetrate through the stacked structure and are positioned in part of the substrate structure; filling a preset metal in the space between two adjacent insulating medium layers, forming a first metal layer between any two adjacent insulating medium layers, and forming a second metal layer on the surface of the gate line slit, wherein the first metal layer is a word line; injecting preset ions into the second metal layer filled with the preset metal; and removing the second metal layer.

Optionally, the predetermined ions comprise at least one of: boron ions, phosphorus ions.

Optionally, forming a base structure comprising: forming the substrate structure, and forming a preparation stacking structure on the surface of the substrate structure, wherein the preparation stacking structure comprises sacrificial layers and insulating medium layers which are alternately arranged; forming a plurality of the dummy channel holes through the preliminary stack structure; forming the gate line slit through the preliminary stacked structure and in a portion of the substrate structure; and removing the sacrificial layer in the preparation stacking structure to form the stacking structure.

Optionally, forming the substrate structure comprises: providing a substrate; forming a first insulating oxide layer, a first silicon layer, a second insulating oxide layer and a second silicon layer in sequence on the surface of the substrate, and forming a preparatory stacking structure on the surface of the substrate structure, including: and forming the preparation stacking structure on the surface of the second silicon layer far away from the second insulating oxide layer.

Optionally, forming a plurality of the virtual channel holes through the preliminary stack structure includes: forming a plurality of vias through the stacked structure; and forming a filling structure in the through holes to form a plurality of virtual channel holes.

Optionally, after removing the second metal layer, the method further includes: performing predetermined treatment on the surface of the gate line slit to form an insulating layer on the surface of the gate line slit; filling a predetermined material into the gate line slit having the insulating layer.

Optionally, the predetermined metal comprises tungsten.

According to another aspect of the embodiments of the present invention, there is also provided a semiconductor device manufactured by any one of the methods.

According to another aspect of the embodiments of the present invention, there is also provided a three-dimensional memory including a semiconductor device obtained by any one of the methods.

According to yet another aspect of the embodiments of the present invention, there is also provided a storage system including a storage controller and the three-dimensional memory, the three-dimensional memory being configured to store data, the storage controller being coupled to the three-dimensional memory and configured to control the three-dimensional memory.

In the embodiment of the invention, firstly, a base structure comprising a substrate structure and a stacked structure is formed, wherein the stacked structure comprises a plurality of insulating medium layers and gate line slits which are arranged at intervals, then, a preset metal is filled in the interval between every two adjacent insulating medium layers, a first metal layer is formed between any two adjacent insulating medium layers, the first metal layer is a word line, a second metal layer is formed on the surface of each gate line slit, the second metal layer filled with the preset metal is implanted with preset ions, and finally, the second metal layer is removed. According to the method, the preset ions are injected into the second metal layer filled with the preset metal, vacancy type defects are introduced into the metal layer by the preset ions, a large number of pores exist in the metal layer, the distance between the preset metal atoms is increased, and the bond energy between the preset metal atoms is reduced, so that when the second metal layer is removed subsequently, the chemical bonds between the preset metal in the second metal layer are easily broken, and the second metal layer in the gate line slit is easily and completely removed, so that the problem that in the prior art, the filling material in the gate line cannot be completely removed, and electric leakage occurs is effectively solved, the process difficulty of removing the conductive material in the gate line slit is reduced, and the process selection is more flexible.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this application, illustrate embodiments of the application and, together with the description, serve to explain the application and are not intended to limit the application. In the drawings:

fig. 1 shows a cross-sectional view of a semiconductor device in the prior art;

FIG. 2 shows a flow chart of a method of fabricating a semiconductor device according to an embodiment of the present application;

fig. 3 to 8 respectively show schematic structural diagrams obtained after each process step according to the method for manufacturing a semiconductor device of the present application.

Wherein the figures include the following reference numerals:

200. a substrate structure; 201. a stacked structure; 202. a virtual channel hole; 203. a gate line slit; 204. an insulating dielectric layer; 205. a first metal layer; 206. a second metal layer; 207. a sacrificial layer; 208. a substrate; 209. a first insulating oxide layer; 210. a first silicon layer; 211. a second insulating oxide layer; 212. a second silicon layer; 213. filling the structure; 214. an insulating layer; 215. and a third metal layer.

Detailed Description

It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict. The present application will be described in detail below with reference to the embodiments with reference to the attached drawings.

In order to make the technical solutions better understood by those skilled in the art, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only partial embodiments of the present application, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

It should be noted that the terms "first," "second," and the like in the description and claims of this application and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It should be understood that the data so used may be interchanged under appropriate circumstances such that embodiments of the application described herein may be used. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present. Also, in the specification and claims, when an element is described as being "connected" to another element, the element may be "directly connected" to the other element or "connected" to the other element through a third element.

At present, a phenomenon of leakage exists between word lines, and the inventor researches and discovers that as the number of layers of the 3D NAND increases, as shown in fig. 1, the top size of the gate line slit etching is larger, and the bottom size is smaller, so that after the word lines are filled, the filling material at the bottom of the gate line slit cannot be removed cleanly, and a leakage situation occurs. In addition, as the number of layers increases, the step region becomes thinner, and the contact hole easily breaks down the step region, so that a short circuit occurs between word lines. In an alternative embodiment, in order to ensure that the contact hole can stay in the step region, the sacrificial layer in the stacked structure is thickened in the step structure region, so that the contact hole can be reduced from puncturing the corresponding word line layer, and short circuit between two adjacent word lines can be caused. However, the inventor further found that, while the word line layer in the step area is thickened, for the word line layer to be sufficiently filled with the conductive layer, the conductive layer filling amount of the word line inevitably needs to be increased, that is, the thickness of the conductive filling material on the sidewall of the gate line slit is also increased, so that during the process of removing the conductive filling material in the gate line slit, due to the process limitation, it is difficult to completely remove the conductive filling material in the gate line slit, so that the word line and the word line are electrically connected together through the conductive material in the gate line slit, thereby further causing the occurrence of electric leakage. In order to solve the problem of leakage between word lines, in an exemplary embodiment of the present application, a method for manufacturing a semiconductor device, a three-dimensional memory and a memory system are provided.

According to an embodiment of the present application, a method of fabricating a semiconductor device is provided.

Fig. 2 is a flow chart of a method of fabricating a semiconductor device according to an embodiment of the present application. As shown in fig. 2, the method comprises the steps of:

step S101, forming a base structure as shown in fig. 3, where the base structure includes a substrate structure 200 and a stacked structure 201, the stacked structure 201 is located on the substrate structure 200, the stacked structure 201 includes a body structure, a plurality of virtual channel holes 202 and gate line slits 203, the body structure includes a plurality of insulating medium layers 204 arranged at intervals, and the gate line slits 203 penetrate through the stacked structure 201 and are located in part of the substrate structure 200;

step S102, filling a predetermined metal into the space between two adjacent insulating dielectric layers 204, forming a first metal layer 205 between any two adjacent insulating dielectric layers, and forming a second metal layer 206 on the surface of the gate line slit, where the first metal layer is a word line, so as to form the structure shown in fig. 4;

step S103, as shown in fig. 5, implanting predetermined ions into the second metal layer filled with the predetermined metal;

in step S104, the second metal layer 206 is removed to form the structure shown in fig. 6.

In the method, a substrate structure comprising a substrate structure and a stacked structure is formed, the stacked structure comprises a plurality of insulating medium layers and gate line slits which are arranged at intervals, then, preset metal is filled in the interval between every two adjacent insulating medium layers, a first metal layer is formed between any two adjacent insulating medium layers, the first metal layer is a word line, a second metal layer is formed on the surface of each gate line slit, the second metal layer filled with the preset metal is implanted with preset ions, and finally, the second metal layer is removed. According to the method, the preset ions are injected into the second metal layer filled with the preset metal, vacancy type defects are introduced into the metal layer by the preset ions, a large number of pores exist in the metal layer, the distance between the preset metal atoms is increased, and the bond energy between the preset metal atoms is reduced, so that when the second metal layer is removed subsequently, the chemical bonds between the preset metal in the second metal layer are easily broken, and the second metal layer in the gate line slit is easily and completely removed, so that the problem that in the prior art, the filling material in the gate line cannot be completely removed, and electric leakage occurs is effectively solved, the process difficulty of removing the conductive material in the gate line slit is reduced, and the process selection is more flexible.

In a specific embodiment, the second metal layer can be removed by an existing process, for example, an acidic liquid or a corrosive gas, and the second metal layer can be completely removed by implanting predetermined ions into the second metal layer.

In another specific embodiment, as shown in fig. 4, after filling a predetermined metal into the space between two adjacent insulating dielectric layers 204, a third metal layer 215 is also formed on the surface of the stacked structure 201 away from the substrate structure 200, and when performing the predetermined ion implantation on the second metal layer 206, the third metal layer 215 may also be ion implanted, or only the second metal layer 206 may be ion implanted.

For more complete removal of the second metal layer, in one embodiment of the present application, the predetermined ions include at least one of: boron ions, phosphorus ions. The energy ratio of boron ions and phosphorus ions is higher, so that more defects can be generated in the metal layer; in addition, when the higher the dose of the implanted predetermined ions, the more defects are generated in the metal layer by the predetermined ions, the faster and more complete the second metal layer can be removed.

Of course, in practical applications, the predetermined ions are not limited thereto, and may be other ions, such as helium ions, and those skilled in the art can select the predetermined ions according to practical situations.

In yet another embodiment of the present application, as shown in fig. 7, a base structure is formed comprising: forming the substrate structure 200, and forming a preliminary stack structure on a surface of the substrate structure 200, wherein the preliminary stack structure comprises sacrificial layers 207 and insulating medium layers 204 which are alternately arranged; forming a plurality of the dummy channel holes 202 penetrating the preliminary stacked structure; forming the gate line slit 203 penetrating the preliminary stacked structure and being located in a portion of the substrate structure 200; the sacrificial layer 207 in the preliminary stacked structure is removed to form the stacked structure. In order to form the base structure, in the present embodiment, a preliminary stacked structure having alternately arranged sacrificial layers and insulating medium layers is first formed, and then gate line slits are formed, and the sacrificial layers in the preliminary stacked structure are removed through the gate line slits to form the above-described stacked structure.

In a specific embodiment of the present application, the preliminary stacked structure further includes a plurality of channel holes, and each of the channel holes includes a charge blocking layer, an electron trapping layer, a tunneling layer, and a channel layer, which are sequentially stacked.

The material of each structural layer in the channel hole may also be any feasible material in the prior art, for example, the material of the charge blocking layer may be silicon dioxide, the material of the electron trapping layer may be silicon nitride, the material of the tunneling layer may be silicon dioxide, and the material of the channel layer may be polysilicon.

These structural layers described above may be formed via one or more of Molecular Beam Epitaxy (MBE), Metal Organic Chemical Vapor Deposition (MOCVD), Metal Organic Vapor Phase Epitaxy (MOVPE), Hydride Vapor Phase Epitaxy (HVPE), and/or other well-known crystal growth processes.

In order to further improve the performance of the semiconductor device, as shown in fig. 3, in another embodiment of the present application, the substrate structure is formed, including: providing a substrate 208; forming a first insulating oxide layer 209, a first silicon layer 210, a second insulating oxide layer 211 and a second silicon layer 212 on the surface of the substrate 208 in sequence, and forming a pre-stack structure on the surface of the substrate structure 200, including: the preliminary stack structure is formed on a surface of the second silicon layer 212 away from the second insulating oxide layer 211. The substrate structure comprises the substrate, the first insulating oxide layer, the first silicon layer, the second insulating oxide layer and the second silicon layer which are sequentially stacked, so that when a channel hole is formed subsequently, due to the existence of the first silicon layer, the first silicon layer can be oxidized to form a protrusion on the side wall of the channel hole, the adverse effect of the over-deep etching of the channel hole on the uniformity of the semiconductor device is avoided, and the performance of the semiconductor device is further improved.

The first silicon layer and the second silicon layer may be a single crystal silicon layer, a polycrystalline silicon layer, or an amorphous silicon layer, and the first silicon layer and the second silicon layer may be made of the same material or different materials.

It should be noted that, each step in the above-mentioned embodiment of forming the substrate can be implemented in a feasible manner in the prior art. The substrate may be selected according to actual requirements of the device, and may include a Silicon substrate, a germanium substrate, a Silicon germanium (sige) substrate, an SOI (Silicon On Insulator) substrate, or a GOI (germanium On Insulator) substrate. In other embodiments, the substrate may also be a substrate including other element semiconductors or compound semiconductors, such as GaAs, InP, SiC, or the like, may also be a stacked structure, such as Si/SiGe, or the like, and may also be another epitaxial structure, such as SGOI (silicon germanium on insulator) or the like. Of course, it may also be other substrates feasible in the art.

In order to form a plurality of the virtual channel holes, in another embodiment of the present application, as shown in fig. 3, forming a plurality of the virtual channel holes 202 penetrating the preliminary stacked structure includes: forming a plurality of through holes penetrating through the stacked structure; a fill structure 213 is formed in the plurality of vias to form a plurality of dummy channel holes 202.

The filling structure may be a silicon dioxide layer, that is, a silicon dioxide layer is formed in the through hole, and in practical applications, the filling structure may be not only a silicon dioxide layer, but also another structure.

In another embodiment of the present application, after removing the second metal layer, the method further includes: performing a predetermined process on the surface of the gate line slit 203 to form an insulating layer 214 on the surface of the gate line slit; a predetermined material is filled in the gate line slit having the insulating layer, thereby forming a structure as shown in fig. 8. After the second metal layer is removed, the gate line slit needs to be filled, so as to form a gate line. In order to avoid the occurrence of leakage, it is necessary to form an insulating layer on the surface of the gate line slit, and then fill the gate line slit to form the gate line.

The predetermined process may be an oxidation process, that is, an insulating oxide layer is formed on the surface of the gate slit, but the predetermined process is not limited to the oxidation process and may be a nitridation process.

The predetermined material may be not only silicon but also a metal material, and may be selected by those skilled in the art according to actual situations.

In still another embodiment of the present application, the predetermined metal includes tungsten.

Similarly, in practical applications, the predetermined metal is not limited to tungsten, but may be other metals, and those skilled in the art may select a suitable metal according to practical situations.

According to an embodiment of the present application, there is also provided a semiconductor device manufactured by any one of the above methods.

The above semiconductor device, which is formed by any of the above methods, in the method, predetermined ions are injected into the second metal layer filled with the predetermined metal, the predetermined ions can introduce vacancy type defects into the metal layer, a large number of pores exist in the metal layer, such that the distance between the predetermined metal atoms is increased, resulting in a decrease in the bond energy between the predetermined metal atoms, so that, when the second metal layer is subsequently removed, the chemical bonds between the predetermined metals in the second metal layer are easily broken, therefore, the second metal layer in the gate line slit is more easily and completely removed, the problem of electric leakage caused by incomplete removal of the filling material in the gate line in the prior art can be effectively solved, the process difficulty of removing the conductive material in the gate line slit can be reduced, and the process selection is more flexible.

According to an embodiment of the present application, there is also provided a three-dimensional memory including a semiconductor device obtained by any one of the above-described methods.

The three-dimensional memory comprises a semiconductor device obtained by any one of the methods, in the method, predetermined ions are injected into the second metal layer filled with predetermined metals, the predetermined ions can introduce vacancy type defects into the metal layer, and a large number of pores exist in the metal layer, so that the distance between the predetermined metal atoms is increased, and the bond energy between the predetermined metal atoms is reduced, therefore, when the second metal layer is subsequently removed, the chemical bonds between the predetermined metals in the second metal layer are easily broken, and the second metal layer in the gate line slit is easily and completely removed, so that the problems that in the prior art, the filling material in the gate line cannot be completely removed, and electric leakage occurs can be effectively solved, the process difficulty of removing the conductive material in the gate line slit can be reduced, and the process selection is more flexible.

There is also provided, in accordance with an embodiment of the present application, a memory system, including a memory controller and the three-dimensional memory described above, the three-dimensional memory configured to store data, the memory controller coupled to the three-dimensional memory and configured to control the three-dimensional memory.

The above-mentioned storage system, including the storage controller and the above-mentioned three-dimensional memory, the above-mentioned three-dimensional memory is configured to store data, the above-mentioned storage controller is coupled to the above-mentioned three-dimensional memory and configured to control the above-mentioned three-dimensional memory, the above-mentioned three-dimensional memory includes the semiconductor device obtained by adopting any of the above-mentioned methods, in this method, the second metal layer after filling with the predetermined metal is implanted with the predetermined ions, the predetermined ions will introduce vacancy type defects in the metal layer, there are a lot of pores in the metal layer, so that the distance between the predetermined metal atoms increases, and the bond energy between the predetermined metal atoms decreases, so when the second metal layer is removed subsequently, the chemical bond between the predetermined metal in the second metal layer is easily broken, so that the second metal layer in the gate line slit is easily removed completely, so as to not only effectively solve the problem that the filling material in the gate line in the prior art cannot be removed completely, the problem of electric leakage is caused, and the process difficulty of removing the conductive material in the gate line slit can be reduced, so that the process selection is more flexible.

From the above description, it can be seen that the above-described embodiments of the present application achieve the following technical effects:

1) the manufacturing method of the semiconductor device comprises the steps of firstly, forming a base structure comprising a substrate structure and a stacking structure, wherein the stacking structure comprises a plurality of insulating medium layers and gate line slits which are arranged at intervals, then, filling preset metal into the space between every two adjacent insulating medium layers, forming a first metal layer between any two adjacent insulating medium layers, forming a second metal layer on the surface of each gate line slit, injecting preset ions into the second metal layer filled with the preset metal, and finally removing the second metal layer. According to the method, the preset ions are injected into the second metal layer filled with the preset metal, vacancy type defects are introduced into the metal layer by the preset ions, a large number of pores exist in the metal layer, the distance between the preset metal atoms is increased, and the bond energy between the preset metal atoms is reduced, so that when the second metal layer is removed subsequently, the chemical bonds between the preset metal in the second metal layer are easily broken, and the second metal layer in the gate line slit is easily and completely removed, so that the problem that in the prior art, the filling material in the gate line cannot be completely removed, and electric leakage occurs is effectively solved, the process difficulty of removing the conductive material in the gate line slit is reduced, and the process selection is more flexible.

2) The semiconductor device is formed by adopting any one of the methods, in the method, predetermined ions are injected into the second metal layer filled with predetermined metal, the predetermined ions can introduce vacancy type defects into the metal layer, a large number of pores exist in the metal layer, so that the distance between the predetermined metal atoms is increased, the bond energy between the predetermined metal atoms is reduced, and therefore when the second metal layer is removed subsequently, the chemical bonds between the predetermined metal atoms in the second metal layer are easily broken, the second metal layer in the gate line slit is easily and completely removed, the problems that in the prior art, the filling material in the gate line cannot be completely removed, the electric leakage is caused can be effectively solved, and the process difficulty for removing the conductive material in the gate line slit can be reduced, so that the process selection is more flexible.

3) The three-dimensional memory of the present application includes a semiconductor device obtained by any one of the above-described methods, in the method, predetermined ions are injected into the second metal layer filled with the predetermined metal, the predetermined ions can introduce vacancy type defects into the metal layer, a large number of pores exist in the metal layer, such that the distance between the predetermined metal atoms is increased, resulting in a decrease in the bond energy between the predetermined metal atoms, so that, when the second metal layer is subsequently removed, the chemical bonds between the predetermined metals in the second metal layer are easily broken, therefore, the second metal layer in the gate line slit is more easily and completely removed, the problem of electric leakage caused by incomplete removal of the filling material in the gate line in the prior art can be effectively solved, the process difficulty of removing the conductive material in the gate line slit can be reduced, and the process selection is more flexible.

4) The memory system comprises a memory controller and the three-dimensional memory, wherein the three-dimensional memory is configured to store data, the memory controller is coupled to the three-dimensional memory and is configured to control the three-dimensional memory, the three-dimensional memory comprises a semiconductor device obtained by adopting any one of the methods, in the method, predetermined ions are injected into a second metal layer filled with predetermined metal, the predetermined ions can introduce vacancy type defects into the metal layer, a large number of pores exist in the metal layer, the distance between the predetermined metal atoms is increased, the bonding energy between the predetermined metal atoms is reduced, when the second metal layer is removed subsequently, chemical bonds between the predetermined metal atoms in the second metal layer are easily broken, so that the second metal layer in a gate line slit is easily removed completely, and the problem that filling materials in the gate line cannot be completely removed in the prior art can be effectively solved, the problem of electric leakage is caused, and the process difficulty of removing the conductive material in the gate line slit can be reduced, so that the process selection is more flexible.

The above description is only a preferred embodiment of the present application and is not intended to limit the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims (10)

1. A method for manufacturing a semiconductor device, comprising:

forming a base structure, wherein the base structure comprises a substrate structure and a stacked structure, the stacked structure is positioned on the substrate structure and comprises a body structure, a plurality of virtual channel holes and gate line slits, the virtual channel holes and the gate line slits are positioned in the body structure, the body structure comprises a plurality of insulating medium layers which are arranged at intervals, and the gate line slits penetrate through the stacked structure and are positioned in part of the substrate structure;

filling a preset metal in the space between two adjacent insulating medium layers, forming a first metal layer between any two adjacent insulating medium layers, and forming a second metal layer on the surface of the gate line slit, wherein the first metal layer is a word line;

injecting preset ions into the second metal layer filled with the preset metal;

and removing the second metal layer.

2. The method of claim 1, wherein the predetermined ions comprise at least one of: boron ions, phosphorus ions.

3. The method of claim 1, wherein forming a base structure comprises:

forming the substrate structure, and forming a preparation stacking structure on the surface of the substrate structure, wherein the preparation stacking structure comprises sacrificial layers and insulating medium layers which are alternately arranged;

forming a plurality of the dummy channel holes through the preliminary stack structure;

forming the gate line slit through the preliminary stacked structure and in a portion of the substrate structure;

and removing the sacrificial layer in the preparation stacking structure to form the stacking structure.

4. The method of claim 3,

forming the substrate structure, including:

providing a substrate;

sequentially forming a first insulating oxide layer, a first silicon layer, a second insulating oxide layer and a second silicon layer on the surface of the substrate,

forming a preliminary stack structure on a surface of the substrate structure, comprising:

and forming the preparation stacking structure on the surface of the second silicon layer far away from the second insulating oxide layer.

5. The method of claim 3, wherein forming a plurality of the virtual channel holes through the preliminary stack structure comprises:

forming a plurality of vias through the stacked structure;

and forming a filling structure in the through holes to form a plurality of virtual channel holes.

6. The method of any of claims 1-5, wherein after removing the second metal layer, the method further comprises:

performing predetermined treatment on the surface of the gate line slit to form an insulating layer on the surface of the gate line slit;

filling a predetermined material into the gate line slit having the insulating layer.

7. The method of any one of claims 1 to 5, wherein the predetermined metal comprises tungsten.

8. A semiconductor device manufactured by the method according to any one of claims 1 to 7.

9. A three-dimensional memory comprising a semiconductor device obtained by the method of any one of claims 1 to 7.

10. A storage system comprising the three-dimensional memory of claim 9 and a storage controller, the three-dimensional memory configured to store data, the storage controller coupled to the three-dimensional memory and configured to control the three-dimensional memory.

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