CN1150334A - 半导体装置 - Google Patents

半导体装置 Download PDF

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Publication number
CN1150334A
CN1150334A CN96119946A CN96119946A CN1150334A CN 1150334 A CN1150334 A CN 1150334A CN 96119946 A CN96119946 A CN 96119946A CN 96119946 A CN96119946 A CN 96119946A CN 1150334 A CN1150334 A CN 1150334A
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Prior art keywords
outer lead
insulation coating
semiconductor device
tab
lead
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CN96119946A
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CN1071493C (zh
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钱兴燮
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Covinson Intelligent Finance N.B.868 Co.
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LG Semicon Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/4985—Flexible insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/0781—Adhesive characteristics other than chemical being an ohmic electrical conductor
    • H01L2924/07811—Extrinsic, i.e. with electrical conductive fillers

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

一种在外引线的外部具有绝缘涂敷区的改进半导体装置，可减少在粘合微小间距外引线时不合格产品的数量，它包括为了防止由于包含于ACA/ACF中的导电球在TAB外引线粘合期间引起外引线间电短路而形成在TAB带的外引线的外部的绝缘涂敷区。

Description

半导体装置
本发明涉及一种半导体装置，特别涉及一种改进半导体装置，在其外引线的外部有绝缘涂敷区，以便减小在粘合微小间距的外引线时所产生的不合格产品的数量。
通常，载带自动粘合(TAB)涉及有效表面安装型封装技术，该技术是用金属凸点直接把大规模集成电路(LSI)粘合到其上形成了金属图形的带上，即，是有关直接粘合LSI和引线框架的互连技术。与常规引线粘合技术相比，TAB技术是一种先进的互连技术。
近来，工业上一流的公司正在试图研制凸点形成技术，因为该技术是产业中的关键技术。
TAB中的凸点起着引线粘合方法中的引线的作用，形成该凸点作为能电连接LSI芯片的焊盘和TAB引线框架的金属突起物。这里，按其材料将凸点分成Au凸点和Sn/Pb凸点，并将它们分成蘑菇型凸点和直壁型凸点。
凸点粘合技术是产业中的关键技术，根据凸点形成方法可它分成以下三种制造方法。
1)引线定位法-引线凸点形成法和传递凸点形成法。(The lead frame accessingmethod-the lead bumping method and a transferred.)
2)晶片高度定位法-引线凸点形成法。(The wafer level accessing method-thewire bumping method.)
3)芯片高度定位法-引线凸点形成法。(The chip level accessing method-the wirebumping method.)
同时，上述方法分别存在以下缺点。
1)引线框定位法：该方法用一般的晶片，并适于制造各种产品和少量的该产品，然而凸起的引线带很贵。
2)晶片凸点形成法：它适于制造各种产品和少量的该产品；然而按晶片凸点形成法另需TAB工艺，精确度降低。
3)引线凸点形成法：它适于制造小尺寸管脚产品，但，它不适于制造小尺寸的多管脚产品。
把TAB工艺制造的产品传递到定位机，并安装在基片上。
图1表示常规半导体装置的外引线粘合后的一种互连。
如图1所示，在基片1的上部形成间隔开的焊盘2。此外，TAB带包括其上形成了与绝缘带的某部分上的粘结剂4有粘结力的金属图形的外引线5。通过控制压力和温度，由如各向异性的导电粘结剂或各向异性导电膜等各向异性的粘结剂粘结TAB的外引线5和基片1。
同时，将导电球6插入外引线5和焊盘2间。此外，将与导电球6无关的导电球6a插入外引线5间。但是，随着半导体产品变成多功能化，及具有高性能和多管脚结构，所以产品的焊盘/引线间距变细。
由于常规半导体装置有与导电球6无关的用于电连接的导电球6a，所以相应元件间会发生电短路。
因此，本发明的一个目的是提供一种半导体装置，克服上存在于常规半导体装置中的问题。
本发明的另一个目的是提供一种改进半导体装置，在外引线的外部有绝缘涂敷区，以便减小在粘合微小间距的外引线时所产生的不合格产品的数量。
为了实现上述目的，本发明提供一种半导体装置，包括形成在TAB带的外引线的外部的绝缘涂敷区，以便防止在TAB外引线粘合时，由包含在ACA/ACF中导电球所引起的外引线间的电短路。
图1是表示外引线粘合后的互连的常规半导体封装的剖面图。
图2是表示按本发明的绝缘涂敷的TAB带的半导体封装的剖面图。
图3是表示在按本发明的外引线粘合后TAB绝缘带与基片连接的互连的半导体封装的剖面图。
图2表示按本发明的绝缘涂敷的TAB带。
首先，由于一般的TAB工艺与已有技术相似，所以不再进行详细说明，下面只说明TAB带的结构。
如图2所示，外引线15与粘结剂14粘结固定在绝缘带13的下部。但，在外引线的外表面形成绝缘涂敷区7，以防止电短路。绝缘涂敷区是用环氧树脂族材料形成的。此外，绝缘涂敷区7的厚度最好小于1000埃。
图3表示外引线粘合后TAB绝缘带和基片间的互连。
如图所示，在粘合外线期间，形成在外引线15的外围的绝缘涂敷区中，包含于ACA/ACF中的导电球6和与上述导电球6无关的导电球6a相互接触，此时，因为外引线15的绝缘涂敷区7被破坏，所以导电球6和有绝缘涂敷区的外引线15电连接。
这里，图3中，通过外引线15给导电球6和焊盘12加电压，或从焊盘12向导电球6和外引线15加电压。
如上所述，半导体装置围绕外引线形成绝缘涂敷区，以防止随着工业上对微小间距产品的研制而使外引线间的间距变近导致的不论导电性如何的导电球所引起的引线间的电短路。
尽管为了说明本发明的目的，公开了本发明的优选实施例，但本领域的技术人员应该理解到，在不脱离所附权利要求书所说明的本发明的范围和精神的情况下，可以有各种改型、附加和替换。

Claims (4)

1.半导体装置，包括：为了防止由于包含在ACA/ACF中的导电球在TAB外引线粘合期间引起外引线间电短路而形成在TAB带的外引线的外部的绝缘涂敷区。
2.如权利要求1的半导体装置，其特征在于：所述绝缘涂敷区是由环氧树脂族材料形成的。
3.如权利要求1的半导体装置，其特征在于：所述绝缘涂敷区的厚度低于1000埃。
4.如权利要求1的半导体装置，其特征在于：通过在一定压力下对绝缘膜的破坏，使所述绝缘涂敷区电连接绝缘带外引线和基片的焊盘。
CN96119946A 1995-10-19 1996-10-04 一种tab带和使用该tab带的半导体器件 Expired - Lifetime CN1071493C (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
KR36165/1995 1995-10-19
KR36165/95 1995-10-19
KR1019950036165A KR0157905B1 (ko) 1995-10-19 1995-10-19 반도체 장치

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CN1150334A true CN1150334A (zh) 1997-05-21
CN1071493C CN1071493C (zh) 2001-09-19

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CN96119946A Expired - Lifetime CN1071493C (zh) 1995-10-19 1996-10-04 一种tab带和使用该tab带的半导体器件

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US (1) US5923080A (zh)
JP (1) JP2753696B2 (zh)
KR (1) KR0157905B1 (zh)
CN (1) CN1071493C (zh)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1332244C (zh) * 2002-02-06 2007-08-15 西尔弗布鲁克研究有限公司 小型显示器组件
CN102446773A (zh) * 2010-10-01 2012-05-09 Lg伊诺特有限公司 用于tab封装的承载带及其制造方法

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DE19801312A1 (de) 1998-01-15 1999-07-22 Siemens Ag Halbleiterbauelement mit mehreren Substratlagen und zumindest einem Halbleiterchip und einem Verfahren zum Herstellen eines solchen Halbleiterbauelementes
US6683368B1 (en) * 2000-06-09 2004-01-27 National Semiconductor Corporation Lead frame design for chip scale package
TW464927B (en) * 2000-08-29 2001-11-21 Unipac Optoelectronics Corp Metal bump with an insulating sidewall and method of fabricating thereof
US6689640B1 (en) 2000-10-26 2004-02-10 National Semiconductor Corporation Chip scale pin array
JP5110744B2 (ja) * 2000-12-21 2012-12-26 フィリップス ルミレッズ ライティング カンパニー リミテッド ライアビリティ カンパニー 発光装置及びその製造方法
US6551859B1 (en) 2001-02-22 2003-04-22 National Semiconductor Corporation Chip scale and land grid array semiconductor packages
US8518304B1 (en) 2003-03-31 2013-08-27 The Research Foundation Of State University Of New York Nano-structure enhancements for anisotropic conductive material and thermal interposers
US7095096B1 (en) 2004-08-16 2006-08-22 National Semiconductor Corporation Microarray lead frame
US7846775B1 (en) 2005-05-23 2010-12-07 National Semiconductor Corporation Universal lead frame for micro-array packages
KR20130091521A (ko) * 2012-02-08 2013-08-19 삼성디스플레이 주식회사 이방성 도전층을 포함하는 미세 전자 소자 및 미세 전자 소자 형성 방법

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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1332244C (zh) * 2002-02-06 2007-08-15 西尔弗布鲁克研究有限公司 小型显示器组件
CN102446773A (zh) * 2010-10-01 2012-05-09 Lg伊诺特有限公司 用于tab封装的承载带及其制造方法
CN102446773B (zh) * 2010-10-01 2016-08-17 Lg伊诺特有限公司 用于tab封装的承载带及其制造方法
US9480152B2 (en) 2010-10-01 2016-10-25 Lg Innotek Co., Ltd. Carrier tape for tab-package and manufacturing method thereof
US9648731B2 (en) 2010-10-01 2017-05-09 Lg Innotek Co., Ltd. Carrier tape for tab-package and manufacturing method thereof

Also Published As

Publication number Publication date
JP2753696B2 (ja) 1998-05-20
KR970025350A (ko) 1997-05-30
CN1071493C (zh) 2001-09-19
KR0157905B1 (ko) 1998-12-01
US5923080A (en) 1999-07-13
JPH09129672A (ja) 1997-05-16

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