CN114975540A - 显示面板及其制造方法 - Google Patents

显示面板及其制造方法 Download PDF

Info

Publication number
CN114975540A
CN114975540A CN202210505649.3A CN202210505649A CN114975540A CN 114975540 A CN114975540 A CN 114975540A CN 202210505649 A CN202210505649 A CN 202210505649A CN 114975540 A CN114975540 A CN 114975540A
Authority
CN
China
Prior art keywords
sub
pixel
pixels
substrate
display panel
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202210505649.3A
Other languages
English (en)
Inventor
刘仲展
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
AU Optronics Corp
Original Assignee
AU Optronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by AU Optronics Corp filed Critical AU Optronics Corp
Publication of CN114975540A publication Critical patent/CN114975540A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission
    • H01L27/153—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars
    • H01L27/156—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars two-dimensional arrays
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
    • H01L22/22—Connection or disconnection of sub-entities or redundant parts of a device in response to a measurement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0095—Post-treatment of devices, e.g. annealing, recrystallisation or short-circuit elimination
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/075—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00
    • H01L25/0753—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/84—Passivation; Containers; Encapsulations
    • H10K50/842—Containers
    • H10K50/8426—Peripheral sealing arrangements, e.g. adhesives, sealants
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/30—Devices specially adapted for multicolour light emission
    • H10K59/35—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13139—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/1319—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/145—Material
    • H01L2224/14505—Bump connectors having different materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8112—Aligning
    • H01L2224/81121—Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors
    • H01L2224/81132—Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors using marks formed outside the semiconductor or solid-state body, i.e. "off-chip"
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Gas-Filled Discharge Tubes (AREA)
  • Electroluminescent Light Sources (AREA)

Abstract

本发明公开一种显示面板及其制造方法。显示面板包括基板、第一子像素及第二子像素。第一子像素设置于基板上。第一子像素具有第一指向特性，且第一子像素与基板之间具有第一接着材料。第二子像素设置于基板上。第二子像素具有第二指向特性，且第二子像素与基板之间具有第二接着材料。第一指向特性与第二指向特性不同，第一接着材料与第二接着材料不同。

Description

显示面板及其制造方法
技术领域
本发明涉及一种面板及方法，且特别涉及一种显示面板及其制造方法。
背景技术
随着显示面板尺寸的增加，如何快速且有效率地针对显示面板中具有缺陷的像素进行修补，已成为了本领域中待解决的重要课题之一。
发明内容
本发明提供一种显示面板及其制造方法，以有效率地显示面板中具有缺陷的像素进行修补。
本发明的显示面板包括基板、第一子像素及第二子像素。第一子像素设置于基板上。第一子像素具有第一指向特性，且第一子像素与基板之间具有第一接着材料。第二子像素设置于基板上。第二子像素具有第二指向特性，且第二子像素与基板之间具有第二接着材料。第一指向特性与第二指向特性不同，第一接着材料与第二接着材料不同。
本发明的显示面板的制造方法，包括：提供基板；在基板上设置第一子像素，其中第一子像素具有第一指向特性，且第一子像素与基板之间具有第一接着材料；以及在基板上设置第二子像素，第二子像素具有第二指向特性，且第二子像素与基板之间具有第二接着材料，其中第一指向特性与第二指向特性不同，第一接着材料与第二接着材料不同。
基于上述，本发明的显示面板及其制造方法可通过相对简单的硬件装置及相对短的操作流程，来修补显示面板上的缺陷，以改善显示面板的显示效果。
附图说明
图1为本发明实施例一显示面板的俯视示意图；
图2A～图2F为本发明实施例中一显示面板中一像素的制造流程的俯视示意图；
图3A～图3E、图3G为本发明实施例中另一显示面板中一像素的制造流程的俯视示意图；
图3F为图3E中转置元件头ST抓取子像素进行按压的侧视示意图；
图4A～图4C为本发明实施例用来替换的子像素的示意图；
图5A～图5C为本发明实施例一像素的排列示意图；
图6A～图6G为本发明实施例一像素的排列示意图。
符号说明
1：显示面板
10：第一像素
10R、10G、10B：子像素
11：第二像素
11R、11G、11B、111、112、113：子像素
PX2、PX3、PX5a、PX5b、PX5c、PX5d、PX6A～PX6E、PX6F1、PX6F2、PX6G1、PX6G2：像素
ST：转置元件头
12：基板
AD2：第二接着材料
D1：第一方向
D2：第二方向
PD1～PD6：接垫
RA：显示像素区
RB：主像素区
RC：备用像素区
具体实施方式
图1为本发明实施例一显示面板1的俯视示意图。显示面板1中包括多个第一像素10、多个第二像素11以及基板12。基板12被区分为多个显示像素区RA，而第一像素10及第二像素11设置在基板12，且分别被设置在对应的显示像素区RA中。具体来说，第一像素10会具有第一指向特性，且第二像素11会具有第二指向特性，而第一指向特性与第二指向特性不同。
在一些实施例中，第一像素10及第二像素11可为通过相同的转置元件头，但通过不同的转置程序所设置的。举例来说，转置元件头可先将各个第一像素10设置于基板12上的各个显示像素区RA中，并进行检查以移除其中具有缺陷的第一像素10之后，再通过相同的转置元件头将第二像素11填补至空缺的显示像素区RA中。如此一来，修补或替换整体显示面板1中具有缺陷的第一像素10的操作，可通过相同的转置元件头来完成，不需切换硬件装置。故整体操作流程可为相对简单，且避免额外硬件配置的成本。
在一些实施例中，由于第一像素10及第二像素11是转置元件头由不同晶片上所拿取的，因此设置在基板12上的第一像素10及第二像素11会具有不同的指向特性。指向特性可例如包含有各个像素与其对应的显示像素区RA之间的位置偏移量以及角度偏移量。举例来说，在图1中的每个第一像素10会具有一致的位置偏移量与角度偏移量，且每个第二像素也会具有一致的位置偏移量与角度偏移量。更具体来说，各个第一像素10相较于其个别对应的显示像素区RA，每个第一像素10都会贴齐在对应显示像素区RA的左上角而设置，且每个第一像素10的设置方向都会平行于对应显示像素区RA的延伸方向(及第二方向D2)也就是每个第一像素10与显示像素区RA之间会具有为零的角度偏移量。相较之下，每个第二像素11与其对应显示像素区RA的左上角之间，在第一方向D1及/或第二方向D2上的会具有位置偏移量，使第二像素11不贴齐其所对应显示像素区RA，且第二像素11的设置方向与显示像素区RA的延伸方向之间不为平行，也就是每个第二像素11与显示像素区RA之间会具有不为零的角度偏移量。
因此，第一像素10彼此之间会具有相同的第一指向特性，而第二像素11彼此之间会具有相同的第二指向特性。而在第一指向特性及第二指向特性中，第一像素10的位置偏移量及第二像素11的位置偏移量不同，及/或第一像素10的角度偏移量及第二像素11的角度偏移量不同。
另一方面，在一些实施例中，转置元件头在设置第一像素10时是通过第一接着材料，以将第一像素10固定于基板12上的各个显示像素区RA中。而为了在通过转置元件头设置第二像素11时，能够选择性地将第二像素11设置在空缺的显示像素区RA中，在转置元件头设置第二像素11之间，会先将具有粘着性的第二接着材料涂布于空缺的显示像素区RA中。如此一来，当转置元件头拿取第二像素11并按压于基板12上时，第二像素11可被第二接着材料粘置在原先为空缺的显示像素区RA中，进而完成第一显示像素10的替换。
在一些实施例中，第一像素10及第二像素11可例如是发光二极管、有机发光二极管(organic light emitting diode，OLED)、次毫米发光二极管(mini LED)、微发光二极管(micro LED)或量子点发光二极管(quantum dot,QD，可例如为QLED、QDLED)或其他适合的像素或材料。在一些实施例中，第一接着材料与第二接着材料不同。第一接着材料可例如是焊锡。第二接着材料可例如包含有金属、光致抗蚀剂、树脂、胶体、黑色遮光层，彩色滤光片、量子点或其他适合的材料。进一步，金属可例如为金、银、铜、锡或其他适合的金属。
图2A～图2F为本发明实施例中一显示面板中一像素PX2的制造流程的俯视示意图。
在图2A中，首先在基板12上会提供像素PX2，像素PX2中具有子像素10R、10G、10B。子像素10R、10G、10B可分别用来显示例如红绿蓝的颜色。每个像素PX2可被设置在对应的显示像素区中，在此实施例中，像素PX2的显示像素区可被区分为三个主像素区RB及三个备用像素区RC。子像素10R、10G、10B被分别设置在对应的主像素区RB中。而每个主像素RB旁设置有相邻的备用像素区RC。
虽然未绘示于图2A，子像素10R、10G、10B与基板12之间设置有第一接着材料，子像素10R、10G、10B可通过第一接着材料被固定于基板12上。第一接着材料可例如是焊锡。
在图2B中，像素PX2上个每个子像素10R、10G、10B会被个别检查其是否具有缺陷。在此实施例中，左上角的像素PX2的子像素10R经过检查后，其被判断出是具有缺陷的子像素10R。
在图2C中，具有缺陷的子像素10R可由左上角的像素PX2中被移除。因此，在左上角的像素PX2中，由于原先设置的子像素10R即被移除，故主像素区RB中为空置的。
在图2D中，在左上角的像素PX2中，针对原先设置有子像素10R的主像素区RB，可在其相邻的备用像素区RC上涂布上与第一接着材料不同的第二接着材料。
在一些实施例中，第二接着材料可通过以喷墨印刷(ink jet printing,IJP)的方式被涂布上备用像素区RC。而第二接着材料可例如为导体或非导体的接着材料，其具有粘性。在此实施例中，第二接着材料可包括例如包含有金属、光致抗蚀剂、树脂、胶体、黑色遮光层(black matrix,BM)，彩色滤光片(color filter,CF)、量子点或其他适合的材料。金属可例如包括金、银、铜、锡或其他适合的金属。
在一些实施例中第二接着材料可例如是光致抗蚀剂材料。第二接着材料在涂布上备用像素区RC之后，可再以激光直写(laser direct imaging,LDI)对第二接着材料进行曝光。而曝光后的第二接着材料会产生粘性。在此实施例中，第二接着材料可例如包含有金属、光致抗蚀剂、树脂、胶体、黑色遮光层，彩色滤光片、量子点或其他适合的材料。金属可例如包括金、银、铜、锡或其他适合的金属。
在图2E中，转置元件头可由备用晶片(未绘示于图2A～图2F中)上抓取多个子像素11R，并于子像素11R上施加适当压力于备用像素区RC所形成的列上。更具体来说，转置元件头可将子像素11R按置在备用像素区RC，而被按置的备用像素区RC旁边即为设置有子像素10R的主像素区RB。
在一些实施例中，当第二接着材料为导体时，转置元件头可以将子像素11R按压于第二接着材料上，使其被第二接着材料粘着即可。在一些实施例中，当第二接着材料为非导体时，转置元件头可以较大的压力以将子像素11R按压于基板12上，使子像素11R可穿透第二接着材料，直接接触并电连接于基板12上的布线。
在图2F中，当转置元件头离开基板12上时，由于第二接着材料的缘故，仅有左上角的像素PX2中的子像素11R会被留下，其他像素PX2中由于并未涂布有第二接着材料，故子像素11R并不会被留置在其他像素的备用像素区RC中。
因此，通过涂布具有粘着性的第二接着材料，使基板12在备用像素区RC上可选择性地由转置元件头上粘取需要的子像素11R，并保持其他不需要设置的备用像素区RC为空置。如此一来，在每个像素PX2中，其所设置的子像素数量总和为相等。故每个像素PX2中的子像素数量并不会因为替换掉具有缺陷的子像素而有所不同，可有效保持整体显示面板的亮度均匀，并降低无谓的消耗功率。
另一方面，在一些实施例中，在图2A中的子像素10R、10G、10B也可是通过与图2E中设置子像素11R相同的转置元件头来设置。在图2A的步骤中设置完子像素10R、10G、10B后，在图2E的步骤中即可通过相同的转置元件头来替换掉具有缺陷的子像素，避免替换转置元件头的操作时间，即可有效节省整体的硬件成本及操作时间成本。
图3A～图3F为本发明实施例中另一显示面板中一像素PX3的制造流程的俯视示意图。图3A～图3F中所绘示的像素PX3可相似于图2A～图2F中所绘示的像素PX2，只是在像素PX3中仅设置有主像素区RB，且未设置有备用像素区。
在图3A中，首先在基板12上会提供像素PX3，像素PX3中具有子像素10R、10G、10B。而子像素10R、10G、10B可分别被设置在对应的主像素区RB中。
虽然未绘示于图3A，子像素10R、10G、10B与基板12之间设置有第一接着材料，子像素10R、10G、10B可通过第一接着材料被固定于基板12上。第一接着材料可例如是焊锡。
在图3B中，像素PX3上个每个子像素10R、10G、10B会被个别检查其是否具有缺陷。在此实施例中，左上角的像素PX3的子像素10G经过检查后，其被判断出是具有缺陷的子像素10G。
在图3C中，具有缺陷的子像素10G可由左上角的像素PX3中被移除。因此，在左上角的像素PX3中，由于原先设置的子像素10G即被移除，故主像素区RB中为空置的。
在图3D中，在左上角的像素PX3中，与第一接着材料不同的第二接着材料可被涂布在原先设置有子像素10G的主像素区RB上。
在一些实施例中，第二接着材料可通过以喷墨印刷(ink jet printing,IJP)的方式被涂布上备用像素区RC。而第二接着材料可例如为导体或非导体的接着材料，其具有粘性。在此实施例中，第二接着材料可包括例如包含有金属、光致抗蚀剂、树脂、胶体、黑色遮光层、彩色滤光层、量子点或其他适合的材料。金属可例如为金、银、铜、锡或其他适合的金属。
在一些实施例中第二接着材料可例如是光致抗蚀剂材料。第二接着材料在涂布上备用像素区RC之后，可再以激光直写(laser direct imaging,LDI)对第二接着材料进行曝光。而曝光后的第二接着材料会产生粘性。在此实施例中，第二接着材料可例如包含金属、光致抗蚀剂、树脂、胶体、黑色遮光层、彩色滤光层、量子点或其他适合的材料。金属可例如为金、银、铜、锡或其他适合的金属。
在图3E中，转置元件头可由备用晶片(未绘示于图3A～图3F中)上抓取多个子像素11G，并将子像素11G以适当压力按压于主像素区RB所形成的列上。更具体来说，转置元件头可将其中一个子像素11R按置在被移除掉子像素RB的主像素区RB上，而其他的子像素11R则是被按置在未移除掉子像素RB上。
关于图3E的操作细节请进一步参考图3F。图3F为图3E中，转置元件头ST抓取子像素11G进行按压的侧视图。图3F中为了方便说明，部分元件(例如是子像素10R、10B)被省略了。
详细来说，当转置元件头ST抓取子像素11G进行按压时，转置元件头ST会将子像素11G按压于原先被移除掉子像素10G的主像素区RB的上方。另一方面，转置元件头ST由于是阵列式的结构，转置元件头ST也会将子像素11G按压在其他像素PX3的子像素10G上方。进一步，为了使子像素11G可较佳地被第二材料AD2粘附，转置元件头ST可以适当的压力按压，在不伤及其他子像素10G的情况下将子像素11G按压在原先被移除掉子像素10G的主像素区RB的上方。
在图3G中，当转置元件头ST离开基板12上时，由于第二接着材料AD2的缘故，仅有左上角的像素PX3中的子像素11G会被留下，故可替换掉具有缺陷的子像素10G。另外，在替换完成的像素PX3中，子像素11G设置在基板12上的设置高度可较子像素10R、10B的设置高度为高。
图4A～图4C为本发明实施例用来替换的子像素111～113的示意图。
在图4A中，用来替换的子像素111可例如是具有横向(lateral)结构的芯片，且子像素111在上方设置有两接垫PD1、PD2。如此一来，子像素111在放置时可在子像素111与基板之间通过非导体的第二接着材料粘着，并在子像素111的上方通过氧化铟锡(Indium TinOxide,ITO)与接垫PD1、PD2进行电连接。
在图4B中，用来替换的子像素112可例如是倒装技术(flip chip)所制造结构的芯片，且子像素112在下方设置有两接垫PD3、PD4。如此一来，子像素112在放置时可在子像素112与基板之间通过导体的第二接着材料粘着，进而与接垫PD3、PD4进行电连接。又或者是，子像素112在放置时可在子像素112与基板之间通过非导体的第二接着材料粘着，并通过转置元件头施加适当的压力，使子像素112的接垫PD3、PD4可与基板直接接触并进行电连接。
在图4C中，用来替换的子像素113可例如是具有垂直(vertical)结构的芯片，且子像素113在其上方及下方分别设置有接垫PD5、PD6。如此一来，子像素113在放置时可在子像素111与基板之间通过导体的第二接着材料粘着，进而与接垫PD6进行电连接。
图5A～图5C为本发明实施例中一显示面板中像素PX5a～PX5d的制造流程的俯视示意图。在本实施例中，像素PX5a～PX5d中可以被区分有三个主像素区RB以及仅一个备用像素区RC。
在图5A中，像素PX5a左上角的子像素10R、像素PX5b右上角的子像素10G、像素PX5d左下角的子像素10B经检查后可被判断为具有缺陷的子像素。
在图5B中，将第二接着材料涂布在像素PX5a的备用像素区RC中，以及转置元件头抓取子像素11R放置于基板上之后，子像素11R可被设置于子像素PX5a的备用像素区RC中。
在图5C中，经过重复图4B的操作，子像素11G及11B可分别被设置在像素PX5b、PX5d的备用像素区RC中。并且，像素PX5a、PX5b、PX5d中具有缺陷的子像素10R、10G、10B也可被移除。
虽然在图2A～图2F及图3A～图3G所绘示的制造流程中，具有缺陷的子像素是先被移除之后，再放置替换的子像素，但在具有备用像素区的情况下，移除具有缺陷的子像素的步骤当然可以弹性地调整。例如是在放置替换的子像素之后，再移除具有缺陷的子像素，亦应属于本发明实施例的范畴中。
图6A～图6G为本发明实施例一像素的排列示意图。由于本领域具通常知识者当然可依据不同的设计需求来调整显示像素区中备用像素区的数量，或显示像素区中主像素区与备用像素区之间的排列方式，故图6A～图6G中示例性地绘示了不同像素的排列示意图。
在图6A中，像素PX6A中可被区分为三个主像素区及三个备用像素区，而每个主像素区与对应的备用像素区互相相邻排列。
在图6B中，像素PX6B中可被区分为三个主像素区及仅有一个备用像素区，主像素区与备用像素区可共同排列为矩形或方形，使每个主像素区都相邻于该备用像素区。
在图6C中，像素PX6C可被区分为三个主像素区及仅有一个备用像素区，主像素区与备用像素区可共同排列为T字型。更具体来说，主像素区三者可共同排为一横列，而备用像素区则排在T字型的横列下方。
在图6D中，像素PX6C可被区分为三个主像素区及仅有一个备用像素区，主像素区与备用像素区可共同排列为T字型。更具体来说，备用像素区则排在T字型的横列正中央，而主像素区三者排列在T字形的三个顶端。
在图6E中，像素PX6C可被区分为三个主像素区及仅有一个备用像素区。主像素区可为具有相同大小的矩形形状，并且共同排为一横列。而备用像素区则排列在主像素区的横列下方，使主像素区及备用像素区共同形成一矩形。
在图6F的左侧中，像素PX6F1可具有两个主像素区及仅有一个备用像素区。两个主像素区中可分别设置红色及绿色的子像素。进一步，在像素PX6F1的右侧可连接有像素PX6F2，也具有两个主像素区及仅有一个备用像素区。像素PX6F2的主像素区可分别设置有蓝色及绿色的子像素。因此，通过重复排列像素PX6F1、PX6F2，显示阵列中的像素可被共同排列成图6F右侧的形式。
在图6G的左侧中，像素PX6G1、PX6G2可共用一个备用像素区。详细来说，像素PX6G1、PX6G2可分别具有红、绿、蓝的子像素，而六个子像素共同环绕备用像素区而设置。因此，通过重复排列像素PX6G1、PX6G2，显示阵列中的像素可被共同排列成图6G右侧的形式。
综上所述，本发明的显示面板及其造方法通过第二接着材料选择性地将第二像素粘置于空缺的显示像素区中，使制造显示面板的过程中，可通过相同的转置元件头来设置第一像素及第二像素，故可通过相对简单的硬件装置及相对短的操作流程，来修补显示面板上的缺陷，以改善显示面板的显示效果。

Claims (14)

1.一种显示面板，包括：
基板；
多个第一子像素，设置于该基板上，该些第一子像素具有第一指向特性，且该些第一子像素与该基板之间具有第一接着材料；以及
多个第二子像素，设置于该基板上，该些第二子像素具有第二指向特性，且该些第二子像素与该基板之间具有第二接着材料，
其中该第一指向特性与该第二指向特性不同，该第一接着材料与该第二接着材料不同。
2.如权利要求1所述的显示面板，其中该些第一子像素与该基板之间具有第一高度，该些第二子像素与该基板之间具有第二高度，该第一高度及该第二高度不相同。
3.如权利要求2所述的显示面板，其中该第二高度大于该第一高度。
4.如权利要求1所述的显示面板，其中该些第一子像素及该些第二子像素分别被设置在对应的多个显示像素区中，
该第一指向特性包括各该第一子像素与对应的各该显示像素区之间的第一位置偏移量及第一角度偏移量，该第二指向特性包括各该第二子像素与对应的各该显示像素区之间的第二位置偏移量及第二角度偏移量，
该第一位置偏移量及该第二位置偏移量不同，及/或该第一角度偏移量及该第一角度偏移量不同。
5.如权利要求1所述的显示面板，其中该第一接着材料或第二接着材料包含金属、光致抗蚀剂、树脂、胶体、黑色遮光层、彩色滤光层或量子点。
6.如权利要求1所述的显示面板，包括多个显示像素区，各该显示像素区包括主像素区及备用像素区，其中子像素被设置在该主像素区及该备用像素区的其中一者上。
7.一种显示面板的制造方法，包括：
提供基板；
在该基板上设置多个第一子像素，其中该些第一子像素具有第一指向特性，且该些第一子像素与该基板之间具有第一接着材料；以及
在该基板上设置多个第二子像素，该些第二子像素具有第二指向特性，且该些第二子像素与该基板之间具有第二接着材料，
其中该第一指向特性与该第二指向特性不同，该第一接着材料与该第二接着材料不同。
8.如权利要求7所述的制造方法，包括：
在设置该些第一子像素之后，检查该些第一子像素以由该些第一子像素中判断出具有缺陷的多个第三子像素；
移除该些第三子像素；以及
在该些第三子像素被移除的多个标记显示像素区中，分别设置该些第二子像素。
9.如权利要求8所述的制造方法，其中在设置该些第三子像素的该些标记显示像素区中，分别设置该些第二子像素的步骤包括：
在该些标记显示像素区中涂布该第二接着材料之后，将该些第二子像素设置于该些显示标记像素区中。
10.如权利要求7所述的制造方法，其中该些第一子像素与该基板之间具有第一高度，该些第二子像素与该基板之间具有第二高度，该第一高度及该第二高度不相同。
11.如权利要求10所述的制造方法，其中该第二高度大于该第一高度。
12.如权利要求7所述的制造方法，其中该些第一子像素及该些第二子像素分别被设置在对应的多个显示像素区中，
该第一指向特性包括各该第一子像素与对应的各该显示像素区之间的第一位置偏移量及第一角度偏移量，该第二指向特性包括各该第二子像素与对应的各该显示像素区之间的第二位置偏移量及第二角度偏移量，
该第一位置偏移量及该第二位置偏移量不同，及/或该第一角度偏移量及该第一角度偏移量不同。
13.如权利要求7所述的制造方法，其中该第一接着材料或第二接着材料包括金属、光致抗蚀剂、树脂、胶体、黑色遮光层、彩色滤光层或量子点。
14.如权利要求7所述的制造方法，还包括提供多个显示像素区，且各该显示像素区包括主像素区及备用像素区，其中一子像素被设置在该主像素区及该备用像素区的其中一者上。
CN202210505649.3A 2021-12-17 2022-05-10 显示面板及其制造方法 Pending CN114975540A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
TW110147535A TWI807544B (zh) 2021-12-17 2021-12-17 顯示面板及其製造方法
TW110147535 2021-12-17

Publications (1)

Publication Number Publication Date
CN114975540A true CN114975540A (zh) 2022-08-30

Family

ID=82981278

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202210505649.3A Pending CN114975540A (zh) 2021-12-17 2022-05-10 显示面板及其制造方法

Country Status (3)

Country Link
US (1) US20230197536A1 (zh)
CN (1) CN114975540A (zh)
TW (1) TWI807544B (zh)

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101890934B1 (ko) * 2017-12-01 2018-08-22 한국광기술원 픽셀형 led 공정
JP2020042955A (ja) * 2018-09-07 2020-03-19 株式会社Ｊｏｌｅｄ 表示パネル、表示パネルの検査方法、及び表示パネルの製造方法
CN111489661A (zh) * 2019-11-15 2020-08-04 友达光电股份有限公司 显示装置
US20200328196A1 (en) * 2019-04-10 2020-10-15 Samsung Electronics Co., Ltd. Display panel and method of manufacturing thereof
CN111798764A (zh) * 2020-06-12 2020-10-20 福州大学 一种μLED像素单元结构及显示器件
CN113054069A (zh) * 2019-12-27 2021-06-29 晶元光电股份有限公司 发光装置的修补方法
CN113169250A (zh) * 2019-05-08 2021-07-23 三星电子株式会社 转移装置和使用该转移装置制造微型led显示器的方法
WO2021212540A1 (zh) * 2020-04-20 2021-10-28 武汉华星光电技术有限公司 Micro-LED 芯片坏点修复方法

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201917811A (zh) * 2017-06-26 2019-05-01 美商特索羅科學有限公司 發光二極體質量傳遞設備及製造方法
WO2019246366A1 (en) * 2018-06-22 2019-12-26 Veeco Instruments Inc. Micro-led transfer methods using light-based debonding
TWI723417B (zh) * 2019-06-06 2021-04-01 錼創顯示科技股份有限公司 微型發光二極體顯示器的製造方法
TWI742522B (zh) * 2020-01-30 2021-10-11 友達光電股份有限公司 顯示面板及其製造方法
US11348905B2 (en) * 2020-03-02 2022-05-31 Palo Alto Research Center Incorporated Method and system for assembly of micro-LEDs onto a substrate

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101890934B1 (ko) * 2017-12-01 2018-08-22 한국광기술원 픽셀형 led 공정
JP2020042955A (ja) * 2018-09-07 2020-03-19 株式会社Ｊｏｌｅｄ 表示パネル、表示パネルの検査方法、及び表示パネルの製造方法
US20200328196A1 (en) * 2019-04-10 2020-10-15 Samsung Electronics Co., Ltd. Display panel and method of manufacturing thereof
CN113169250A (zh) * 2019-05-08 2021-07-23 三星电子株式会社 转移装置和使用该转移装置制造微型led显示器的方法
CN111489661A (zh) * 2019-11-15 2020-08-04 友达光电股份有限公司 显示装置
CN113054069A (zh) * 2019-12-27 2021-06-29 晶元光电股份有限公司 发光装置的修补方法
WO2021212540A1 (zh) * 2020-04-20 2021-10-28 武汉华星光电技术有限公司 Micro-LED 芯片坏点修复方法
CN111798764A (zh) * 2020-06-12 2020-10-20 福州大学 一种μLED像素单元结构及显示器件

Also Published As

Publication number Publication date
US20230197536A1 (en) 2023-06-22
TWI807544B (zh) 2023-07-01
TW202326242A (zh) 2023-07-01

Similar Documents

Publication Publication Date Title
KR102543408B1 (ko) 발광 디스플레이 유닛 및 디스플레이 장치
US11799063B2 (en) Display apparatus comprising light emitting devices coupled to a wiring board with conductive adhesive
US20150249069A1 (en) Display device and method for manufacturing display device
EP3579663A1 (en) Display device using semiconductor light emitting element, and manufacturing method therefor
US11289633B2 (en) LED array package and manufacturing method thereof
JP6438536B2 (ja) Ｌｅｄチップグループのアレイを含むディスプレイモジュール
US11296061B2 (en) Micro semiconductor stacked structure and electronic apparatus having the same
KR20180018246A (ko) Led칩 그룹들의 어레이를 포함하는 디스플레이 모듈 및 그 제조방법
CN113594194A (zh) 一种堆叠结构、显示屏及显示装置
KR102174847B1 (ko) 디스플레이 장치의 제조 방법 및 디스플레이 장치
KR102385376B1 (ko) 마이크로 진공모듈을 이용한 마이크로 led 어레이 전사를 위한 기판, 마이크로 led 어레이, 마이크로 진공모듈 간의 배치 구조 및 이를 이용한 마이크로 led 디스플레이 제작 방법
KR102173090B1 (ko) 캐리어 기판의 선택적 전사 방법, 이를 이용한 디스플레이 장치의 제조 방법 및 그 방법에 의해 제조되는 디스플레이 장치
CN114975540A (zh) 显示面板及其制造方法
KR102323586B1 (ko) 확장 패드를 갖는 led 서브 픽셀 csp
KR102323587B1 (ko) 디스플레이 장치의 제조 방법 및 그 방법에 의해 제조되는 디스플레이 장치
KR102262748B1 (ko) 전극패드의 확장 및 영역 이동을 통한 디스플레이 장치의 제조 방법 및 그 방법에 의해 제조되는 디스플레이 장치
KR20200104060A (ko) 마이크로 led 전사 방법 및 이를 이용한 디스플레이 장치
KR102203639B1 (ko) 디스플레이 장치의 제조 방법 및 디스플레이 장치
KR102626606B1 (ko) 디스플레이 장치의 제조 방법 및 디스플레이 장치
KR20210011631A (ko) 확장형 전극패드를 갖는 픽셀 csp 제조방법 및 그 방법에 의해 제조되는 픽셀 csp
US20230282792A1 (en) Thermocompression device and method of manufacturing display device using same
KR102203649B1 (ko) 서브 픽셀 csp, 서브 픽셀 csp의 제조 방법, 디스플레이 장치의 제조 방법 및 그 방법에 의해 제조되는 디스플레이 장치
KR102173094B1 (ko) 디스플레이 장치의 제조 방법 및 디스플레이 장치
CN216362025U (zh) 显示面板
KR102262749B1 (ko) 솔더 페이스트 선택적 도포 방법, 이를 이용한 디스플레이 장치 제조 방법

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination