CN114975127A - 一种新型碳化硅平面式功率mosfet器件的制造方法 - Google Patents
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Abstract
本发明公开了一种新型碳化硅平面式功率MOSFET器件的制造方法,包括以下步骤:S1:在外延层部分区域形成N‑掺杂区;S2:在外延层上蚀刻出凹槽;S3:在氮化物层对应的外延层内依次形成P‑掺杂区,N+掺杂区和P+掺杂区;S4:在外延层上表面生长闸极氧化层,随后在闸极氧化层上表面沉积闸极多晶硅层;S5:去除部分闸极多晶硅层和闸极氧化层,随后沉积介电质层;S6:在介电质层表面沉积金属层即得MOSFET器件。本发明不仅可以降低接面场效应的电阻RJFET,且可控制通道浓度在1017‑1018cm‑3之间时,可将载子迁移率提高到80cm2/Vs,为现有组件载子迁移率的4倍以上,降低了通道阻值。
Description
技术领域
本发明属于电子元器件领域,特别涉及一种新型碳化硅平面式功率MOSFET器件的制造方法。
背景技术
随着全球对节能减碳的要求越来越严格,功率组件也开始广泛的使用起所谓的第三代宽能隙材料。相对于传统的纯硅组件,宽能隙材料能够大幅降低组件的功率损耗,因此被认为是新世纪的半导体主流,而目前最被广泛开发的便是氮化镓(GaN)及碳化硅(SiC)二种材质。
碳化硅本身为一种极性晶体,不同极性面皆可能对电性能(热电性能、铁电性能)、生长性能等特性有所影响。而对于采用碳化硅(SiC)材料做成的平面式功率金属氧化物半导体场效晶体管(MOSFET)而言,通道阻值对整体阻值而言是一个最大的考虑点。现有的平面式SiC MOSFET的通道电流为水平面方向(0001面),以600V的产品为例,电流流经此水平面(0001面),通道载子迁移率因为通道极性面的关系而不到基材的10%,使得整体组件不能发挥材料本身的优势,仅仅通道阻值就占了全部阻值Rdson的8成以上。
发明内容
针对现有技术中存在的问题,本发明公开了一种新型碳化硅平面式功率MOSFET器件的制造方法,不仅可以降低接面场效应的电阻RJFET,而且可以控制通道浓度在1017-1018cm-3之间,将载子迁移率提高到80cm2/Vs,为现有组件载子迁移率的4倍以上,大大降低了通道阻值。
本发明的上述技术目的是通过以下技术方案得以实现的:
一种新型碳化硅平面式功率MOSFET器件的制造方法,具体制备步骤如下:
S1:在位于基底表面的外延层上表面沉积氮化物层,之后利用光刻板完成曝光制程,使得氮化物层位于外延层上表面两侧,接着采用离子布值工艺在外延层部分区域形成N-掺杂区;
S2:在900-1000℃高温氯气环境下以湿蚀刻制程的方式在外延层上蚀刻出凹槽,直至凹槽两侧有倾斜面显露出来;
S3:采用三层光刻板和三道离子布值工艺后在氮化物层对应的外延层内依次形成P-掺杂区, N+掺杂区和P+掺杂区;
S4:在1300℃高温氧气环境下,在外延层上表面生长闸极氧化层,随后在闸极氧化层上表面沉积闸极多晶硅层,最后采用化学机械研磨工艺将闸极多晶硅层的表面平坦化;
S5:使用光刻工艺将部分闸极多晶硅层和闸极氧化层去除,随后沉积介电质层,使得介电质层包覆闸极多晶硅层和闸极氧化层,并采用光刻工艺在介电质层两侧开设金属接触孔;
S6:在介电质层表面沉积金属层,且所述金属层通过金属接触孔与P+掺杂区上表面和N+掺杂区部分上表面接触,即得到MOSFET器件。
优选地,所述基底和外延层均为碳化硅材料,且所述外延层为N型外延层,其生长的水平面晶格面向为0001。
优选地,所述步骤S1中,所述N-掺杂区的布值材料为磷,且磷的整体浓度为1014cm-2等级。
优选地,所述步骤S1中的氮化物层的厚度为1-2μm。
优选地,所述步骤S2中,所述凹槽的倾斜面与水平面的夹角θ为52°-56°。
优选地,所述凹槽的倾斜面与水平面的夹角θ为54.7°。
优选地,所述步骤S3中,所述N+掺杂区和P+掺杂区均位于所述P-掺杂区内,所述P+掺杂区包覆所述N+掺杂区一侧边以及所述N+掺杂区平行于外延层上表面的部分区域,所述N+掺杂区和P+掺杂区的上表面与外延层上表面齐平;
所述P-掺杂区的布值材料为铝,且铝的整体浓度为1015cm-2等级;
所述N+掺杂区的布值材料为磷,且磷的整体浓度为1015cm-2等级;
所述P+掺杂区的布值材料为铝,且铝的整体浓度为1016cm-2等级。
优选地,所述步骤S4中,所述闸极氧化层的厚度为0.02-0.06μm。
优选地,所述步骤S4中,所述闸极多晶硅层的厚度为0.4-1.0μm。
优选地,所述金属层为铝金属层,且金属层厚度为3-5μm 。
有益效果:本发明公开了一种新型碳化硅平面式功率MOSFET器件及其制造方法,具有如下优点:
1)本发明通过一层光刻工艺及湿蚀刻制程在外延层形成N-掺杂区,从而降低了器件阻值中的接面场效应阻值RJFET;
2)本发明将通道电流的路径面向从水平面转换成倾斜面,使得通道浓度在1017-1018cm-3之间,将载子迁移率提高到80 cm2/Vs,将通道阻值大大地降低。
附图说明
图1为实施例1中步骤S1完成后的示意图;
图2为实施例1中步骤S2完成后的示意图;
图3为实施例1中步骤S3完成后的示意图;
图4为实施例1中步骤S4完成后的示意图;
图5为实施例1中步骤S5完成后的示意图;
图6为实施例1中步骤S6完成后的示意图;
图7为实施例1的局部示意图;
图8为实施例2的MOSFET器件中电流流向示意图;
图9为现有的MOSFET器件中电流流向示意图;
图10为实施例1的MOSFET器件的信道仿真示意图;
图11为对比例的MOSFET器件的的信道仿真示意图;
图12为实施例1的MOSFET器件的逆向崩溃电压仿真示意图;
图13为对比例的MOSFET器件的逆向崩溃电压仿真示意图;
图14为实施例1的MOSFET器件在不同闸极电压条件下漏极电压电流仿真示意图;
图15为对比例的MOSFET器件在不同闸极电压条件下漏极电压电流仿真示意图;
图中:外延层1、掺杂区2、N+掺杂区2-1、P+掺杂区2-2、P-掺杂区2-3、倒梯形凹槽3、N-掺杂区4、闸极氧化层5、闸极多晶硅层6、介电质层7、金属接触孔7-1、金属层8、氮化硅层9。
具体实施方式
为了使本发明的目的、技术方案及优点更加清楚明白,以下结合附图及实施例,对本发明进行进一步详细说明。应当理解,此处所描述的具体实施例仅用以解释本发明,并不用于限定本发明。
实施例1
一种新型碳化硅平面式功率MOSFET器件的制造方法,其具体步骤如下:
S1:在位于基底表面的外延层上表面沉积氮化物层9,且所述氮化物层9的厚度为2μm,且氮化物层为氮化硅层,之后利用光刻板完成曝光制程,使得氮化物层9位于外延层1上表面两侧,接着采用离子布值工艺在外延层1部分区域形成N-掺杂区4,如图1所示,所述N-掺杂区4位于两侧氮化物层之间的外延层1内,基底和外延层均为碳化硅材料,且外延层为N型外延层,其生长的水平面晶格面向为0001;
S2:在900-1000℃高温氯气环境下以湿蚀刻制程的方式在外延层1上蚀刻出凹槽3,直至凹槽3两侧有倾斜面显露出来,如图2所示,所述凹槽3两侧的倾斜面的晶格面向为0338;
S3:采用三层光刻板和三道离子布值工艺在氮化物层对应的外延层内依次形成P-掺杂区2-3, N+掺杂区2-1和P+掺杂区2-2,如图3所示,其中,
所述P-掺杂区的布值材料为铝,且铝的整体浓度为1015cm-2等级;
所述N+掺杂区的布值材料为磷,且磷的整体浓度为1015cm-2等级;
所述P+掺杂区的布值材料为铝,且铝的整体浓度为1016cm-2等级;
S4:在1300℃高温氧气环境下,在外延层1上表面生长闸极氧化层5,随后在闸极氧化层5上表面沉积闸极多晶硅层6,最后采用化学机械研磨工艺将闸极多晶硅层6的表面平坦化,如图4所示,其中,闸极氧化层厚度为0.06μm,闸极多晶硅层的厚度为1.0μm;
S5:使用光刻工艺将部分闸极多晶硅层6和闸极氧化层5去除,使得闸极氧化层5的两端分别延伸至两侧的N+掺杂区部分上表面,随后沉积介电质层7,使得介电质层7包覆闸极多晶硅层6和闸极氧化层5,并采用光刻工艺在介电质层7两侧开设金属接触孔7-1,如图5所示;
S6:在介电质层7表面沉积金属层8,且所述金属层8通过金属接触孔7-1与P+掺杂区2-2上表面和N+掺杂区2-1部分上表面接触,即得到MOSFET器件,如图6所示,金属层为铝金属层,且金属层厚度为3μm。
如图7所示,本实施例1中,凹槽两侧的倾斜面与水平面的夹角为θ,且夹角θ为54.7°,则倾斜面的晶格面向为0338。
本实施例1中提及的沉积工艺、离子布值工艺、湿蚀刻工艺、光刻工艺均为现有技术,可由本领域技术人员根据实际需求调整工艺参数。
实施例2
一种碳化硅平面式功率MOSFET器件,如图8所示,包括基底、外延层1、掺杂区2、闸极氧化层5、闸极多晶硅层6、介电质层7、金属层8,实施例2中的MOSFET器件的制造方法与实施例1相同,其中,氮化物层9的厚度为1μm的氮化硅层,凹槽3两侧的倾斜面与水平面的夹角θ为56°,闸极多晶硅层的厚度为0.5μm,金属层厚度为4μm铝金属层,其余结构参数与实施例1相同。从图8中可以看出,MOSFET器件的通道电流的路径面向从水平面转换成了倾斜面。
对比例:
一种碳化硅平面式功率MOSFET器件,如图9所示,包括基底、外延层1、掺杂区2、闸极氧化层5、闸极多晶硅层6、介电质层7、金属层8,与实施例1相比,区别在于,闸极氧化层5平铺设置在外延层上表面,且闸极氧化层5覆盖掺杂区2的P-掺杂区2-3和部分N+掺杂区2-1上表面,其余结构的设置方式以及结构参数与实施例1均相同,从图中可以看出,MOSFET器件的通道电流的路径面向为水平面(0001面)。
(1)仿真图比较
如图10和图11所示,分别为实施例1与对比例的信道仿真示意图,从图10中可以看出,采用实施例1的方法制得的MOSFET器件的信道处有一个54.7°的倾斜面,此面向即为晶格面向0338面。而对比例中制得的MOSFET器件的信道为正常的水平面向,即为0001面,如图11所示。由此可以看出,实施例1制得的MOSFET器件的通道电流的路径面向从水平面转换成了倾斜面,使得通道浓度在1017-1018cm-3之间,将载子迁移率提高到80 cm2/Vs,大大地降低了通道阻值在整体阻值中的占比。
(2)逆向崩溃电压仿真对比(以1200v的外延层为例)
如图12和图13所示,分别为实施例1与对比例的逆向崩溃电压仿真示意图,从图中可知,实施例1中虽然采用湿蚀刻制程的方式在外延层成型浅沟凹槽3形成54.7°的倾斜面,但是由于其并没有改变其电场位置,故仍然维持着与对比例一样的逆向崩溃电压值。
(3)逆向崩溃电压仿真对比(以1200v的外延层为例)
如图14和图15所示,分别为实施例1与对比例的MOSFET器件在不同闸极电压条件下漏极电压电流仿真示意图,从图中可知,以闸极电压10V为例,当漏极电压为20V时,实施例1制得的倾斜面结构的阻值约为83mΩ,而实施例1中的水平面结构的阻值约为125 mΩ,其整体阻值减少了30%以上。
本具体实施例仅仅是对本发明的解释,其并不是对本发明的限制,本领域技术人员在阅读完本说明书后可以根据需要对本实施例做出没有创造性贡献的修改,但只要在本发明的权利要求范围内都受到专利法的保护。
Claims (10)
1.一种新型碳化硅平面式功率MOSFET器件的制造方法,其特征在于,其具体制备步骤如下:
S1:在位于基底表面的外延层上表面沉积氮化物层,之后利用光刻板完成曝光制程,使得氮化物层位于外延层上表面两侧,接着采用离子布值工艺在外延层部分区域形成N-掺杂区;
S2:在900-1000℃高温氯气环境下以湿蚀刻制程的方式在外延层上蚀刻出凹槽,直至凹槽两侧有倾斜面显露出来;
S3:采用三层光刻板和三道离子布值工艺在氮化物层对应的外延层内依次形成P-掺杂区、N+掺杂区和P+掺杂区;
S4:在1300℃高温氧气环境下,在外延层上表面生长闸极氧化层,随后在闸极氧化层上表面沉积闸极多晶硅层,最后采用化学机械研磨工艺将闸极多晶硅层的表面平坦化;
S5:使用光刻工艺将部分闸极多晶硅层和闸极氧化层去除,随后沉积介电质层,使得介电质层包覆闸极多晶硅层和闸极氧化层,并采用光刻工艺在介电质层两侧开设金属接触孔;
S6:在介电质层表面沉积金属层,且所述金属层通过金属接触孔与P+掺杂区上表面和N+掺杂区部分上表面接触,即得到MOSFET器件。
2.根据权利要求1所述的新型碳化硅平面式功率MOSFET器件的制造方法,其特征在于,所述基底和外延层均为碳化硅材料,且所述外延层为N型外延层,其生长的水平面晶格面向为0001。
3.根据权利要求1所述的新型碳化硅平面式功率MOSFET器件的制造方法,其特征在于,所述步骤S1中,所述N-掺杂区的布值材料为磷,且磷的整体浓度为1014cm-2等级。
4.根据权利要求1所述的新型碳化硅平面式功率MOSFET器件的制造方法,其特征在于,所述步骤S1中的氮化物层的厚度为1-2μm。
5.根据权利要求1所述的新型碳化硅平面式功率MOSFET器件的制造方法,其特征在于,所述步骤S2中,所述凹槽的倾斜面与水平面的夹角θ为52°-56°。
6.根据权利要求5所述的新型碳化硅平面式功率MOSFET器件的制造方法,其特征在于,所述凹槽的倾斜面与水平面的夹角θ为54.7°。
7.根据权利要求1所述的新型碳化硅平面式功率MOSFET器件的制造方法,其特征在于,所述步骤S3中,所述N+掺杂区和P+掺杂区均位于所述P-掺杂区内,所述P+掺杂区包覆所述N+掺杂区一侧边以及所述N+掺杂区平行于外延层上表面的部分区域,所述N+掺杂区和P+掺杂区的上表面与外延层上表面齐平,其中,
所述P-掺杂区的布值材料为铝,且铝的整体浓度为1015cm-2等级;
所述N+掺杂区的布值材料为磷,且磷的整体浓度为1015cm-2等级;
所述P+掺杂区的布值材料为铝,且铝的整体浓度为1016cm-2等级。
8.根据权利要求1所述的新型碳化硅平面式功率MOSFET器件的制造方法,其特征在于,所述步骤S4中,所述闸极氧化层的厚度为0.02-0.06μm。
9.根据权利要求1所述的新型碳化硅平面式功率MOSFET器件的制造方法,其特征在于,所述步骤S4中,所述闸极多晶硅层的厚度为0.4-1.0μm。
10.根据权利要求1所述的新型碳化硅平面式功率MOSFET器件的制造方法,其特征在于,所述金属层为铝金属层,且金属层厚度为3-5μm 。
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