CN114858020B

CN114858020B - Anti-interference method and medium for electronic detonator

Info

Publication number: CN114858020B
Application number: CN202210446563.8A
Authority: CN
Inventors: 朱志明; 郑弘毅
Original assignee: Shanghai Xinyang Technology Co ltd
Current assignee: Shanghai Xinyang Technology Co ltd
Priority date: 2022-04-26
Filing date: 2022-04-26
Publication date: 2023-09-29
Anticipated expiration: 2042-04-26
Also published as: CN114858020A

Abstract

The application provides an anti-interference method, a system and a medium for an electronic detonator, comprising the following steps: step S1: after the electronic detonator chip is electrified, the electric reset circuit outputs a reset signal POR, and the electronic detonator chip enters a normal mode and waits for receiving an instruction; step S2: the detonators send detonating commands after normal communication, chip configuration, high-voltage power charging and delay time setting operations are completed; step S3: after the electronic detonator chip receives the detonation command, the main control logic control chip enters a delay mode of countdown before detonation; step S4: the anti-interference logic shields the reset signal input by the delay module, simultaneously sends a LOAD signal LOAD to the delay logic, and then sends a START signal START to the delay logic to drive a counter; step S5: starting a counter of delay logic to start counting down; step S6: and outputting an ignition control signal to detonate the medicine head after the timer counts down to zero. The application can solve the problem of explosion rejection frequently occurring in blasting of the tunneling surface.

Description

Anti-interference method and medium for electronic detonator

Technical Field

The application relates to the technical field of electronic detonators, in particular to an anti-interference method and medium for an electronic detonator.

Background

Along with the application of the electronic detonator, the electronic detonator is more and more protected, and obvious blind blasting problems occur when the electronic detonator is blasted on the tunneling surface of some underground ores. Because the time delay is different when the electronic detonator is blasted in networking, the blasting area of the tunneling surface is smaller, the distance between the networked electronic detonators is relatively close, and strong electromagnetic waves or static and other interference signals generated after the blasting of the electronic detonator can enter the electronic detonator module from two leg wires of the electronic detonator which is not blasted yet, thereby instantaneously puncturing the electronic detonator chip or causing the chip to reset, leading the electronic detonator module to stop working and generating the explosion rejection.

In many existing electronic detonator modules, a protective circuit is added at the front stage of the electronic detonator chip or a discharging device is added to inhibit some interference signals generated in the blasting environment, but the problem of explosion rejection in the blasting site of the tunneling surface of underground mine is relatively large, and the analysis of the explosion rejection electronic detonator modules is mostly caused by resetting of the detonator chip.

The disturbing signals in the blasting environment are basically high-frequency pulses, and cannot be completely eliminated through an external circuit, so that the reset of the chip is easily caused after the signals enter the chip. And once reset, blind shots will appear.

The application patent with the publication number of CN112393653A discloses an electronic detonator explosion control system for improving anti-interference performance, which comprises an exploder and a plurality of electronic detonator modules, wherein each electronic detonator module is connected with the exploder in a parallel mode, each electronic detonator module is provided with a switch structure, and after the electronic detonator module receives an explosion command sent by the exploder and starts to execute explosion, the electronic detonator module controls the switch structure to be in a closed state, so that the electronic detonator module, the exploder and other electronic detonator modules are in a physical separation state at the moment.

Disclosure of Invention

Aiming at the defects in the prior art, the application provides an anti-interference method and medium for an electronic detonator.

The application provides an anti-interference method and medium for an electronic detonator, wherein the scheme is as follows:

the application provides an anti-interference method for an electronic detonator, which comprises the following steps:

step S1: after the electronic detonator chip is electrified, an internal power-on reset circuit outputs a reset signal POR, and after the reset is finished, the electronic detonator chip enters a normal mode and waits for receiving an instruction;

step S2: controlling the exploder of the whole electronic detonator module to complete normal communication, chip configuration, high-voltage power charging and delay time setting operation and then sending an explosion command;

step S3: after the electronic detonator chip receives the detonation command, the main control logic control chip enters a countdown delay mode before detonation from a normal mode;

step S4: after entering the deferred mode, the anti-interference logic shields the reset signal input by the deferred module, simultaneously sends a LOAD signal LOAD to the deferred logic, and then sends a START signal START to a deferred logic drive counter;

step S5: starting a counter of delay logic to start counting down;

step S6: outputting an ignition control signal to detonate the medicine head after the timer counts down to zero;

the immunity logic includes: a 24-bit delay control register, a comparator, an OR gate, two D flip-flops, an NOT gate and an AND gate;

the output end of the 24-bit delay control register is connected with the input end of a comparator, and the output end of the comparator is connected with the input ends of the first trigger and the OR gate;

the output end of the OR gate is connected with the input end of the first trigger, the output end of the first trigger is connected with the input end of the second trigger and the AND gate, and the output end of the second trigger is connected with the NOT gate and then connected with the AND gate.

Preferably, the step S3 specifically includes: after receiving the initiation command, all the electronic detonator chips enter a delay mode, and the chip is cut off from a path to delay logic through anti-interference logic before initiation.

Preferably, upon power up, the 24-bit delay control register will load a characteristic value of 0xA5F05A, and after the characteristic value is loaded, the comparator will output a high level to turn off the POR path.

In a second aspect, a computer readable storage medium storing a computer program is provided, which when executed by a processor, implements steps in the method.

Compared with the prior art, the application has the following beneficial effects:

1. after the electronic detonator chip receives the initiation command and enters the delay mode, the reset passage is automatically cut off in the chip, and even if the chip is reset due to external interference, the normal operation of delay logic is not affected, so that the detonator chip is not interfered by electromagnetic pulse or electrostatic signals caused by explosion;

2. the method is easy to realize, has good electromagnetic pulse or electrostatic interference resistance effect, and can solve the problem of explosion rejection frequently occurring in blasting of the tunneling surface.

Drawings

Other features, objects and advantages of the present application will become more apparent upon reading of the detailed description of non-limiting embodiments, given with reference to the accompanying drawings in which:

FIG. 1 is a schematic diagram of a circuit configuration;

FIG. 2 is a schematic diagram of an anti-tamper logic circuit;

fig. 3 is an exemplary diagram of an operational waveform.

Detailed Description

The present application will be described in detail with reference to specific examples. The following examples will assist those skilled in the art in further understanding the present application, but are not intended to limit the application in any way. It should be noted that variations and modifications could be made by those skilled in the art without departing from the inventive concept. These are all within the scope of the present application.

The embodiment of the application provides an anti-interference method for an electronic detonator, wherein special anti-interference logic is designed in the electronic detonator chip, and reset signals input by the delay logic can be automatically shielded in the chip once the chip receives a detonation command and enters a delay mode of detonation countdown. The method comprises the following steps:

referring to fig. 1, a schematic diagram of a circuit composition structure in the present application is shown, in which an electronic detonator module receives an instruction of an electronic detonator initiator through a leg wire to complete initiation of detonating explosive. The electronic detonator comprises a front-stage protection circuit, an electronic detonator chip and other elements, wherein the front-stage protection circuit is connected with the electronic detonator chip.

Specifically, the front-stage protection circuit generally includes some transient high-voltage suppressing tubes, electrostatic protection tubes, and the like, which suppress transient high-voltage signals entering from the leg wire.

The electronic detonator chip is a main control chip of the electronic detonator module, receives the instruction, controls delay and completes detonation. The electronic detonator chip comprises a high-voltage circuit, an LDO low-voltage stabilizing circuit and an anti-interference logic subsystem, wherein the output end of the high-voltage circuit is connected with the input end of the LDO low-voltage stabilizing circuit, and the output end of the LDO low-voltage stabilizing circuit is connected with the input end of the anti-interference logic subsystem and used as a power supply of the anti-interference logic subsystem.

Wherein, the high voltage circuit: the detonator mainly comprises a detonator chip external communication circuit, an internal voltage reference circuit and the like.

LDO low-voltage stabilizing circuit: the low voltage generating circuit for digital circuit and partial analog circuit of electronic detonator chip outputs VCORE in 1.8-5V.

The anti-interference logic subsystem comprises an OSC crystal oscillator, a POR power-on reset circuit, a master control logic, anti-interference logic and a delay logic. The output end of the OSC crystal oscillator is connected with the main control logic input end, the anti-interference logic input end and the delay logic input end; the main control logic output end is connected with the anti-interference logic input end and the delay logic input end; the output end of the POR power-on reset circuit is connected with the input end of the main control logic and the input end of the anti-interference logic; the anti-interference logic output end is connected with the delay logic input end.

Specifically, an OSC crystal oscillator: and the oscillator is integrated inside the electronic detonator chip and is used for generating a CLOCK for the work of the detonator chip.

POR power-on reset circuit: and a circuit of a full-chip reset signal POR generated after the electronic detonator chip is electrified, wherein the effective level of the POR signal is low level.

Master control logic: and the logic circuit for completing external communication and chip state switching control of the electronic detonator chip outputs an effective DELAY signal and a DELAY VALUE delay_value after entering a pre-detonation DELAY mode, and the effective level of the DELAY signal is high.

Anti-jamming logic: the POR is processed and then sent to the delay logic, so that the normal countdown of the counter of the delay logic is not influenced even if the chip resets after the chip enters the delay, and the initiation of the electronic detonator is not influenced. The signals output to the delay logic are counter START (START), counter initial LOAD (LOAD), and processed reset signal (POR_GATE)

Delay logic: the chip enters a control logic circuit for counting down before detonation and mainly comprises a counter. The counter START signal is from the START signal of the anti-jamming logic, the loading signal of the counter is from the LOAD signal of the anti-jamming logic, the CLOCK signal of the counter is from the CLOCK of the OSC crystal oscillator, and the reset signal of the counter is from the por_gate of the anti-jamming logic. And after the countdown is finished, opening an ignition switch to detonate the detonator.

Referring to fig. 2, the anti-interference logic circuit in the present application includes a 24-bit delay control register, a comparator, an or gate, two D flip-flops, an not gate, and an and gate.

The output end of the 24-bit delay control register is connected with the input end of the comparator, and the output end of the comparator is connected with the input ends of the first trigger and the OR gate; the output end of the OR gate is connected with the reset input end of the first trigger, the output end of the first trigger is connected with the input end of the second trigger and the AND gate, and the output end of the second trigger is connected with the NOT gate and then connected with the AND gate.

The application provides an anti-interference method for an electronic detonator, which is shown by referring to fig. 2 and 3, and comprises the following steps:

step S1: after the electronic detonator chip is normally powered on, an internal power-on reset circuit outputs a reset signal POR for resetting main control logic, anti-interference logic and delay logic of the chip. After the reset is finished, the electronic detonator chip enters a normal mode and waits for receiving an instruction.

Step S2: and controlling the exploder of the whole electronic detonator module to complete normal communication, chip configuration, high-voltage electric charge, delay time setting and other operations and then sending an explosion command.

Step S3: after the electronic detonator chip receives the detonation command, the main control logic control chip enters a countdown delay mode before detonation from a normal mode.

Step S4: after entering the deferred mode, the anti-interference logic shields the reset signal input by the deferred module, simultaneously sends a LOAD signal LOAD to the deferred logic for loading the deferred value of the 24-bit deferred counter, and then sends a START signal START to the deferred logic for driving the counter.

Step S5: the counter of the delay logic is started to start counting down.

Step S6: after the timer counts down to zero, an ignition control signal is output to detonate the medicine head.

After receiving the initiation command, all the electronic detonator chips enter a delay mode, and the paths from the chips to the delay logic are cut off through the anti-interference logic before initiation, so that the normal operation of the delay logic is not affected. Thus, even if an interference signal is generated by the detonator which is blasted after entering, the detonator which is blasted first causes the chip to reset, the detonator can not be blasted.

The whole working principle of the application is as follows: after receiving the initiation command, the master logic outputs an active DELAY signal (active high) and a 24-bit DELAY VALUE (delay_value) to the immunity logic and the DELAY logic, respectively.

The 24-bit delay control register in the anti-interference logic can load a characteristic value of 0xA5F05A, after the characteristic value is loaded, the comparator can output high level, the POR channel is cut off, namely the POR_GATE outputs high level, and the delay logic part is not controlled by chip reset.

Meanwhile, a LOAD signal with a clock width is generated through a two-stage D trigger, an NOT gate and an AND gate and is used for loading a 24-bit delay counter in delay logic, and the counter STARTs to count continuously because a counter starting signal START is kept at a high level in the next clock beat.

The counter of the delay logic is counted to zero and then detonates the electronic detonator.

The 24-bit delay control register in the anti-interference logic is not controlled by a reset signal, even if the state is uncertain when the anti-interference logic is powered on, the probability that the delay counter counts in advance due to the characteristic value of 0xA5F05A is smaller than 1/(2-24) to = 0.1 PPM, and the probability is far lower than the index of 1PPM of the industrial electronic detonator explosion rejection rate. And even if the electronic detonator is counted in advance, the storage capacitor of the electronic detonator is not charged at the moment, so that the electronic detonator is not actually influenced.

The embodiment of the application provides an anti-interference method and medium for an electronic detonator, wherein special anti-interference logic is designed in the electronic detonator chip, and reset signals input by the delay logic can be automatically shielded in the chip once the chip receives a detonation command to enter a delay mode of detonation countdown. Therefore, even if external interference enters the chip to cause the chip to reset, the normal countdown of delay logic is not influenced, and the medicine head can be detonated normally after the countdown is finished, so that the explosion rejection is avoided.

Those skilled in the art will appreciate that the application provides a system and its individual devices, modules, units, etc. that can be implemented entirely by logic programming of method steps, in addition to being implemented as pure computer readable program code, in the form of logic gates, switches, application specific integrated circuits, programmable logic controllers, embedded microcontrollers, etc. Therefore, the system and various devices, modules and units thereof provided by the application can be regarded as a hardware component, and the devices, modules and units for realizing various functions included in the system can also be regarded as structures in the hardware component; means, modules, and units for implementing the various functions may also be considered as either software modules for implementing the methods or structures within hardware components.

The foregoing describes specific embodiments of the present application. It is to be understood that the application is not limited to the particular embodiments described above, and that various changes or modifications may be made by those skilled in the art within the scope of the appended claims without affecting the spirit of the application. The embodiments of the application and the features of the embodiments may be combined with each other arbitrarily without conflict.

Claims

1. An anti-interference method for an electronic detonator, comprising:

step S5: starting a counter of delay logic to start counting down;

2. The anti-interference method for electronic detonator according to claim 1, wherein the step S3 specifically comprises: after receiving the initiation command, all the electronic detonator chips enter a delay mode, and the chip is cut off from a path to delay logic through anti-interference logic before initiation.

3. The method of claim 1, wherein upon power-up, the 24-bit delay control register loads a characteristic value of 0xA5F05A, and the comparator outputs a high level to turn off the POR path after the characteristic value is loaded.

4. A computer-readable storage medium storing a computer program, characterized in that the computer program, when executed by a processor, implements the steps of the method of any one of claims 1 to 3.