CN111948931A - Clock rapid correction method for electronic detonator - Google Patents
Clock rapid correction method for electronic detonator Download PDFInfo
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- CN111948931A CN111948931A CN202010791210.2A CN202010791210A CN111948931A CN 111948931 A CN111948931 A CN 111948931A CN 202010791210 A CN202010791210 A CN 202010791210A CN 111948931 A CN111948931 A CN 111948931A
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- clock
- value
- electronic detonator
- correction
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- G—PHYSICS
- G04—HOROLOGY
- G04G—ELECTRONIC TIME-PIECES
- G04G5/00—Setting, i.e. correcting or changing, the time-indication
- G04G5/02—Setting, i.e. correcting or changing, the time-indication by temporarily changing the number of pulses per unit time, e.g. quick-feed method
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- F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
- F42—AMMUNITION; BLASTING
- F42C—AMMUNITION FUZES; ARMING OR SAFETY MEANS THEREFOR
- F42C21/00—Checking fuzes; Testing fuzes
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
- G05B19/042—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
- G05B19/0423—Input/output
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- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Automation & Control Theory (AREA)
- General Engineering & Computer Science (AREA)
- Manipulation Of Pulses (AREA)
- Electric Clocks (AREA)
Abstract
The invention provides a clock rapid correction method for an electronic detonator, which comprises the following steps: the electronic detonator chip is powered on, data are loaded from the nonvolatile memory circuit, whether clock correction is conducted or not is judged, if no clock correction is conducted, the electronic detonator chip continuously feeds back information, whether a clock writing configuration register instruction sent by an upper computer is received or not is judged, if the clock writing configuration register instruction is received, the electronic detonator chip stops feeding back, and after the clock correction instruction sent by the upper computer is received by the electronic detonator, the counter counts in a set period based on the clock correction instruction, and a counting value OSC _ C is obtained. The initiator reads the OSC _ C, adjusts the clock configuration word according to the OSC _ C and writes the clock configuration word into a register CKCFG of the electronic detonator chip; the above steps are repeated until the clock frequency is within a stable range, and finally the value in the register CKCFG is written into the non-volatile memory circuit. The invention realizes the accurate correction of the clock.
Description
Technical Field
The invention relates to the field of electronic detonators, in particular to a clock quick correction method for an electronic detonator.
Background
The electronic detonator chip is applied to the blasting industry, so that all indexes of the electronic detonator chip are stable and reliable. The application scenes are various, and even strong interference can be generated in part of the application scenes, so that the accuracy of communication is seriously hindered. Stable communication can not be generated, the probability of the electronic detonator generating the misfire can be greatly increased, and great damage is caused to production activities. The stable and accurate clock is the primary guarantee that the detonator can work correctly.
The invention patent of the prior document CN 103868416 a discloses a method for correcting the original oscillation frequency clock of a chip, which is based on that the chip comprises a digital logic processing circuit, a nonvolatile memory circuit, an oscillator clock circuit and a current feedback circuit, which are connected with the digital logic processing circuit, the output port of the digital logic processing circuit is used for adjusting the output frequency of the oscillator clock circuit, and a first counter and a second counter are arranged in the digital logic processing circuit, a host sends an instruction for modifying the output port to the chip, the instruction contains a data, and the data is stored in the memory circuit. The scheme realizes the correction of the clock by continuously modifying the clock configuration word and continuously timing the feedback interval, but the reading precision of the clock counting of the scheme is low.
Disclosure of Invention
Aiming at the defects in the prior art, the invention aims to provide a clock quick correction method for an electronic detonator.
The invention provides a clock quick correction method for an electronic detonator, which comprises the following steps:
and clock correction judgment: electrifying the electronic detonator chip, loading data from the nonvolatile memory circuit, judging whether the clock is corrected or not, and if so, enabling the electronic detonator chip to work normally; if the judgment result is negative, entering a feedback step;
a feedback step: continuously feeding back information to the upper computer by the electronic detonator chip, judging whether a clock writing configuration register instruction sent by the upper computer is received or not, if so, stopping feeding back by the electronic detonator chip, and entering a step of acquiring a clock correction value; if the judgment result is negative, the electronic detonator chip continues to feed back information to the upper computer;
acquiring a clock correction value: after the electronic detonator receives a clock correction instruction sent by an upper computer, the counter counts in a set period based on the clock correction instruction to obtain a count value OSC _ C; the upper computer sends a command to read the OSC _ C;
and a comparison writing step: the upper computer compares the OSC _ C value with the standard value to obtain a clock frequency deviation range, modifies the value of the clock configuration word and writes the value into a register CKCFG of the electronic detonator chip again;
a data writing step: and repeating the steps of acquiring the clock correction value and comparing and writing until the clock frequency is in a stable range, sending a command by the upper computer to write the value in the CKCFG register into the nonvolatile memory circuit, and automatically writing the PROG into the nonvolatile memory circuit after the electronic detonator chip receives the command.
Preferably, the clock correction instruction is followed by two square waves or alternatively a flag signal.
Preferably, the counter OSC _ C starts counting clock edges when a first rising edge of the square wave is detected and ends counting when a second rising edge of the square wave is received.
Preferably, the value of PROG in the non-volatile memory circuit represents whether the clock has been corrected.
Preferably, the PROG initial value is a value representing uncorrected.
Preferably, when the PROG value becomes representative of a corrected value, then the PROG value is always that value.
Preferably, the upper computer calculates the approximate value of the clock frequency of the electronic detonator chip at the moment according to two feedback time intervals before and after the electronic detonator chip, and selects the data transmission frequency according to the approximate value of the clock frequency.
Preferably, the clock correction instruction sent by the upper computer is adjusted according to the clock frequency of the electronic detonator.
Preferably, the initial value of the configuration word CKCFG of the clock is a gear intermediate value.
Compared with the prior art, the invention has the following beneficial effects:
1. according to the invention, the pulse with fixed duration is counted by the electronic detonator, and the clock configuration word is modified after the count value is read by the detonator, so that accurate correction is realized;
2. according to the method, the fixed duration signal sent by the detonator is timed through the electronic detonator, and then the detonator reads out the count value in the chip for calibration, so that the clock can be calibrated to the most accurate gear;
3. the invention directly reads the value counted by the clock, and has high reading precision.
Drawings
Other features, objects and advantages of the invention will become more apparent upon reading of the detailed description of non-limiting embodiments with reference to the following drawings:
FIG. 1 is a schematic circuit diagram of an electronic detonator;
FIG. 2 is a flow chart of the clock fast correction method for the electronic detonator of the present invention.
Detailed Description
The present invention will be described in detail with reference to specific examples. The following examples will assist those skilled in the art in further understanding the invention, but are not intended to limit the invention in any way. It should be noted that it would be obvious to those skilled in the art that various changes and modifications can be made without departing from the spirit of the invention. All falling within the scope of the present invention.
As shown in fig. 1 and 2, the invention provides a clock fast correction method for an electronic detonator, which can continuously generate current feedback when clock correction is not performed on the basis of an electronic detonator chip. And the upper computer calculates the deviation of the clock configuration word according to the time intervals of the front feedback and the back feedback, then switches the sending frequency of the instruction, writes the calculated configuration word into the electronic detonator chip and completes the coarse clock adjustment. The upper computer sends a specified command and a fixed number of square waves, and the electronic detonator chip counts the number of clocks during the sending of the square waves. And then the upper computer reads the count value of the core slice, adjusts the configuration word and rewrites the configuration word to realize fine adjustment. The fine tuning process is repeated for a plurality of times, so that the clock is more accurate.
More specifically, the electronic detonator of the present invention comprises an input signal processing circuit, a power supply, a reference voltage, a current feedback circuit, an oscillator, a nonvolatile memory circuit, a reset circuit, a digital logic circuit, a charge control unit, a discharge control unit, an ignition control unit, an external bridge wire terminal, an energy storage capacitor, and a detonator, wherein:
the input signal processing circuit is connected with two buses and used for realizing rectification, converting signals into digital logic levels and inputting the digital logic levels into the digital logic circuit.
The power supply provides stable voltage for the reference voltage module, provides charging voltage for the charging module and provides voltage and current for normal work of the chip.
The reference voltage provides a stable voltage current for the chip to work.
When the current feedback circuit is opened, the current consumed by the chip is increased, and the upper computer judges whether the chip generates feedback or not by detecting whether the bus current is increased or not. During feedback, the digital logic circuit opens and closes the current feedback circuit through dout, and the feedback duration time of the current feedback circuit is controlled by the digital logic circuit.
The oscillator provides a stable clock clk through the digital logic module.
The non-volatile memory circuit is controlled by a digital logic circuit, and the EEPROM is used in the invention.
The reset circuit is used for detecting whether the power supply voltage is normal or not, and generating a reset signal nrst if the power supply voltage is abnormal.
The digital logic circuit is used for controlling the chip to work.
The charging control unit is used for controlling charging, the digital logic circuit controls whether the detonator chip carries out charging operation, and the charging voltage is provided by the power supply.
The discharge control unit is used for controlling discharge, and the digital logic circuit controls whether the detonator chip carries out discharge operation or not.
The ignition control unit is used for ignition control, and the digital logic circuit controls whether the detonator chip is ignited and detonated.
The detonating tube is a low-on-resistance NMOS for controlling whether to detonate, the base level is connected with the ignition control unit, and the emitter level is grounded.
One end of the external bridgewire terminal is connected with the charging control unit and the discharging control unit, and the other end of the external bridgewire terminal is connected with a collector of the detonating tube.
The energy storage capacitor is used for supplying power to the chip during the delay period and supplying energy required by detonation under the condition that the bus is broken.
The working principle of the invention is as follows:
assuming that the clock range of the electronic detonator is 150K-250KHZ, the clock needs to be adjusted to 200 KHZ.
The configuration word CKCFG of the clock is 8 bits wide with an initial value of 8' h 80.
PROG in the non-volatile memory circuit represents whether clock correction is performed, and the initial 0 is always 1 after one correction. CKCFG in a non-volatile memory circuit is only valid for PROG of 1 and can be loaded into a register as a clock configuration word.
The method specifically comprises the following steps:
step 1: after the electronic detonator chip is powered on, data is loaded from the nonvolatile memory circuit, and the PROG is not 1, the CKCFG in the nonvolatile memory circuit is invalid. At this time, the electronic detonator chip will autonomously and continuously feed back a signal, which indicates that the clock correction is not performed by itself.
Step 2: the upper computer calculates the approximate value of the clock frequency of the electronic detonator chip at the moment according to the time intervals of the front feedback and the back feedback of the electronic detonator chip, and then selects the data transmission frequency according to the value. The instruction sent by the upper computer needs to be adjusted according to the clock frequency of the detonator chip, otherwise, communication errors can be caused due to frequency deviation.
And step 3: the upper computer sends a clock correction instruction, and the instruction is followed by 2 square waves.
And 4, step 4: after the electronic detonator receives the instruction, the counter OSC _ C starts counting the clock edges when detecting the first square wave rising edge of the square wave, and finishes counting when receiving the second square wave rising edge.
And 5: and the upper computer sends a correction value reading instruction and reads out the value of OSC _ C.
Step 6: and the upper computer compares the value of the OSC _ C with the standard value to obtain a deviation range, modifies the value of the clock configuration word and sends a write clock configuration word instruction to write the write clock configuration word into a register CKCFG of the detonator chip.
And 7: repeating steps 3-6 until the clock is in a stable range.
And 8: the host computer sends a command to write the value in register CKCFG into the non-volatile memory circuit. After the detonator chip receives the command, the PROG is also automatically written into the non-volatile memory circuit.
According to the invention, the pulse with fixed duration is counted by the electronic detonator, and the clock configuration word is modified after the count value is read by the detonator, so that accurate correction is realized; the method comprises the steps that a fixed duration signal sent by an initiator is timed through an electronic detonator, and then the initiator reads out a count value in a chip for calibration, so that a clock can be calibrated to the most accurate gear; the invention directly reads the value counted by the clock, and has high reading precision.
The foregoing description of specific embodiments of the present invention has been presented. It is to be understood that the present invention is not limited to the specific embodiments described above, and that various changes or modifications may be made by one skilled in the art within the scope of the appended claims without departing from the spirit of the invention. The embodiments and features of the embodiments of the present application may be combined with each other arbitrarily without conflict.
Claims (9)
1. A clock rapid correction method for an electronic detonator is characterized by comprising the following steps:
and clock correction judgment: electrifying the electronic detonator chip, loading data from the nonvolatile memory circuit, judging whether the clock is corrected or not, and if so, enabling the electronic detonator chip to work normally; if the judgment result is negative, entering a feedback step;
a feedback step: continuously feeding back information to the upper computer by the electronic detonator chip, judging whether a clock writing configuration register instruction sent by the upper computer is received or not, if so, stopping feeding back by the electronic detonator chip, and entering a step of acquiring a clock correction value; if the judgment result is negative, the electronic detonator chip continues to feed back information to the upper computer;
acquiring a clock correction value: after the electronic detonator receives a clock correction instruction sent by an upper computer, the counter counts in a set period based on the clock correction instruction to obtain a count value OSC _ C; the upper computer sends a command to read out the OSC _ C value;
and a comparison writing step: the upper computer compares the OSC _ C value with the standard value to obtain a clock frequency deviation range, modifies the value of the clock configuration word and writes the value into a register CKCFG of the electronic detonator chip again;
a data writing step: and repeating the steps of acquiring the clock correction value and comparing and writing until the clock frequency is in a stable range, sending a command by the upper computer to write the value in the CKCFG register into the nonvolatile memory circuit, and automatically writing the PROG into the nonvolatile memory circuit after the electronic detonator chip receives the command.
2. The method of claim 1 in which the clock correction instruction is followed by two square waves or alternatively a flag signal.
3. The method of claim 2, wherein the counter OSC _ C starts counting clock edges when a first rising edge of a square wave is detected and ends counting when a second rising edge of the square wave is received.
4. The method for quickly correcting the clock for the electronic detonator as claimed in claim 1, wherein the value of PROG in the nonvolatile memory circuit represents whether the clock has been corrected.
5. The method for rapid clock correction for electronic detonators according to claim 4, wherein the PROG initial value is a value representing no correction.
6. The method for rapid clock correction for electronic detonators according to claim 4, wherein when the PROG value becomes a value representing a corrected value, the PROG value is always that value.
7. The method for rapidly correcting the clock of the electronic detonator according to claim 1, wherein the upper computer calculates the approximate value of the clock frequency of the detonator chip at the moment according to two feedback time intervals before and after the electronic detonator chip, and selects the data transmission frequency according to the approximate value of the clock frequency.
8. The method for rapidly correcting the clock of the electronic detonator according to claim 1, wherein the clock correction instruction sent by the upper computer is adjusted according to the clock frequency of the electronic detonator.
9. The method for rapidly correcting the clock for the electronic detonator according to claim 1, wherein the initial value of the configuration word CKCFG of the clock is a gear intermediate value.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010791210.2A CN111948931B (en) | 2020-08-07 | 2020-08-07 | Clock rapid correction method for electronic detonator |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202010791210.2A CN111948931B (en) | 2020-08-07 | 2020-08-07 | Clock rapid correction method for electronic detonator |
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| CN111948931A true CN111948931A (en) | 2020-11-17 |
| CN111948931B CN111948931B (en) | 2021-06-04 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114858020A (en) * | 2022-04-26 | 2022-08-05 | 上海芯飏科技有限公司 | Anti-interference method, system and medium for electronic detonator |
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2020
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114858020A (en) * | 2022-04-26 | 2022-08-05 | 上海芯飏科技有限公司 | Anti-interference method, system and medium for electronic detonator |
| CN114858020B (en) * | 2022-04-26 | 2023-09-29 | 上海芯飏科技有限公司 | Anti-interference method and medium for electronic detonator |
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