CN114858020A

CN114858020A - Anti-interference method, system and medium for electronic detonator

Info

Publication number: CN114858020A
Application number: CN202210446563.8A
Authority: CN
Inventors: 朱志明; 郑弘毅
Original assignee: Shanghai Xinyang Technology Co ltd
Current assignee: Shanghai Xinyang Technology Co ltd
Priority date: 2022-04-26
Filing date: 2022-04-26
Publication date: 2022-08-05
Anticipated expiration: 2042-04-26
Also published as: CN114858020B

Abstract

The invention provides an anti-interference method, a system and a medium for an electronic detonator, which comprise the following steps: step S1: after the electronic detonator chip is powered on, the electric reset circuit outputs a reset signal POR, and the electronic detonator chip enters a normal mode to wait for receiving an instruction; step S2: the detonator sends a detonation command after completing normal communication, chip configuration, high-voltage capacitor charging and delay time setting operations; step S3: after the electronic detonator chip receives the detonation command, the main control logic control chip enters a delay mode of countdown before detonation; step S4: the anti-interference logic shields a reset signal input by the delay module, simultaneously sends a LOAD signal LOAD to the delay logic, and then sends a START signal START to the delay logic to drive a counter; step S5: starting a counter of the delay logic, and starting counting down; step S6: after the timer counts down to zero, an ignition control signal is output to detonate the explosive head. The invention can solve the frequent misfire problem in the blasting of the tunneling face.

Description

Anti-interference method, system and medium for electronic detonator

Technical Field

The invention relates to the technical field of electronic detonators, in particular to an anti-interference method, system and medium for an electronic detonator.

Background

With the application of the electronic detonator being more and more prevented, the electronic detonator has an obvious blind shot problem when blasting on the driving face of some underground mines. When the electronic detonators are subjected to networking blasting, the set time delay is different, the blasting area of the tunneling surface is smaller, the distance between the networked electronic detonators is closer, and interference signals such as strong electromagnetic waves or static electricity and the like generated after the electronic detonators which are blasted firstly explode can enter the electronic detonator module from two leg wires of the electronic detonators which are not exploded, so that the electronic detonator chip is instantaneously punctured or reset, the electronic detonator module stops working, and the electronic detonator module fails to explode.

In the existing electronic detonator modules, a protection circuit is added at the front stage of an electronic detonator chip or a discharge device is added to inhibit some interference signals generated in a blasting environment, but the problem of explosion rejection on a blasting field of a tunneling surface of an underground mine is still more, and the electronic detonator module which is subjected to explosion rejection is analyzed, and most of reasons are that the detonator chip is reset.

Interference signals in the blasting environment are basically high-frequency pulses, the signals cannot be completely eliminated through an external circuit, and the reset of the chip is easily caused after the signals enter the chip. And once reset, blind shots will appear.

The invention with the publication number of CN112393653A discloses an electronic detonator blasting control system for improving the anti-interference performance, which comprises an initiator and a plurality of electronic detonator modules, wherein each electronic detonator module is connected with the initiator in parallel, each electronic detonator module is provided with a switch structure, and when the electronic detonator modules receive an initiation instruction sent by the initiator and start to perform initiation, the electronic detonator modules control the switch structures to be in a closed state, so that the electronic detonator modules, the initiator and other electronic detonator modules are in a physical isolation state.

Disclosure of Invention

Aiming at the defects in the prior art, the invention provides an anti-interference method, a system and a medium for an electronic detonator.

According to the anti-interference method, the anti-interference system and the anti-interference medium for the electronic detonator, the scheme is as follows:

in a first aspect, there is provided an anti-tamper method for an electronic detonator, the method comprising:

step S1: after the electronic detonator chip is powered on, an internal power-on reset circuit outputs a reset signal POR, and after the reset is finished, the electronic detonator chip enters a normal mode to wait for receiving an instruction;

step S2: controlling an exploder of the whole electronic detonator module to complete normal communication, chip configuration, high-voltage capacitor charging and delay time setting operation and then sending an explosion command;

step S3: after the electronic detonator chip receives the detonation command, the main control logic control chip enters a delay mode of countdown before detonation from a normal mode;

step S4: after entering a delay mode, the anti-interference logic shields a reset signal input by a delay module, simultaneously sends a LOAD signal LOAD to the delay logic, and then sends a START signal START to the delay logic to drive a counter;

step S5: starting a counter of the delay logic, and starting counting down;

step S6: after the timer counts down to zero, an ignition control signal is output to detonate the explosive head.

Preferably, the step S3 specifically includes: after receiving a detonation command, all electronic detonator chips enter a delay mode, and before detonation, the anti-interference logic cuts off the path of the chips to be reset to delay logic.

Preferably, the interference rejection logic comprises: the delay circuit comprises a 24-bit delay control register, a comparator, an OR gate, two D triggers, a NOT gate and an AND gate;

the output end of the 24-bit delay control register is connected with the input end of a comparator, and the output end of the comparator is connected with the input ends of a first trigger and an OR gate;

the output end of the OR gate is connected with the input end of the first trigger, the output end of the first trigger is connected with the input end of the second trigger and the AND gate, and the output end of the second trigger is connected with the AND gate after being connected with the NOT gate.

Preferably, a 24-bit delay control register in the anti-interference logic is not controlled by a reset signal, the characteristic value of 0xA5F05A is met when the anti-interference logic is powered on, and the probability of early counting of a delay counter is less than 1/(2^24) to less than 0.1 PPM.

In a second aspect, there is provided an anti-tamper system for an electronic detonator, the system comprising:

module M1: after the electronic detonator chip is powered on, an internal power-on reset circuit outputs a reset signal POR, and after the reset is finished, the electronic detonator chip enters a normal mode to wait for receiving an instruction;

module M2: controlling an exploder of the whole electronic detonator module to complete normal communication, chip configuration, high-voltage capacitor charging and delay time setting operation and then sending an explosion command;

module M3: after the electronic detonator chip receives the detonation command, the main control logic control chip enters a delay mode of countdown before detonation from a normal mode;

module M4: after entering a delay mode, the anti-interference logic shields a reset signal input by a delay module, simultaneously sends a LOAD signal LOAD to the delay logic, and then sends a START signal START to the delay logic to drive a counter;

module M5: starting a counter of the delay logic, and starting counting down;

module M6: after the timer counts down to zero, an ignition control signal is output to detonate the explosive head.

Preferably, the module M3 specifically includes: after receiving a detonation command, all electronic detonator chips enter a delay mode, and before detonation, the anti-interference logic cuts off the path of the chips to be reset to delay logic.

In a second aspect, a computer-readable storage medium is provided, in which a computer program is stored, which computer program, when being executed by a processor, carries out the steps of the method.

Compared with the prior art, the invention has the following beneficial effects:

1. after the electronic detonator chip receives the detonation command and enters a delay mode, the interior of the chip can automatically cut off a reset passage, even if the chip is reset by external interference, the normal work of delay logic can not be influenced, and the detonator chip is not interfered by electromagnetic pulse or electrostatic signals caused by explosion;

2. the method is easy to realize, has good electromagnetic pulse or electrostatic interference resistance effect, and can solve the problem of frequent misfire in the blasting of the driving face.

Drawings

Other features, objects and advantages of the invention will become more apparent upon reading of the detailed description of non-limiting embodiments with reference to the following drawings:

FIG. 1 is a schematic diagram of a circuit configuration;

FIG. 2 is a schematic diagram of an interference rejection logic circuit;

fig. 3 is an exemplary diagram of an operating waveform.

Detailed Description

The present invention will be described in detail with reference to specific examples. The following examples will assist those skilled in the art in further understanding the invention, but are not intended to limit the invention in any way. It should be noted that it would be obvious to those skilled in the art that various changes and modifications can be made without departing from the spirit of the invention. All falling within the scope of the present invention.

The embodiment of the invention provides an anti-interference method for an electronic detonator, wherein special anti-interference logic is designed in an electronic detonator chip, and once the chip receives a detonation command and enters a delay mode of detonation countdown, a reset signal input by the delay logic can be automatically shielded in the chip. The method comprises the following specific steps:

referring to fig. 1, the invention is a schematic diagram of a circuit composition structure in the invention, and in the figure, an electronic detonator module receives an instruction of an electronic detonator initiator through a leg wire to complete detonation and explosive detonation. The electronic detonator chip protection circuit comprises a preceding stage protection circuit, an electronic detonator chip and other elements, wherein the preceding stage protection circuit is connected with the electronic detonator chip.

Specifically, the front-stage protection circuit generally includes some transient high-voltage suppression tubes, electrostatic protection tubes, etc. to suppress the transient high-voltage signal entering from the pin line.

The electronic detonator chip is a main control chip of the electronic detonator module, receives an instruction, controls delay and completes detonation. The electronic detonator chip comprises a high-voltage circuit, an LDO low-voltage stabilizing circuit and an anti-interference logic subsystem, wherein the output end of the high-voltage circuit is connected with the input end of the LDO low-voltage stabilizing circuit, and the output end of the LDO low-voltage stabilizing circuit is connected with the input end of the anti-interference logic subsystem and serves as a power supply of the anti-interference logic subsystem.

Wherein, high-voltage circuit: the detonator chip mainly comprises an external communication circuit, an internal voltage reference circuit and the like of the detonator chip.

The LDO low-voltage stabilizing circuit comprises: the low voltage generating circuit used for the digital circuit and part of the analog circuit of the electronic detonator chip outputs VCORE, which is generally 1.8V-5V.

The anti-interference logic subsystem comprises an OSC crystal oscillator, a POR power-on reset circuit, a main control logic, an anti-interference logic and a delay logic. The output end of the OSC crystal oscillator is connected with the main control logic input end, the anti-interference logic input end and the delay logic input end; the main control logic output end is connected with the anti-interference logic input end and the delay logic input end; the output end of the POR power-on reset circuit is connected with the main control logic input end and the anti-interference logic input end; the anti-interference logic output end is connected with the delay logic input end.

Specifically, the OSC crystal oscillator: and the oscillator is integrated in the electronic detonator chip and is used for generating a CLOCK for the work of the detonator chip.

POR power-on reset circuit: the circuit of the full chip reset signal POR generated after the electronic detonator chip is powered on, wherein the effective level of the POR signal is low level.

The master control logic: the logic circuit for finishing external communication of the electronic detonator chip and chip state switching control outputs an effective DELAY signal and a DELAY VALUE DELAY _ VALUE after entering a DELAY mode before detonation, and the effective level of the DELAY signal is high level.

And (3) anti-interference logic: the chip power-on reset POR is processed and then sent to the delay logic, so that the normal countdown of a counter of the delay logic cannot be influenced even if the chip is reset once the chip enters the delay, and the detonation of the electronic detonator cannot be influenced. The signals output to the delay logic include a counter START (START), a counter initial LOAD (LOAD), and a processed reset signal (POR _ GATE)

The delay logic: the chip enters a control logic circuit for counting down before detonation, and mainly comprises a counter. The counter START signal is from the START signal of the interference rejection logic, the LOAD signal of the counter is from the LOAD signal of the interference rejection logic, the CLOCK signal of the counter is from the CLOCK of the OSC crystal oscillator, and the reset signal of the counter is from the POR _ GATE of the interference rejection logic. And after the countdown is finished, opening an ignition switch to ignite the detonator.

Referring to fig. 2, the anti-interference logic circuit of the present invention includes a 24-bit delay control register, a comparator, an or gate, two D flip-flops, a not gate, and an and gate.

The output end of the 24-bit delay control register is connected with the input end of a comparator, and the output end of the comparator is connected with the first trigger and the input end of an OR gate; the output end of the OR gate is connected with the reset input end of the first trigger, the output end of the first trigger is connected with the input end of the second trigger and the AND gate, and the output end of the second trigger is connected with the NOT gate and then the AND gate.

The invention provides an anti-interference method for an electronic detonator, which is shown in a reference figure 2 and a reference figure 3, and comprises the following steps:

step S1: after the electronic detonator chip is normally powered on, the internal power-on reset circuit outputs a reset signal POR for resetting the main control logic, the anti-interference logic and the delay logic of the chip. After the resetting is finished, the electronic detonator chip enters a normal mode and waits for receiving an instruction.

Step S2: and controlling the exploder of the whole electronic detonator module to complete normal communication, chip configuration, high-voltage capacitor charging, delay time setting and the like, and then sending an explosion command.

Step S3: after the electronic detonator chip receives the detonation command, the main control logic control chip enters a delay mode of countdown before detonation from a normal mode.

Step S4: after entering the delay mode, the anti-interference logic shields the reset signal input by the delay module, and simultaneously sends a LOAD signal LOAD to the delay logic for loading a delay value to the 24-bit delay counter, and then sends a START signal START to the delay logic to drive the counter.

Step S5: the counter of the deferral logic starts to count down.

After receiving the detonation command, all the electronic detonator chips enter a delay mode, and before detonation, the chips are cut off through anti-interference logic to reset to a path of delay logic, and the normal operation of the delay logic is not influenced. Therefore, even if the detonator which is blasted first generates an interference signal and enters the detonator which is blasted later, the chip reset can not cause the detonator to fail.

The overall working principle of the invention is as follows: after receiving the firing command, the master logic outputs an active DELAY signal (active high) and a 24-bit DELAY VALUE (DELAY _ VALUE) to the interference suppression logic and the DELAY logic, respectively.

The 24-bit delay control register in the anti-interference logic is loaded with a feature word "0 xA5F 05A", after the feature word is loaded, the comparator outputs high level to cut off the POR path, i.e. POR _ GATE outputs high level, and the delay logic part is not controlled by the chip reset any more.

And meanwhile, a LOAD signal with a clock width is generated through a two-stage D flip-flop, a NOT gate and an AND gate and is used for loading a 24-bit delay counter in the delay logic, and the counter STARTs to count continuously because a counter START signal START of the next clock beat also keeps high level.

The counter of the delay logic counts until zero and then detonates the electronic detonator.

A24-bit delay control register in the anti-interference logic is not controlled by a reset signal, and even if the state is uncertain when the anti-interference logic is electrified, the probability that the delay counter counts in advance due to the characteristic value '0 xA5F 05A' is just less than 1/(2^24) ~ 0.1PPM, and is far lower than the index of the industry electronic detonator misfire rate 1 PPM. Even if counting is carried out in advance, the energy storage capacitor of the electronic detonator is not charged at the moment, and the detonator is not actually influenced.

The embodiment of the invention provides an anti-interference method, a system and a medium for an electronic detonator. Therefore, even if external interference enters the chip to cause the chip to reset, normal countdown of delay logic cannot be influenced, and the explosive head can be detonated normally after the countdown is finished, so that the misfire is avoided.

Those skilled in the art will appreciate that, in addition to implementing the system and its various devices, modules, units provided by the present invention as pure computer readable program code, the system and its various devices, modules, units provided by the present invention can be fully implemented by logically programming method steps in the form of logic gates, switches, application specific integrated circuits, programmable logic controllers, embedded microcontrollers and the like. Therefore, the system and various devices, modules and units thereof provided by the invention can be regarded as a hardware component, and the devices, modules and units included in the system for realizing various functions can also be regarded as structures in the hardware component; means, modules, units for performing the various functions may also be regarded as structures within both software modules and hardware components for performing the method.

The foregoing description of specific embodiments of the present invention has been presented. It is to be understood that the present invention is not limited to the specific embodiments described above, and that various changes or modifications may be made by one skilled in the art within the scope of the appended claims without departing from the spirit of the invention. The embodiments and features of the embodiments of the present application may be combined with each other arbitrarily without conflict.

Claims

1. An anti-interference method for an electronic detonator, comprising:

step S2: controlling the exploder of the whole electronic exploder module to complete normal communication, chip configuration, high-voltage capacitor charging and delay time setting operation and then sending an explosion command;

step S5: starting a counter of the delay logic, and starting counting down;

2. The method according to claim 1, wherein the step S3 specifically includes: after receiving a detonation command, all electronic detonator chips enter a delay mode, and before detonation, the anti-interference logic cuts off the path of the chips to be reset to delay logic.

3. The method of claim 1, wherein the immunity logic comprises: the delay circuit comprises a 24-bit delay control register, a comparator, an OR gate, two D triggers, a NOT gate and an AND gate;

4. The method according to claim 3, wherein the 24-bit delay control register in the anti-jamming logic is not controlled by the reset signal, meets a characteristic value of "0 xA5F 05A" immediately after power-on, and has a probability of counting in advance by the delay counter of less than 1/(2^24) to less than 0.1 PPM.

5. An anti-jamming system for an electronic detonator, comprising:

module M5: starting a counter of the delay logic, and starting counting down;

6. The anti-jamming system for electronic detonators of claim 5 wherein the module M3 specifically comprises: after receiving a detonation command, all electronic detonator chips enter a delay mode, and before detonation, the anti-interference logic cuts off the path of the chips to be reset to delay logic.

7. The immunity system for electronic detonators of claim 5 wherein the immunity logic includes: the delay circuit comprises a 24-bit delay control register, a comparator, an OR gate, two D triggers, a NOT gate and an AND gate;

8. The system of claim 7, wherein the 24-bit delay control register in the interference rejection logic is not controlled by the reset signal, and satisfies a characteristic value of "0 xA5F 05A" immediately after power-on, and the probability of the delay counter counting ahead is less than 1/(2^24) to 0.1PPM or less.

9. A computer-readable storage medium, in which a computer program is stored which, when being executed by a processor, carries out the steps of the method of any one of claims 1 to 4.