CN115325892B

CN115325892B - Method and system for analyzing whether electronic detonator is interfered to reset or not

Info

Publication number: CN115325892B
Application number: CN202211177949.XA
Authority: CN
Inventors: 朱志明; 金越海; 郑弘毅; 金宝全; 冯吉诚; 刘浩
Original assignee: Shanghai Xinyang Technology Co ltd
Current assignee: Shanghai Xinyang Technology Co ltd
Priority date: 2022-09-27
Filing date: 2022-09-27
Publication date: 2023-02-03
Anticipated expiration: 2042-09-27
Also published as: CN115325892A

Abstract

The invention provides a method and a system for analyzing whether an electronic detonator is interfered and reset, wherein the method comprises the following steps: the detonator supplies power to the electronic detonator module through the buses A and B; the electronic detonator chip accumulates the reset times stored in the reset time register; the initiator carries out networking of electronic detonator chips and carries out online roll calling on the electronic detonator chips; after receiving the roll call command, the electronic detonator chip returns the user identification code UID of the electronic detonator chip; the method comprises the steps that a UID of an electronic detonator chip and a corresponding reset number N are built in a mapping table and then stored in Flash inside an exploder; after networking is completed, the exploder performs a series of operations to complete the actual explosion of the current electronic detonator module; after the solid explosion is completed, if the electronic detonator module fails to explode, the electronic detonator module is further analyzed by the exploder. The invention is beneficial to the improvement and optimization of the anti-interference scheme of the electronic detonator, and reduces the anti-explosion rate of the electronic detonator in various small-section applications.

Description

Method and system for analyzing whether electronic detonator is interfered to reset or not

Technical Field

The invention relates to the technical field of electronic detonators, in particular to a method and a system for analyzing whether the electronic detonators are interfered and reset.

Background

With the wide application of the electronic detonator, the electronic detonator has obvious blind shot problem in some blasting sites, particularly in the small-section tunneling blasting of underground mines. Different from the application of ground open blasting, the underground small-section blasting surface is narrow and small, the hole spacing is small, different delays are usually required to be set when the electronic detonators are subjected to networking blasting, the spacing between the electronic detonators subjected to networking is relatively close, and strong shock waves and electromagnetic interference generated after the electronic detonators which are blasted first explode can influence the detonators subjected to post blasting, so that the electronic detonators stop working or are abnormal. The electronic detonators which are not detonated have good appearance and no obvious structural damage, wherein some internal circuits of the detonators are damaged and cannot be repaired; some of the detonator circuits were intact. Some misfired detonators with damaged appearance are usually caused by mechanical damage caused by earlier explosion, and similar situations can exist in other blasting scenes.

In the prior art, part of electronic detonator modules inhibit or weaken the influence of interference through an additional protective circuit or a discharging device at the front stage of a chip, but actually, because the frequency of an interference signal is too high, the interference signal is difficult to completely eliminate, and residual signals still easily enter the chip to cause detonator failure. Once the chip is reset, all information in the field is lost, and an effective means for further analysis is lacked.

The invention discloses an anti-electromagnetic interference method for an electronic detonator, which is disclosed in patent document with publication number CN 111750748A. When the small-section blasting is carried out, the electromagnetic interference is easy to cause the false triggering and the misfire of the electronic detonator. The method is characterized in that a level output pin g is additionally arranged in a control chip, the pin g outputs a low level after the control chip is powered on and reset, and outputs a high level after the control chip receives a detonation command; an Nmos tube and an anti-reflux diode are additionally arranged; and a pin g is connected with the grid electrode of the Nmos tube, the drain electrode of the Nmos tube is connected with the anode of the anti-reflux diode, the cathode of the anti-reflux diode is connected with the power supply end of the control chip, and the source electrode of the Nmos tube is connected with the grounding end of the rectifier bridge. When an electronic detonator is detonated, current pulses generated by electromagnetic interference caused by explosion are induced on a pin wire of the post-detonating electronic detonator, the current pulses are directly transmitted to the ground, and the control chip cannot be interfered by the electromagnetic pulses caused by the explosion.

Therefore, a new technical solution is needed to improve the above technical problems.

Disclosure of Invention

Aiming at the defects in the prior art, the invention aims to provide a method and a system for analyzing whether an electronic detonator is reset by interference.

According to the invention, the method for analyzing whether the electronic detonator is reset under interference comprises the following steps:

step S1: the initiator supplies power to the electronic detonator module through the buses A and B, the electronic detonator chip in the electronic detonator module completes reset after being electrified, and reset frequency information is loaded to a reset frequency register from the electrified erasable programmable read-only memory EEPROM after being reset;

step S2: accumulating the reset times stored in the reset time register by the electronic detonator chip, storing the result into an electrically erasable programmable read-only memory (EEPROM) after the reset times are completed, and entering the step S3, or not carrying out any treatment;

and step S3: the initiator carries out networking of electronic detonator chips and carries out online roll calling on the electronic detonator chips;

and step S4: after receiving the roll call command, the electronic detonator chip returns the user identification code UID of the electronic detonator chip and returns the current reset times N of the electronic detonator chip to the initiator;

and step S4: the method comprises the steps that a UID of an electronic detonator chip and a corresponding reset number N are built in a mapping table and then stored in Flash inside an exploder;

step S5: after networking is completed, the detonator performs a series of operations including delay setting, detonation password verification, high-voltage capacitor charging and detonation command sending, and then the current electronic detonator module is subjected to actual detonation;

step S6: after the full explosion is finished, if the electronic detonator module fails to detonate, the electronic detonator module is further analyzed by the detonator.

Preferably, the step S6 includes the steps of:

step S6.1: the detonator carries out roll calling operation on the single-shot electronic detonator chip to obtain the UID and the current reset number value M of the electronic detonator chip;

step S6.2: the initiator retrieves a reset count value N of the electronic detonator chip before the electronic detonator chip is actually exploded from Flash according to the UID of the current electronic detonator chip;

step S6.3: if M = N +1, it is stated that the electronic detonator chip is not reset in the process of the actual explosion; if M > = N +2, the situation that more than one reset occurs in the process of the real explosion of the electronic detonator chip is shown.

Preferably, the detonator completes detonation control of the electronic detonator module;

the electronic detonator module receives an instruction of the detonator through the leg wire to finish detonating and detonating the explosive, and the electronic detonator module comprises an electronic detonator chip and a preceding stage protection circuit;

the front-stage protection circuit comprises a transient high-voltage suppression tube and an electrostatic protection tube, and suppresses a transient high-voltage signal entering from a pin line;

the electronic detonator chip is a main control chip of the electronic detonator module, receives an instruction, controls delay and completes detonation.

Preferably, the electronic detonator chip comprises an adjustable low dropout regulator (LDO), a reference voltage circuit, a charge-discharge circuit, an oscillator circuit, a POR power-on reset circuit, a digital logic circuit, a charged erasable programmable read-only memory (EEPROM), an ignition control tube, a power tube, a communication circuit, an energy storage capacitor C, an ignition resistor R and an ignition switch MOS tube;

the adjustable low dropout regulator LDO is respectively connected with the charging and discharging circuit, the power-on reset circuit, the digital logic circuit and the reference voltage circuit; the charging and discharging circuit is respectively connected with the digital logic circuit, the reference voltage circuit, the ignition resistor R and the energy storage capacitor C; the power-on reset circuit is respectively connected with the reference voltage circuit and the digital logic circuit; the digital logic circuit is respectively connected with the oscillator circuit, the communication circuit, the electrified erasable programmable read-only memory EEPROM and the grid electrode of the ignition switch MOS tube; the other end of the ignition resistor R is connected with the drain electrode of an ignition switch MOS tube, the other end of the energy storage capacitor C is grounded, and the source electrode of the ignition switch MOS tube is grounded.

Preferably, the adjustable low dropout regulator LDO converts a high voltage power supply into a low voltage power supply, outputs a low voltage for the oscillator, the digital logic circuit, the communication circuit, and the electrically-charged erasable programmable read only memory EEPROM, and controls a driving voltage as a gate of the firing switch power tube through the firing control tube;

the reference voltage circuit generates reference voltages REF1, REF2 and REF3 required by the power-on reset circuit and the programmable low-voltage linear voltage regulator, and the reference voltages REF1, REF2 and REF3 are respectively used for the LDO, the power-on reset circuit and the charge pump;

the charging and discharging circuit comprises a current-limiting resistor, a charging tube and a discharging tube and is used for charging and discharging the energy storage capacitor C.

Preferably, the oscillator circuit provides a clock CLK for the digital logic circuit, the clock frequency being above 100K;

the POR power-on reset circuit is a circuit of a full-chip reset signal POR generated after the electronic detonator chip is powered on, and the effective level of the POR signal is low level;

the digital logic circuit is a logic circuit for external communication of the electronic detonator chip and internal state conversion and delay control of the chip.

Preferably, the electrically-charged erasable programmable read-only memory EEPROM stores a user identification code UID, a detonation password, a delay value, reset times and other user configuration information of the detonator;

the communication circuit writes the two bus signals into data to complete digital logic signals in the detonator chip, and short circuit A and short circuit B are carried out to provide feedback current when the two buses read data from the detonator chip; the communication circuit is a circuit which is arranged in the electronic detonator and has a communication function with the initiator, and receives the instruction of the initiator and returns data to the initiator;

the ignition control tube is controlled by a digital logic circuit, when FIRE is high, the ignition control tube is conducted, the LDO output voltage is output to the grid electrode of the ignition switch power tube, and the power tube is turned on.

Preferably, the power tube adopts an ignition switch MOS tube of LDMOS laterally diffused metal oxide semiconductor, when a grid control signal FIRE is effective, the MOS tube is opened, the energy storage capacitor C releases energy, the ignition resistor R is heated, and a charge head on the ignition resistor is ignited;

the energy storage capacitor C supplies power to the chip after the electronic detonator chip enters a delay period, and provides energy to heat the firing resistor R during detonation;

the ignition resistor R adopts a bridgewire resistor or a patch metal resistor and is used for igniting and igniting the explosive head;

the ignition switch MOS tube controls a current path of the energy storage capacitor C to release energy, and the ignition element is detonated.

The invention also provides a system for analyzing whether the electronic detonator is interfered and reset, which comprises the following modules:

a module M1: the initiator supplies power to the electronic detonator module through the buses A and B, the electronic detonator chip in the electronic detonator module completes reset after being electrified, and reset frequency information is loaded to a reset frequency register from the electrified erasable programmable read-only memory EEPROM after being reset;

a module M2: the electronic detonator chip accumulates the reset times stored in the reset time register, and stores the result into an electrically erasable programmable read-only memory EEPROM after the reset times are completed, and then the electrically erasable programmable read-only memory EEPROM enters a module M3, or else, the electrically erasable programmable read-only memory EEPROM is not processed;

a module M3: the initiator carries out networking of electronic detonator chips and carries out online roll calling on the electronic detonator chips;

a module M4: after receiving the roll call command, the electronic detonator chip returns the user identification code UID of the electronic detonator chip, and returns the current reset times N of the electronic detonator chip to the initiator;

a module M4: the method comprises the steps that a UID of an electronic detonator chip and a corresponding reset number N are built in a mapping table and then stored in Flash inside an exploder;

a module M5: after networking is finished, the detonator carries out a series of operations including delay setting, detonation password verification, high-voltage capacitor charging and detonation command sending, and the current electronic detonator module is subjected to real explosion;

a module M6: after the solid explosion is completed, if the electronic detonator module fails to explode, the electronic detonator module is further analyzed by the exploder.

Preferably, said module M6 comprises the following modules:

module M6.1: the detonator carries out roll calling operation on the single-shot electronic detonator chip to obtain the UID and the current reset number value M of the electronic detonator chip;

module M6.2: the initiator searches a reset count value N of the electronic detonator chip before the electronic detonator chip is actually exploded from Flash according to the UID of the current electronic detonator chip;

module M6.3: if M = N +1, it is stated that the electronic detonator chip is not reset in the process of the actual explosion; if M > = N +2, the situation that the electronic detonator chip is reset more than once in the process of real explosion is shown.

Compared with the prior art, the invention has the following beneficial effects:

1. the invention can be used for evaluating the effectiveness of different impact-resistant circuits, thereby improving the success rate of the application of the electronic detonator in various small sections and laying a foundation for the electronic detonator to comprehensively replace the traditional detonator;

2. the method is easy to realize, is particularly suitable for the electronic detonator chip comprising a memorizer which can be programmed for many times (such as an EEPROM (electrically erasable and programmable read only memory)), only needs to add information for recording the reset times in the memorizer, and updates the memorizer after automatically adding 1 after the chip is reset each time;

3. by applying the invention, the detonator only needs to add a detonator UID and a mapping table of reset times in the memory, and can be realized without large adjustment;

4. after the invention is adopted, whether the electronic detonator is detonated because of resetting can be effectively confirmed, and the anti-interference scheme of the electronic detonator is favorably improved and optimized, thereby reducing the misfire rate of the electronic detonator in various small-section applications.

Drawings

Other features, objects and advantages of the invention will become more apparent upon reading of the detailed description of non-limiting embodiments with reference to the following drawings:

FIG. 1 is a schematic diagram of an electronic detonator networking of the present invention;

FIG. 2 is a circuit composition structure diagram of the detonation system of the invention;

FIG. 3 is a schematic view of an electronic detonator chip of the present invention;

FIG. 4 is a flowchart of the internal processing of a detonator chip of the present invention;

FIG. 5 is a flow chart of the analysis of the misfire detonator of the present invention.

Detailed Description

The present invention will be described in detail with reference to specific examples. The following examples will aid those skilled in the art in further understanding the present invention, but are not intended to limit the invention in any manner. It should be noted that variations and modifications can be made by persons skilled in the art without departing from the concept of the invention. All falling within the scope of the invention.

Example 1:

according to the method for analyzing whether the electronic detonator is reset under interference, which is provided by the invention, the method comprises the following steps:

step S2: accumulating the reset times stored in the reset time register by the electronic detonator chip, storing the result into an electrically erasable programmable read-only memory EEPROM after the reset times are completed, and entering the step S3, or not performing any processing;

step S5: after networking is finished, the detonator carries out a series of operations including delay setting, detonation password verification, high-voltage capacitor charging and detonation command sending, and the current electronic detonator module is subjected to real explosion;

step S6.3: if M = N +1, it is stated that the electronic detonator chip is not reset in the process of the actual explosion; if M > = N +2, the situation that the electronic detonator chip is reset more than once in the process of real explosion is shown.

The detonator finishes detonation control on the electronic detonator module; the electronic detonator module receives an instruction of the detonator through a leg wire to complete detonation and explosive detonation, and the electronic detonator module comprises an electronic detonator chip and a preceding stage protection circuit; the front-stage protection circuit comprises a transient high-voltage suppression tube and an electrostatic protection tube, and suppresses a transient high-voltage signal entering from a leg wire; the electronic detonator chip is a main control chip of the electronic detonator module, receives an instruction, controls delay and completes detonation.

The electronic detonator chip comprises an adjustable low dropout regulator (LDO), a reference voltage circuit, a charging and discharging circuit, an oscillator circuit, a POR power-on reset circuit, a digital logic circuit, a charged erasable programmable read-only memory (EEPROM), an ignition control tube, a power tube, a communication circuit, an energy storage capacitor C, an ignition resistor R and an ignition switch MOS tube; the adjustable low dropout regulator LDO is respectively connected with the charging and discharging circuit, the power-on reset circuit, the digital logic circuit and the reference voltage circuit; the charging and discharging circuit is respectively connected with the digital logic circuit, the reference voltage circuit, the ignition resistor R and the energy storage capacitor C; the power-on reset circuit is respectively connected with the reference voltage circuit and the digital logic circuit; the digital logic circuit is respectively connected with the oscillator circuit, the communication circuit, the electrified erasable programmable read-only memory EEPROM and the grid electrode of the ignition switch MOS tube; the other end of the ignition resistor R is connected with the drain electrode of the ignition switch MOS tube, the other end of the energy storage capacitor C is grounded, and the source electrode of the ignition switch MOS tube is grounded.

The adjustable low dropout regulator LDO converts a high-voltage power supply into a low-voltage power supply, the output low voltage is used by an oscillator, a digital logic circuit, a communication circuit and an EEPROM (electrically erasable programmable read-only memory), and the drive voltage of the grid electrode of the ignition switch power tube is controlled by an ignition control tube; the reference voltage circuit generates reference voltages REF1, REF2 and REF3 required by the power-on reset circuit and the programmable low-voltage linear voltage regulator, and the reference voltages REF1, REF2 and REF3 are respectively used for the LDO, the power-on reset circuit and the charge pump; the charging and discharging circuit comprises a current-limiting resistor, a charging tube and a discharging tube and is used for charging and discharging the energy storage capacitor C.

The oscillator circuit provides a clock CLK for the digital logic circuit, and the clock frequency is more than 100K; the POR power-on reset circuit is a circuit of a full-chip reset signal POR generated after the electronic detonator chip is powered on, and the effective level of the POR signal is low level; the digital logic circuit is a logic circuit for external communication of the electronic detonator chip and state conversion and delay control in the chip.

The EEPROM stores the user ID UID, the detonation code, the delay value, the reset times and other user configuration information of the detonator; the communication circuit writes the signals of the two buses into data to complete digital logic signals in the detonator chip, and short circuit A and short circuit B are carried out to provide feedback current when the two buses read data from the detonator chip; the communication circuit is a circuit which is arranged in the electronic detonator and has a communication function with the initiator, and receives the instruction of the initiator and returns data to the initiator; the ignition control tube is controlled by a digital logic circuit, when FIRE is high, the ignition control tube is conducted, the LDO output voltage is output to the grid electrode of the ignition switch power tube, and the power tube is turned on.

The power tube adopts an ignition switch MOS tube of LDMOS transverse diffusion metal oxide semiconductor, when a grid control signal FIRE is effective, the MOS tube is opened, an energy storage capacitor C releases energy, an ignition resistor R is heated, and a charge head on the ignition resistor is detonated; the energy storage capacitor C supplies power to the chip after the electronic detonator chip enters a delay period, and provides energy to heat the firing resistor R during detonation; the ignition resistor R adopts a bridgewire resistor or a patch metal resistor and is used for ignition to ignite the explosive head; and the ignition switch MOS tube controls a current path of the energy storage capacitor C to release energy, so as to detonate the ignition element.

Example 2:

example 2 is a preferred example of example 1, and the present invention will be described in more detail.

a module M1: the initiator supplies power to the electronic detonator module through the buses A and B, the electronic detonator chip in the electronic detonator module completes reset after being powered on, and reset frequency information is loaded to a reset frequency register from an electrically erasable programmable read-only memory EEPROM after reset;

a module M2: the electronic detonator chip accumulates the reset times stored in the reset time register, and after the reset times are completed, the result is stored in an electrically erasable programmable read-only memory EEPROM and enters a module M3, otherwise, no processing is performed;

a module M3: the initiator carries out networking on the electronic detonator chip and carries out online roll calling on the electronic detonator chip;

module M6.2: the initiator retrieves a reset count value N of the electronic detonator chip before the electronic detonator chip is actually exploded from Flash according to the UID of the current electronic detonator chip;

module M6.3: if M = N +1, it is indicated that the electronic detonator chip is not reset in the process of actual explosion; if M > = N +2, the situation that the electronic detonator chip is reset more than once in the process of real explosion is shown.

Example 3:

example 3 is a preferred example of example 1, and the present invention will be described in more detail.

The invention discloses a method for analyzing whether an electronic detonator is interfered and reset or not.

The invention provides a method for analyzing an electronic detonator which is subjected to misfire to determine whether the electronic detonator is subjected to the misfire caused by reset caused by external interference. The invention relates to an electronic detonator chip which is internally integrated with a charged erasable programmable read-only memory EEPROM (charged erasable programmable read-only memory which supports multiple programming), when the electronic detonator chip is electrified, the information (2 bytes in total) of the reset times of the detonator chip stored in the charged erasable programmable read-only memory EEPROM is firstly read out after the reset is finished, and the numerical value is added with 1 and then written back to the charged erasable programmable read-only memory EEPROM for updating. Networking is carried out firstly when the electronic detonator is actually exploded on site, the detonator carries out online roll calling of each detonator, the detonator chip returns the current reset times (assuming that the current times are N) in the roll calling process, and the information is stored in the detonator. When the detonated detonator is analyzed, the reset times of the detonator chip can be read by the initiator through online roll calling again, and if the read reset time value is N +1, the reason that the detonator is detonated is not reset; if the read reset value is N +2, the reason that the detonator is refused to be detonated is determined to be that the reset occurs.

An initiator: and the main control equipment is used for finishing detonation control of the electronic detonator.

An electronic detonator module: and receiving an instruction of the detonator through the leg wire to finish detonating and detonating the explosive. The electronic detonator comprises an electronic detonator chip, a preceding stage protection circuit and other elements.

Preceding stage protection circuit: the device generally comprises a plurality of transient high voltage suppression tubes, electrostatic protection tubes and the like, and suppresses transient high voltage signals entering from a leg wire.

An electronic detonator chip: and the main control chip of the electronic detonator module receives the instruction, controls the delay and completes the detonation.

Adjustable low dropout linear regulator (LDO): and the conversion from the high-voltage power supply to the low-voltage power supply is realized. The output low voltage is mainly used as a digital power supply for an oscillator, a digital logic circuit, a communication circuit and an EEPROM (electrically erasable programmable read-only memory), and is also used as the driving voltage of the grid electrode of the ignition switch power tube under the control of the ignition control tube.

Reference voltage circuit: reference voltages REF1, REF2 and REF3 required by the power-on reset circuit and the programmable low-voltage linear voltage regulator are generated and are respectively used for the LDO, the power-on reset circuit and the charge pump.

A charge and discharge circuit: the energy storage capacitor C comprises a current limiting resistor, a charging tube and a discharging tube, and charging and discharging management of the energy storage capacitor C is achieved.

An oscillator circuit: a stable clock CLK is provided for the digital logic circuit, typically at a clock frequency above 100K.

POR power-on reset circuit: the circuit of the full chip reset signal POR generated after the electronic detonator chip is powered on, wherein the effective level of the POR signal is low level.

A digital logic circuit: and the logic circuit completes external communication of the electronic detonator chip and state conversion and delay control in the chip.

Electrically erasable programmable read only memory EEPROM: the electrified erasable programmable read-only memory is used for storing a user identification code UID, a detonation password, a delay value, the reset times and other user configuration information of the detonator.

A communication circuit: the purpose of writing the signals of the two buses into data is achieved, digital logic signals in the detonator chip are completed, and when the two buses read data from the detonator chip, the purpose of short circuit A and B is achieved, and feedback current is provided.

Ignition control pipe: and under the control of a digital logic circuit, when FIRE is high, the ignition control tube is conducted, the LDO output voltage is output to the grid electrode of the ignition switch power tube, and the power tube is further opened.

A power tube: when a grid control signal FIRE is effective, the MOS tube is opened, energy on the energy storage capacitor C is released, and the ignition resistor R is heated, so that a charge head on the ignition resistor is ignited.

A communication circuit: the circuit which is arranged in the electronic detonator and has the communication function with the initiator is mainly responsible for receiving the initiator instruction and returning data to the initiator.

An energy storage capacitor C: the ignition resistor R is used for supplying power to the electronic detonator chip after the chip of the electronic detonator enters the delay period and supplying energy to heat the ignition resistor R during detonation.

Firing resistance R: a bridgewire resistor or a patch metal resistor is generally adopted for firing and igniting the explosive head. Typically a few ohms

Ignition switch MOS pipe: and the current path is used for controlling the energy storage capacitor C to release energy, and the ignition element is detonated.

The working principle of the system is as follows:

step S1: the detonator supplies power to the electronic detonator module through the buses A and B, the detonator chip completes reset after being electrified, and reset frequency information (2 bytes, marked as N-1) is loaded to a reset frequency register from the electrified erasable programmable read-only memory EEPROM after reset.

Step S2: the detonator chip accumulates (updates to N) the reset times stored in the reset time register, and stores the result into an electrically erasable programmable read-only memory (EEPROM) after the reset times are completed, and the step S3 is entered; otherwise, no processing is performed.

And step S3: and the detonator is subjected to detonator networking and is subjected to online roll calling.

And step S4: after the electronic detonator chip receives the roll call command, the current reset times N of the detonator chip are returned to the detonator except for returning the detonator user identification code UID.

And step S4: the UID of the detonator and the corresponding reset times N are stored in Flash after a mapping table is established in the detonator, so that power failure loss is prevented.

Step S5: after networking is completed, the detonator carries out a series of operations including delay setting, detonation password verification, high-voltage capacitor charging and detonation command sending to complete the current detonator real explosion.

Step S6: after the full explosion is completed, if the phenomenon of the detonator refusing explosion exists, the detonator can be used for further analyzing the refused explosion detonator. The analytical procedure was as follows:

step S6.1: and the detonator carries out roll call operation on the single detonator to obtain the detonator UID and the current reset number value M.

Step S6.2: and the initiator retrieves a reset count value N before the detonator is actually exploded from the Flash according to the UID of the current detonator.

Step S6.3: if M = N +1, it is indicated that the reset does not occur in the process of the blasting of the detonator, and the increased 1-time reset is caused by one-time reset after the detonator is electrified again; if M > = N +2, the situation that more than one reset is definitely generated in the process of blasting the detonator is stated.

The reset times in the invention are different from other conventional functions of counting and recording by receiving reset instructions. In the field of electronic detonators, a power-on reset POR is integrated in a chip by a high-integration-level electronic detonator chip, and reset operation is automatically completed after the detonator chip is powered on and cannot be controlled by an external command, so that the recording function of reset times is required to be automatically completed by a circuit.

Fig. 4 details the complete control method of the reset number recording. Firstly, two types of information related to RESET times are stored in an EEPROM (electrically erasable programmable read-only memory) of a detonator chip, wherein the first type is RESET times RESET _ CNT, the second type is similar to a RESET times recording function enabling mark RESET _ FLAG, and the RESET _ FLAG is set to be a characteristic value (taking 0x58 as an example) only after an initiator or detonator production line production equipment issues a command to open the RESET times recording function. And after the detonator chip is RESET, loading a RESET _ CNT and a RESET _ FLAG respectively, and updating and recording the RESET _ CNT in the EEPROM after the RESET _ FLAG =0x58 is only met, otherwise, not recording.

This special design approach mainly aims at solving two problems:

on one hand, when the chip is electrified for the first time, the EEPROM is not programmed, the data in the EEPROM may be all 0 or all 1, the EEPROM types of different EEPROM types have different results, and a special reset recording mark is designed for being compatible with all the EEPROM types of the EEPROM, the initiator or detonator production line production equipment can firstly issue an instruction to write the reset times in the EEPROM into 0, then write the reset time recording enabling mark 0x58, open the recording function, and then automatically start the reset time recording function after the chip is electrified for each time.

On the other hand, the service life of the EEPROM is limited, if the number of times of charging and discharging the electric detonator in the early production process is excessive, the corresponding reset record fails, so that the function can be opened through production line equipment when the electronic detonator is manufactured into a finished product for analysis and use after field explosion.

The reading of the reset times during analysis of the misfire is also different from conventional methods. Because the reset in the invention is not based on the conventional reset instruction receiving, but automatically completed after each power-on, and the accumulation of the reset times is automatically completed, after the detonators which are not detonated are obtained, the power-on and the power-off can not be carried out randomly, a matched initiator is required to carry out the power-on the detonators, if the initiator used for the field real explosion can be used, the better effect is achieved, and the comparison with the records stored before the initiator can be directly carried out for judgment after the power-on of the detonators is carried out for on-line roll calling and the reset times are read. If the detonators are not the same set, the stored records of the detonators used on site need to be called out and compared to determine whether the reason for the misfire is reset.

The design of strengthening the impact resistance of the electronic detonator module chip and the circuit is the key for solving the application of small sections of detonators, but an effective method is also needed to confirm whether the detonators which are not detonated are reset because the chip is interfered by the outside.

Those skilled in the art can understand this embodiment as a more specific description of embodiments 1 and 2.

Those skilled in the art will appreciate that, in addition to implementing the system and its various devices, modules, units provided by the present invention as pure computer readable program code, the system and its various devices, modules, units provided by the present invention can be fully implemented by logically programming method steps in the form of logic gates, switches, application specific integrated circuits, programmable logic controllers, embedded microcontrollers and the like. Therefore, the system and various devices, modules and units thereof provided by the invention can be regarded as a hardware component, and the devices, modules and units included in the system for realizing various functions can also be regarded as structures in the hardware component; means, modules, units for realizing various functions can also be regarded as structures in both software modules and hardware components for realizing the methods.

The foregoing description has described specific embodiments of the present invention. It is to be understood that the present invention is not limited to the specific embodiments described above, and that various changes or modifications may be made by one skilled in the art within the scope of the appended claims without departing from the spirit of the invention. The embodiments and features of the embodiments of the present application may be combined with each other arbitrarily without conflict.

Claims

1. A method for analyzing whether an electronic detonator is reset by interference, the method comprising the steps of:

and step S4: after receiving the roll call command, the electronic detonator chip returns the user identification code UID of the electronic detonator chip, and returns the current reset times N of the electronic detonator chip to the initiator;

step S6: after the solid explosion is finished, if the electronic detonator module has the phenomenon of explosion rejection, the electronic detonator module is further analyzed by an exploder;

step S6.3: if M = N +1, it is indicated that the electronic detonator chip is not reset in the process of actual explosion; if M > = N +2, the situation that more than one reset occurs in the process of the real explosion of the electronic detonator chip is shown.

2. The method for analyzing whether the electronic detonator is reset due to interference according to claim 1, wherein the initiator completes initiation control of the electronic detonator module;

3. The method for analyzing whether the electronic detonator is reset by interference according to claim 1, wherein the electronic detonator chip comprises an adjustable low dropout regulator (LDO), a reference voltage circuit, a charge-discharge circuit, an oscillator circuit, a POR power-on reset circuit, a digital logic circuit, a charged erasable programmable read-only memory (EEPROM), an ignition control tube, a power tube, a communication circuit, an energy storage capacitor (C), an ignition resistor (R) and an ignition switch (MOS) tube;

the LDO is respectively connected with the charge-discharge circuit, the power-on reset circuit, the digital logic circuit and the reference voltage circuit; the charging and discharging circuit is respectively connected with the digital logic circuit, the reference voltage circuit, the ignition resistor R and the energy storage capacitor C; the power-on reset circuit is respectively connected with the reference voltage circuit and the digital logic circuit; the digital logic circuit is respectively connected with the oscillator circuit, the communication circuit, the electrified erasable programmable read-only memory EEPROM and the grid electrode of the ignition switch MOS tube; the other end of the ignition resistor R is connected with the drain electrode of the ignition switch MOS tube, the other end of the energy storage capacitor C is grounded, and the source electrode of the ignition switch MOS tube is grounded.

4. The method for analyzing whether the electronic detonator is reset due to interference according to claim 3, wherein the adjustable low dropout regulator LDO converts a high voltage power supply into a low voltage power supply, the output low voltage is used by an oscillator, a digital logic circuit, a communication circuit and a charged erasable programmable read only memory EEPROM, and a drive voltage serving as a grid electrode of the firing switch power tube is controlled by a firing control tube;

5. A method for analysing an electronic detonator as claimed in claim 3 wherein the oscillator circuit provides a clock CLK to the digital logic circuit, the clock frequency being above 100K;

the digital logic circuit is a logic circuit for external communication of the electronic detonator chip and state conversion and delay control in the chip.

6. The method for analyzing whether the electronic detonator is reset due to interference according to claim 3, wherein the electrically-charged erasable programmable read-only memory EEPROM stores the user identification code UID, the detonation password, the delay value, the reset times and other user configuration information of the detonator;

the communication circuit writes the two bus signals into data and converts the data into digital logic signals inside the detonator chip, and when the two buses read data from the detonator chip, the A and B short circuits are carried out to provide feedback current; the communication circuit is a circuit which is arranged in the electronic detonator and has a communication function with the initiator, and receives the instruction of the initiator and returns data to the initiator;

7. The method for analyzing whether the electronic detonator is reset due to interference according to claim 3, wherein the power tube adopts an ignition switch MOS tube of LDMOS transverse diffusion metal oxide semiconductor, and when a gate control signal FIRE is effective, the MOS tube is opened, the energy storage capacitor C releases energy, the ignition resistor R is heated, and a charge head on the ignition resistor is detonated;

8. A system for analyzing whether an electronic detonator is reset due to interference, the system comprising the following modules:

a module M5: after networking is completed, the detonator performs a series of operations including delay setting, detonation password verification, high-voltage capacitor charging and detonation command sending, and then the current electronic detonator module is subjected to actual detonation;

a module M6: after the solid explosion is finished, if the electronic detonator module has the phenomenon of explosion rejection, the electronic detonator module is further analyzed by an exploder;

module M6.3: if M = N +1, it is stated that the electronic detonator chip is not reset in the process of the actual explosion; if M > = N +2, the situation that more than one reset occurs in the process of the real explosion of the electronic detonator chip is shown.