CN114814731A

CN114814731A - Data interface device, and data acquisition equipment and sensor system suitable for same

Info

Publication number: CN114814731A
Application number: CN202210113788.1A
Authority: CN
Inventors: 张友华; 周文婷
Original assignee: Calterah Semiconductor Technology Shanghai Co Ltd
Current assignee: Calterah Semiconductor Technology Shanghai Co Ltd
Priority date: 2022-01-28
Filing date: 2022-01-30
Publication date: 2022-07-29
Also published as: CN114779171A; CN218734353U

Abstract

The application discloses data interface device, and data acquisition equipment and sensor system that are suitable for. Wherein, data interface device, it includes coupled: an input unit; a sampling unit; a clock recovery control unit; a clock generation unit; an output unit; the clock recovery control unit outputs a clock recovery control signal reflecting the phase deviation between the second analog signal and the clock signal by detecting the received first digital signal within a preset number of clock half cycles; wherein the clock recovery control signal uses a field to represent the phase value of the adjusted clock signal. The clock generating unit utilizes the clock recovery control signal to adjust a clock signal, so that the sampling unit can accurately sample the received analog signal to obtain various data provided by the sensor. According to the method and the device, the clock signal is quickly recovered by adjusting the phase interval and the phase value in the phase interval, so that the clock recovery efficiency in the real-time data transmission process of the sensor is improved.

Description

Data interface device, and data acquisition equipment and sensor system suitable for same

Technical Field

The embodiment of the application relates to a data transmission technology, in particular to a data interface device, and data acquisition equipment and a sensor system which are suitable for the data interface device.

Background

The data interface device includes a data interface device that transmits an analog signal, which is used to convert a received digital signal into an analog signal according to a transmission medium, a transmission path length, and the like, for transmission in the transmission medium. The data interface device also includes a data interface device that receives the analog signal for restoring the analog signal from the transmission medium to a digital signal.

In some data transmission technologies, in order to recover a digital signal from an analog signal, each data interface device needs to select a transmitting and receiving circuit system according to a transmission mode of the analog signal, so as to ensure that the analog signal has a recognizable signal change at a circuit resolution level after passing through a transmission medium, and thus ensure that the data interface device on the receiving side can extract the digital signal from the analog signal.

Disclosure of Invention

The application provides a data interface device, and applicable data acquisition equipment and a sensor system, which are used for solving the technical problems that the time consumed by the data interface device is long and the clock signal used for sampling a digital signal is long when the data interface device recovers the clock signal from an analog signal.

In a first aspect, the present application provides a data interface device comprising: the input unit is coupled with a channel to receive a first analog signal from the channel and output a corresponding second analog signal to be converted; the sampling unit is coupled to the input unit and used for sampling the received second analog signal according to the received clock signal so as to output a first digital signal and the clock signal; a clock recovery control unit, coupled to the sampling unit, for outputting a clock recovery control signal reflecting a phase deviation between a second analog signal and the clock signal by detecting the received first digital signal within a preset number of clock half-cycles; wherein the clock recovery control signal represents a phase value of the adjusted clock signal with a field; a clock generating unit, coupled to the clock recovery control unit and the sampling unit, for adjusting the generated clock signal according to the received clock recovery control signal and outputting the adjusted clock signal to the sampling unit; and the output unit is coupled with the sampling unit and used for converting the correspondingly acquired first digital signal into a second digital signal under the control of the received clock signal and outputting the second digital signal.

In a second aspect, an embodiment of the present application provides a sensor system, which includes: a first radar sensor comprising a first data interface device; the first data interface device is used for transmitting a measuring signal obtained by detection of the first radar sensor; wherein the measurement signal is used to reflect at least one of: a baseband digital signal detected by the first radar sensor, at least one of a distance, a speed, and an azimuth between the first radar sensor and a target, and target detection data of the target; a second radar sensor comprising a second data interface device and a third data interface device; wherein the second data interface device is connected with the first data interface device through a channel; the second data interface device is the data interface device of the first aspect, configured to receive the measurement signal; the third data interface device is used for forwarding the measuring signal.

In a third aspect, the present application also provides a sensor system comprising: a first radar sensor comprising a first data interface device; the first data interface device is used for transmitting a measuring signal obtained by detection of the first radar sensor; wherein the measurement signal is used to reflect at least one of: a baseband digital signal detected by the first radar sensor, at least one of a distance, a speed, and an azimuth between the first radar sensor and a target, and target detection data of the target; a second radar sensor comprising a second data interface device and a third data interface device; wherein the second data interface device is connected with the first data interface device through a channel; the second data interface device is the data interface device of the first aspect, configured to receive the measurement signal; the third data interface device is used for forwarding the measuring signal.

The data interface device, the data acquisition equipment and the sensor system which are suitable for the data interface device adjust the phase of the clock signal for sampling by detecting the sampled digital signal, and quickly and accurately recover the clock signal for sampling from the analog signal by adjusting the phase interval and the phase value in the phase interval so as to meet the requirement of the sensor on the clock recovery efficiency in the real-time data transmission process.

Drawings

Fig. 1 is a block diagram of a hardware architecture of a data transmission interface device according to the present application.

Fig. 2 is a schematic circuit diagram of a parallel-to-serial conversion unit according to the present application.

Fig. 3 is a schematic circuit diagram of a first serial signal output device according to the present application.

Fig. 4 is a schematic circuit diagram of a second serial signal output device according to the present application.

Fig. 5 is a schematic circuit diagram of an encoding unit according to the present application.

Fig. 6 is a schematic diagram of an equalized waveform of a third analog signal according to the present application.

Fig. 7 is a schematic circuit diagram of an output driving unit according to the present application.

Fig. 8 is a schematic circuit diagram of another output driving unit according to the present application.

Fig. 9 is a schematic circuit structure diagram of a data transmission interface device provided in the present application in conjunction with the examples provided in fig. 2 and 8.

Fig. 10 is a schematic circuit diagram of a data receiving interface device according to the present application.

Fig. 11 is a schematic circuit diagram of an equalizer unit according to the present application.

Fig. 12 is a diagram of a spectrum in an equalizer unit according to the present application.

Fig. 13 is a schematic circuit diagram of an input unit of the data interface device according to the present application.

Fig. 14 is a schematic circuit diagram of a calibration circuit in the data interface device according to the present invention.

FIG. 15 is a schematic circuit diagram of a detection sub-circuit in the calibration circuit of the present application.

FIG. 16 is a logic flow diagram of a calibration control sub-circuit in the calibration circuit of the present application for processing a detection signal at least once.

Fig. 17 is a schematic diagram of another hardware architecture of the data receiving interface device of the present application.

Fig. 18 is a schematic circuit diagram of a clock recovery control unit in the data receiving interface device according to the present application.

FIG. 19 is a timing diagram of a phase shift detection circuit in the data receiving interface device according to the present application.

Fig. 20 is a schematic circuit diagram of a phase shift control circuit structure in the data receiving interface device according to the present application.

Fig. 21 is a schematic circuit diagram of a second shift decision circuit in the data receiving interface device according to the present application.

Fig. 22 is a schematic diagram of a conditional-state transition of the second phase adjustment circuit adjusting the phase interval in the data receiving interface device according to the present application.

Fig. 23 is a schematic circuit diagram of a clock recovery control unit in the data receiving interface device according to the present application.

Fig. 24 is a schematic diagram of a condition-state transition of a first phase adjusting circuit adjusting binary phase values in a data receiving interface device according to the present application.

Fig. 25 is a schematic diagram of a hardware configuration of a sensor system according to the present application.

Fig. 26 is a schematic diagram of a hardware configuration of the data acquisition device according to the present application.

Detailed Description

The present application will be described in further detail with reference to the following drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the application and are not limiting of the application. It should be further noted that, for the convenience of description, only some of the structures related to the present application are shown in the drawings, not all of the structures.

In some data transmission techniques, a data interface device is coupled to a channel made of a material that conducts signals for the purpose of transmitting analog signals to another data interface device through the channel. Wherein the channel examples include: microstrip lines, coaxial cables, or optical fibers.

The term "coupled" or "coupling" can have several different meanings depending on the context in which the term is used. For example, the term coupled may have the meaning of mechanically coupled or electrically coupled. As used herein, the term "coupled" or "coupling" may mean that two elements or devices may be connected to each other directly or through one or more intermediate elements or devices via electrical, or mechanical elements (such as, but not limited to, wires or cables, for example, depending on the particular application). Examples of couplings described herein include: direct electrical, inductive, or opto-coupling, etc. For example, electrical connections between two electrical devices are made using connections used in semiconductor manufacturing processes. For another example, signal connection between two electric devices is realized by using a non-contact connection mode such as an optical coupler assembly or an inductive sensing assembly. For another example, the connection mode between the chip pin and the socket is used to assist the electrical connection or signal connection between two electrical devices.

For convenience of description, in the embodiments of the present application, a data interface device that transmits an analog signal is referred to as a data transmission interface device, and a data interface that receives an analog signal is referred to as a data reception interface device.

In some data transmission techniques, the data transmission interface device and the data reception interface device transmit analog signals represented by differential signals using channels, thereby reducing the channels through which clock signals are transmitted. The data transmitting interface device and the data receiving interface device include: LVDS interface devices, Serdes interface devices, or the like. In the transmission of analog signals using differential signaling, two channels are typically used to transmit the differential signal. When the two channels are long, filtering of high-frequency signals and/or signal interference, attenuation and other practical situations are easily generated. This is particularly true for analog signals transmitted at frequencies of, for example, 10GHz and above.

Therefore, the present application provides a data transmission interface device, which is intended to be applied to a sensing system such as a sensor, and converts digital signals such as baseband digital signals, measurement data, or target detection data generated by the sensor into analog signals, and ensures that the data reception interface device can accurately analyze the corresponding analog signals when the analog signals are transmitted to the data reception interface device through a channel. The accuracy of the method can meet the error precision of a sensing system. Taking an example that a sensing system including a sensor is applied to an automatic assistant driving system of an automobile, the length of a channel between a data processing device and the sensor in the sensing system is related to the installation position of the sensor on an automobile body, the length of the automobile body and the like; when the data transmitting interface device transmits various digital signals generated by the sensor to the data receiving interface device through the channel (or through the channel and a repeater on the channel), the data receiving interface device can easily and accurately extract the digital signals from the received analog signals of the swing amplitude, so that the requirement of the automatic auxiliary driving system on the accuracy of the data/signals output by the sensor is met.

For convenience of description, the analog signal transmitted to the channel by the data transmission interface device is referred to as a third analog signal, and the analog signal received by the data reception interface device is referred to as a first analog signal. The first analog signal is formed by attenuating the third analog signal after channel transmission and superimposing channel noise and the like.

Please refer to fig. 1, which is a block diagram of a hardware architecture of a data transmission interface device. Wherein, the data transmission interface device 1 comprises: a parallel-to-serial conversion unit 11, an encoding unit 112, and an output drive unit 13.

The parallel-serial conversion unit is used for converting the parallel digital signals generated in the sensor into a first serial digital signal and a second serial digital signal and outputting the first serial digital signal and the second serial digital signal.

Here, the parallel-to-serial conversion unit outputs the first serial digital signal and the second serial digital signal in order of bits from high to low, or from low to high in the parallel digital signal. Wherein the first serial digital signal and the second serial digital signal have the same level change and have a set time gap. In other words, the first serial digital signal and the second serial digital signal are the same-direction signals (or opposite-direction signals) separated from each other by a preset delay time. Wherein the delay time duration (also called symbol time interval) is determined based on the pulse width of the operation clock signal of the parallel-to-serial conversion unit. For example, the delay time is a half period of the operating clock signal.

Please refer to fig. 2, which is a schematic circuit diagram of a parallel-to-serial conversion unit. The parallel-serial conversion unit 11 includes a parallel-serial converter 110, and a first serial outputter 111 and a second serial outputter 112 connected in cascade. The parallel-to-serial converter 110 operates under the control of the first operating clock signal DIV _1, and the first serial output 111 and the second serial output 112 operate under the control of the second operating clock signal DIV _ 2. The first operating clock signal DIV _1 and the second operating clock signal DIV _2 have a frequency division/multiplication relationship. Taking the parallel-to-serial conversion unit 11 as an example of outputting the serial signal at the full rate, if the parallel-to-serial converter converts the parallel digital signal into a 10-bit digital signal into a 2-bit serial digital signal, and the first serial output device and the second serial output device output the 2-bit serial digital signal, the frequency ratio of the first operating clock signal DIV _1 to the second operating clock signal DIV _2 is 1: 5.

the parallel-serial converter is used for converting the received parallel digital signals TXD < n:0> into two paths of serial digital signals according to parity bits. Where n is an integer > 1, e.g., n-8 or 10.

The first serial signal output device is coupled to the parallel-to-serial converter, and is configured to sequentially output the received parity signals under the control of the received second operating clock signal to form the first serial digital signal D _ MAIN.

Here, the parallel-to-serial converter outputs two signals of ODD bits and EVEN bits in the order from high to low bits (or the order from low to high bits) in the parallel digital signal through the ODD signal output terminal EVEN and the EVEN signal output terminal ODD respectively corresponding thereto under the control of the second operation clock signal DIV _ 2. The first serial signal output unit sequentially outputs the received odd bit signal and the even bit signal under the control of the second operation clock signal DIV _ 2. Taking the example where the first serial signal outputter outputs the first serial digital signal at full rate, the first serial signal outputter outputs the serial digital signal in accordance with the clock cycle of the second operating clock signal DIV _2 only in response to the rising edge or the falling edge of the second operating clock signal DIV _ 2. Taking the example where the first serial signal outputter outputs the first serial digital signal at a half rate, the first serial signal outputter outputs the serial digital signal in accordance with the clock half period of the second operating clock signal DIV _2 in response to the rising edge and the falling edge of the second operating clock signal DIV _ 2.

Please refer to fig. 3, which is a schematic circuit diagram of the first serial signal output device. The first serial signal output device includes two flip-flops D11, D12, a controller C1, and an output device P1. The input terminal of the flip-flop D11 is connected to the odd signal output terminal EVEN, the control terminal (also called the enable terminal) of the flip-flop D11 receives the second operating clock signal DIV _2, and the output terminal of the flip-flop D11 is connected to the first input terminal of the controller C1 and the second serial signal output terminal, respectively. The input terminal of the flip-flop D12 is connected to the even signal output terminal ODD, the control terminal (also called the enable terminal) of the flip-flop D12 receives the inverted signal of the second operating clock signal DIV _2, and the output terminal of the flip-flop D12 is connected to the second input terminal of the controller C1 and the second serial signal output terminal, respectively. The output P1 is optionally a comparator, or an and gate device to improve the level stability of the output signal. In some examples, as shown in the dashed box of fig. 3, the first serial signal outputter further includes a duty ratio calibration circuit DCC1 to improve the stability of the pulse ratio in the second operating clock signal DIV _ 2; correspondingly, the duty cycle calibration circuit DCC1 receives the second operation clock signal DIV _2 and outputs it to the control terminal of the controller C1.

Under the control of the second operating clock signal DIV _2, taking the half-rate transmission of the serial digital signal as an example, in one clock cycle of the second operating clock signal DIV _ 2: during the high-level active period of the second operating clock signal DIV _2, the signal path formed by the flip-flop D11, the controller C1, and the output P1 outputs an odd-bit signal, and during the low-level active period of the second operating clock signal DIV _2, the signal path formed by the flip-flop D12, the controller C1, and the output P1 outputs an even-bit signal.

The second serial signal output device is cascaded with the first serial signal output device and is used for outputting the first serial digital signal D _ MAIN transmitted by the first serial signal converter as a second serial digital signal D _ POST according to the delay time length.

The second serial signal output unit sequentially outputs the received odd bit signal and the even bit signal under the control of a second working clock signal DIV _2 to form a second serial digital signal D _ POST. Taking the second serial signal outputter for outputting the second serial digital signal at full rate as an example, the second serial signal outputter outputs the second serial digital signal D _ POST according to the clock period of the second operating clock signal DIV _2 only in response to the falling edge or the rising edge of the second operating clock signal DIV _ 2. Taking the example that the second serial signal outputter outputs the second serial digital signal at a half rate, the second serial signal outputter outputs the second serial digital signal D _ POST according to a clock half period of the second operating clock signal DIV _2 in response to a down-skip edge and a up-skip edge of the second operating clock signal DIV _ 2. Wherein the second serial signal follower is delayed by one symbol time gap (i.e., one half clock cycle of the second operating clock signal DIV _2) from the first serial signal follower.

Please refer to fig. 4, which is a schematic circuit diagram of the second serial signal output device. The second serial signal follower includes two flip-flops D21, D22, a controller C2, and an follower P2. An input end of the flip-flop D21 is connected to an output end D11_ output of the flip-flop D11 of the first serial signal output device, a control end (also called an enable end) of the flip-flop D21 receives an inverted signal of the second operating clock signal DIV _2, and an output end of the flip-flop D21 is connected to a first input end of the controller C2. The input terminal of the flip-flop D22 is connected to the output terminal D12_ output of the flip-flop D12 of the first serial signal output device, the control terminal (also called the enable terminal) of the flip-flop D22 receives the second operating clock signal DIV _2, and the output terminal of the flip-flop D22 is connected to the second input terminal of the controller C2. The output P2 is optionally a comparator, or an and gate device to improve the level stability of the output signal. In some examples, as shown in the dashed box of fig. 4, the second serial signal outputter further includes a duty cycle calibration circuit DCC2 to improve the pulse ratio stability in the second operating clock signal DIV _ 2; correspondingly, the duty cycle calibration circuit DCC2 receives the second operation clock signal DIV _2 and outputs it to the control terminal of the controller C2. The duty cycle calibration circuit DCC2 and the duty cycle calibration circuit DCC1 may be the same device or separate devices.

Under the control of the second operating clock signal DIV _2, taking the half-rate transmission of the serial digital signal as an example, in one clock cycle of the second operating clock signal DIV _ 2: during the active low period of the second operating clock signal DIV _2, the signal path formed by the flip-flop D21, the controller C2, and the output P2 outputs the odd bit signal, and during the active high period of the second operating clock signal DIV _2, the signal path formed by the flip-flop D22, the controller C2, and the output P2 outputs the even bit signal.

The parallel-serial conversion unit with the half-rate structure converts the received n-bit parallel digital signal into an odd-even two-bit digital signal, and then converts the odd-even two-bit digital signal into a one-bit serial digital signal through a controller (such as an alternative selector). Because of the half rate structure, the required clock frequency is half of the serial data rate, on one hand, the requirement on the clock is reduced, on the other hand, because the high and low levels of the clock are used, the clock duty ratio is sensitive, jitter of an output serial data eye pattern is directly influenced by the clock duty ratio, and DCC is added on the clock path to correct the clock duty ratio, so that the deviation is within a certain range. In the figure, D _ MAIN is the first serial digital signal finally output, and D _ POST is delayed by one symbol time gap compared with D _ MAIN, and is mainly used for the following channel equalization. Signals P _0 and P _1 may control the polarity of D _ MAIN and D _ POST, respectively. And the first serial digital signal D _ MAIN and the second serial digital signal D _ POST are output to an encoding unit of the data transmitting interface device.

The encoding unit is coupled to the parallel-serial conversion unit and is configured to encode the first serial data and the second serial data into a first driving control digital signal and a second driving control digital signal according to a preset equalization coefficient and output the first driving control digital signal and the second driving control digital signal. The equalization coefficients are intended for the output driving unit to adjust the swing of partial voltage in the output third analog signal so as to improve the filtering resistance of the high-frequency section in the channel transmission process, and the equalization coefficients include, for example, equalization coefficients for pre-emphasis or equalization coefficients for de-emphasis. The equalization coefficient is preset according to the transmission distance between the data transmitting interface device and the data receiving interface device, the channel medium and the like. For example, the encoding unit provides an equalization coefficient encoder, such as a thermometer encoder, that is available for editing. The equalization coefficient encoder generates a control signal according to an externally input encoding instruction, so that the encoding unit performs an encoding operation on the received first serial digital signal D _ MAIN and the second serial digital signal D _ POST.

The encoding unit encodes the first serial digital signal D _ MAIN and the second serial digital signal D _ POST by using a multi-channel digital circuit encoding mode, and integrates the data transmitting interface device and the sensor into a chip within a limited size range by effectively using a semiconductor manufacturing process.

Please refer to fig. 5, which is a schematic circuit diagram of an encoding unit. The coding unit comprises two paths: the differential converters SD1 and SD2, the encoder groups MUX1< m:1>, MUX2< m:1>, where m > 1, for example m ═ 14. The differential converter SD1 converts the first serial digital signal D _ MAIN into differential serial signals DP _ MAIN and DN _ MAIN. The differential converter SD2 converts the second serial digital signal D _ POST into serial signals DP _ POST and DN _ POST in differential form. Taking the first serial digital signal D _ MAIN and the second serial digital signal D _ POST as the same signal having the delay time as an example, for convenience of description, the serial signals DP _ MAIN and DP _ POST are the same signal having the delay time, and the serial signals DN _ MAIN and DN _ POST are the same signal having the delay time; and the serial signals DP _ MAIN and DN _ MAIN are synchronous inverted signals, and the serial signals DP _ POST and DN _ POST are synchronous inverted signals.

The encoder set MUX1< m:1> receives the serial signals DP _ MAIN and DN _ POST, encodes the serial signals DP _ MAIN and DN _ POST according to control bits in the received control signals, and outputs a first driving control digital signal DP _ INT. Wherein each encoder group is controlled by a control signal output by the equalizer coefficient encoder. The encoder set MUX2< m:1> receives the serial signals DN _ MAIN and DP _ POST, encodes the serial signals DN _ MAIN and DP _ POST according to control bits in the received control signals, and outputs a second driving control digital signal DN _ INT.

Wherein the encoder set MUX1< m:1> and the encoder set MUX2< m:1> may have the same circuit structure. Taking the encoder group MUX1< m:1> as an example, the encoder group is formed by m two-out-of-one selectors, each selector in the encoder group MUX1< m:1> selects the serial signals DP _ MAIN and DN _ POST according to the high level or the low level of the corresponding control bit in the received control signal, so as to output the m-bit first driving control digital signal DP _ INT.

In this example, the alternative selector is controlled by a Thermometer code (Thermometer decoder) to generate a control signal required for the output driving unit. For example, the signals D _ MAIN and D _ POST are converted into DP _ MAIN and DN _ MAIN, and DP _ POST and DN _ POSTN, respectively, by the single-ended to differential converter; these two sets of signals are then connected to 15 two alternative selectors, respectively, and finally converted to DP _ INT and DN _ INT outputs. The two-choice selector is controlled by thermometer coding, when a channel needs high compensation quantity, DP _ POST and DN _ POST output can be selected more through the two-choice selector, and the balance quantity can be increased one by one through thermometer coding, so that high accuracy can be achieved.

Since the first driving control digital signal DP _ INT and the second driving control digital signal DN _ INT are encoded in the same encoding manner according to the received differential signal pair { DP _ MAIN, DN _ POST } and { DN _ MAIN, DP _ POST } with the delay time, the first driving control digital signal DP _ INT and the second driving control digital signal DN _ INT include control changes in one clock cycle, which can be used by a subsequent circuit to perform pre-emphasis (or pre-de-emphasis) processing according to the delay time. And under the control of the first driving control digital signal DP _ INT and the second driving control digital signal DN _ INT, outputting a differential signal which is a third analog signal and is obtained by equalizing the voltage swing of the driving unit.

The output driving unit is coupled to the encoding unit and is used for generating an analog signal representing one of 0 and 1 in the first serial digital signal under the drive control of the first drive control digital signal; or generating an analog signal representing the other of 0 or 1 in the first serial digital signal under the drive control of the second drive control digital signal; and outputting the corresponding analog signal according to the time sequence to form a third analog signal. Wherein the magnitude of the energy of the third analog signal over the extended time period after the selection switch is processed by the pre-emphasis/de-emphasis equalization. For example, please refer to fig. 6, which is a waveform diagram of the third analog signal after equalization processing, wherein the time slots T1 and T2 are level signals output after equalization processing of the output driving unit in the differential signal, respectively.

Here, the output driving unit includes a plurality of controlled power supply circuits (e.g., digital-to-analog conversion drivers, DAC drivers) to generate the equalized differential analog signals under the control variation of the first and second driving control digital signals. The signal output requirement of large swing is provided by selecting a plurality of controlled power supply circuits, so that the difficulty that the sizes of electric devices in a high-power driving circuit cannot be integrated is reduced, and the control precision is effectively improved. Each controlled power circuit may be a circuit that generates the same electrical signal or a circuit configured to generate electrical signals that are not identical. The output driving unit comprises two groups of controlled power supply circuits, namely a first controlled power supply circuit group and a second controlled power supply circuit group, and the number of each group of controlled power supply circuits respectively corresponds to the maximum digit of the received first drive control digital signal or the second drive control digital signal. The first controlled power supply circuit group is connected with the positive output end of the output driving unit; the second controlled power supply circuit group is connected with the negative output end of the output driving unit. Thereby outputting a single third analog signal represented by the differential signal.

To output the third analog signal with symmetrical amplitude swing, please refer to fig. 7, which shows a schematic circuit structure diagram of the output driving unit in some examples. The first controlled power supply circuit group and the second controlled power supply circuit group have the same circuit structure. Taking the first controlled power circuit group as an example, the first controlled power circuit group includes m parallel first controlled power circuits, and each control bit in the first driving control digital signal correspondingly controls a controlled switch in one first controlled power circuit. Under the control of two groups of first driving control digital signals DP _ INT spaced by the delay time length, the m parallel first controlled power supply circuits generate analog signals after equalization processing and output the analog signals to the positive output terminal TXP of the output driving unit 13. Unlike the first controlled power supply circuit group, the second controlled power supply circuit group generates an analog signal subjected to equalization processing and outputs the analog signal to the negative output terminal TXN of the output drive unit 13.

In other examples, please refer to fig. 8, which shows another circuit structure diagram of the output driving unit. The output driving unit includes a first controlled power circuit group 131, a second controlled power circuit group 132, and a swing compensation circuit 133.

Unlike the example shown in fig. 7, the swing compensation circuit is connected to the positive output terminal and the negative output terminal of the output driving unit and is controlled by the first driving control digital signal and the second driving control digital signal. And one control bit in the first drive control digital signal and one control bit in the second drive control digital signal are respectively connected with two control ends of the swing amplitude compensation circuit. The two control bits are inverted signals so that the swing compensation circuit compensates voltage to the positive output terminal of the output driving unit when the level of the output analog signal swings in the positive direction, and compensates voltage to the negative output terminal of the output driving unit when the level of the output analog signal swings in the negative direction.

As shown in fig. 8, the swing compensation circuit 133 includes a power source IS and two controlled switches connected in parallel, and a control terminal of each controlled switch receives a control bit of the first driving control digital signal and a control bit of the second driving control digital signal, respectively, so that the two controlled switches are not turned on simultaneously.

Referring to fig. 9, it shows a schematic circuit structure of a data transmission interface device provided in connection with the examples provided in fig. 2 and 8, wherein the output driving unit is a full-rate structure, and the output driving unit only needs to generate a differential serial signal under the control of the first driving control digital signal and the second driving control digital signal, without simultaneously processing clock and data, thereby greatly simplifying the structure of the output driving. The output driving unit is formed by connecting two groups of DAC driver arrays as shown in the figure, each group of DAC driver array is composed of 15 DAC drivers, so that a 4-bit voltage mode DAC driver is formed, and the relation of a voltage dividing resistor RU and a load resistor RT is as follows: RU ═ n × RT.

If for an N-bit voltage-mode DAC driver, the following relationship is used: n is 2 ^N -1. Since a 4-bit voltage mode DAC driver is used in this example, n is calculated to be equal to 15 from the above equation, RT is typically 50 ohms, and RU is calculated to be equal to 750 ohms. In addition to RU, there are two PMOS and NMOS drivers used as switches in the DAC driver. Assuming that the switch on-resistance IS zero, it can be calculated that the output differential peak-to-peak value of the DAC driver at this time IS VS, which can be obtained through a regulator, and the output swing of the driver IS also changed by adjusting the output voltage of the regulator, and in addition, in order to further increase the output swing, the swing enhancement module as shown in the figure IS added, and the output swing can be increased from VS to VS + IS 2 RT.

By using the differential signals output by the data transmission interface device provided by each example, the swing requirement of the circuit system in which the sensor is arranged on the transmission of high-speed serial signals is effectively solved.

The application also provides a data receiving interface device, which aims to accurately recover the differential signal transmitted by the channel. Please refer to fig. 10, which is a schematic circuit diagram of a data receiving interface device, wherein the data receiving interface device 2 includes: an input unit 21, a sampling unit 22, a clock recovery control unit 23, a clock generation unit 24, and an output unit 25.

The input unit is configured to receive a first analog signal from a channel. The first analog signal is transmitted in the form of wave in the channel and is influenced by the environment of the channel, the material of the channel, the length range of the channel and the like, and the influence enables the high-frequency component of the first analog signal to be easily filtered out in the transmission process. In some examples, the data transmission interface device reduces the problem of mis-decoding and the like caused by the influence on the data receiving side by increasing the voltage swing of the transmitted first analog signal. In other examples, the input unit configures the compensation mechanism according to predetermined parameters/information related to the channel environment. For example, a feedback circuit for compensating the first analog signal level is configured in the input unit, wherein an electrical parameter of a reference signal in the feedback circuit is determined according to a material, a length range, and the like of a channel. For another example, a feedback circuit in the input unit suppresses noise generated by the environment of the channel through a feedback effect during the process of receiving the first analog signal, so that the input unit can accurately output the second analog signal.

Taking the first analog signal as an example of a differential signal, the input unit includes: two signal leads and an equalizer circuit connected to the signal leads. Wherein the two signal leads are configured to be coupled to the channel to receive a first analog signal represented in a differential signal from the channel. The equalization circuit is used for performing equalization processing on the received first analog signal to output the second analog signal. To facilitate the distinction between the first equalization circuit (e.g., DAC driver array) in the data transmitting interface device, the equalization circuit in the data receiving interface device is referred to as the second equalization circuit.

The second equalization circuit comprises at least one equalizer unit. The gate circuit device in the equalizer unit responds to the voltage difference between two inverted signals in the received first analog signal, and accordingly the equalizer unit outputs a differential signal inverted from the first analog signal, namely a second analog signal. When the number of the equalizer units in the second equalization circuit is plural, the equalizer units are connected in cascade.

In order to output a differential signal which is opposite to the first analog signal and is subjected to equalization compensation, the circuit of the equalizer unit comprises switches M1 and M2 which are respectively controlled by two opposite signals in the first analog signal, the equalizer unit is also connected with a constant voltage VDD, a circuit branch L1 where the switch M1 is located is connected with a positive output end, and a circuit branch L2 where the switch M2 is located is connected with a negative output end; an isolation circuit branch is connected between the two circuit branches. The circuit branches L1 and L2 are provided with electric devices with the same electric parameters, so as to achieve the purpose of symmetry of differential signals.

In order to improve the shaping effect of the output second analog signal, so as to facilitate the subsequent sampling circuit to perform accurate signal extraction, in some examples, the equalizer unit further includes a compensation circuit, which is respectively connected to the positive output terminal and the negative output terminal, and performs corresponding equalization compensation according to the level output by the positive input terminal or the level output by the negative output terminal. For example, when the positive output end outputs high level, the compensating circuit pulls down the level of the negative output end; or when the negative output end outputs high level, the compensating circuit pulls down the level of the positive output end. Thereby achieving the purpose of increasing the common mode voltage difference. In other examples, the second equalization circuit utilizes a plurality of cascaded equalizer units to provide shaping of the high frequency second analog signal. For example, each equalizer unit in the cascade provides an equalization compensation voltage which is not identical, so as to achieve the purpose of improving the shaping of the high-frequency second analog signal.

In order to make the equalizer unit self-adapt to the interference caused by the channel environment, the equalizer unit comprises a device adjusted by an external correction circuit; and the second equalization circuit further comprises the correction circuit. Wherein the adjustable device is configured according to a circuit structure of the equalizer unit, such as at least one of a power amplifier, a capacitor, or a resistor. The adjustable device realizes the purpose that the second equalization circuit outputs the second analog signal along with the correction of the correction circuit by adjusting the voltage, the current or the property (such as the capacitance value or the resistance value) of the device.

For example, the equalizer unit includes: circuit branch L1, circuit branch L2, a regulating circuit, and a correction circuit. The circuit branches L1 and L2 are respectively connected to the positive output terminal and the negative output terminal of the equalizer unit, the circuit branches L1 and L2 are respectively provided with switches M1 and M2, and the control terminals of the switches M1 and M2 respectively receive differential signals. The adjusting circuit is connected with the correcting circuit and used for adjusting the signal electrical parameters of the positive output end or the negative output end according to the correcting signal output by the correcting circuit. The correction circuit is connected with the positive output end and the negative output end and used for outputting a correction signal which indicates that the common mode voltage difference is increased or decreased by detecting the common mode voltage difference of the positive output end and the negative output end. In some examples, the equalizer unit further includes a compensation circuit as described in the above examples.

Referring to fig. 11, which is a schematic diagram of a circuit structure of an equalizer unit, a circuit branch L1 further includes a resistor RL1 and a switch M5; circuit branch L2 also includes a resistor RL2 and a switch M6. The resistance RL1 and the resistance RL2 are equal in resistance; the switches M5 and M6 have the same electrical parameters. VDD is a reference high voltage, VSS is a reference ground voltage, and VBN is a bias voltage.

As shown in fig. 11, the regulating circuit 2111 is coupled between the output terminals of the switches M1 and M2, and includes energy storage devices (e.g., capacitors) C0_1 and C0_2 connected in series. The connection of the energy storage devices C0_1 and C0_2 receives the correction signal. The compensation circuit 2112 includes, for example: switches M3 and M7 connected in series with the negative output of the equalizer unit, switches M4 and M8 connected in series with the positive output of the equalizer unit; the control end of the switch M3 is connected with the positive output end of the equalizer unit, and the control end of the switch M4 is connected with the negative output end of the equalizer unit. In order to further increase the common mode voltage difference, the compensation circuit further comprises energy storage devices Cc _1 and Cc _2 connected in series between the output terminals of the switches M3 and M4, wherein the connection of the energy storage devices Cc _1 and Cc _2 receives the correction signal. Similarly to the energy storage devices C0_1 and C0_2, when the correction signal is at a high level, the level of the valid signal output from the positive output terminal is increased or the level of the valid signal output from the positive output terminal is increased under the energy storage effect of the energy storage devices Cc _1 and Cc _ 2. When the correction signal is low, Cc _1 and Cc _2 in the regulating circuit have no energy storage, namely the level of the effective signal output by the positive output terminal is not increased or the level of the effective signal output by the negative output terminal is not increased.

In order to improve the high frequency compensation capability of the equalizer unit, the equalizer unit is implemented by four-stage cascade based on negative capacitance technology in the present example, VIN and VOUT are respectively the input and output of the equalizer unit, and since R0 uses fixed resistance in the present example, only one control voltage VC is used to adjust the variable capacitances C0 and Cc of the circuit, thereby adjusting the high frequency compensation gain of the equalizer unit. In the figure, a negative capacitance structure is arranged in a dotted line, and the equivalent impedance is as follows:

wherein gmNC and CgsNC are transconductance and gate-source capacitance of MOS transistor M3(M4), respectively.

Wherein Z is _NC Can be expressed as a negative capacitance-C _C And a negative resistance-R _C In which R is _C The values are:

therefore, the output impedance of the negative capacitance equalizer unit is:

Z _NC the output impedance of the equalizer unit is added with a zero point and a pole approximately positioned

The spectrum of the equalizer filter using negative capacitance is shown in fig. 12 (where the dotted line is the frequency response of the basic equalizer unit without negative capacitance), where W _n Is composed of

W _n The zero point and the pole point at both sides are Z _NC Zero pole of (c). It is evident that the negative capacitance structure increases the high frequency compensation gain of the equalizer unit and the bandwidth of the high frequency gain.

Please refer to fig. 13, which is a schematic diagram of a circuit structure of an input unit, wherein the input unit includes a plurality of cascaded equalizer units 212 and a correction circuit 211. Wherein the number of cascaded equalizer units 212 is related to the number of bits of the correction signal provided by the correction circuit 211. The equalizer unit 212 may be exemplified by the circuit structure of the equalizer unit described in any of the above examples. The correction circuit 211 performs correction detection on the second analog signal output by the equalizer units in cascade so that at least one equalizer unit 212 adjusts the amplitude of the output differential signal.

In some examples, the correction circuit performs correction detection and outputs a real-time correction signal during the input unit receiving the first analog signal representing the measurement signal of the sensor.

In other examples, the calibration circuit receives a first analog signal for a test channel interference signal transmitted by the data transmission interface device to calibrate interference of a channel environment with the analog signal before receiving the first analog signal representing the measurement signal of the sensor. Therefore, please refer to fig. 14, which is a schematic circuit diagram of the calibration circuit. The correction circuit includes: a detection sub-circuit 2121, and a correction control sub-circuit 2124.

The detection sub-circuit is coupled to an output terminal of the input unit, and is configured to detect a common mode voltage of the second analog signals (VOP and VON) output by the output terminal, so as to output a detection signal reflecting over-compensation or under-compensation of the input unit. The detection signal is, for example, a level signal whose high and low levels indicate overcompensation or undercompensation, or a level signal indicating an overcompensation amount or an undercompensation amount.

Here, the detection sub-circuit includes: the device comprises a common-mode voltage detection module, a reference signal generation module and a detection output module. The common mode voltage detection module detects a common mode Voltage (VCM) of the second analog signal and outputs a fluctuating electrical signal reflecting a change of the common mode voltage. The reference signal generation module outputs a reference electric signal. The detection output module is respectively connected with the common-mode voltage detection module and the reference signal generation module and is used for outputting a detection signal by detecting the fluctuation electric signal and the reference electric signal.

In order to adapt the reference electrical signal to the amplitude of the interference signal in the channel environment to improve the signal-to-noise ratio of the second analog signal, please refer to fig. 15, which is a schematic circuit structure diagram of the detection sub-circuit. The common-mode voltage detection module comprises a common-mode detection submodule 2122 and a first amplitude detection submodule 2123; the reference signal generation module comprises a reference signal generation submodule 2125 and a second amplitude detection submodule 2126; the detection output module 2127 includes a comparator.

The common mode detection submodule receives the second analog signal and outputs a common mode Voltage (VCM) to the reference signal generation submodule. The output ends of the first amplitude detection submodule and the second amplitude detection submodule are respectively connected with the detection output module so as to output high and low level detection signals. The common mode detection submodule detects a common mode voltage of an input serial differential signal (namely, the second analog signals RXP and RXN), and the reference signal generation submodule converts the reference differential signal (C1 and C2) into a reference differential signal according to the detected common mode voltage VCM, so that the swing amplitude of the reference differential signal changes along with the change of the common mode voltage VCM. The first amplitude detection submodule and the second amplitude detection submodule respectively output single-ended level signals in direct proportion to the amplitude of the signal peak value according to the respective amplitudes of the received serial differential signals and the reference differential signals. The comparator compares the level signals output by the first amplitude detection submodule and the second amplitude detection submodule, and judges whether the swing amplitude of the input serial differential signal is higher than that of the reference differential signal, so that whether the state of each equalizer unit needs to be compensated is judged.

The correction control sub-circuit is connected to the detection sub-circuit and the adjusting end of each equalizer unit in the input unit, and is used for carrying out feedback compensation processing by using the detection signal at least once so as to transmit corresponding control signals to each adjusting end. The adjusting terminal is exemplified as the connecting terminal with the correcting circuit in the adjusting circuit mentioned in the above example.

The calibration control sub-circuit may be formed by connecting digital electrical devices including logic operations such as counters, registers, comparators, and encoders to implement the calibration control logic. Referring to fig. 16, a logic flow diagram of a process for processing at least one detection signal by the calibration control sub-circuit is shown. After the chip is powered on or meets other triggering conditions, setting the chip in a correction mode, namely setting an initial compensation coefficient to be 0, starting to send test data to each equalizer unit through a channel by the digital transmission interface device, enabling the digital transmission interface device to start working, simultaneously comparing the amplitude and the threshold value of a second analog signal by the detection sub-circuit, and judging the state of an equalizer formed by the cascaded equalizer units by the digital circuit in the correction control sub-circuit according to the comparison result of the two; and if the compensation circuit is judged to be in an under-compensation state, increasing the compensation coefficient, and if the compensation circuit is judged to be in an over-compensation state, decreasing the compensation coefficient until the compensation is judged not to be needed or other cut-off conditions are met, turning off the correction circuit, and finishing the correction. The detection sub-circuit enters a normal working stage and serves as a coefficient for normal working of each subsequent equalizer unit according to the stored compensation coefficient so as to compensate the gain of the high-frequency signal. Wherein, the other trigger conditions include: handshaking communication between the data transmitting interface device and the data receiving interface device before transmitting the effective measuring signal of the sensor; or a trigger instruction generated according to temperature, humidity and other measurement data affecting the channel environment, and the like.

With reference to fig. 16, the operation of the correction control sub-circuit is as follows: when the power is on, the register, the counter and the like in the correction control sub-circuit are reset to initial values (such as 0 value), each digital electric device in the correction control sub-circuit samples the received detection signal, judges whether the sampled detection signal is overcompensation or undercompensation, and adjusts the count value of the corresponding counter according to the judgment result. And under the step frequency of the clock signal, the process is circularly executed until the counting value or the judgment times meet a preset cut-off condition. An encoder in the correction control sub-circuit encodes the count value after the cycle is finished, and outputs corresponding binary correction signals according to the number of the equalizer units, so that each equalizer unit performs equalization compensation according to the binary correction signals during the period of receiving the first analog signals representing the measuring signals of the sensor. The cutoff condition includes, for example, that the count value is unchanged or the number of times of determination reaches a maximum value.

The input unit carries out equalization compensation on the first analog signal from the channel and then outputs the second analog signal to the sampling unit so as to recover the digital measurement signal processed by the data transmission interface device through the sampling unit.

The sampling unit is coupled to the input unit and used for sampling the received second analog signal according to the received clock signal so as to output a first digital signal and the clock signal.

Here, the sampling unit responds to a transition edge of the received clock signal and outputs a first digital signal having an inverse relationship. For the example where the first analog signal is a differential signal, the first digital signal output by the sampling unit has a large bit error condition because the clock signal is not synchronized with the electrical phase representing the data/information in the first analog signal.

To this end, the sampling unit samples the second analog signal according to a plurality of clock signals having a phase offset. The first digital signal output by the sampling unit comprises: sampling according to the corresponding moments of different clock signals to obtain high/low levels; the output first digital signal and one path of clock signal are output to an output unit for a subsequent circuit to carry out digital signal processing; the sampled first digital signal is output to the clock recovery control unit, so that the clock recovery control unit can perform phase detection on the first digital signal generated within a preset number of clock half cycles. Wherein the phase shift (also called phase difference) is less than 180 °, for example, the phase shift includes 30 °, 45 °, or 90 °, etc.

The clock recovery control unit is coupled to the sampling unit, and outputs a clock recovery control signal reflecting a phase deviation between the second analog signal and one of the clock signals by detecting the received first digital signal.

Here, the clock recovery control unit detects the first digital signal sampled at different phases for a period of time to determine a phase lead or lag between any one of the clock signals and the second analog signal, and outputs a corresponding clock recovery control signal. Wherein the period of time is determined based on a time period required to sample a preset number of the first digital signals. For example, the period of time is an integer multiple of a half period of the clock, or is determined according to the sum of phase deviations of the plurality of clock signals.

The clock recovery control unit utilizes digital electric devices such as a register, a trigger, a comparator and the like to construct a detection logic circuit so as to detect whether the phase of the second analog signal is advanced or delayed with the phase of the sampled clock signal, and outputs a corresponding clock recovery control signal to the clock generation unit. The clock recovery control unit may obtain the phase amount of the phase lead or lag by detecting, or obtain the identifier of the phase lead or lag, and represent the phase amount by using information such as amplitude and code of the clock recovery control signal.

The clock generating unit is coupled to the clock recovery control unit and the sampling unit, and is configured to adjust the generated clock signal according to the received clock recovery control signal and output the adjusted clock signal to the sampling unit.

Here, the clock generation unit adjusts the frequency and/or initial phase of each output clock signal in accordance with the received clock recovery control signal.

Taking the identifier that the clock recovery control signal indicates a phase lead or lag as an example, the clock generation unit adjusts the frequency (and/or initial phase) of each clock signal according to a preset frequency step (and/or phase step).

Taking as an example a phase amount by which the clock recovery control signal indicates a phase lead or lag, the clock generation unit adjusts the initial phase of each clock signal in accordance with the phase amount. Or the clock generating unit converts the phase quantity into a frequency variation quantity and adjusts each generated clock signal.

The clock generation unit includes, for example: a regulating circuit, a signal generator, a phase locking circuit and the like. The adjusting circuit adjusts the frequency division ratio in the phase-locked circuit according to the clock recovery control signal, and the phase-locked circuit performs phase locking and phase shifting operations on the square wave signal provided by the signal generator according to the frequency division ratio and outputs a plurality of paths of clock signals with phase offset.

The sampling unit adjusts the phase position of the sampling second analog signal by using the clock signal generated by the clock generating unit so as to accurately sample the digital signal which reflects the data transmission interface device. The sampled first digital signal is transmitted to an output unit.

The output unit is coupled to the sampling unit, and is used for converting the correspondingly acquired first digital signal into a second digital signal under the control of the received clock signal and outputting the second digital signal.

The clock signal received by the output unit is one of the multiple clock signals, and 0, 1 data is extracted from the first digital signal according to the one clock signal and converted into a second digital signal for subsequent circuit processing.

For example, if the output unit includes a differential serial output terminal, a second digital signal sampled according to a corresponding clock signal in the first digital signal is output.

For another example, if the output unit includes a parallel output end, the output unit includes a serial-to-parallel conversion circuit coupled to the sampling unit, and the serial-to-parallel conversion circuit is configured to convert the received first digital signal represented by the differential signal into a plurality of second digital signals represented by parallel signals and output the second digital signals. The serial-parallel conversion circuit includes a circuit with an 8-bit or 10-bit parallel output end, for example.

According to the above descriptions of the examples, the data receiving interface device and the data transmitting interface device test the channel environment by using the transmission signal for testing between the transmissions of the effective data, thereby implementing the equalization compensation operation in which the data receiving interface device is pre-adjusted to suppress the channel noise and improve the accuracy of the transmission signal.

In a data interface device such as a radar sensor for an automobile, the radar sensor transmits a first analog signal representing measurement data in real time using a data transmission interface device and a data reception interface device during a triggered transmission of the detected measurement data. Considering that the real-time requirement of the automobile on the measured data is extremely high, the data transmitting interface device and the data receiving interface device comprise a signal processing process for clock recovery operation during the transmission of the differential signal according to the serial transmission protocol, and therefore, if the process can be shortened, the delay time of the transmitted data can be effectively shortened.

Therefore, the present application also provides a data interface device (also called a data receiving interface device) aiming to shorten the time length for recovering a clock signal from a received analog signal. The data interface device can transmit data (or signals) in millisecond-level or even nanosecond-level time intervals for sensors used in application fields such as automobiles and traffic monitoring, and effectively shortens the time duration.

Please refer to fig. 17, which is a schematic diagram of another hardware architecture of the data receiving interface device. The data reception interface device 3 includes: an input unit 31, a sampling unit 32, a clock recovery control unit 33, a clock generation unit 34, and an output unit 35.

The input unit is coupled to a channel to receive a first analog signal from the channel and output a corresponding second analog signal to be converted.

The clock recovery control unit is coupled to the sampling unit, and outputs a K-bit clock recovery control signal reflecting a phase deviation between a second analog signal and the clock signal by detecting the received first digital signal within a preset number of clock half cycles; wherein the clock recovery control signal represents the phase value of the adjusted clock signal with a field.

The clock generation unit is coupled to the clock recovery control unit and the sampling unit, and is configured to adjust the generated clock signal according to the received clock recovery control signal and output the adjusted clock signal to the sampling unit.

Wherein the input unit, the sampling unit and the output unit are the same as or similar to any of the data receiving interface devices mentioned in the foregoing fig. 10-16 and their respective examples. For example, the input unit performs swing compensation on the received first analog signal by using a cascade of equalizer units previously set via a test channel, and outputs a second analog signal. The sampling unit samples the second analog signal according to the received clock signal to output a paired inverted first digital signal. The output unit converts two paths of the inverted first digital signals into a plurality of paths of parallel second digital signals. The second digital signal is exemplified by an 8-way or 10-way parallel digital signal.

As described above, the sampling unit is responsive to transition edges of the received clock signal and outputs a corresponding inverted first digital signal. When the sampling unit receives a plurality of clock signals with phase offset, the first digital signal output by the sampling unit comprises, in response to each clock signal: sampling according to the corresponding moments of different clock signals to obtain high/low levels; the output first digital signal and one path of clock signal are output to an output unit for a subsequent circuit to carry out digital signal processing; the sampled first digital signal is output to the clock recovery control unit, so that the clock recovery control unit can perform phase detection on the first digital signal generated within a preset number of clock half cycles. Wherein the phase shift (also called phase difference) is less than 180 °, for example, the phase shift is 30 °, 45 °, or 90 °.

Unlike the previous examples, the clock signal is output by the clock generation unit according to the clock recovery control signal provided by the clock recovery control unit, which includes the phase interval and the phase value. The clock recovery control unit detects the clock phase of the received first digital signal according to the half period (also called clock half period) of the currently received clock signal, and generates a clock recovery control signal to feed back to the clock generation unit; the clock generating unit adjusts the phase of the clock signal accordingly so as to be synchronized with the clock signal used by the data transmission interface device for transmitting the analog signal. The clock recovery control signal provides the phase interval and the phase value in the phase interval at the same time, so that the clock recovery control unit and the clock generation unit synchronously adjust the phase interval and the accurate phase value in the feedback-adjustment process, thereby greatly shortening the feedback-adjustment time length in the clock recovery process.

In some examples, the clock recovery control unit includes: an N-bit first register and an output circuit. The N-bit first register is used for providing a phase value of a corresponding field. Wherein, N is an integer greater than 1, which is used to represent the precision of the binary phase value provided by the N-bit first register. The N-bit first register may be cascaded by a plurality of registers to implement a shift operation, or a shift register. The N-bit first register is used for adjusting the temporarily stored binary phase value by using a shifting interpolation mode. The method of shift interpolation includes: shift interpolation from higher bits to lower bits, and/or shift interpolation from lower bits to higher bits. The shift interpolation from high bit to low bit or the shift interpolation from low bit to high bit is used to indicate that the phase is shifted in the phase interval clockwise or counterclockwise. For example, a shift interpolation of 1 from high to low indicates that the N-bit first register has shifted the phase value counterclockwise; shifting 0 from low to high indicates that the N-bit first register is shifted by a phase value clockwise.

The output circuit is connected with the N-bit first register and the clock generation unit, and is used for generating the clock recovery control signal according to the binary phase value stored in the N-bit first register and outputting the clock recovery control signal to the clock generation unit. Examples of the output circuit include a circuit including a flip-flop. For example, each output terminal of the N-bit first register is connected to a flip-flop, and each flip-flop is triggered to output the binary phase value according to a transition edge of the clock signal.

Here, the clock recovery control unit may perform an interpolation operation by performing clock phase detection on the second analog signal for a preset number of clock half cycles to control the N-bit first register to perform high-to-low shifting or low-to-high shifting. The preset number can be determined according to the system stability, robustness and other indexes of the whole data receiving interface device. For example, the number is 8.

In some examples, the clock generating unit generates multiple clock signals at the current time according to a clock recovery control signal at the previous time, wherein the multiple clock signals have a certain phase difference therebetween, so that the sampling unit samples the received second analog signal multiple times within a single clock half period and outputs the sampled high and low levels to the clock recovery control unit; a comparison circuit or the like in the clock recovery control unit selectively controls the interpolation of the N-bit first register from the high bit side or the low bit side by comparing the high and low levels. When the preset number is executed, the output circuit outputs the binary phase value stored by the N-bit first register. It can be seen that the clock generation unit maintains outputting the clock signal having a certain phase for a period of at least the preset number and a clock half period.

In still other examples, the clock recovery control unit is configured to count all high and low levels during a period of a preset number of clock half cycles received, in contrast to the previous example; the N-bit first register is controlled to interpolate from the high-order side or the low-order side by comparing the count value, and is output by the output circuit.

To this end, please refer to fig. 18, which is a schematic circuit diagram of the clock recovery control unit; the clock recovery control unit includes: a first shift decision circuit 331, a first phase adjustment circuit 332, an N-bit first register 333, and an output circuit 334.

The first shift decision circuit is coupled to the sampling unit, detects the first digital signal within each clock half period of a preset number, and outputs a control signal determined according to the number of level logics.

Here, the first digital signal received by the first shift decision circuit is obtained by sampling the second analog signal by the sampling unit according to the multiple clock signals. For example, the first shift decision circuit and the sampling unit are connected by two differential lines to receive the first digital signal; the first digital signal is obtained by sampling the second analog signal at different moments by the sampling unit according to the clock phase offset among the multiple clock signals.

The first shift decision circuit performs level counting of the first digital signal using circuit devices such as a counter and a comparator, and outputs a control signal according to the level counting for at least the preset number of clock half cycles, wherein the control signal includes at least an identification signal indicating whether the phase of the first digital signal is advanced or retarded compared to the phase of the clock signal. For example, the identification signal is a 2-bit signal set according to a preset truth table of phase advance, phase lag and phase alignment; or a different level signal corresponding to a truth table.

In some examples, the first shift decision circuit includes: a phase-shift detection circuit structure and a phase-shift control circuit structure.

The phase shift detection circuit structure is coupled to the sampling unit and detects the first digital signals within a preset number of clock half cycles to obtain phase demodulation detection data.

Here, the phase shift detection circuit structure includes: the phase detection logic circuit is constructed by utilizing a plurality of comparators according to a preset truth table and is used for phase detection (also called phase detection). The phase shift detection circuit structure also comprises a temporary storage circuit constructed by a plurality of triggers/registers, and the temporary storage circuit is used for temporarily storing the phase discrimination detection result of each phase discrimination logic. The phase shift detection circuit structure also comprises an output control circuit, so that when the detection is carried out by a preset number, the data temporarily stored by each trigger is used as the phase discrimination detection data and is output.

In some specific examples, a logic circuit in the phase shift detection circuit structure generates n-bit phase detection results (n ≧ 1) according to the high/low levels of the first digital signal detected in the opposite direction in each clock half period; the phase discrimination detection result is output to a low-order/high-order trigger in the temporary storage circuit; the temporary storage circuit temporarily stores the received phase discrimination detection result each time by using a shifted circuit structure; when the output control circuit detects that the phase discrimination detection of a preset number is performed, the phase discrimination detection result of each bit in the temporary storage circuit is output, namely phase discrimination detection data are output, and the temporary storage circuit is reset.

In still other specific examples, the phase shift detection circuit structure performs count detection in the nth clock half period by using the first and/or last level detected in the (n-1) th clock half period in the first digital signal, thereby effectively reducing the data transmission rate of the phase detection data. For example, the phase shift detection circuit configuration may reduce the data transfer rate of the phase detected data to half the frequency of the clock signal.

On the basis of the above-described circuit configuration example, in some examples, the phase shift detection circuit configuration performs phase shift detection of the levels of the respective times in the inverted first digital signal using the received different clock signals, and performs a preset number of counting operations and the like. In other examples, the phase shift detection circuit arrangement samples the received first digital signal with an internal clock signal having a frequency that is at least 2 times a frequency of a clock signal used by the sampling unit; and the sampled data is used for phase shift detection and the like.

Please refer to fig. 19, which is a timing diagram of the phase shift detection circuit structure. By utilizing the time sequence schematic diagram, the phase-shifting detection circuit structure can utilize a circuit structure comprising the circuit structure to realize the purpose of phase discrimination detection on the first digital signals with preset quantity. The phase shift detection circuit structure receives a first digital signal which is obtained by sampling a second analog signal D by using a plurality of clock signals (CLK0, CLK90, CLK180 and CLK270) with 90-degree phase shift within a clock half period. The phase-shifting detection circuit structure uses three adjacent first digital signals received in sequence as a group to carry out displacement phase discrimination detection. As shown in fig. 19, { D0, E0, D1} represents a sampling level obtained by collecting the second analog signal D on the transition edge of three clock signals with a phase offset of 90 ° in the first digital signal, and outputs a 2-bit phase detection result based on preset phase detection logic, which is specifically shown in table 1 below:

TABLE 1

Phase discrimination logic	Phase discrimination detection result	Explanation of the invention
			D0≠E0＝D1	10	Data advance timingClock (CN)
D0＝E0≠D1	01	Data lagging clock
			D0＝E0＝D1	00/11	Data no-jump

The phase shift detection circuit structure continues to detect { D1, E1, D2}, …, { Dn-1, E n-1, Dn } group sampling levels accordingly; caching each group of phase discrimination detection results; when the number of detections reaches a preset number, outputting phase discrimination detection data consisting of up < n,0> and dn < n,0 >; wherein, each pair { up (i), dn (i) } in the phase detection data represents the phase detection data detected once, and i belongs to [ n,0 ].

The phase shift detection circuit structure sends the generated phase discrimination detection data to the phase shift control circuit structure. The phase shift control circuit structure is coupled to the phase shift detection circuit structure and the first phase adjustment circuit, counts bit values in the phase detection data, and outputs a control signal reflecting a count result, so that the first phase adjustment circuit selects a binary phase value stored in the N-bit first register to be adjusted from a high-order side or a low-order side.

Here, the phase shift control circuit structure includes a counter to count 0 or 1 in each bit number of the received phase detection data; and a comparator for outputting the control signal to the first phase adjusting circuit by comparing the counting result with a preset reference level or comparing two counting results obtained by counting each bit of the pairs up < n,0> and dn < n,0 >.

For example, please refer to fig. 20, which shows a circuit structure diagram of the phase shift control circuit structure. The phase shift control circuit structure comprises two counters (Count _ vot _1 and Count _ vot _2) and a comparator CP _ vot _1, wherein the counter Count _ vot _1 is used for counting 1 or 0 bits in up < n,0 >; the counter Count _ vote _2 is used for the number of bits of 1 or 0 in dn < n,0 >; the comparator CP _ vote _1 receives level signals reflecting the count values output from the two counters, and outputs control signals including UPV and DNV. Referring to table 2, for example, if UPV is 1& DNV is 0, it indicates that N (up 1) > N (dn 1), i.e. data advance clock, and under the control of the control signal, the first phase adjustment circuit performs interpolation from the upper side of the N-bit first register; if UPV is 0 and DNV is 1, it means that N (up 1) < N (dn 1), i.e. a data lag clock, and the first phase adjustment circuit performs interpolation from the lower side of the N-bit first register under the control of the control signal; if UPV is 0& DNV is 0, it means that N (up 1) is N (dn 1), that is, there is no change in data, and the first phase adjustment circuit does not perform an interpolation operation under the control of the control signal. Where N (#) represents the number of bit 1 in the pair up < N,0>, or dn < N,0 >.

TABLE 2

Wherein, the number of bits interpolated by the first phase adjusting circuit can be 1 bit or multiple bits. To this end, in order to adjust the binary phase value quickly and accurately, the first phase adjustment circuit further includes: a selection circuit structure, connected to the first shift decision circuit, for selectively adjusting the value of a bits on the high side or the low side in the first register or selectively adjusting the value of b bits on the high side or the low side in the first register according to the control signal; wherein a and b are integers less than N, and a is not equal to b. In other words, the selection circuit arrangement is used to select either a coarse binary phase value in the first register or a fine binary phase value in the first register.

The specific values of a and b can be adjusted according to the total time limit of the actual clock recovery.

In some specific examples, the number of bits a or b of interpolation provided by the selection circuit structure is a fixed value. For example, the logic circuit configuration includes a parser which outputs a or b pieces of interpolation data according to the received control signal and inserts from the upper side of the first register or from the lower side of the first register accordingly. The first register adjusts the stored binary phase value according to the shifting mode of the first register.

In some embodiments, the number of bits a or b of interpolation provided by the selection circuit structure may be externally set. For example, the selection circuit structure includes an encoder or a decoder (e.g., a temperature encoder) coupled to the phase shift control circuit structure and receiving an externally input command, encoding the externally input command into a value of a or b, and performing the interpolation operation as exemplified above upon receiving a control signal accordingly.

The N-bit first register is used for providing 32-bit storage, and when the received external instruction contains instruction information for setting the value a by using a 4-bit stepping value, the thermometer encoder encodes the 4-bit stepping value to obtain that a is 2; when the received external instruction contains instruction information for setting the b value with a step value of 5 bits, the thermometer encoder encodes the step value of 5 bits to obtain b as 1. The set value and the temperature encoder are examples, and the used encoder and the set step value can be selected according to the control requirement, the process requirement and the like of the actual clock recovery.

To select either a coarse or fine adjustment mode to control the number a or b of shift bits in the N-bit first register, in some specific examples, the selection circuit structure determines whether coarse or fine adjustment is selected by level logic processing the received at least one control signal.

In some specific examples, the control signal includes a control bit for selecting coarse adjustment or fine adjustment for identification by the selection circuit structure.

For example, the clock recovery control unit further includes: and a second shift decision circuit, coupled to the phase shift detection circuit structure and the selection circuit structure, for performing count statistics of data advance and data lag on at least one group of received phase detection data, and outputting a control signal for selecting coarse tuning or fine tuning according to the count statistics, so that the selection circuit structure performs a selection operation according to the control signal.

The second shift decision circuit is a circuit structure constructed by digital and analog electronic devices such as a pulse counting circuit, an adder/subtractor, a comparator, a capacitor, a charge-discharge control circuit, an isolation circuit and the like, so as to execute a judgment logic for selecting coarse adjustment or fine adjustment.

Wherein the example of the judging logic includes: counting a plurality of sets of phase detection data (such as up < n,0> and dn < n,0 >); and judging whether the difference value between the accumulated count values respectively reflecting the data advance and the data lag reaches a preset threshold, and selecting and outputting a control signal for selecting coarse adjustment or fine adjustment according to the judgment result. The threshold is related to the number of coarse shifts, which can be represented by a level signal.

The second shift decision circuit includes: the phase-shift detection circuit structure is coupled to the phase-shift detection circuit structure, and is used for performing pulse counting statistics of data advance and data lag on at least one group of received phase-demodulation detection data respectively, and outputting a level signal for reflecting phase deviation amplitude obtained through multiple phase demodulation; the comparator is coupled with the judging logic circuit structure and the phase-shifting control circuit structure and is used for comparing the level signal with a preset reference level so as to output a control signal containing selection coarse adjustment or fine adjustment.

For this purpose, the phase shift detection circuit structure provides two paths of phase detection data respectively representing data lead and data lag, such as up < n,0> and dn < n,0 >. Fig. 21 is a schematic circuit diagram of the second shift decision circuit 335, in which the decision logic circuit structure includes two pulse counters (3351_ a, 3351_ b) for respectively counting the number of leading data or lagging data in each phase detection data, and outputting the counted number in the form of level signal/digital signal. The judging logic circuit structure further comprises: a difference calculating circuit component 3352 for signal processing by means of a control level, which performs subtraction calculation of the received level signal/digital signal representing the number of times for detecting the magnitude of the phase deviation resulting from phase discrimination to a plurality of times; and converting the amplitude of the phase deviation into a level signal and outputting the level signal. The comparator 3353 compares the level signal with a preset reference level to output a high level or a low level, wherein the high/low level signal is a control signal LOCK that selects coarse or fine adjustment. The control signal and the control signal output by the first phase shift decision circuit form a control signal containing a plurality of control bits and output to the first phase adjustment circuit.

To improve the accuracy of phase alignment between the phase of a clock signal and the level of a second analog signal reflecting valid data. The clock recovery control unit further includes: an M-bit second register and a second phase adjustment circuit.

The M-bit second register is used for storing binary phase interval values of the clock signals. The second phase adjusting circuit is coupled to the N-bit first register, the M-bit second register, and the first shift decision circuit, and configured to selectively adjust a binary phase interval value in the M-bit second register according to a control logic composed of a binary phase value in the N-bit first register and the control signal. Wherein the control logic is configured to adjust the binary phase interval value in the M-bit second register when the binary phase value in the N-bit first register reaches a boundary value and the control signal indicates to continue adjusting the phase beyond the current boundary value. Therefore, the aim of quickly and accurately realizing the phase alignment between the clock signal and the second analog signal is fulfilled by synchronously adjusting the phase interval value and the phase value.

Please refer to fig. 22, which shows a conditional-state transition diagram of the phase interval adjusted by the second phase adjustment circuit. Wherein the N-bit first register comprises 32 bits: c0, C1, …, C31; the control signal received by the second phase adjustment circuit comprises UPV and DNV, and the M-bit second register is preset for storing the number information of the current phase interval according to preset four phase intervals (Z0, Z1, Z2 and Z3). Wherein, the example of the number information includes: two pieces of boundary information of the phase section, or identification information of the phase boundary that can correspond to the phase section, and the like.

As shown in fig. 22, when all the number bits stored in the current N-bit first register are 1 and (UPV ═ 1& DNV ═ 0), the phase intervals are adjusted in the preset positive direction of the cycle of each phase interval; when the number bits stored in the current N-bit first register are all 0 and (UPV ═ 0& DNV ═ 1), adjusting the phase interval along the preset cyclic negative direction of each phase interval; when the value bits stored in the current first register are not all 1's or all 0's, the current phase interval is maintained. Wherein the above-described condition-to-state transition mode is also applicable for the clock recovery control unit providing coarse and fine tuning.

The output circuit is further connected to the M-bit second register, so as to generate the clock recovery control signal according to the phase interval and the corresponding phase value stored in the M-bit second register and the N-bit first register, and output the clock recovery control signal to the clock generation unit.

According to one of the above examples, the present application exemplifies a specific example of a clock recovery control unit. Please refer to fig. 23, which is a schematic circuit diagram of a clock recovery control unit. The clock recovery control unit includes a first shift decision circuit 331, a second shift decision circuit 335(LD), a first phase adjustment circuit 332, an N-bit first register 333, a second phase adjustment circuit 336, an M-bit second register 337, and an output circuit 334'. The first shift decision circuit 331 includes: phase shift detection circuit structure PD and phase shift control circuit structure Vote.

When the sampling unit outputs a first digital signal, the phase shift detection circuit structure detects sampling levels { D0, E0, D1} of the first digital signal according to a preset number T sampled in a clock half period according to the phase discrimination logic of table 1 so as to obtain a phase discrimination detection result representing a 2-bit value in a clock in the clock half period, wherein j belongs to T; all 2bit values of the preset quantity T are output to the phase shift control circuit structure by phase discrimination detection data consisting of up < n,0> and dn < n,0 >.

The phase shift control circuit structure respectively counts the numerical values of all bit positions in the received phase discrimination detection data up < n,0> and dn < n,0> at each time, wherein the numerical values are 1; comparing the count value of the data before and the count value of the data after the phase discrimination detection data, and outputting a first control signal containing a binary phase value to a first phase adjusting circuit; and outputting the control signal to a second phase adjustment circuit. During this period, the second shift decision circuit performs accumulated counting of data advance and data lag for at least one group of received phase detection data according to the phase interval detection logic of table 2, and outputs a second control signal for selecting coarse adjustment or fine adjustment to the first phase adjustment circuit according to a phase deviation amplitude signal obtained by accumulated counting and reflecting multiple phase detections.

The first phase adjustment circuit shifts and adjusts the binary phase value stored in the N-bit first register according to the coarse adjustment bit number a and referring to the condition-state transition diagram of fig. 22 under the control of coarse adjustment. Alternatively, the first phase adjustment circuit shifts and adjusts the binary phase value stored in the N-bit first register according to the fine adjustment bit number b and referring to the condition-state transition diagram of fig. 22 under the control of fine adjustment.

Please refer to fig. 24, which is a diagram illustrating a condition-state transition of the first phase adjusting circuit for adjusting the binary phase value. Taking the coarse adjustment digit number a as 2 and the fine adjustment digit number b as 1 as an example, the received control signals include a first control signal and a second control signal, when UPV in the first control signal is 1& DNV as 0 and the second control signal represents a fine adjustment phase, the first phase adjustment circuit selects the digit number according to 1 bit, shifts from the C0 bit in the N-bit first register to the C31 bit direction, and inserts the C0 bit into the value 0; when UPV 0& DNV 1 in the first control signal and the second control signal indicates the fine adjustment phase, the first phase adjustment circuit selects a bit number of 1 bit, shifts from the C31 bit in the N-bit first register to the C0 bit direction, and inserts the value 1 in the C31 bit. By analogy, when the N-bit first register stores all 1 values as shown in fig. 22 and the UPV & DNV in the first control signal is 0, the second phase adjustment circuit adjusts the value in the M-bit second register in the positive direction of the cycle of the phase interval to adjust one phase interval; when the N-bit first register stores all 0 values as shown in fig. 22 and UPV & DNV & 0 values in the first control signal, the second phase adjustment circuit adjusts the M-bit second register values in the cyclically negative direction of the phase interval to adjust one phase interval. When the first control signal indicates fine adjustment and UPV & DNV & 0 in the second control signal, the phase adjustment is completed. The output circuit generates a clock recovery control signal and outputs the clock recovery control signal to the clock generation unit every time the N-bit first register or the M-bit second register is adjusted.

The clock generating unit generates a plurality of clock signals with phase difference within a clock half period according to the received phase interval and the binary phase value within the corresponding phase interval, and feeds back the clock signals to the sampling unit. The sampling unit outputs one of the clock signals and the first digital signal to the output unit so as to output a second digital signal which can be identified by a subsequent circuit.

With the signal transmission methods mentioned in the above examples, before the data transmitting interface device and the data receiving interface device transmit the valid data, the test data with the preset data amount is transmitted according to the preset transmission protocol to recover the clock signal and test the environmental noise of the current channel, so as to recover the accurate second digital signal from the channel.

In some electronic devices, both data transmitting and receiving interface devices are integrated into the data interface device for the purpose of bidirectional communication. In other electronic devices, the interface device and the data receiving interface device are respectively configured in different hardware modules according to data transmission design between the hardware modules in the electronic device.

Please refer to fig. 25, which is a diagram illustrating a hardware structure of a sensor system. The sensor system 4 includes a first radar sensor 41 and a second radar sensor 42, wherein the first radar sensor 41 or the second radar sensor 42 is exemplified by: a chip-level sensor, or a printed circuit board integrated with multifunctional devices including an antenna and a signal transceiver chip. The two are connected through the data transmitting interface device 411 and the data receiving interface device 421, so as to achieve the purposes of expanding the detection range of the sensor system, improving the resolution and the like. Examples of such sensor systems are: the circuit board of the first radar sensor and the circuit board of the second radar sensor are cascaded by utilizing a printed circuit board, or the first radar sensor and the second radar sensor of a chip level are cascaded by utilizing an SOC technology.

Wherein at least one of the first and second radar sensors further comprises: an antenna device and a signal transmitting/receiving device. The antenna device is driven by the signal transceiver to transmit detection signal waves and receive echo signal waves formed by target reflection. The signal transceiver outputs a baseband digital signal corresponding to the echo signal wave. For example, the signal transceiving means includes a signal transmitter and a signal receiver. The antenna device, and the signal transceiver are integrated in the first radar sensor or the second radar sensor at a chip level, for example, using a circuit structure of a semiconductor manufacturing process. The signal transmitter transmits detection signal waves in a preset frequency range or a fixed frequency mode through an antenna device; the signal receiver performs signal processing including mixing, filtering, and automatic gain adjustment on the echo electric signal corresponding to the echo signal wave, and performs analog-to-digital conversion on the analog signal to output the baseband digital signal. Wherein, the echo signal wave is formed by reflecting the detection signal wave by an object; the echo electric signal is an electric signal generated by the receiving antenna sensing the echo signal wave.

In some examples, at least one of the first radar sensor and the second radar sensor may further include: and the signal processing device is used for carrying out signal processing on the baseband digital signal and outputting the measurement data. The signal processing device outputs measurement data including at least one of an angle, a distance, and a velocity by performing signal processing including Fast Fourier Transform (FFT) operation, etc. on a baseband digital signal.

In still other examples, at least one of the first radar sensor and the second radar sensor may further include a target detection device for performing data processing such as target detection, target tracking, and the like on the measurement data to output target detection data. The target detection device is used for carrying out target detection processing on the received measurement data so as to output corresponding target detection data.

The first radar sensor further includes a first data interface device, such as the data transmission interface device described in any of the above examples, configured to transmit the measurement signal detected by the first radar sensor. Wherein the measurement signal is used to reflect at least one of: the first radar sensor obtains a baseband digital signal through detection, at least one of measurement data of a distance, a speed and an azimuth angle between the first radar sensor and a target, and target detection data of the target.

The second radar sensor further comprises a second data interface device and a third data interface device; wherein the second data interface device is connected with the first data interface device through a channel; wherein the second data interface device is a data receiving interface device as in any of the above examples, configured to receive the measurement signal; and the third data interface device is used for forwarding the measuring signal. Wherein the channel is a medium for the first radar sensor and the second radar sensor to transmit measurement signals, examples of which include any one of: microstrip lines, coaxial cables, or optical fibers.

Here, the third data interface device may be a data transmission interface device as described in any of the above examples; or other data interface devices such as a CAN bus interface, etc.

As a sensor system including a plurality of radar sensors, a master device and a slave device are generally provided, in which the master device manages an operation state of the slave device and coordinates data/signals generated by itself and the slave device to be input/output through a designated data interface device. Wherein the operation state examples include at least one of the following: the signal receiving and transmitting device adopts at least one channel of receiving and transmitting channel to receive and transmit signals; a standby state; data read and write status, etc.

Taking one of the first radar sensor or the second radar sensor as a master device in the cascade sensor, and the other of the first radar sensor or the second radar sensor as a slave device in the cascade sensor, under the control of the master device, both the first radar sensor and the second radar sensor utilize the third data interface device to perform data transmission with an external device. For example, the measurement signals detected by the first radar sensor and the second radar sensor are transmitted via a third data interface. In order to provide a more complete sensing solution, in some examples, the sensor system further includes a data processing device coupled to the third data interface device, for performing at least one data processing on the measurement signal, and outputting a corresponding target detection result, interaction data, or control instruction through the third data interface device.

Wherein the target detection result is information extracted from the measurement data describing dynamic and/or static objects in the surrounding environment detected by the sensor system, including but not limited to single target (or multiple targets): vital sign information, movement information, or boundary information, identification information, and the like. The interaction data is data determined for the purpose of delivering the measurement data or the target detection result to the user, and includes, but is not limited to, at least one of the following data for the user to feel: reminders, warnings, graphics, or sounds, etc. The control instruction is information which is generated after data processing is carried out on the received measurement data or the target detection result according to a preset trigger condition and is used for enabling other hardware systems to change the running state; wherein the trigger condition is related to a data processing purpose of the measurement data or the target detection result. For example, the control instructions include, but are not limited to, at least one of: control commands for the purpose of slowing down or turning the vehicle, control commands for the purpose of detecting vital movements in the cabin (or in the room), and the like.

For this purpose, the working process of the sensor system is exemplified as follows: taking a second radar sensor as a master device, taking a first radar sensor as a slave device as an example, the second radar sensor manages the first radar sensor to synchronously transmit and receive signal waves with the first radar sensor, and performs signal processing such as frequency mixing, filtering and the like on electric signals provided by virtual transmitting and receiving channels distributed by the first radar sensor and the second radar sensor so as to output baseband digital signals; the first and second radar sensors each also perform digital signal processing on the baseband digital signals to produce measurement data. The first radar sensor establishes a communication mechanism that outputs the generated measurement data to the second radar sensor using the first data interface device, the channel, and the physical link of the second data interface device under the management control of the second radar sensor. For example, in a handshake link in a signal transmission protocol, a first radar sensor transmits a handshake signal through a first data interface device, and on one hand, a communication link is established with a second radar sensor so as to transmit measurement data obtained by the first radar sensor; on the other hand, by using the handshake signal, the equalization circuit in the second data interface device can preset a compensation amplitude according to the detected noise condition in the current channel; and the clock recovery unit and the clock unit in the second data interface device recover a clock signal from the handshake signal that can sample the subsequent measurement signal. After the communication link is established, the first data interface device and the second data interface device accurately realize the receiving and transmitting processing of the measuring signal. The measurement signal is an analog signal which is formed by the measurement data after the communication processing is carried out by the first data interface device and is convenient to transmit. Under the management control of the second radar sensor, the second radar sensor also sends the first radar sensor and the measurement data obtained by the second radar sensor to the data processing device, so that the data processing device extracts target detection data from the measurement data provided by the two radar sensors and obtains a target detection result, interactive data or a control instruction by utilizing the target detection data; and the target detection result, the interactive data, the control instruction and other information are output through a third data interface device so as to be used for subsequent hardware circuit systems to execute corresponding operations.

The application also provides a data acquisition device. The data acquisition equipment is used for connecting a chip-level radar sensor with a peripheral circuit so as to enable the radar sensor to operate, and forwarding or continuously processing any one of baseband digital signals, measurement data or target detection results which can be provided by the radar sensor.

To this end, the data acquisition device comprises: the data receiving interface device, the data processing device mentioned in the above example; a data transmission interface device Out _ Port _1 may also be included. For convenience of description, the data receiving interface device is also referred to as a fourth data interface device in this example; the data transmission interface device is also called as a fifth data interface device. The fourth data interface device is connected with a data transmitting interface device Out _ Port _2 (also called as a sixth data interface device) in the radar sensor through a channel.

Please refer to fig. 26, which is a schematic diagram of a hardware structure of the data acquisition device 5, wherein the third radar sensor 51, the fourth data interface device 52, the data processing device 53 and the fifth data interface device 54 are all disposed on the printed circuit board; wherein the sixth data interface device 511 of the third radar sensor 51 is coupled with the fourth data interface device 52. Not shown, the third radar sensor and its peripheral circuits are arranged on one printed circuit board, the fourth data interface device 52, the data processing device 53 and the fifth data interface device 54 are arranged on another printed circuit board, and the two printed circuit boards are coupled to the fourth data interface device 52 through the sixth data interface device 511 of the third radar sensor 51.

Wherein, the third radar sensor is exemplified by the first radar sensor, the second radar sensor, or the sensor system in the above example; the data interface device comprises a sixth data interface device which is coupled with the fourth data interface device through a channel. The sixth data interface device is any one of the data receiving interface devices provided by the above examples; the fourth data interface device is any one of the data transmission interface devices provided in the above examples. Examples of the fifth data interface device include, but are not limited to, at least one of: USB interface, CAN interface, and Serdes interface, etc.

The third radar sensor transmits the measurement signal to the data processing device through the coupled sixth data interface device and the fourth data interface device. The data processing device is an electronic device which forwards or continues to process any one of the baseband digital signal, the measurement data and the target detection result provided by the fourth data interface device. The data processing apparatus includes, for example, at least one of: CPU, MCU, DSP, FPGA and other editable processors. Wherein, the forwarding operation includes at least one of the following: the parallel data output by the fourth data interface device is converted into data in at least one data format supported by the USB interface, and the parallel data is converted into data in a data format supported by the CAN interface. The continued processing operation is data processing based on the received digital signal. For example, if the received digital signal is a baseband digital signal, the example of the continued processing operation includes at least one of the following: detecting an interference signal in the baseband digital signal; the baseband digital signal is subjected to signal processing to obtain measurement data including at least one of a distance, a velocity, and an angle, and the like. As another example, if the received digital signals are measurement data, then the example of the continued processing operation includes, for a single target (or multiple targets): and data processing such as vital sign information, movement information, boundary information, identification information, interactive processing and the like. As another example, if the received digital signal is a target detection result, the continued processing operation includes at least one of the following: interactive processing, control processing, and the like. Wherein, the interaction data obtained through the interaction processing is data determined for the purpose of delivering the measurement data or the target detection result to the user, and includes but is not limited to at least one of the following data for the user to feel: reminders, warnings, graphics, or sounds, etc. The control instruction obtained by the control processing is information which is generated after the received measurement data or the target detection result is subjected to data processing according to a preset trigger condition and is used for changing the running state of other hardware systems; wherein the trigger condition is related to a data processing purpose of the measurement data or the target detection result.

The signal generated by the processing operation in any of the above examples is output by the fifth data interface device for corresponding processing by the subsequent circuit apparatus.

In one embodiment, the present application also provides an electronic device configured with the sensor system or the data acquisition apparatus, including: an antenna; a carrier; such as the sensor system or data acquisition device of the above-described embodiments. Wherein, the antenna is arranged on the carrier; or a chip or integrated circuit integrated with the sensor and then placed on the carrier (i.e., the antenna may be AiP or an antenna provided in an AoC configuration). Wherein, the chip or the integrated circuit is connected with the peripheral circuit device through a fifth data interface device (namely, the chip or the integrated circuit is not integrated with an antenna at the moment, and can be SoC and the like). The carrier may be a printed circuit board PCB (e.g., a development board, a data board, or a motherboard of a device, etc.) that provides channels such as PCB traces.

The electronic device realizes signal transmission of measurement signals between electronic devices according to at least one pair of the data transmission interface device and the data reception interface device provided in the above examples. Therefore, the purpose of interacting the target objects which are not in the same space range with the user is achieved; or the purpose of automatic control of the electronic equipment according to the detected target object is realized. For example, the target detection information is marked on a map and displayed to a terminal device or the like held by the user. The map is a coordinate system for abstract description of the measurement space range, can be displayed in the terminal device in a patterning mode, and is marked on a map interface of the patterning display according to the position, the speed and the like corresponding to the obtained target detection information. For another example, when abnormal information such as breathing slowing is obtained through analysis of target detection information, corresponding users are reminded of pre-rescue treatment and the like by using interaction modes such as acoustoelectric and photoelectric modes. For another example, when vital sign information such as breathing is obtained through analysis of target detection information in the room, output energy, pose or the like of electronic equipment in the room is adjusted.

In some embodiments, the electronic device may be a component and a product applied to fields such as smart home, transportation, smart home, consumer electronics, monitoring, industrial automation, in-cabin detection, health care, and the like. For example, the device body may be an intelligent transportation device (such as an automobile, a bicycle, a motorcycle, a ship, a subway, a train, etc.), a security device (such as a camera), a liquid level/flow rate detection device, an intelligent wearable device (such as a bracelet, glasses, etc.), an intelligent household device (such as a sweeping robot, a door lock, a television, an air conditioner, an intelligent lamp, etc.), various communication devices (such as a mobile phone, a tablet computer, etc.), etc., and a barrier gate, an intelligent traffic indicator lamp, an intelligent indicator board, a traffic camera, various industrial mechanical arms (or robots), etc., and may also be various instruments for detecting vital sign parameters and various devices carrying the instruments, such as an automobile cabin detection, an indoor personnel monitoring, an intelligent medical device, a consumer electronic device, etc.

The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.

It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present application and the technical principles employed. It will be understood by those skilled in the art that the present application is not limited to the particular embodiments illustrated herein, and that various obvious changes, rearrangements and substitutions may be made therein by those skilled in the art without departing from the scope of the application. Therefore, although the present application has been described in more detail with reference to the above embodiments, the present application is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present application, and the scope of the present application is determined by the scope of the appended claims.

Claims

1. A data interface device, comprising:

the input unit is coupled with a channel to receive a first analog signal from the channel and output a corresponding second analog signal to be converted;

the sampling unit is coupled to the input unit and used for sampling the received second analog signal according to the received clock signal so as to output a first digital signal and the clock signal;

a clock recovery control unit, coupled to the sampling unit, for outputting a clock recovery control signal reflecting a phase deviation between a second analog signal and the clock signal by detecting the received first digital signal within a preset number of clock half-cycles; the clock recovery control signal uses a field to represent the phase value of the clock signal to be adjusted;

a clock generating unit, coupled to the clock recovery control unit and the sampling unit, for adjusting the generated clock signal according to the received clock recovery control signal and outputting the adjusted clock signal to the sampling unit;

and the output unit is coupled with the sampling unit and used for converting the correspondingly acquired first digital signal into a second digital signal under the control of the received clock signal and outputting the second digital signal.

2. The data interface device of claim 1, wherein the input unit comprises:

two signal leads for coupling with the channel to receive a first analog signal represented in a differential signal from the channel;

and the equalization circuit is connected with the two signal leads and is used for performing equalization processing on the received first analog signal so as to output the second analog signal.

3. The data interface device of claim 1, wherein the clock recovery control unit comprises:

the N-bit first register is used for adjusting the temporarily stored binary phase value by using a shifting interpolation mode; wherein N is an integer greater than 1;

and the output circuit is connected with the N-bit first register and the clock generation unit, and is used for generating the clock recovery control signal according to the binary phase value stored in the N-bit first register and outputting the clock recovery control signal to the clock generation unit.

4. The data interface device of claim 3, wherein the clock recovery control unit further comprises:

a first shift decision circuit, coupled to the sampling unit, for detecting a phase of the first digital signal within a predetermined number of each clock half-cycle and outputting a control signal determined according to the number of phase discrimination results;

a first phase adjusting circuit, coupled to the N-bit first register and the first shift decision circuit, for adjusting the stored binary phase value from a higher bit side or a lower bit side of the N-bit first register according to the control signal.

5. The data interface device of claim 4, wherein the first shift decision circuit comprises:

the phase shift detection circuit structure is coupled with the sampling unit and is used for detecting the first digital signals within a preset number of clock half cycles so as to obtain phase discrimination detection data;

and the phase shift control circuit structure is coupled with the phase shift detection circuit structure and the first phase adjustment circuit, counts bit values in the phase detection data and outputs a control signal reflecting a counting result, so that the first phase adjustment circuit selects a binary phase value which is stored by adjusting from the high-order side or the low-order side in the N-bit first register.

6. The data interface device of claim 4, wherein the first phase adjustment circuit comprises:

and the selection circuit structure is connected with the first shift judgment circuit and used for selecting the value of the high-order side or the low-order side in the coarse adjustment first register or selecting the value of the high-order side or the low-order side in the fine adjustment first register according to the control signal.

7. The data interface device of claim 5, wherein the selection circuit structure comprises: an encoder or decoder coupled to the phase shift detection circuit structure for outputting information for the coarse or fine adjustment bits according to the received external command.

8. The data interface device of claim 6, wherein the clock recovery control unit further comprises:

the second shift decision circuit is coupled to the phase shift detection circuit structure and the selection circuit structure, and configured to perform count statistics on data advance and data lag of at least one group of received phase demodulation detection data, and output a control signal for selecting coarse tuning or fine tuning according to the count statistics, so that the selection circuit structure performs a selection operation according to the control signal.

9. The data interface device of claim 8, wherein the second shift decision circuit comprises:

a judging logic circuit structure, coupled to the phase shift detection circuit structure, for performing pulse counting statistics of data advance and data lag respectively on at least one group of received phase discrimination detection data, and outputting a level signal reflecting a phase deviation amplitude obtained by multiple phase discrimination;

and the comparator is coupled with the judging logic circuit structure and the phase-shifting control circuit structure and is used for comparing the level signal with a preset reference level so as to output a control signal containing selection coarse adjustment or fine adjustment.

10. The data interface device of claim 4, wherein the clock recovery control unit further comprises:

the M-bit second register is coupled to the output circuit and used for storing a binary phase interval value of a clock signal, so that the clock recovery control signal output by the output circuit comprises the binary phase interval value and a binary phase value;

and a second phase adjustment circuit, coupled to the N-bit first register, the M-bit second register, and the first shift decision circuit, for selectively adjusting a binary phase interval value in the M-bit second register according to a control logic composed of the binary phase value in the N-bit first register and the control signal.

11. The data interface device of claim 1, wherein the output port unit comprises: and the serial-parallel conversion circuit is coupled to the sampling unit and used for converting the received first digital signal represented by the differential signal into a second digital signal represented by a plurality of paths of parallel signals and outputting the second digital signal.

12. A sensor system, comprising:

a first radar sensor comprising a first data interface device; the first data interface device is used for transmitting a measuring signal obtained by detection of the first radar sensor; wherein the measurement signal is used to reflect at least one of: a baseband digital signal detected by the first radar sensor, at least one of a distance, a speed, and an azimuth between the first radar sensor and a target, and target detection data of the target;

a second radar sensor comprising a second data interface device and a third data interface device; wherein the second data interface device is connected with the first data interface device through a channel; the second data interface device is a data interface device as claimed in any one of claims 1 to 11 for receiving the measurement signal; the third data interface device is used for forwarding the measuring signal.

13. The sensor system of claim 12, further comprising: and the data processing device is coupled to the third data interface device and used for performing at least one type of data processing on the measurement signal and outputting a corresponding target detection result, interactive data or a control command.

14. The sensor system of claim 12, wherein the channel comprises any one of: microstrip lines, coaxial cables, or optical fibers.

15. A sensor system, comprising:

16. The data acquisition device of claim 15, further comprising a radar sensor including a third data interface means; the third data interface device is used for sending out the measurement signal obtained by detection.