CN112332817A - Wide-speed high-linearity phase interpolator suitable for 1-28Gbps SerDes - Google Patents

Wide-speed high-linearity phase interpolator suitable for 1-28Gbps SerDes Download PDF

Info

Publication number
CN112332817A
CN112332817A CN202011090340.XA CN202011090340A CN112332817A CN 112332817 A CN112332817 A CN 112332817A CN 202011090340 A CN202011090340 A CN 202011090340A CN 112332817 A CN112332817 A CN 112332817A
Authority
CN
China
Prior art keywords
frequency
clock
buffer
input
phase interpolator
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202011090340.XA
Other languages
Chinese (zh)
Inventor
吕方旭
郭凯乐
王和明
冯刚
赖明澈
庞征斌
武宇轩
吴苗苗
刘涛
陆德超
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Air Force Engineering University of PLA
Original Assignee
Air Force Engineering University of PLA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Air Force Engineering University of PLA filed Critical Air Force Engineering University of PLA
Priority to CN202011090340.XA priority Critical patent/CN112332817A/en
Publication of CN112332817A publication Critical patent/CN112332817A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Manipulation Of Pulses (AREA)

Abstract

The invention discloses a wide-speed high-linearity phase interpolator suitable for 1-28Gbps SerDes, which comprises a buffer arranged at an input end to enhance the driving capability of a clock signal, and is characterized in that a digital control capacitor array connected in parallel is arranged at an output end of the buffer to form a low-pass filter, the frequency of a main pole point of the buffer is controlled at the frequency point of an input signal, and the input frequency is further ensured to be single. Compared with the prior art, the invention accurately calculates the capacitance values corresponding to different frequency points by carrying out thevenin equivalence on the buffer, and realizes the capacitance values in the circuit, so that the linearity between the output clock phase and the input control code is approximately in a linear relation in the range of 1-28Gb/s of the input data signal, and the deterministic jitter of the clock data recovery circuit is effectively reduced.

Description

Wide-speed high-linearity phase interpolator suitable for 1-28Gbps SerDes
Technical Field
The invention belongs to the technical field of circuit design and data transmission, relates to a phase interpolator, and particularly relates to a wide-speed high-linearity phase interpolator applicable to 1-28Gbps SerDes.
Background
In a high-speed serial interface receiver, a clock recovery circuit mainly has the task of extracting clock information from input data with amplitude noise and phase noise and then retiming the data; but also to be able to track low frequency phase jitter introduced in the input data. The phase interpolator has the main task of adjusting the phase of the sampling clock according to the judgment of the phase tracking control logic circuit in the clock data recovery circuit, so that the clock signal is always sampled in the middle of the data signal, and the accurate sampling of the data is ensured.
Fig. 1 shows a system block diagram of a clock data recovery circuit based on a phase interpolator. The clock data recovery circuit adopts an 1/4 rate architecture and mainly comprises a phase interpolator, a sampler and a phase tracking control logic circuit. In order to reduce the system power consumption, the phase interpolator is implemented by a CMOS digital circuit in a phase tracking control logic circuit. The working process is as follows: the 8 time-domain interleaved samplers sample the input high-speed data using an 8-phase 1/4 rate clock generated by a phase interpolator. After the lead/lag/hold information of the clock and the data is processed by a phase tracking control logic circuit, Gray codes IG and QG of a 2-Bit control quadrant and temperature codes Bit [1:16] of a 16-Bit control phase are finally generated, the phase of a phase interpolator is correspondingly adjusted, so that the clock signal is always sampled in the middle of the data signal, and the accurate sampling of the data is ensured.
Fig. 2 is a diagram of a buffer within the phase interpolator of fig. 1 within a dashed box. In order to enhance the driving capability of the clock signal, a buffer is added to the input terminal of the phase interpolator. Since the resistances of RD1 and RD2 in the buffer are much larger than the large signal resistances of M2 and M3, the output waveform inevitably rises slowly and falls quickly under large signals, and the fourier transform of the waveform inevitably contains the frequency doubling spectrum of the working frequency. The theory of the phase interpolator is obtained on the basis of sine waves with single frequency, so that the linearity of the phase interpolator is necessarily deteriorated by the incorporation of frequency multiplication frequency, and the deterministic jitter of the phase interpolator is increased. Furthermore, the buffer is only suitable for operation in a fixed frequency clock data recovery circuit.
Disclosure of Invention
To overcome the above-mentioned shortcomings of the prior art, the present invention aims to provide a wide-speed high-linearity phase interpolator suitable for 1-28Gbps SerDes, which makes the output clock phase and the input control code have a linear relationship, thereby reducing the deterministic jitter of the clock data recovery current; and enables the phase interpolator to be adapted for use in a wide-rate operating environment.
In order to achieve the purpose, the invention adopts the technical scheme that:
a wide-speed high-linearity phase interpolator suitable for 1-28Gbps SerDes comprises a buffer arranged at an input end to enhance the driving capability of a clock signal, and is characterized in that a digital control capacitor array connected in parallel is arranged at an output end of the buffer to form a low-pass filter, and the frequency of a main pole point of the buffer is controlled at the frequency point of an input signal, so that the input frequency is single.
Preferably, the buffer comprises a MOS transistor M1、M2And M3，M1And M2G pole of the transformer is respectively connected with two paths of input signals Vin1And Vin2，M1D pole of the output signal Vout1，M2D pole of the output signal Vout2，Vout1Through a resistance RD1Is connected with VDD，Vout2Through a resistance RD2Is connected with VDD，M1S pole, M of2S pole and M3D of (A)Polar connection, M3The S-pole of the digitally controlled capacitor array is grounded, and each path of the digitally controlled capacitor array is composed of a capacitor and a control switch connected in series.
Preferably, the control switch adopts an NMOS tube.
Preferably, the digitally controlled capacitor array is at V of the bufferout1And Vout2Three paths are respectively arranged on the frequency conversion circuit, namely the three paths are respectively controlled by three control bits, so that the capacitance of the output end of the buffer is adjusted according to the frequency of the input clock, the frequency range of 3.5-7GHz is quantized into 8 frequency points, and 0.5GHz is covered between every two frequency points.
Correspondingly, the invention also provides a clock data recovery circuit based on the wide-speed high-linearity phase interpolator applicable to the 1-28Gbps SerDes.
Compared with the prior art, the invention accurately calculates the capacitance values corresponding to different frequency points by carrying out thevenin equivalence on the buffer, and realizes the capacitance values in the circuit, so that the linearity between the output clock phase and the input control code is approximately in a linear relation in the range of 1-28Gb/s of the input data signal, and the deterministic jitter of the clock data recovery circuit is effectively reduced.
Drawings
Fig. 1 is a system architecture of a phase interpolator based clock data recovery circuit.
Fig. 2 is a schematic diagram of a conventional buffer.
Fig. 3 is a schematic diagram of a buffer with a digitally controlled capacitor array designed according to the present invention.
Fig. 4 is a davinin equivalent circuit at the output of the buffer of fig. 2.
FIG. 5 shows the improved linearity contrast of the pre-and post-phase interpolators when the input data is 28 Gb/s. Wherein (a) is PI output linearity before improvement, and (b) is PI output linearity after improvement.
FIG. 6 is a comparison of the recovered clock eye before and after improvement when the input data is 28 Gb/s. Wherein (a) is the PI output clock eye pattern before improvement, and (b) is the PI output clock eye pattern after improvement.
FIG. 7 is a graph showing a comparison of jitter performance of recovered clocks before and after improvement when the input data is 28Gb/s and the frequency difference is +200 ppm. Wherein, the first is PI control code before improvement, (b) is PI control code after improvement, (c) is clock eye pattern recovered before improvement, and (d) is clock eye pattern recovered after improvement.
FIG. 8 shows the improved linearity contrast of the pre-and post-phase interpolators when the input data is 22 Gb/s. Wherein (a) is PI output linearity before improvement, and (b) is PI output linearity after improvement.
FIG. 9 is a comparison of the recovered clock eye before and after improvement when the input data is 22 Gb/s. Wherein (a) is the PI output clock eye pattern before improvement, and (b) is the PI output clock eye pattern after improvement.
FIG. 10 is a graph showing a comparison of jitter performance of recovered clocks before and after improvement when input data is 22Gb/s and the frequency difference is +200 ppm. Wherein, the first is PI control code before improvement, (b) is PI control code after improvement, (c) is clock eye pattern recovered before improvement, and (d) is clock eye pattern recovered after improvement.
FIG. 11 shows the improved linearity contrast of the pre-and post-phase interpolators when the input data is 18 Gb/s. Wherein (a) is PI output linearity before improvement, and (b) is PI output linearity after improvement.
FIG. 12 is a comparison of the recovered clock eye before and after improvement when the input data is 18 Gb/s. Wherein (a) is the PI output clock eye pattern before improvement, and (b) is the PI output clock eye pattern after improvement.
FIG. 13 is a graph showing a comparison of jitter performance of recovered clocks before and after improvement when the input data is 18Gb/s and the frequency difference is +200 ppm. Wherein, the first is PI control code before improvement, (b) is PI control code after improvement, (c) is clock eye pattern recovered before improvement, and (d) is clock eye pattern recovered after improvement.
FIG. 14 shows the improved linearity contrast of the pre-and post-phase interpolators when the input data is 14 Gb/s. Wherein (a) is PI output linearity before improvement, and (b) is PI output linearity after improvement.
FIG. 15 is a comparison of the recovered clock eye diagrams before and after improvement when the input data is 14 Gb/s. Wherein (a) is the PI output clock eye pattern before improvement, and (b) is the PI output clock eye pattern after improvement.
FIG. 16 is a graph showing a comparison of jitter performance of recovered clocks before and after improvement when the input data is 14Gb/s and the frequency difference is +200 ppm. Wherein, the first is PI control code before improvement, (b) is PI control code after improvement, (c) is clock eye pattern recovered before improvement, and (d) is clock eye pattern recovered after improvement.
Detailed Description
The preferred embodiments will be described in detail below with reference to the accompanying drawings. It should be emphasized that the following description is merely exemplary in nature and is not intended to limit the scope of the invention or its application.
FIG. 3 shows an embodiment of a wide-speed high-linearity phase interpolator according to the present invention, in which a buffer for enhancing the driving capability of a clock signal is disposed at an input terminal of the phase interpolator. The invention arranges a digital control capacitor array connected in parallel at the output end of the buffer to form a low-pass filter, and controls the dominant pole frequency of the buffer at the frequency point of the input signal, thereby ensuring the single input frequency.
In this embodiment, the buffer includes a MOS transistor M1、M2And M3，M1And M2G pole of the transformer is respectively connected with two paths of input signals Vin1And Vin2，M1D pole of the output signal Vout1，M2D pole of the output signal Vout2，Vout1Through a resistance RD1Is connected with VDD，Vout2Through a resistance RD2Is connected with VDD，M1S pole, M of2S pole and M3D pole connection of (1), M3The S-pole of (a) is grounded.
Each route of the digital control capacitor array is composed of a capacitor and a control switch which are connected in series, and the control switch can adopt an NMOS tube.
In this embodiment, the digitally controlled capacitor array is controlled by three control bits to adjust the capacitance at the output of the buffer stage according to the input clock frequency. I.e. the digitally controlled capacitor array is at V of the bufferout1And Vout2The frequency range of 3.5-7GHz is quantized into 8 frequency points in this way, and 0.5GHz is covered between every two frequency points, so that the clock data recovery circuit can adapt to wide-speed data reception and realize the function of supporting continuous data rate transmission. .
The detailed principle of the invention is as follows:
the circuit of fig. 2 can be simplified to fig. 4 for analysis by the davinin equivalent theorem.
When an excitation signal is input to the circuit, its frequency domain response is:
Figure BDA0002721887860000051
it is known that the output contains two poles, one determined by the stimulus signal and the other determined by the circuit itself. The corresponding time domain response signal is:
Figure BDA0002721887860000052
wherein E is a forced response, determined by the excitation signal,
Figure BDA0002721887860000053
the transient response is determined by the circuit itself. ReqC is the time constant of the circuit, determines the main pole frequency of the circuit, and s is the laplace transform factor.
Frequency of main pole
Figure BDA0002721887860000054
The following can be obtained:
Figure BDA0002721887860000055
therefore, according to different data rates, the required capacitance value can be calculated, and each capacitance value in the capacitor array is digitally controlled, and can be the same or different according to the requirement
Such as:
when the receiving data rate is 22Gb/s and the local clock rate is 5.5GHz
Figure BDA0002721887860000056
When the receiving data rate is 18Gb/s and the local clock rate is 4.5GHz
Figure BDA0002721887860000057
When the receiving data rate is 14Gb/s and the local clock rate is 3.5GHz
Figure BDA0002721887860000058
C5.5G、C4.5GAnd C3.5GThe equivalent values of the capacitor array are respectively 5.5GHz, 4.5GHz and 3.5GHz of the local clock, G is a frequency unit, and f is a capacitance unit.
It should be noted that the method is universal, is not limited to 3 digital capacitor array control bits, and can be applied to a phase interpolator for any digitally controlled capacitor control bit; and is not limited to wide rate data of only 1-28Gb/s, and is applicable to any wide rate data range.
From (a) and (b) of fig. 5, it can be seen that the linearity of the control code and the output phase is significantly improved by using the non-equivalent current source phase interpolator.
From (a) and (b) of fig. 6, it can be seen that, when the local clock is 7GHz, the ideal PI output eye interval is 2.232ps, the maximum time interval of the improved front eye is 3.053ps, and the maximum error is (3.053-2.232)/2.232 ═ 36.8%; the maximum time interval of the improved eye pattern is 2.346ps, the maximum error is (2.346-2.232)/2.232-5.1%, and the linearity is improved by 31.7%.
From (a), (b), (c), (d) of fig. 7, it can be seen that when the received data rate is 28.0056Gb/s (frequency difference +200ppm from 28Gb/s data), and the local clock rate is 7 GHz: the clock jitter before improvement is 5.9ps, 0.083 UI; after improvement, the clock jitter is 5.3ps, 0.074 UI; the jitter performance of the recovered clock is improved by 10.2%.
From fig. 8 (a) and (b), it can be seen that, when the local clock is 5.5GH, and the numerical control capacitor array value is 547.3f, the linearity of the phase interpolator is significantly improved compared to the phase interpolator without the capacitor array.
At 5.5GHz of local clock, the ideal PI output eye interval is 2.84ps, and according to (a) and (b) of fig. 9, it can be seen that the maximum time interval of the improved front eye is 4.709ps, and the maximum error is 65.8%; the maximum time interval of the improved eye pattern is 3.144ps, the maximum error is 10.7%, and the linearity is improved by 55.1%.
From (a), (b), (c), (d) of fig. 10, it can be seen that when the received data rate is 22.0044Gb/s (frequency difference +200ppm from 22Gb/s data), and the local clock rate is 5.5 GHz: the clock jitter before improvement is 8.9ps, 0.098 UI; the clock jitter after improvement is 6.9ps, 0.076 UI; the jitter performance of the recovered clock is improved by 22.5%.
From fig. 11 (a) and (b), it can be seen that, when the local clock is 4.5GH, and the numerical control capacitor array value is 669f, the linearity of the phase interpolator is significantly improved compared to the phase interpolator without the capacitor array.
At a local clock of 4.5GHz, the ideal PI output eye interval is 3.47ps, and according to (a) and (b) of fig. 12, it can be seen that the maximum time interval of the improved front eye is 6.793ps, and the maximum error is 95.8%; the maximum time interval of the improved eye pattern is 4.238ps, the maximum error is 22%, and the linearity is improved by 73.8%.
From (a), (b), (c), (d) of fig. 13, it can be seen that when the received data rate is 18.0036Gb/s (frequency difference from 18Gb/s data is +200ppm), the local clock rate is 4.5 GHz: the clock jitter before improvement is 13.87ps, 0.125 UI; the improved clock jitter is 8.59ps and 0.073 UI; the jitter performance of the recovered clock is improved by 38.1%.
From fig. 14 (a) and (b), it can be seen that, when the local clock is 3.5GH, and the numerical control capacitor array value is 860f, the linearity of the phase interpolator is significantly improved compared to the phase interpolator without the capacitor array.
From (a) and (b) of fig. 15, it can be seen that the ideal PI output eye interval is 4.464ps for a local clock of 3.5 GHz. The maximum time interval of the improved front eye diagram is 10.63ps, and the maximum error is 138.1%; the maximum time interval of the improved eye pattern is 5.576ps, the maximum error is 24.9%, and the linearity is improved by 113.2%.
From (a), (b), (c), (d) of fig. 16, it can be seen that when the received data rate is 14.0028Gb/s (frequency difference from 14Gb/s data is +200ppm), the local clock rate is 3.5 GHz: the clock jitter before improvement was 22.26ps, 0.156 UI; the improved clock jitter is 12.75ps, 0.089 UI; the jitter performance of the recovered clock is improved by 42.72%.
By adopting the phase interpolator of the invention, based on fig. 1, it is obvious that a corresponding clock data recovery circuit can be obtained, and the sampling precision is further improved.
The above description is only for the preferred embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims (8)

1. A wide-speed high-linearity phase interpolator suitable for 1-28Gbps SerDes comprises a buffer arranged at an input end to enhance the driving capability of a clock signal, and is characterized in that a digital control capacitor array connected in parallel is arranged at an output end of the buffer to form a low-pass filter, and the frequency of a main pole point of the buffer is controlled at the frequency point of an input signal, so that the input frequency is single.
2. The wide-rate, high-linearity phase interpolator for 1-28Gbps SerDes according to claim 1, wherein said buffer comprises MOS transistor M1、M2And M3，M1And M2G pole of the transformer is respectively connected with two paths of input signals Vin1And Vin2，M1D pole of the output signal Vout1，M2D pole of the output signal Vout2，Vout1Through a resistance RD1Is connected with VDD，Vout2Through a resistance RD2Is connected with VDD，M1S pole, M of2S pole and M3D pole connection of (1), M3The S-pole of the digitally controlled capacitor array is grounded, and each path of the digitally controlled capacitor array is composed of a capacitor and a control switch connected in series.
3. The wide-speed, high-linearity phase interpolator for 1-28Gbps SerDes of claim 2, wherein said control switch is implemented with NMOS transistors.
4. The wide-speed high-linearity phase interpolator for 1-28Gbps SerDes according to claim 2 or 3, wherein the digitally controlled capacitor array is at V of the bufferout1And Vout2Three paths are respectively arranged on the frequency conversion circuit, namely the three paths are respectively controlled by three control bits, so that the capacitance of the output end of the buffer is adjusted according to the frequency of the input clock, the frequency range of 3.5-7GHz is quantized into 8 frequency points, and 0.5GHz is covered between every two frequency points.
5. The wide-speed high-linearity phase interpolator applicable to 1-28Gbps SerDes according to claim 4, wherein the values of the capacitance corresponding to different frequency points are accurately calculated by performing Davining equivalence on the buffer, so that the linearity between the output clock phase and the input control code is approximately linear in the range of 1-28Gb/s of the input data signal.
6. A wide-rate high-linearity phase interpolator for 1-28Gbps SerDes according to claim 5, wherein the resultant Davining equivalent circuit has a frequency domain response when an excitation signal is input to the circuit of:
Figure FDA0002721887850000021
the output contains two poles, one determined by the excitation signal and the other by the circuit itself, and the corresponding time domain response signal is:
Figure FDA0002721887850000022
wherein E is a forced response, determined by the excitation signal,
Figure FDA0002721887850000023
for transient response, determined by the circuit itself, ReqC is the time constant of the circuit, determines the main pole frequency of the circuit, s is the Laplace transform factor, fcIs the main pole frequency;
Figure FDA0002721887850000024
then
Figure FDA0002721887850000025
Thus, the required capacitance value is calculated according to different data rates.
7. The wide-speed, high-linearity phase interpolator suitable for 1-28Gbps SerDes according to claim 6, wherein when the received data rate is 22Gb/s and the local clock rate is 5.5GHz,
Figure FDA0002721887850000026
when the received data rate is 18Gb/s, the local clock rate is 4.5GHz,
Figure FDA0002721887850000027
when the received data rate is 14Gb/s, the local clock rate is 3.5GHz,
Figure FDA0002721887850000028
C5.5G、C4.5Gand C3.5GThe equivalent values of the capacitor array are respectively 5.5GHz, 4.5GHz and 3.5GHz of the local clock, G is a frequency unit, and f is a capacitance unit.
8. Clock data recovery circuit for wide-speed high-linearity phase interpolator suitable for 1-28Gbps SerDes based on claim 1.
CN202011090340.XA 2020-10-13 2020-10-13 Wide-speed high-linearity phase interpolator suitable for 1-28Gbps SerDes Pending CN112332817A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202011090340.XA CN112332817A (en) 2020-10-13 2020-10-13 Wide-speed high-linearity phase interpolator suitable for 1-28Gbps SerDes

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202011090340.XA CN112332817A (en) 2020-10-13 2020-10-13 Wide-speed high-linearity phase interpolator suitable for 1-28Gbps SerDes

Publications (1)

Publication Number Publication Date
CN112332817A true CN112332817A (en) 2021-02-05

Family

ID=74313771

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202011090340.XA Pending CN112332817A (en) 2020-10-13 2020-10-13 Wide-speed high-linearity phase interpolator suitable for 1-28Gbps SerDes

Country Status (1)

Country Link
CN (1) CN112332817A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117767948A (en) * 2024-02-22 2024-03-26 成都电科星拓科技有限公司 nonlinear response correction method for phase interpolator

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060076993A1 (en) * 2004-10-12 2006-04-13 Broadcom Corporation High speed clock and data recovery system
US7551909B1 (en) * 2002-08-29 2009-06-23 Silicon Image, Inc. CMOS transceiver with dual current path VCO
US7915941B1 (en) * 2009-07-01 2011-03-29 Altera Corporation Phase interpolator circuits and methods
US20180351510A1 (en) * 2017-06-01 2018-12-06 City University Of Hong Kong Phase-tuning oscillators
CN109104170A (en) * 2018-08-23 2018-12-28 上海奥令科电子科技有限公司 A kind of adaptive broadband digital clock interpolation device unit
JP2019022136A (en) * 2017-07-20 2019-02-07 ローム株式会社 Phase interpolator and timing generator, semiconductor integrated circuit

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7551909B1 (en) * 2002-08-29 2009-06-23 Silicon Image, Inc. CMOS transceiver with dual current path VCO
US20060076993A1 (en) * 2004-10-12 2006-04-13 Broadcom Corporation High speed clock and data recovery system
US7915941B1 (en) * 2009-07-01 2011-03-29 Altera Corporation Phase interpolator circuits and methods
US20180351510A1 (en) * 2017-06-01 2018-12-06 City University Of Hong Kong Phase-tuning oscillators
JP2019022136A (en) * 2017-07-20 2019-02-07 ローム株式会社 Phase interpolator and timing generator, semiconductor integrated circuit
CN109104170A (en) * 2018-08-23 2018-12-28 上海奥令科电子科技有限公司 A kind of adaptive broadband digital clock interpolation device unit

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
G. WU ET AL.: "1–16 Gb/s All-Digital Clock and Data Recovery With a Wideband High-Linearity Phase Interpolator", IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, pages 2511 - 2520 *
郭凯乐, 王和明, 刘涛等: "于高速SerDes中非等值尾电流源技术的新型高线性度相位插值器设计", 空军工程大学学报(自然科学版), pages 61 - 67 *

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117767948A (en) * 2024-02-22 2024-03-26 成都电科星拓科技有限公司 nonlinear response correction method for phase interpolator
CN117767948B (en) * 2024-02-22 2024-04-26 成都电科星拓科技有限公司 Nonlinear response correction method for phase interpolator

Similar Documents

Publication Publication Date Title
CN111149308B (en) Method for measuring and correcting multi-line time offset
US12034447B2 (en) Low latency combined clock data recovery logic network and charge pump circuit
TWI622283B (en) A clock and data recovery circuit and a phase interpolator therefor
CN102801667B (en) Current integrating decision feedback equalizer used in high-speed serial interface
TW201644241A (en) Low power high speed receiver with reduced decision feedback equalizer samplers
US10700903B2 (en) Circuit structure for efficiently demodulating FSK signal in wireless charging device
CN111868661A (en) Multi-line time offset correction method and system
CN104281553A (en) Adaptation of crossing DFE tap weight
JP6250873B1 (en) Digital / phase converter
CN111194077B (en) Timing synchronization method under low sampling rate
CN218734353U (en) Data interface device, sensor system and data acquisition equipment
CN105429642A (en) Method for extending dynamic range of data acquisition system
TWI363510B (en) Data receiver and data retrieval method
CN112468139B (en) Clock data recovery circuit, method and device
WO2020210062A1 (en) Variable gain amplifier and sampler offset calibration without clock recovery
CN114301441A (en) Linear equalizer and MIPI C-PHY circuit
CN112332817A (en) Wide-speed high-linearity phase interpolator suitable for 1-28Gbps SerDes
CN100512457C (en) Digital TV-set signalling comprehensive analyzer
US20130002460A1 (en) Multichannel Analog To Digital Converter Apparatus And Method For Using
CN101488845B (en) Multiple phases matching system applied to receiver
CN110995212A (en) Integrated circuit device, phase interpolator, interface circuit and electronic equipment
EP2323256A1 (en) Method and system for improving limiting amplifier phase noise for low slew-rate input signals
US9215106B2 (en) Method and apparatus for pre-cursor intersymbol interference correction
CN109617666A (en) A kind of feedforward timing method suitable for continuously transmitting
CN114301469B (en) Serial-parallel conversion circuit and MIPI C-PHY circuit

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination