CN117675156B

CN117675156B - Clock self-calibration circuit, data receiving system, controller and vehicle

Info

Publication number: CN117675156B
Application number: CN202410132509.5A
Authority: CN
Inventors: 孙振玮; 石刚; 徐沛文
Original assignee: Hefei Smart Chip Semiconductor Co ltd; Shanghai Sasha Mai Semiconductor Co ltd; Tianjin Smart Core Semiconductor Technology Co ltd; Suzhou Sasama Semiconductor Co ltd
Current assignee: Hefei Smart Chip Semiconductor Co ltd; Shanghai Sasha Mai Semiconductor Co ltd; Tianjin Smart Core Semiconductor Technology Co ltd; Suzhou Sasama Semiconductor Co ltd
Priority date: 2024-01-31
Filing date: 2024-01-31
Publication date: 2024-04-30
Anticipated expiration: 2044-01-31
Also published as: CN117675156A

Abstract

The invention discloses a clock self-calibration circuit, a data receiving system, a controller and a vehicle, wherein the clock self-calibration circuit comprises: the clock frequency division unit is suitable for being connected with at least one data receiving channel, and is configured to generate a channel clock of each data receiving channel according to a module clock and a frequency division coefficient corresponding to each data receiving channel, and send the channel clock of each data receiving channel to the corresponding data receiving channel so that each data receiving channel counts synchronous pulses according to the corresponding channel clock; the caching unit is configured to cache the count value sent by each data receiving channel; the calibration unit is configured to calibrate the frequency division coefficient of the corresponding data receiving channel according to the count value of each data receiving channel, so that the clock frequency division unit updates the channel clock of the corresponding data receiving channel according to the calibrated frequency division coefficient.

Description

Clock self-calibration circuit, data receiving system, controller and vehicle

Technical Field

The present application relates to the field of circuit technologies, and in particular, to a clock self-calibration circuit, a data receiving system, a controller, and a vehicle.

Background

The send (SINGLE EDGE Nibble Transmission, single sided half word transfer) protocol is used for high resolution sensor data transfer from the sensor to the electronic control unit. It is intended as a substitute for the lower resolution approach using a 10bit analog to digital converter and PWM (Pulse Width Modulation ) and as a low cost alternative to CAN (Controller Area Network, controller area network bus) or LIN (Local Interconnect Network ). With the continued development of automotive electronics, more and more sensors use the send protocol. Therefore, it is increasingly important for the electronic control unit to quickly and accurately receive and parse the data of these sensors.

There are two kinds of send receiving schemes in the related art, namely a digital-analog hybrid receiving analysis scheme and a pure digital receiving analysis scheme. The digital-analog mixed receiving analysis scheme is that the SENT signal is filtered and then becomes an analog signal, then an analog-digital converter is used for sampling to obtain a voltage value, and the voltage value is decoded. The pure digital receiving and analyzing schemes are two, one is that a special receiving module is used for receiving digital signals and carrying out hardware analysis, the other is that a General-Purpose Input/Output (General-Purpose Input/Output) module is used for receiving signals and carrying out protocol analysis by matching with a timer, however, the software expense of receiving the signals by the GPIO or the PWM module is higher, the accuracy of analysis cannot be ensured, the digital analyzing mode is often only analyzed by using fixed clock frequency, the precision requirement on the clock is higher, or an adjusting means is not automatic, software dynamic adjustment is needed, and the adjustment is too complex and the response is not timely when the number of receiving channels is too large.

Disclosure of Invention

The present invention aims to solve at least one of the technical problems in the related art to some extent. Therefore, a first object of the present invention is to provide a clock self-calibration circuit, which calibrates the frequency division coefficient of the corresponding data receiving channel according to the count value of the data receiving channel, so as to update the channel clock of the corresponding data receiving channel, so that the data receiving and decoding are more accurate, the accuracy requirement of the channel clock is relaxed, and the robustness is higher; and a plurality of data receiving channels share one clock self-calibration circuit, so that hardware resources can be saved, and the cost is reduced.

A second object of the present invention is to propose a data receiving system.

A third object of the present invention is to propose a controller.

A fourth object of the present invention is to propose a vehicle.

To achieve the above object, an embodiment according to a first aspect of the present invention provides a clock self-calibration circuit, including: the clock frequency division unit is suitable for being connected with at least one data receiving channel, and is configured to generate a channel clock of each data receiving channel according to a module clock and a frequency division coefficient corresponding to each data receiving channel, and send the channel clock of each data receiving channel to the corresponding data receiving channel so that each data receiving channel counts synchronous pulses according to the corresponding channel clock; the buffer unit is configured to buffer the count value sent by each data receiving channel, wherein each data receiving channel sends the count value to the buffer unit after counting the synchronous pulse and when the count value meets a preset count range; the calibration unit is configured to calibrate the frequency division coefficient of the corresponding data receiving channel according to the count value of each data receiving channel, so that the clock frequency division unit updates the channel clock of the corresponding data receiving channel according to the calibrated frequency division coefficient.

According to the clock self-calibration circuit, the clock self-calibration circuit comprises a clock frequency division unit, a buffer unit and a calibration unit, wherein the clock frequency division unit generates a channel clock of each data receiving channel according to a module clock and a frequency division coefficient corresponding to each data receiving channel, each data receiving channel counts synchronous pulses according to the corresponding channel clock, a standard count value of the synchronous pulses is a preset count value, and a certain margin is reserved for the preset count value in the related art, so that after the data receiving channels count the synchronous pulses, if the count value meets a preset range, the data receiving channels output count values to the buffer unit, the calibration unit calibrates the frequency division coefficient of the corresponding data receiving channels according to the count value of each data receiving channel, the clock frequency division unit updates the channel clock of the corresponding data receiving channel according to the calibrated frequency division coefficient, and the data receiving channels use the updated channel clock to receive the data after the synchronous pulses, so that the data receiving and decoding are more accurate, the accuracy requirement of the channel clock is relaxed, and the robustness is higher; and a plurality of data receiving channels share one clock self-calibration circuit, so that hardware resources can be saved, and the cost is reduced.

According to one embodiment of the invention, the calibration unit comprises: the first input end of the first multiplier is connected with the clock frequency division unit, the second input end of the first multiplier is suitable for inputting the count value of the corresponding data receiving channel, and the first multiplier is configured to multiply the count value of the corresponding data receiving channel with the frequency division coefficient of the corresponding data receiving channel to obtain a first product; the first input end of the second multiplier is connected with the output end of the first multiplier, the second input end of the second multiplier is suitable for inputting a preset multiplier factor, and the second multiplier is configured to multiply the first product with the preset multiplier factor to obtain a second product; the input end of the shifting module is connected with the output end of the second multiplier, the output end of the shifting module is connected with the clock frequency dividing unit, and the shifting module is configured to shift the second product rightward by a preset number of bits, generate calibrated frequency dividing coefficients of the corresponding data receiving channels and provide the calibrated frequency dividing coefficients of the corresponding data receiving channels to the clock frequency dividing unit.

According to one embodiment of the invention, the preset multiplier factor is calculated according to the following formula: f=round (2 ^M/56), where F is a preset multiplier factor and M is a preset number of bits.

According to an embodiment of the invention, the calibration unit is further configured to generate a calibration complete flag in case the calibration of the division coefficients of the respective data reception channels is completed.

According to an embodiment of the present invention, in the case where there is one data reception channel, the clock dividing unit includes: the frequency division coefficient control module is configured to take a preset frequency division coefficient as the frequency division coefficient of the data receiving channel under the condition of an initial state, and take the calibrated frequency division coefficient as the frequency division coefficient of the data receiving channel under the condition of receiving a calibration completion mark; and the clock frequency division module is suitable for being connected with the data receiving channel and is configured to generate a channel clock of the data receiving channel according to the module clock and the frequency division coefficient of the data receiving channel.

According to one embodiment of the present invention, the division factor control module includes: the first input end of the first selector is connected with the output end of the calibration unit, the second input end of the first selector is suitable for inputting a preset frequency division coefficient, and the first selector is configured to output the preset frequency division coefficient or the calibrated frequency division coefficient according to the first selection signal; the first D trigger is configured to output a preset frequency division coefficient under the condition that the preset completion mark is received, and output the calibrated frequency division coefficient under the condition that the calibration completion mark is received.

According to an embodiment of the present invention, in the case where there are a plurality of data reception channels, the calibration complete flag is used to characterize the number of the data reception channels for which the division coefficient calibration is completed, the clock division unit includes: the updating control module is configured to generate an updating enabling signal of the corresponding data receiving channel according to the calibration completion mark; the system comprises a plurality of frequency division coefficient control modules, a plurality of data receiving channels and a plurality of data transmission channels, wherein each frequency division coefficient control module is configured to take a preset frequency division coefficient of the corresponding data receiving channel as a frequency division coefficient of the corresponding data receiving channel under the condition of an initial state, and take the calibrated frequency division coefficient as the frequency division coefficient of the corresponding data receiving channel under the condition of receiving an update enabling signal of the corresponding data receiving channel; and each clock frequency division module is connected with one frequency division coefficient control module and is suitable for being connected with one data receiving channel, and each clock frequency division module is configured to generate a channel clock of the corresponding data receiving channel according to the module clock and the frequency division coefficient of the corresponding data receiving channel.

According to one embodiment of the present invention, the division factor control module includes: the first selector, the first input end of the first selector couples to output end of the calibration unit, the second input end of the first selector is suitable for inputting the preset frequency division coefficient of the corresponding data receiving channel, the first selector is configured to output the preset frequency division coefficient or frequency division coefficient after calibrating of the corresponding data receiving channel according to the first selection signal; the first D trigger is configured to output a preset frequency division coefficient of the corresponding data receiving channel when the preset completion flag of the corresponding data receiving channel is received, and output a calibrated frequency division coefficient of the corresponding data receiving channel when the update enabling signal of the corresponding data receiving channel is received.

According to one embodiment of the invention, the preset division factor is determined based on the module clock and the beat time.

According to an embodiment of the present invention, in the case that there is one data receiving channel, the buffer unit includes: and the data caching module is suitable for being connected with the data receiving channel and is configured to cache the count value sent by the data receiving channel.

According to one embodiment of the present invention, the clock self-calibration circuit further includes: the input end of the second D trigger is connected with the clock frequency division unit, the enabling end of the second D trigger is suitable for inputting and outputting an enabling signal, the output end of the second D trigger is connected with the calibration unit, and the second D trigger is configured to output the frequency division coefficient of the data receiving channel under the condition that the enabling signal is received; the input end of the third D trigger is connected with the data buffer module, the enabling end of the third D trigger is suitable for inputting an output enabling signal, the output end of the third D trigger is connected with the calibration unit, and the third D trigger is configured to output the count value of the data receiving channel under the condition that the output enabling signal is received.

According to an embodiment of the present invention, in the case that there are a plurality of data receiving channels, the buffer unit includes a plurality of data buffer modules, each data buffer module is adapted to be connected to one data receiving channel, and a space number of each data buffer module is consistent with a channel number of a corresponding data receiving channel, so as to receive the count value sent by the corresponding data receiving channel.

According to an embodiment of the invention, the buffering unit is further configured to generate a count valid flag bit in case that the at least one data buffering module receives the count value sent by the corresponding data receiving channel, wherein the count valid flag bit is used for characterizing a space number of the data buffering module that receives the count value sent by the corresponding data receiving channel.

According to one embodiment of the present invention, the clock self-calibration circuit further includes: and the data selection unit is configured to output the frequency division coefficient of the corresponding data receiving channel and the count value of the corresponding data receiving channel according to the count valid flag bit.

According to one embodiment of the present invention, a data selecting unit includes: the input end of the second selector is connected with the clock frequency division unit, and the second selector is configured to output frequency division coefficients of corresponding data receiving channels according to a second selection signal, wherein the second selection signal is output based on the counting valid flag bit; the input end of the second D trigger is connected with the output end of the second selector, the output end of the second D trigger is connected with the calibration unit, and the second D trigger is configured to output the frequency division coefficient of the corresponding data receiving channel under the condition of receiving the output enabling signal; the input end of the third selector is connected with each data buffer module, and the third selector is configured to output the count value of the corresponding data receiving channel according to the second selection signal; and the input end of the third D trigger is connected with the output end of the second selector, the output end of the third D trigger is connected with the calibration unit, and the third D trigger is configured to output the count value of the corresponding data receiving channel under the condition that the output enabling signal is received.

According to one embodiment of the invention, each data receiving channel is adapted to input a send signal comprising synchronization pulses.

To achieve the above object, an embodiment according to a second aspect of the present invention provides a data receiving system, including: at least one data receiving channel, each data receiving channel adapted to receive a SENT signal; the clock self-calibration circuit of any one of the preceding embodiments, the clock self-calibration circuit being coupled to each data reception channel, the clock self-calibration circuit being configured to provide a corresponding channel clock to each data reception channel such that each data reception channel receives the send signal according to the corresponding channel clock.

According to the data receiving system provided by the embodiment of the invention, the clock self-calibration circuit is adopted, the frequency division coefficient of the corresponding data receiving channel is calibrated according to the count value of the data receiving channel, so that the channel clock of the corresponding data receiving channel is updated, the data receiving and decoding are more accurate, the precision requirement of the channel clock is relaxed, and the robustness is higher; and a plurality of data receiving channels share one clock self-calibration circuit, so that hardware resources can be saved, and the cost is reduced.

To achieve the above object, an embodiment according to a third aspect of the present invention provides a controller including the aforementioned data receiving system.

According to the controller provided by the embodiment of the invention, by adopting the data receiving system, the frequency division coefficient of the corresponding data receiving channel is calibrated according to the count value of the data receiving channel, so that the channel clock of the corresponding data receiving channel is updated, the data receiving and decoding are more accurate, the precision requirement of the channel clock is relaxed, and the robustness is higher; and a plurality of data receiving channels share one clock self-calibration circuit, so that hardware resources can be saved, and the cost is reduced.

To achieve the above object, according to a fourth aspect of the present invention, there is provided a vehicle including the aforementioned controller.

According to the vehicle provided by the embodiment of the invention, the frequency division coefficient of the corresponding data receiving channel is calibrated according to the count value of the data receiving channel by adopting the controller so as to update the channel clock of the corresponding data receiving channel, so that the data receiving and decoding are more accurate, the precision requirement of the channel clock is relaxed, and the robustness is higher; and a plurality of data receiving channels share one clock self-calibration circuit, so that hardware resources can be saved, and the cost is reduced.

Additional aspects and advantages of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.

Drawings

Fig. 1 is a system diagram of a data receiving system according to one embodiment of the present invention;

FIG. 2 is a schematic diagram of a basic frame structure of a SENT signal according to one embodiment of the invention;

FIG. 3 is a schematic diagram of the structure of a calibration unit according to one embodiment of the invention;

Fig. 4 is a schematic diagram of a clock dividing unit when there is only one data receiving channel according to an embodiment of the present invention;

Fig. 5 is a schematic diagram of a clock dividing unit when there is only one data receiving channel according to another embodiment of the present invention;

Fig. 6 is a schematic diagram of a clock dividing unit when there are a plurality of data receiving channels according to an embodiment of the present invention;

Fig. 7 is a schematic diagram of a clock dividing unit when there are a plurality of data receiving channels according to another embodiment of the present invention;

FIG. 8 is a schematic diagram of a buffer unit when there is only one data receiving channel according to one embodiment of the present invention;

Fig. 9 is a schematic diagram of a structure of a buffer unit and a data selection unit when there are a plurality of data reception channels according to an embodiment of the present invention;

FIG. 10 is a system schematic diagram of a controller according to one embodiment of the invention;

FIG. 11 is a system schematic of a vehicle according to one embodiment of the invention.

Detailed Description

Embodiments of the present invention are described in detail below, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to like or similar elements or elements having like or similar functions throughout. The embodiments described below by referring to the drawings are illustrative and intended to explain the present invention and should not be construed as limiting the invention.

The following describes a clock self-calibration circuit, a data receiving system, a controller, and a vehicle according to an embodiment of the present invention with reference to the accompanying drawings.

Fig. 1 is a system diagram of a data receiving system according to an embodiment of the present invention. As shown in fig. 1, the clock self-calibration circuit 100 includes: a clock dividing unit 10, a buffer unit 20 and a calibration unit 30.

Wherein the clock dividing unit 10 is adapted to connect at least one data receiving channel 200, the clock dividing unit 10 is configured to generate a channel clock of each data receiving channel 200 according to the module clock and a frequency division coefficient corresponding to each data receiving channel 200, and send the channel clock of each data receiving channel 200 to the corresponding data receiving channel 200, so that each data receiving channel 200 counts the synchronization pulses according to the corresponding channel clock; the buffer unit 20 is configured to buffer the count value sent by each data receiving channel 200, wherein each data receiving channel 200 sends the count value to the buffer unit 20 after counting the synchronization pulse and when the count value meets a preset count range; the calibration unit 30 is configured to calibrate the division coefficient of the corresponding data reception channel 200 according to the count value of each data reception channel 200, so that the clock division unit 10 updates the channel clock of the corresponding data reception channel 200 according to the calibrated division coefficient.

Specifically, the module clock is a high-frequency clock, the module clock may be a system clock of the controller, the clock frequency dividing unit 10 divides the frequency of the module clock according to a frequency division coefficient corresponding to each data receiving channel 200, so as to obtain a channel clock of each data receiving channel 200, then the channel clock of each data receiving channel 200 is sent to the corresponding data receiving channel 200, each data receiving channel 200 counts the synchronization pulse according to the corresponding channel clock, the standard count value of the synchronization pulse is a preset count value, and when the count value of the synchronization pulse is the preset count value, the data stream behind the synchronization pulse can be correctly received. In the related art, a certain margin is reserved for the preset count value, so after the data receiving channel 200 finishes counting the synchronization pulse, if the count value meets the preset count range, the data receiving channel 200 in the preset count range considers that the count value is valid, and can start receiving the data stream after the synchronization pulse. However, the count value cannot meet the preset count value due to the reasons of signal edge detection, external condition change and the like, so that the reception of the data stream is affected, and therefore, the channel clock needs to be corrected, so that the data stream at the back side can be normally received. After the data receiving channels 200 finish counting the synchronization pulses, if the count value meets the preset range, the data receiving channels 200 output the count value to the buffer unit 20, the calibration unit 30 corrects the count value of each data receiving channel 200 to the preset count value by adjusting the frequency division coefficient of each data receiving channel 200, then the clock frequency division unit 10 generates the channel clock of the corresponding data receiving channel 200 by using the calibrated frequency division coefficient and the module clock, and then sends the new channel clock to the corresponding data receiving channel 200, and if the corresponding data receiving channel 200 counts the synchronization pulses according to the new channel clock, the count value is closer to the preset count value, so that the corresponding data receiving channel 200 can accurately receive the data stream after the synchronization clock according to the new channel clock. In addition, the clock calibration circuit is connected to the plurality of data receiving channels 200 at the same time, so that the channel clocks of the plurality of data receiving channels 200 can be adjusted in time.

In some embodiments, each data receiving channel 200 is adapted to input a SENT signal, which includes a synchronization pulse.

Specifically, as shown in fig. 2, the send signal is clocked by a unit of beats, and the send signal includes a synchronization pulse, a status and communication pulse, a data stream, a check pulse, and an optional pause pulse, where the data stream includes 6 data halfwords, and the number of the data halfwords can be set according to practical situations, and is at least 1. The SENT signal corresponds to the time interval of the adjacent falling edge with the data value, so that the key of analyzing the SENT signal is that the time interval is detected, and the number of beats is calculated. The theoretical period of the synchronization pulse in the send signal is 56 standard beats, that is, the preset count value is 56, and an error of +/-20% is allowed in the period length in actual processing, so that the maximum value of the preset count range is 56×120%, and the minimum value of the preset count range is 56×80%. The status and communication pulses are 12-27 beats, the data stream is 12-162 beats, the check pulse is 12-27 beats, and the pause pulse is 12-768 beats, so except before the pause pulse, the SENT signal is between 154-270 beats.

The period of the channel clock is the same as the period of the beat, and when the count value of the synchronous pulse is 56, the channel clock is accurate at the moment, and the data stream can be normally received. In practical applications, the count value of the synchronization pulse may deviate due to the signal edge detection or the change of external conditions such as temperature, and the channel clock is inaccurate at this time, and if data is received according to the channel clock at this time, there may be an error in receiving the data stream, so the period of the channel clock needs to be adjusted according to the count value of the synchronization pulse by the data receiving channel 200, so that the data receiving channel 200 can correctly receive the data.

For example, if the count value of the data receiving channel 200 is 54, 54 is within the preset range, the calibration unit 30 adjusts the frequency division coefficient of the data receiving channel 200 so that the count value of the data receiving channel 200 becomes 56, and the clock frequency division unit 10 generates a new channel clock according to the calibrated frequency division coefficient, that is, if the data receiving channel 200 counts the synchronization pulse according to the new channel clock, the count value is 56, and therefore, the data receiving channel 200 can accurately receive the data stream after the synchronization pulse according to the new channel clock.

In the above embodiment, the frequency division coefficient of the corresponding data receiving channel is calibrated according to the count value of the data receiving channel, so as to update the channel clock of the corresponding data receiving channel, and the data receiving channel can accurately receive data according to the new channel clock, so that the decoding is more accurate, the precision requirement of the channel clock is relaxed, and the robustness is higher; and a plurality of data receiving channels share one clock self-calibration circuit, so that hardware resources can be saved, and the cost is reduced.

In some embodiments, as shown in fig. 3, the calibration unit 30 includes: the first multiplier 31, the second multiplier 32 and the shift module 33, wherein a first input end of the first multiplier 31 is connected with the clock frequency division unit 10, a second input end of the first multiplier 31 is suitable for inputting the count value of the corresponding data receiving channel 200, and the first multiplier 31 is configured to multiply the count value of the corresponding data receiving channel 200 with the frequency division coefficient of the corresponding data receiving channel 200 to obtain a first product; a first input end of the second multiplier 32 is connected with an output end of the first multiplier 31, a second input end of the second multiplier 32 is suitable for inputting a preset multiplier factor, and the second multiplier 32 is configured to multiply the first product with the preset multiplier factor to obtain a second product; an input of the shift module 33 is connected to an output of the second multiplier 32, an output of the shift module 33 is connected to the clock dividing unit 10, and the shift module 33 is configured to shift the second product by a preset number of bits to the right, generate calibrated division coefficients of the corresponding data receiving channels 200, and provide the calibrated division coefficients of the corresponding data receiving channels 200 to the clock dividing unit 10.

Specifically, the first multiplier 31 multiplies the count value and the division coefficient of the same data receiving channel 200 to obtain a first product, the second multiplier 32 multiplies the first product by a fixed preset multiplier factor to obtain a second product, the shift module 33 shifts the second product rightward by a preset number of bits to generate a calibrated division coefficient, and provides the calibrated division coefficient to the clock dividing unit 10, and the clock dividing unit 10 generates a new channel clock according to the calibrated division coefficient and sends the new channel clock to the corresponding data receiving channel 200.

It should be noted that, the preset number of bits may be a positive integer greater than or equal to 6, the larger the preset number of bits is, the smaller the error after calibration is, but the larger the preset number of bits is, the more hardware resources are occupied, so in practical application, the appropriate preset number of bits needs to be selected according to the requirement of actual precision.

In the above embodiment, the first multiplier, the second multiplier and the shift module calibrate the frequency division coefficient to obtain the calibrated frequency division coefficient, and provide the calibrated frequency division coefficient to the clock frequency division unit to update the channel clock of the data receiving channel.

Further, in some embodiments, the preset multiplier factor is calculated according to the following formula:

F=ROUND（2^M/56）

wherein F is a preset multiplier factor, and M is a preset number of bits.

It will be appreciated that the preset multiplier factor F is a value obtained by rounding 2 ^M/56. 56 is the count of sync pulses.

In some embodiments, the calibration unit 30 is further configured to generate a calibration complete flag in case the calibration of the division coefficients of the respective data reception channels 200 is completed.

That is, the calibration unit 30 sets the calibration completion flag of the data reception channel 200 at the same time when the calibration of the frequency division coefficient of the corresponding data reception channel 200 is completed according to the count value of the corresponding data reception channel 200, so that the clock dividing unit 10 can update the channel clock of the corresponding data reception channel 200 according to the calibration completion flag.

In some embodiments, as shown in fig. 4, in the case where there is one of the data reception channels 200, the clock dividing unit 10 includes: a frequency division coefficient control module 11 and a clock frequency division module 12, wherein the frequency division coefficient control module 11 is configured to take a preset frequency division coefficient as the frequency division coefficient of the data receiving channel 200 in the case of an initial state, and take the calibrated frequency division coefficient as the frequency division coefficient of the data receiving channel 200 in the case of receiving a calibration completion flag; the clock division module 12 is adapted to be connected to the data reception channel 200, the clock division module 12 being configured to generate a channel clock of the data reception channel 200 from the module clock and a division factor of the data reception channel 200.

Specifically, in the case where there is only one data reception channel 200, after the calibration unit 30 completes the calibration of the frequency division coefficient of the data reception channel 200, a calibration complete flag is generated. The frequency division coefficient control module 11 takes the preset frequency division coefficient as the frequency division coefficient of the data receiving channel 200 in the initial state, that is, the clock frequency division module 12 divides the module clock according to the preset frequency division coefficient when the frequency division coefficient is not calibrated yet. After the calibration unit 30 performs the first calibration on the frequency division coefficient, when the frequency division coefficient control module 11 receives the calibration completion flag, the frequency division coefficient control module 11 outputs the calibrated frequency division coefficient, the clock frequency division module 12 divides the frequency of the module clock according to the calibrated frequency division coefficient, and sends the new channel clock to the data receiving channel 200, and the data receiving channel 200 receives the data stream after the synchronization pulse according to the new channel clock. Then, the data receiving channel 200 counts the synchronization pulses of the data inputted for the second time according to the new channel clock, the calibration unit 30 performs the second calibration on the frequency division coefficient according to the count value, and generates a calibration completion flag, the frequency division coefficient control module 11 outputs the frequency division coefficient obtained by the second calibration, the clock frequency division module 12 generates the new channel clock according to the frequency division coefficient obtained by the second calibration, and the data receiving channel 200 receives the data inputted for the second time according to the new channel clock.

In some embodiments, as shown in fig. 4, the division coefficient control module 11 includes: a first selector 111 and a first D flip-flop 112, wherein a first input terminal of the first selector 111 is connected to an output terminal of the calibration unit 30, a second input terminal of the first selector 111 is adapted to input a preset division factor, and the first selector 111 is configured to output the preset division factor or the calibrated division factor according to the first selection signal; the input end of the first D flip-flop 112 is connected to the output end of the first selector 111, the enabling end of the first D flip-flop 112 is connected to the output end of the calibration unit 30 and is adapted to input a preset completion flag, and the first D flip-flop 112 is configured to output a preset division factor in case of receiving the preset completion flag and to output the calibrated division factor in case of receiving the calibration completion flag.

Specifically, the first input end of the first selector 111 is connected to the output end of the calibration unit 30, and is adapted to input the calibrated frequency division coefficient, the second input end of the first selector 111 is adapted to input the preset frequency division coefficient, the first selector 111 outputs the preset frequency division coefficient in an initial state according to the first selection signal, and the calibrated frequency division coefficient is output when the calibration of the frequency division coefficient is started. The input end of the first D flip-flop 112 is connected to the output end of the first selector 111, and the first D flip-flop 112 outputs the preset frequency division coefficient when receiving the preset frequency division coefficient and the preset completion flag, and outputs the calibrated frequency division coefficient when receiving the calibration completion flag and the calibrated frequency division coefficient.

In an alternative embodiment, after the first selector 111 is disposed on the first D flip-flop 112, as shown in fig. 5, an input terminal of the first D flip-flop 112 is connected to an output terminal of the calibration unit 30, an enable terminal of the first D flip-flop 112 is connected to an output terminal of the calibration unit 30, the first D flip-flop 112 is configured to output the calibrated division factor when receiving the calibration completion flag, a first input terminal of the first selector 111 is connected to an output terminal of the first D flip-flop 112, a second input terminal of the first selector 111 is adapted to input the preset division factor, and the first selector 111 is configured to output the preset division factor or the calibrated division factor according to the first selection signal.

Specifically, the input end of the first D flip-flop 112 is adapted to input the calibrated frequency division coefficient, and output the calibrated frequency division coefficient after receiving the calibration completion flag, so that the first D flip-flop 112 does not output in the initial state, and the first selector 111 outputs the preset frequency division coefficient in the initial state according to the first selection signal. After the calibration is completed, the first D flip-flop 112 outputs the calibrated division coefficient upon receiving the calibration completion flag, and the first selector 111 outputs the calibrated division coefficient according to the first selection signal. In some embodiments, as shown in fig. 6, in the case that there are a plurality of data receiving channels 200, the calibration complete flag is used to characterize the number of the data receiving channels 200 that complete the division coefficient calibration, and the clock division unit 10 includes: an update control module 13, a plurality of division coefficient control modules 11, and a plurality of clock division modules 12, wherein the update control module 13 is configured to generate an update enable signal of the corresponding data reception channel 200 according to the calibration complete flag; each frequency division coefficient control module 11 is configured to, in the case of an initial state, set a preset frequency division coefficient of the corresponding data reception channel 200 as the frequency division coefficient of the corresponding data reception channel 200, and in the case of receiving an update enable signal of the corresponding data reception channel 200, set the calibrated frequency division coefficient as the frequency division coefficient of the corresponding data reception channel 200; each clock dividing module 12 is connected to one of the division factor control modules 11 and is adapted to be connected to one of the data receiving channels 200, each clock dividing module 12 being configured to generate a channel clock of the corresponding data receiving channel 200 based on the module clock and the division factor of the corresponding data receiving channel 200.

Specifically, when there are a plurality of data reception channels 200, the calibration complete flag is used to characterize the number of the data reception channels 200 for which the division coefficient calibration is completed, for example, if there are 4 data reception channels 200, when the division coefficient calibration is not performed, the calibration complete flag is 0000, and if the division coefficient calibration is completed by the third data reception channel 200, the calibration complete flag is 0010. Each clock dividing module 12 is connected to one dividing factor control module 11 and one data receiving channel 200, and the number of each clock dividing module 12 is the same as the number of the corresponding data receiving channel 200, and the number of each dividing factor control module 11 is the same as the number of the corresponding clock dividing module 12. For example, if the third data receiving channel 200 is the third data receiving channel, the clock dividing module 12 connected to the third data receiving channel is the third clock dividing module, and the frequency dividing coefficient control module 11 connected to the third clock dividing module is the third frequency dividing coefficient control module. The update control module 13 generates an update enable signal of the corresponding data receiving channel 200 according to the calibration completion flag, and provides the update enable signal to the frequency division coefficient control module 11 corresponding to the corresponding data receiving channel 200, and the frequency division coefficient module outputs the calibrated frequency division coefficient according to the update enable signal, so that the clock frequency division module 12 can generate a new channel clock according to the calibrated frequency division coefficient module.

Taking the calibration completion flag as 0010 as an example, at this time, the frequency division coefficient of the third data receiving channel completes calibration, the update control module 13 generates a third update enable signal of the third data receiving channel according to the calibration completion flag, then sends the third update enable signal to the third frequency division coefficient control module, and when receiving the third update enable signal, the third frequency division coefficient control module outputs the calibrated frequency division coefficient, sends the calibrated frequency division coefficient to the third clock frequency division module, and the third clock frequency division module generates a new channel clock according to the calibrated frequency division coefficient and sends the new channel clock to the third data receiving channel.

It should be noted that, the preset frequency division coefficient of each frequency division coefficient control module 11 is determined according to the corresponding data receiving channel 200, the first frequency division coefficient control module corresponding to the first data receiving channel is adapted to input the first preset frequency division coefficient, the second frequency division coefficient control module corresponding to the second data receiving channel is adapted to input the second preset frequency division coefficient, and the nth frequency division coefficient control module corresponding to the nth data receiving channel is adapted to input the nth preset frequency division coefficient, so that the preset frequency division coefficients of each frequency division coefficient control module 11 may be the same or different.

In some embodiments, as shown in fig. 6, the division coefficient control module 11 includes: a first selector 111 and a first D flip-flop 112, wherein a first input terminal of the first selector 111 is connected to an output terminal of the calibration unit 30, a second input terminal of the first selector 111 is adapted to input a preset division factor of the corresponding data reception channel 200, and the first selector 111 is configured to output the preset division factor of the corresponding data reception channel 200 or the calibrated division factor according to the first selection signal; the input terminal of the first D flip-flop 112 is connected to the output terminal of the first selector 111, the enable terminal of the first D flip-flop 112 is connected to the update control module 13 and is adapted to input a preset completion flag of the corresponding data reception channel 200, and the first D flip-flop 112 is configured to output the preset division factor of the corresponding data reception channel 200 upon receiving the preset completion flag of the corresponding data reception channel 200, and to output the calibrated division factor of the corresponding data reception channel 200 upon receiving the update enable signal of the corresponding data reception channel 200.

It will be appreciated that when there are a plurality of time division factor control modules 11 in the data receiving channel 200 and only one time division factor control module 11 in the data receiving channel 200, each of the time division factor control modules 11 includes the first selector 111 and the first D flip-flop 112, but the enabling end of the first D flip-flop 112 is connected to the update control module 13 at this time, so as to receive the update enable signal generated by the update control module 13, and is adapted to input a corresponding preset completion flag. For example, the first D flip-flop 112 of the first frequency division coefficient control module is adapted to input a first preset completion flag and a first update enable signal, the first D flip-flop 112 of the second frequency division coefficient control module is adapted to input a second preset completion flag and a second update enable signal, and the first D flip-flop 112 of the nth frequency division coefficient control module is adapted to input an nth preset completion flag and an nth update enable signal.

In an alternative embodiment, after the first selector 111 is disposed on the first D flip-flop 112, as shown in fig. 7, an input terminal of the first D flip-flop 112 is connected to an output terminal of the calibration unit 30, an enable terminal of the first D flip-flop 112 is connected to an output terminal of the update control module 13, the first D flip-flop 112 is configured to output the calibrated division factor of the corresponding data receiving channel 200 when receiving the update enable signal of the corresponding data receiving channel 200, a first input terminal of the first selector 111 is connected to an output terminal of the first D flip-flop 112, a second input terminal of the first selector 111 is adapted to input the preset division factor of the corresponding data receiving channel 200, and the first selector 111 is configured to output the preset division factor of the corresponding data receiving channel 200 or the calibrated division factor according to the first selection signal.

It should be understood that, when there are a plurality of data receiving channels 200, the first selector 111 may be disposed after the first D flip-flop 112, where the input end of the first D flip-flop 112 is adapted to input the calibrated division factor, and output the calibrated division factor of the corresponding data receiving channel 200 after receiving the update enable signal of the corresponding data receiving channel 200, so that, in the initial state, the first D flip-flop 112 does not output, and the first selector 111 outputs the preset division factor of the corresponding data receiving channel 200 in the initial state according to the first selection signal. After the calibration is completed, the first D flip-flop 112 outputs the calibrated division coefficient of the corresponding data reception channel 200 upon receiving the update enable signal of the corresponding data reception channel 200, and the first selector 111 outputs the calibrated division coefficient of the corresponding data reception channel 200 according to the first selection signal.

It should be noted that, the preset completion flag, the calibration completion flag, and the update enable signal need to be cleared after the channel clock of the corresponding data receiving channel 200 is updated, so as to avoid the occurrence of a situation that updating of one data receiving channel 200 is repeated.

In some embodiments, the preset division factor is determined based on the module clock and the beat time.

Specifically, the preset frequency division coefficient is configured by a register, and the period of the channel clock generated by the clock frequency division module 12 according to the preset frequency division coefficient coincides with the beat period. In practical applications, the beat time is between 3us and 90us, and the frequency division coefficient is calculated according to the beat time and the period of the module clock. It should be noted that, the takt time of each device is different, and the preset division coefficient needs to be determined according to the takt time of each device.

In some embodiments, as shown in fig. 8, in the case that there is one data receiving channel 200, the buffering unit 20 includes: the data buffering module 21, the data buffering module 21 is adapted to be connected to the data receiving channel 200, and the data buffering module 21 is configured to buffer the count value sent by the data receiving channel 200.

It will be appreciated that in the case where there is only one data receiving channel 200, there is only one data buffering module 21, and the data buffering module 21 buffers the count value of the data receiving channel 200.

In some embodiments, as shown in fig. 8, the clock self-calibration circuit 100 further includes: a second D flip-flop 41 and a third D flip-flop 42, wherein an input terminal of the second D flip-flop 41 is connected to the clock frequency dividing unit 10, an enable terminal of the second D flip-flop 41 is adapted to input an output enable signal, an output terminal of the second D flip-flop 41 is connected to the calibration unit 30, and the second D flip-flop 41 is configured to output a frequency division coefficient of the data receiving channel 200 upon receiving the output enable signal; an input terminal of the third D flip-flop 42 is connected to the data buffer module 21, an enable terminal of the third D flip-flop 42 is adapted to input an output enable signal, an output terminal of the third D flip-flop 42 is connected to the calibration unit 30, and the third D flip-flop 42 is configured to output the count value of the data receiving channel 200 upon receiving the output enable signal.

Specifically, the clock self-calibration circuit 100 further includes a second D flip-flop 41 and a third D flip-flop 42, the second D flip-flop 41 is connected to the clock frequency division module 12 of the clock frequency division unit 10, the clock frequency division module 12 sends the frequency division coefficient to the second D flip-flop 41, the third D flip-flop 42 is connected to the data buffer channel, the second D flip-flop 41 and the third D flip-flop 42 output the frequency division coefficient and the count value of the data receiving channel 200 to the calibration unit 30 when receiving the output enable signal, and then the calibration unit 30 performs calibration.

In some embodiments, as shown in fig. 9, in the case that there are a plurality of data receiving channels 200, the buffer unit 20 includes a plurality of data buffer modules 21, each data buffer module 21 is adapted to be connected to one data receiving channel 200, and the space number of each data buffer module 21 is consistent with the channel number of the corresponding data receiving channel 200 to receive the count value sent by the corresponding data receiving channel 200.

Specifically, in the case where there are a plurality of data reception channels 200, there are a plurality of data buffer modules 21, the number of data buffer modules 21 is the same as the number of data reception channels 200, and the spatial number of each data buffer module 21 coincides with the channel number of the corresponding data reception channel 200. For example, the spatial number of the data buffer module 21 corresponding to the third data receiving channel is the third data buffer module.

The clock signal inputs of the first D flip-flop 112, the second D flip-flop 41, and the third D flip-flop 42 are all adapted to input the module clock.

In some embodiments, the buffering unit 20 is further configured to generate a count valid flag bit in case that at least one data buffering module 21 receives the count value transmitted by the corresponding data receiving channel 200, wherein the count valid flag bit is used to characterize the spatial number of the data buffering module 21 that receives the count value transmitted by the corresponding data receiving channel 200.

Specifically, assuming that the second data receiving channel and the fourth data receiving channel respectively transmit count values to the second data caching module and the fourth data caching module, the caching unit 20 starts the count valid flag positions corresponding to the second data caching module and the fourth data caching module.

For example, when the count value is not received by the plurality of data buffer modules 21, the count valid flag bit is 0000, and when the count value is received by the second data buffer module and the fourth data buffer module, the count valid flag bit is 0101.

It should be noted that, the encoding mode of the count valid flag bit and the calibration complete flag is not limited to binary codes, but may be single hot codes or gray codes, and is not limited in this particular case.

In some embodiments, as shown in fig. 9, the clock self-calibration circuit 100 further includes: and a data selecting unit 40, the data selecting unit 40 being configured to output the frequency division coefficient of the corresponding data receiving channel 200 and the count value of the corresponding data receiving channel 200 according to the count valid flag bit.

Specifically, the calibration unit 30 can calibrate the frequency division coefficient of only one data reception channel 200 at a time, and therefore, the data selection unit 40 outputs the frequency division coefficient of the corresponding data reception channel 200 and the count value of the corresponding data reception channel 200 according to the count valid flag bit.

Taking the example that the second data receiving channel and the fourth data receiving channel send count values to the second data buffer module and the fourth data buffer module respectively, the count valid flag bit is 0101, the data selecting unit 40 outputs the count value and the frequency division coefficient of the second data receiving channel according to the count valid flag bit, the calibration unit 30 calibrates the frequency division coefficient of the second data receiving channel, and then generates a calibration completion flag. Then the data selecting unit 40 outputs the count value and the frequency division coefficient of the fourth data reception channel, and the calibration unit 30 calibrates the frequency division coefficient of the fourth data reception channel, and then generates a calibration complete flag.

It should be noted that, after the frequency division coefficients of the corresponding data receiving channels 200 are calibrated, the count valid flag bit corresponding to the corresponding data receiving channel 200 needs to be cleared.

In some embodiments, as shown in fig. 9, the data selection unit 40 includes: a second selector 43, a second D flip-flop 41, a third selector 44, and a third D flip-flop 42, wherein an input terminal of the second selector 43 is connected to the clock dividing unit 10, and the second selector 43 is configured to output a division coefficient of the corresponding data receiving channel 200 according to a second selection signal, wherein the second selection signal is output based on the count valid flag; an input terminal of the second D flip-flop 41 is connected to an output terminal of the second selector 43, an output terminal of the second D flip-flop 41 is connected to the calibration unit 30, and the second D flip-flop 41 is configured to output the division factor of the corresponding data reception channel 200 upon receiving the output enable signal; an input terminal of the third selector 44 is connected to each data buffer module 21, and the third selector 44 is configured to output the count value of the corresponding data receiving channel 200 according to the second selection signal; an input of the third D flip-flop 42 is connected to an output of the second selector 43, an output of the third D flip-flop 42 is connected to the calibration unit 30, and the third D flip-flop 42 is configured to output the count value of the corresponding data reception channel 200 upon receiving the output enable signal.

Specifically, when the plurality of count valid flag bits are valid, the second selection signal may sequentially output the count value and the division coefficient generation of the data reception channel 200 according to the count valid flag bits and the manner of polling from small to large. Assuming that the second data buffer module and the fourth data buffer module receive the count values, the second selection signal controls the second selector 43 to output the frequency division coefficient of the second data receiving channel and controls the third selector 44 to output the count value of the second data buffer module, and then the second selection signal controls the second selector 43 to output the frequency division coefficient of the fourth data receiving channel and controls the third selector 44 to output the count value of the fourth data buffer module.

The second selection signal may also be generated by sequentially outputting the count value and the division coefficient of the data reception channel 200 according to the count valid flag bit and the odd-before-even manner. Assuming that the second data buffer module and the third data buffer module receive the count values, the second selection signal controls the second selector 43 to output the frequency division coefficient of the third data receiving channel and controls the third selector 44 to output the count value of the third data buffer module, and then the second selection signal controls the second selector 43 to output the frequency division coefficient of the second data receiving channel and controls the third selector 44 to output the count value of the second data buffer module.

The control method of the data selecting unit 40 is not limited to the small-to-large polling method and the odd-before-even method described above, but may be other methods, such as the even-before-odd method, and the specific method is not limited thereto.

In an alternative embodiment, in a case that there are a plurality of data receiving channels 200, and the plurality of data receiving channels 200 sequentially send corresponding count values to the buffer unit 20, the buffer unit 20 includes a data buffer module 21, and the data buffer module 21 is adapted to connect the plurality of data receiving channels 200 to receive the count values sent by the plurality of data receiving channels 200. Because the count values of the plurality of data reception channels 200 are not generated at the same time, there is a relationship, the data buffer module 21 may buffer the count value transmitted from the first data reception channel 200 that completes the count, and then output the buffered count value. After the data buffer module 21 sends the count value sent by the first completed count data receiving channel 200, the data buffer module 21 may buffer the count value sent by the second completed count data receiving channel 200, so only one data buffer module 21 is needed at this time, thereby reducing the occupation of the memory of the buffer unit 20.

Further, if a part of the data receiving channels 200 sequentially transmit the count value, another part of the data receiving channels 200 simultaneously transmit the count value, and the number of the data buffer modules 21 is set according to the number of the data receiving channels 200 simultaneously transmitting the count value.

For example, if there are four data receiving channels 200, the first data receiving channel and the third data receiving channel send count values simultaneously, the second data receiving channel and the fourth data receiving channel send count values simultaneously, and the first data receiving channel and the third data receiving channel send count values earlier than the second data receiving channel and the fourth data receiving channel, at this time, the buffer unit 20 may only set 2 data buffer modules 21, respectively, the first data buffer module buffers the count values sent by the first data receiving channel first, then buffers the count values sent by the second data receiving channel, and the second data buffer module buffers the count values sent by the third data receiving channel first, and then buffers the count values sent by the fourth data receiving channel.

It should be noted that, at this time, the buffer unit 20 also needs to generate the count valid flag bit, and if there is only one data buffer module 21, the data selecting unit 40 does not need to set the third selector 44, and the second selection signal is determined according to the count valid flag bit. If there are a plurality of data buffer modules 21, the data selecting unit 40 also needs to set a third selector 44, and the second selection signal is determined according to the count valid flag bit and the control manner mentioned in the foregoing.

In summary, the clock self-calibration circuit according to the embodiment of the invention includes a clock frequency division unit, a buffer unit and a calibration unit, where the clock frequency division unit generates a channel clock of each data receiving channel according to a module clock and a frequency division coefficient corresponding to each data receiving channel, each data receiving channel counts a synchronization pulse according to the corresponding channel clock, a standard count value of the synchronization pulse is a preset count value, and in the related art, a certain margin is reserved for the preset count value, so after the data receiving channel counts the synchronization pulse, if the count value meets a preset range, the data receiving channel outputs the count value to the buffer unit, the calibration unit calibrates the frequency division coefficient of the corresponding data receiving channel according to the count value of each data receiving channel, the clock frequency division unit updates the channel clock of the corresponding data receiving channel according to the calibrated frequency division coefficient, and the data receiving channel uses the updated channel clock to receive the data after the synchronization pulse, thereby making the data receiving and decoding more accurate, and widening the accuracy requirement of the channel clock, and having higher robustness. And a plurality of data receiving channels share one clock self-calibration circuit, so that hardware resources can be saved, and the cost is reduced.

Corresponding to the above embodiment, the embodiment of the invention also provides a data receiving system. As shown in fig. 1, the data receiving system includes: at least one data receiving channel 200 and the clock self-calibration circuit 100 of any of the preceding embodiments, wherein each data receiving channel 200 is adapted to receive a send signal; a clock self-calibration circuit 100 is coupled to each data reception channel 200, the clock self-calibration circuit 100 being configured to provide each data reception channel 200 with a corresponding channel clock so that each data reception channel 200 receives the send signal according to the corresponding channel clock.

Corresponding to the above embodiment, the embodiment of the invention also provides a controller. As shown in fig. 10, the controller 400 includes the aforementioned data receiving system 300.

It should be noted that, the controller of the present embodiment may be an electronic control unit in a vehicle.

Corresponding to the above embodiment, the embodiment of the invention also provides a vehicle. As shown in fig. 11, a vehicle 500 includes the aforementioned controller 400.

It is to be understood that portions of the present invention may be implemented in hardware, software, firmware, or a combination thereof. In the above-described embodiments, the various steps or methods may be implemented in software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, may be implemented using any one or combination of the following techniques, as is well known in the art: discrete logic circuits having logic gates for implementing logic functions on data signals, application specific integrated circuits having suitable combinational logic gates, programmable Gate Arrays (PGAs), field Programmable Gate Arrays (FPGAs), and the like.

In the description of the present specification, a description referring to terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiments or examples. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

Furthermore, the terms "first," "second," and the like, as used in embodiments of the present invention, are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or as implying any particular number of features in the present embodiment. Thus, a feature of an embodiment of the invention that is defined by terms such as "first," "second," etc., may explicitly or implicitly indicate that at least one such feature is included in the embodiment. In the description of the present invention, the word "plurality" means at least two or more, for example, two, three, four, etc., unless explicitly defined otherwise in the embodiments.

In the present invention, unless explicitly stated or limited otherwise in the examples, the terms "mounted," "connected," and "fixed" as used in the examples should be interpreted broadly, e.g., the connection may be a fixed connection, may be a removable connection, or may be integral, and it may be understood that the connection may also be a mechanical connection, an electrical connection, etc.; of course, it may be directly connected, or indirectly connected through an intermediate medium, or may be in communication with each other, or in interaction with each other. The specific meaning of the above terms in the present invention can be understood by those of ordinary skill in the art according to specific embodiments.

While embodiments of the present invention have been shown and described above, it will be understood that the above embodiments are illustrative and not to be construed as limiting the invention, and that variations, modifications, alternatives and variations may be made to the above embodiments by one of ordinary skill in the art within the scope of the invention.

Claims

1. A clock self-calibration circuit, comprising: the clock frequency dividing unit, the buffer memory unit and the calibration unit, wherein,

The clock frequency dividing unit is suitable for being connected with at least one data receiving channel, and is configured to generate a channel clock of each data receiving channel according to a module clock and a frequency division coefficient corresponding to each data receiving channel, and send the channel clock of each data receiving channel to the corresponding data receiving channel so that each data receiving channel counts synchronous pulses according to the corresponding channel clock;

The buffer unit is configured to buffer the count value sent by each data receiving channel, wherein each data receiving channel sends the count value to the buffer unit after counting the synchronous pulse and when the count value meets a preset count range;

the calibration unit is configured to calibrate the frequency division coefficient of the corresponding data receiving channel according to the count value of each data receiving channel, so that the clock frequency division unit updates the channel clock of the corresponding data receiving channel according to the calibrated frequency division coefficient;

The calibration unit includes:

The first input end of the first multiplier is connected with the clock frequency dividing unit, the second input end of the first multiplier is suitable for inputting the count value of the corresponding data receiving channel, and the first multiplier is configured to multiply the count value of the corresponding data receiving channel with the frequency dividing coefficient of the corresponding data receiving channel to obtain a first product;

The first input end of the second multiplier is connected with the output end of the first multiplier, the second input end of the second multiplier is suitable for inputting a preset multiplier factor, and the second multiplier is configured to multiply the first product with the preset multiplier factor to obtain a second product;

the input end of the shifting module is connected with the output end of the second multiplier, the output end of the shifting module is connected with the clock frequency dividing unit, and the shifting module is configured to shift the second product rightward by a preset number of bits, generate calibrated frequency dividing coefficients of corresponding data receiving channels, and provide the calibrated frequency dividing coefficients of the corresponding data receiving channels to the clock frequency dividing unit.

2. The clock self-calibration circuit of claim 1, wherein the preset multiplier factor is calculated according to the following equation:

F=ROUND（2^M/56）

Wherein F is a preset multiplier factor, and M is the preset number of bits.

3. The clock self-calibration circuit of claim 1, wherein the calibration unit is further configured to generate a calibration complete flag if calibration of the division coefficients of the respective data reception channels is complete.

4. A clock self-calibration circuit according to claim 3, wherein in the case where there is one of the data receiving channels, the clock dividing unit comprises:

The frequency division coefficient control module is configured to take a preset frequency division coefficient as the frequency division coefficient of the data receiving channel under the condition of an initial state, and take the calibrated frequency division coefficient as the frequency division coefficient of the data receiving channel under the condition that the calibration completion mark is received;

And the clock frequency division module is suitable for being connected with the data receiving channel and is configured to generate a channel clock of the data receiving channel according to the module clock and the frequency division coefficient of the data receiving channel.

5. The clock self-calibration circuit of claim 4, wherein the divide-by-factor control module comprises:

A first selector, a first input end of which is connected with the output end of the calibration unit, a second input end of which is suitable for inputting the preset frequency division coefficient, and the first selector is configured to output the preset frequency division coefficient or the calibrated frequency division coefficient according to a first selection signal;

The first D trigger is configured to output the preset frequency division coefficient when the preset completion mark is received, and output the calibrated frequency division coefficient when the calibration completion mark is received.

6. A clock self-calibration circuit according to claim 3, wherein said calibration complete flag is used to characterize the number of data receiving channels for which the division coefficient calibration is completed in the case where there are a plurality of said data receiving channels, said clock dividing unit comprising:

An update control module configured to generate an update enable signal for a corresponding data reception channel according to the calibration complete flag;

the system comprises a plurality of frequency division coefficient control modules, a plurality of data receiving channels and a plurality of data transmission channels, wherein each frequency division coefficient control module is configured to take a preset frequency division coefficient of the corresponding data receiving channel as a frequency division coefficient of the corresponding data receiving channel under the condition of an initial state, and take the calibrated frequency division coefficient as the frequency division coefficient of the corresponding data receiving channel under the condition of receiving an update enabling signal of the corresponding data receiving channel;

And each clock frequency division module is connected with one frequency division coefficient control module and is suitable for being connected with one data receiving channel, and each clock frequency division module is configured to generate a channel clock of the corresponding data receiving channel according to the module clock and the frequency division coefficient of the corresponding data receiving channel.

7. The clock self-calibration circuit of claim 6, wherein the divide-by-factor control module comprises:

the first input end of the first selector is connected with the output end of the calibration unit, the second input end of the first selector is suitable for inputting the preset frequency division coefficient of the corresponding data receiving channel, and the first selector is configured to output the preset frequency division coefficient of the corresponding data receiving channel or the calibrated frequency division coefficient according to a first selection signal;

The first D trigger is configured to output a preset frequency division coefficient of the corresponding data receiving channel under the condition that the preset completion mark of the corresponding data receiving channel is received, and output a calibrated frequency division coefficient of the corresponding data receiving channel under the condition that the updating enabling signal of the corresponding data receiving channel is received.

8. The clock self-calibration circuit of any one of claims 4-7, wherein the preset division factor is determined from the module clock and a beat time.

9. The clock self-calibration circuit according to claim 1, wherein in case of one of the data receiving channels, the buffering unit comprises: and the data caching module is suitable for being connected with the data receiving channel and is configured to cache the count value sent by the data receiving channel.

10. The clock self-calibration circuit of claim 9, further comprising:

the input end of the second D trigger is connected with the clock frequency division unit, the enabling end of the second D trigger is suitable for inputting an output enabling signal, the output end of the second D trigger is connected with the calibration unit, and the second D trigger is configured to output the frequency division coefficient of the data receiving channel under the condition that the output enabling signal is received;

And the input end of the third D trigger is connected with the data caching module, the enabling end of the third D trigger is suitable for inputting the output enabling signal, the output end of the third D trigger is connected with the calibration unit, and the third D trigger is configured to output the count value of the data receiving channel under the condition that the output enabling signal is received.

11. The clock self-calibration circuit according to claim 1, wherein in case of a plurality of the data receiving channels, the buffer unit comprises a plurality of data buffer modules, each data buffer module is adapted to be connected to one of the data receiving channels, and a space number of each data buffer module is consistent with a channel number of the corresponding data receiving channel to receive the count value transmitted by the corresponding data receiving channel.

12. The clock self-calibration circuit of claim 11, wherein the buffer unit is further configured to generate a count valid flag bit in case at least one of the data buffer modules receives a count value transmitted by a corresponding data receiving channel, wherein the count valid flag bit is used to characterize a space number of the data buffer module that receives the count value transmitted by the corresponding data receiving channel.

13. The clock self-calibration circuit of claim 12, further comprising: and the data selection unit is configured to output the frequency division coefficient of the corresponding data receiving channel and the count value of the corresponding data receiving channel according to the count valid flag bit.

14. The clock self-calibration circuit of claim 13, wherein the data selection unit comprises:

the input end of the second selector is connected with the clock frequency division unit, and the second selector is configured to output frequency division coefficients of corresponding data receiving channels according to a second selection signal, wherein the second selection signal is output based on the counting valid flag bit;

the input end of the second D trigger is connected with the output end of the second selector, the output end of the second D trigger is connected with the calibration unit, and the second D trigger is configured to output the frequency division coefficient of the corresponding data receiving channel under the condition of receiving the output enabling signal;

the input end of the third selector is connected with each data caching module, and the third selector is configured to output the count value of the corresponding data receiving channel according to the second selection signal;

and the input end of the third D trigger is connected with the output end of the second selector, the output end of the third D trigger is connected with the calibration unit, and the third D trigger is configured to output the count value of the corresponding data receiving channel under the condition of receiving the output enabling signal.

15. The clock self-calibration circuit of claim 1, wherein each of the data receiving channels is adapted to input a send signal, the send signal comprising the synchronization pulse.

16. A data receiving system, comprising:

at least one data receiving channel, each of said data receiving channels adapted to receive a SENT signal;

the clock self-calibration circuit of any one of claims 1-15, coupled to each of the data reception channels, configured to provide a corresponding channel clock to each of the data reception channels so that each of the data reception channels receives the send signal according to the corresponding channel clock.

17. A controller comprising the data receiving system of claim 16.

18. A vehicle comprising a controller according to claim 17.