TWI519102B - Flexray receiver - Google Patents

Description

FlexRay receiver

The present disclosure is directed to a FlexRay circuit, and more particularly to a FlexRay transceiver circuit.

In recent years, FlexRay, a vehicle network communication protocol, has flourished and related system technologies have become more mature. This standard protocol is primarily a communication system for advanced automation control applications that provides high transmission rates and redundant transmission channels. At present, FlexRay has gradually replaced the Control Area Network (CAN), which has become the main technology of X-by-wire vehicle applications.

In particular, because automotive electronic control applications require deterministic, fault-tolerant, and high-speed bus systems that support distributed control systems, FlexRay technology is well suited. FlexRay enables the car to develop into a 100% electronic control system, thereby reducing the support requirements of the backup mechanical system. However, FlexRay products are currently large and expensive. Among the packaged FlexRay products, the FlexRay chipset model TJA1080 produced by Philips is the first; however, this chipset uses Bipolar Junction Transistor (BJT) and is complex and undisclosed. The circuit is designed to comply with FlexRay's specifications for communication protocols.

Therefore, there is currently no open technology on the market to explore how to design a circuit architecture to comply with FlexRay's protocol specifications.

Therefore, one aspect of the present disclosure is to provide a FlexRay receiver, which is implemented by a CMOS logic gate, which is cheaper to manufacture and lower in power consumption than commercially available products.

In accordance with an embodiment of the present disclosure, a FlexRay receiver is provided that includes a hysteresis comparator, a window comparator, and a charge and discharge pump. The hysteresis comparator is configured to compare a first input voltage and a second input voltage, and generate an output signal according to the comparison result. The window comparator is a parallel hysteresis comparator for outputting an idle state signal when the first input voltage and the second input voltage are in a predetermined voltage interval. The charge and discharge pump series window comparator is used to eliminate the pulse noise of the idle state signal.

According to another embodiment of the present disclosure, the method further includes a sampling circuit and an inverter, wherein the sampling circuit is a series hysteresis comparator for sampling the output signal to generate a data signal. The inverter is a series charge and discharge pump, so that the idle state signal logically matches the data signal. The sampling circuit includes a delay circuit to match the data signal to the idle state signal in time.

Thereby, the FlexRay receiver of the present disclosure can meet the specifications of the vehicle network communication protocol and realize low cost and low power consumption products.

100‧‧‧FlexRay Transmitter

110‧‧‧First launcher

111‧‧‧First CMOS current mirror

112‧‧‧First transmission gate

131‧‧‧Second CMOS current mirror

132‧‧‧Second transmission gate

150‧‧‧CMOS current mirror

120‧‧‧ busbar

121‧‧‧ first end

122‧‧‧ second end

123‧‧‧First resistance

124‧‧‧ bias power supply

125‧‧‧second resistance

130‧‧‧Second launcher

140‧‧‧CMOS transmission gate

141‧‧‧N type field effect transistor

142‧‧‧P type field effect transistor

151‧‧‧PMOS current source

152‧‧‧NMOS current tank

200‧‧‧FlexRay Receiver

201‧‧‧First input voltage

202‧‧‧second input voltage

210‧‧‧hysteresis comparator

220‧‧‧Window Comparator

221‧‧‧Preset voltage range

222‧‧‧ Idle state signal

230‧‧‧Charge and discharge pump

240‧‧‧Sampling circuit

241‧‧‧Delay circuit

242‧‧‧Factor

250‧‧‧ reverser

M1~M6, m1~m6‧‧‧O crystal

1 is a schematic structural diagram of a FlexRay transmitter corresponding to a FlexRay receiver according to an embodiment of the present disclosure.

Fig. 2 is a circuit diagram of the bus bar 120 of Fig. 1.

Figure 3 is a circuit diagram of the transfer gate 112/132 of Figure 1.

Fig. 4 is a circuit diagram of the CMOS current mirror 111/131 of Fig. 1.

Fig. 5 is a detailed circuit diagram of Fig. 1.

Figure 6 is a block diagram showing the structure of a FlexRay receiver in accordance with an embodiment of the present disclosure.

Figure 7 is a detailed circuit diagram of Figure 6.

Figure 8 is a waveform diagram of the transmission signal.

Figure 9A is a waveform diagram of the FlexRay Receiver 200 receiving data correctness indicators.

Figure 9B is a waveform diagram of the data received by the FlexRay receiver 200.

Figure 10 is a waveform diagram of the present invention in which the signal timing of a transmitter is defined in accordance with the FlexRay communication protocol.

Figure 11 is a waveform diagram of the simulation of the FlexRay transmitter 100 delay time specification.

Figure 12 is a waveform diagram of the present invention in which the signal timing of a receiver is defined in accordance with the FlexRay communication protocol.

Figure 13 is a waveform diagram of the simulation of the FlexRay receiver 200 delay time specification.

Figure 14 is a waveform diagram of the FlexRay transmitter 100 and the FlexRay receiver 200 in a simulated operating state.

Please refer to FIG. 1 , which is an embodiment of the present disclosure. Schematic diagram of the FlexRay transmitter. In FIG. 1 , the FlexRay transmitter 100 mainly includes a first transmitter 110 and a second transmitter 130. The first transmitter 110 includes a first CMOS current mirror 111 and a first transmission gate 112. The first transmission gate 112 of the first transmitter 110 is configured to determine whether to generate a current by the first CMOS current mirror 111 of the first transmitter 110 according to a first state code to provide a positive voltage difference to a bus. The first end 121 of the 120 is simultaneously provided with a negative pressure differential to the second end 122 of the bus bar 120. The second transmitter 130 also includes a second CMOS current mirror 131 and a second transmission gate 132. The second transmission gate 132 of the second transmitter 130 is configured to determine whether to generate a current by the second CMOS current mirror 131 of the second transmitter 130 according to a second state code to provide a negative voltage difference to the bus bar 120. The first end 121 and a positive pressure difference are simultaneously provided to the second end 122 of the bus bar 120.

Specifically, in the FlexRay communication protocol, the input data signal is required to be two groups of potential logic opposite signals, that is, the first state code and the second state coded potential logic in the data transmission state must be opposite to ensure the correct signal. Sex. When the first state code and the second state code are respectively a high logic potential and a low logic potential, it indicates that the FlexRay transmitter 100 can generate two sets of signals with the same potential logic opposite according to the input signal. When the first state code and the second state code are both high or low, it indicates that the input signal is not reliable or the FlexRay transmitter 100 is in an idle state, and the FlexRay transmitter 100 should not rely on the pair of input signals. , produces a meaningful output potential signal. This is because in the vehicle electronics, the negative factors such as electromagnetic interference, leakage interference, and grounding level drift of the circuit are much higher than those of the circuit that is normally placed in a fixed environment.

Therefore, the FlexRay transmitter 100 of the present embodiment can be closely studied. Obviously, the following operation rule is known: when the first transmission gate 112 and the second transmission gate 132 receive the first state code and the second state code which are opposite in logic, if the first state code represents driving the first CMOS current mirror 111 to map one The current is applied to the bus bar 120, and the second state code represents that the second CMOS current mirror 131 is not driven to map a current to the bus bar 120. At this time, the first transmitter 110 provides a positive pressure difference to the first end 121 of the bus bar 120 and simultaneously provides a negative voltage difference to the second end 122 of the bus bar 120. In other words, the output potential signal of the bus bar 120 is the first potential of the potential logic opposite to the high potential logic and the low potential logic of the second terminal 122, which is denoted as (1, 0).

When the first transmission gate 112 and the second transmission gate 132 receive the input signal, the first state code represents not driving the first CMOS current mirror 111 to map a current to the bus bar 120, and the second state code represents the driving second. The CMOS current mirror 131 maps a current to the bus bar 120; the second transmitter 130 provides a positive voltage difference to the second terminal 122 of the bus bar 120, and simultaneously provides a negative voltage difference to the first end 121 of the bus bar 120. , recorded as (0,1).

As for the other non-operating state or the disturbed state, the first current mirror 111 of the first emitter 110 and the second current mirror 131 of the second emitter 130 simultaneously map current or do not map current to the bus bar 120, and then confluence The first end 121 and the second end 122 of the row 120 naturally do not generate a set of output potential signals having opposite logic potentials.

In summary, the FlexRay transmitter 100 of the present embodiment can meet the specifications of the automotive network protocol FlexRay.

Please refer to FIG. 2 again, and FIG. 2 is a circuit diagram of the bus bar 120 of FIG. 1. In FIG. 2, the bus bar 120 further includes a first resistor 123, a bias power source 124, and a second resistor 125. Here is a feasible exchange The flow row 120 is designed such that the currents mapped by the first CMOS current mirror 111 and the second CMOS current mirror 131 can be converted into a positive pressure difference or a negative pressure difference between the first end 121 and the second end of the bus bar 120. 122; rather than limiting other possible aspects of the FlexRay transmitter 100 of the present embodiment in the design of the busbar 120.

Specifically, when the first emitter 110 drives the first CMOS current mirror 111 to generate a mapping current, a mapping current flows from the node a through the first resistor 123 to the bias power source 124, so that the potential of the first terminal 121 is higher than the bias voltage. The pressure source 124 has a pressure difference, which is called a positive pressure difference. At the same time, the first CMOS current mirror 111 also generates a mapping current from the bias power source 124 to the node c via the second resistor 125, so that the potential of the second terminal 122 is lower than the voltage difference of the bias power source 124. The so-called negative pressure difference. Interestingly, the two sets of mapped currents can be the same current through the matching design on the circuit. Similarly, the absolute value of the positive pressure difference can be equal to the absolute value of the negative pressure difference through the matching design on the circuit.

It should be noted that, at this time, the second emitter 130 cannot simultaneously drive the second CMOS current mirror 131 to pass the current between the node b and the node d; otherwise, the first end 121 and the second end 122 cannot generate a stable positive pressure difference. The negative voltage difference, and the so-called first state code and the second state code, are mutually opposite to each other.

On the other hand, the second transmitter 130 operates in the same manner as the first transmitter 110 described above; the difference is only that when the second transmitter 130 is actuated, the mapping current flows from the node d to the second terminal 122, and is caused by the node b. The first end 121 flows out, and the positive and negative pressure differences are translocated.

Please continue to refer to Figure 3, which is a circuit diagram of the transmission gate of Figure 1. Specifically, in order to implement FlexRay transmission using CMOS circuits The device 100 has balanced circuit characteristics. The first transfer gate 112 and the second transfer gate 132 can also adopt the circuit structure of the CMOS transfer gate 140, except that the current mirror can adopt the CMOS current mirror. In other words, the CMOS transfer gate 140 can be composed of an N-type field effect transistor 141 and a P-type field effect transistor 142. The source of the P-type field effect transistor 142 is co-located with the drain of the N-type field effect transistor 141, and the drain of the P-type field effect transistor 142 is co-located with the source of the N-type field effect transistor 141.

Next, please refer to FIG. 4, which is a circuit diagram of the CMOS current mirror of FIG. 1. The first CMOS current mirror 111 of the first emitter 110 and the second CMOS current mirror 131 of the second emitter 130 can adopt the structural design shown in FIG. Specifically, the CMOS current mirror 150 is composed of a PMOS current source 151 and an NMOS current sink 152, and is controlled by the aforementioned CMOS transmission gate 140. Since both the first transmitter 110 and the second transmitter 130 are in a CMOS circuit design manner, the FlexRay transmitter 100 of the present embodiment saves power and has a lower manufacturing cost than the BJT circuit used by Philips.

Finally, please refer to Figure 5, which is a detailed circuit diagram of Figure 1. In the fifth figure, the PMOS current source of the first transmitter 110 includes a first P-type field effect transistor M1 and a second P-type field effect transistor M5, and the source of the first P-type field effect transistor M1 A voltage source Vdd is connected to the gate, and its gate is co-located with its drain, and its drain is electrically connected to the transmission gate 112. The transfer gate 112 is composed of an N-type field effect transistor M2 and a P-type field effect transistor M3. The source of the second P-type field effect transistor M5 is electrically connected to the voltage source Vdd, and the gate thereof is co-located with the gate of the first P-type field effect transistor M1, and the gate is electrically connected to the first end 121.

The NMOS current slot of the first transmitter 110 includes a first N-type Field effect transistor M4 and a second N-type field effect transistor M6. The source of the first N-type field effect transistor M4 is grounded, its drain is co-located with its gate, and its drain is electrically connected to the transfer gate 112. The gate of the second N-type field effect transistor M6 is co-located with the gate of the first N-type field effect transistor M4, the source thereof is grounded, and the drain is electrically connected to the second end 122.

Similarly, the PMOS current source of the second emitter 130 includes a first P-type field effect transistor m1 and a second P-type field effect transistor m5 (note its position), and the first P-type field effect transistor m1 The source is electrically connected to the voltage source Vdd, and its gate is co-located with its drain, and its drain is electrically connected to the transfer gate 132. The source of the second P-type field effect transistor m5 is electrically connected to the voltage source Vdd, the gate thereof is co-located with the gate of the first P-type field effect transistor m1, and the gate is electrically connected to the second end 122, Instead of the first end 121.

The NMOS current slot of the second emitter 130 includes a first N-type field effect transistor m4 and a second N-type field effect transistor m6 (note its position). The source of the first N-type field effect transistor m4 is grounded, its drain is co-located with its gate, and its drain is electrically connected to the transfer gate 132. The gate of the second N-type field effect transistor m6 is co-located with the gate of the first N-type field effect transistor m4, the source thereof is grounded, and the drain is electrically connected to the first end 121 instead of the second end 122. .

Please refer to FIG. 6. FIG. 6 is a schematic structural diagram of a FlexRay receiver 200 according to another embodiment of the present disclosure. In FIG. 6, the FlexRay receiver 200 includes a hysteresis comparator 210, a window comparator 220, and a charge and discharge pump 230. The hysteresis comparator 210 is configured to compare a first input voltage 201 and a second input voltage 202, and generate an output signal according to the comparison result. The window comparator 220 is a parallel hysteresis comparator 210 for outputting an idle state signal 222 when the first input voltage 210 and the second input voltage 220 are in a predetermined voltage interval 221 . Charge and discharge pump 230 The series window comparator 220 is used to cancel the pulse wave noise of the idle state signal 222.

Specifically, the voltage values of the first end 121 and the second end 122 of the aforementioned FlexRay transmitter 100 are transmitted to the FlexRay receiver 200 as the first input voltage 201 and the second input voltage 202. When the first input voltage 201 is logically opposite to the potential of the second input voltage 202, that is, when the generation is based on the meaningful first state encoding and the second state encoding, the hysteresis comparator 210 according to the first input voltage 201 and the second The comparison of the input voltages 202 produces an output signal. More correctly, the hysteresis comparator 210 is to ensure a certain difference between the first input voltage 201 and the second input voltage 202; that is, when the first input voltage 201 and the second input voltage 202 are logic In the transition state (one from low to low and the other from low to high), the hysteresis comparator 210 can confirm that one of the two input comparison signal voltages must be greater than or less than another input voltage. The main purpose of the voltage value is to eliminate the effects of noise to obtain the correct output signal.

For example, if the first state code and the second state code are one high and one low (1, 0), the output of the hysteresis comparator 210 can be assumed to be a logic high potential (1); otherwise, the first state code and the first state The second state code is a low one high (0, 1), then the output of the hysteresis comparator 210 is a logic low (0); the emphasis is that when the first state code and the second state code are both high (1, 1) Or low potential (0, 0), the potentials of the first terminal 121 and the second terminal 122 are unpredictable, and the hysteresis comparator 210 does not have a certain difference due to the first input voltage 201 and the second input voltage 202. (The difference between high and low potential is expected), regardless of this noise disturbance or idle state. Therefore, the output signal of the hysteresis comparator 210 can correctly reflect the first state code and the second state code generation. The signal meaning of the table.

The function of the window comparator 220 is that when the input voltage, that is, the difference between the first input voltage 201 and the second input voltage 202, falls within a certain design voltage interval, it can be detected and indicated. As described above, the interval represents that the first state code and the second state code do not exhibit a state opposite to the logic potential, and is an idle state (Idle); the window comparator 220 thus generates the idle state signal 222. Therefore, the output signal generated by the hysteresis comparator 210 can be used as the data signal R-data required by the vehicle network protocol FlexRay; and the idle state signal 222 generated by the window comparator 220 conforms to the vehicle network. The idle indicator R-idle required by the road protocol FlexRay.

However, due to the transition state of the input signal, the designed voltage interval, that is, the preset voltage interval 221, must be passed, thereby causing the output value of the window comparator 220, that is, the idle state signal 222, and short pulse noise. Therefore, in this embodiment, the two inputs of the charge and discharge pump 230 are connected together, and the designed load capacitance value is matched to filter out short pulse noise.

Finally, please refer to Figure 7, which is a detailed circuit diagram of Figure 6. In Fig. 7, the FlexRay receiver 200 of the present embodiment further includes a sampling circuit 240. The sampling circuit 240 is connected in series to the hysteresis comparator 210 to sample the output signals to generate data signals in digital form. Further, the sampling circuit 240 may include a delay circuit 241 and a D-type flip-flop 242; when the FlexRay receiver 200 is in a non-low power mode, that is, the data transmitted by the FlexRay transmitter 100 is not representative of an idle state. The sampling circuit 240 allows the data signal to conform to the initial input signal, that is, the first state code and the second state code. Therefore, the delay circuit 241 can make the data signal match the idle state signal 222 in time; and the D type is positive and negative. The 242 can make the data signal conform to the initial input signal.

On the other hand, the charge and discharge pump 230 can be connected in series with an inverter 250, and when the FlexRay receiver 200 is in the non-low power mode, the inverter 250 can make the differential signal (the first input voltage 201 and the second The magnitude of the difference in input voltage 202 is in accordance with the requirements of the FlexRay protocol. Specifically, the FlexRay protocol requires a logic 1 to indicate that the signal is small and the bus 120 state should be Idle or Idle_LP. A logic 0 indicates that the signal is large enough to indicate that the bus status should be Data. However, the logical relationship of the idle state signal 222 is reversed, so that it can be adjusted by the inverter 250 to make the idle state signal logically match the data signal.

Next, the present disclosure performs point-to-point transmission with a bidirectional differential voltage transmission architecture to test the FlexRay transmitter 100 and the FlexRay receiver 200 disclosed in the above embodiments to verify its performance as follows.

Please refer to Figure 8. Figure 8 is a waveform diagram of the transmission signal. In Fig. 8, the solid line is the waveform eye diagram of the signal between the aforementioned FlexRay transmitter 100 and the FlexRay receiver 200; and the dashed line is the waveform eye diagram of the minimum requirement of the FlexRay protocol.

Specifically, the various qualities of a signal can be observed from the waveform eye diagram of a data sequence. A receiver's signal has many characteristics, such as amplitude noise, interpolated interference, or jitter, which can affect the probability of extracting the correct information from the signal. A waveform eye diagram of a signal can be used to interpret information about the characteristics of these signals. In the bidirectional differential voltage transmission architecture, assuming that the FlexRay transmitter 100 is to transmit a signal to the FlexRay receiver 200, the solid line in FIG. 8 represents the voltage difference between the first end 121 and the second end 122 on the FlexRay transmitter 100. The dotted line is the waveform eye diagram of the minimum size required by FlexRay. The wavy eye diagram formed by the solid line part is obvious Contains a dotted line and therefore meets the requirements of the FlexRay specification. The same phenomenon can also be observed in the waveform eye diagram of the voltage difference between the first input voltage 201 and the second input voltage 202 of the FlexRay receiver 200. As can be seen from Fig. 8, the signal of this embodiment conforms to the signal requirements required by the FlexRay protocol.

Please refer to FIG. 9A and FIG. 9B together; FIG. 9A is a waveform diagram of the FlexRay receiver 200 receiving the data correctness index, and FIG. 9B is a waveform diagram of the FlexRay receiver 200 receiving the data. It can also be seen from FIG. 9A and FIG. 9B that the receiver 200 of the present embodiment also meets the signal requirements required by the FlexRay protocol when outputting the transfer function. The specific comparison data is shown in the following table:

Please refer to Figure 10 and Figure 11 together. Figure 10 is a waveform diagram of the present invention in which the signal timing of a transmitter is defined in accordance with the FlexRay communication protocol. Figure 11 is a waveform diagram simulating the aforementioned FlexRay transmitter 100 delay time specification. It can be seen from FIGS. 10 and 11 that the signal waveform generated by the aforementioned FlexRay transmitter 100 is also in compliance with the FlexRay protocol. A comparison of relevant data is also included in the above table.

Please refer to Figure 12 and Figure 13 together. Figure 12 is a waveform diagram of the present invention in which the signal timing of a receiver is defined in accordance with the FlexRay communication protocol. Figure 13 is a waveform diagram simulating the delay time specification of the aforementioned FlexRay receiver 200. It can be seen from Figures 12 and 13 that the signal waveform generated by the aforementioned FlexRay receiver 200 is also in compliance with the FlexRay protocol. A comparison of relevant data is also included in the above table.

Referring to FIG. 14, FIG. 14 is a waveform diagram of the FlexRay transmitter 100 and the FlexRay receiver 200 of the above embodiment in a simulated operation state. As can be seen from Fig. 14, when the FlexRay transmitter 100 is in the normal transmission and reception state, assuming that the transmission data (TxD) changes every 100 ns, when the bus transmission index (BusGuardian_Enable, BGE) is logic 1 and the data is correctly corrected. When the indicator (TxEN) is logic 0, the received data correctness indicator (RxEN) is logic 0. If the voltage difference (TP1) on the bus is positive, the received data (RxD) is logic 1, if the voltage difference on the bus is (TP1) is negative, the received data (RxD) is logic 0; when the bus transmission indicator (BGE) is logic 0 or the output data correctness indicator (TxEN) is logic 1, the voltage difference (TP1) on the bus is 0, Receive Data Correctness Indicator (RxEN) and Receive Data (RxD) are both logic 1. Therefore, the FlexRay transmitter 100 and the FlexRay receiver 200 operate correctly and comply with the FlexRay protocol.

Although the present invention has been disclosed in the above embodiments, it is not The scope of the present invention is defined by the scope of the appended claims, and the scope of the invention is defined by the scope of the appended claims. .

201‧‧‧First input voltage

202‧‧‧second input voltage

210‧‧‧hysteresis comparator

220‧‧‧Window Comparator

221‧‧‧Preset voltage range

222‧‧‧ idle device signal

230‧‧‧charge and discharge voltage pump

Claims (1)

A FlexRay receiver includes: a hysteresis comparator that receives a first input voltage and a second input voltage, the hysteresis comparator is configured to compare the first input voltage with the second input voltage, and generate a An output signal; a window comparator receiving the first input voltage and the second input voltage, wherein the window comparator is configured to output an idle when the first input voltage and the second input voltage are in a predetermined voltage interval a state signal; a charge and discharge pump, the window comparator is connected in series to cancel the pulse wave noise of the idle state signal; a sampling circuit is connected in series with the hysteresis comparator to sample the output signal to generate a data signal, And the sampling circuit includes a delay circuit connected to the flip-flop, the delay circuit connecting the data signal to match the idle state signal in time, the flip-flop causing the data signal to conform to the first An input voltage and a logic potential of the second input voltage; and an inverter connected in series with the charge and discharge pump to cause the idle state signal to be in phase The data signal is logically matched.