CN114787988A - 金属微线的异位制作和ic电路中的fib放置 - Google Patents
金属微线的异位制作和ic电路中的fib放置 Download PDFInfo
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Abstract
一种制造电路封装件的方法(200)包括:安装(205)用于运送的微线,其中微线具有10微米或更小的直径;以及将所安装的微线和电路封装件引入(210)聚焦离子束(FIB)装置。该FIB装置包括FIB显微镜和纳米定位器(210)。将微线、纳米定位器和电路封装件带入(215)用于FIB装置的工作区域中。使用(220)纳米定位器将微线和电路封装件在用于附接的位置处结合在一起。将微线焊接(225)到位,并释放(230)微线。
Description
背景技术
在半导体集成电路(IC)芯片的生产和评估的早期阶段,“电路编辑”是通常用于通过削减到现有IC芯片的现有耦合或添加到现有IC芯片的新耦合来有效缩短开发周期和上市时间的做法。电路编辑可以提供快速的原型修改,例如在几小时或几天内执行修改。这些相同的修改可能需要数周的时间来通过半导体制造厂进行处理,因为通常需要生产或修改昂贵的掩模组。尽管执行电路编辑的技术解决了许多持续存在的挑战,但是在建立某些类型的新连接方面仍然存在一些漏洞。
发明内容
一些实施例提供了制造微线以及使用采用聚焦离子束(FIB)显微镜、FIB与扫描电子显微镜(SEM)的组合、等离子FIB显微镜或类似显微镜的装置将微线放置在IC芯片和电路封装件中的方法。在开发期间可以使用微线来增强FIB装置在当前难以或不可能的各类型的电路编辑中的能力。使用FIB装置,微线也可以被结合到IC芯片和封装件的生产中。尽管为与IC芯片一起使用而开发,但是所描述的方法和器件也可以用于不属于IC部分的电路中。
在一方面,描述了IC封装件的实施例。IC封装件包括制造为IC封装件的一部分的第一导电元件;以及具有耦合到第一导电元件的第一端的微线,该微线已经被异位(ex-situ)制造并且包括具有10微米或更小的直径的金属。
在另一方面,描述了制造具有由金属形成的微线的集成电路封装件的方法的实施例。该方法包括安装用于运送的微线,该微线由金属形成并具有10微米或更小的直径;将所安装的微线和电路封装件引入包括FIB显微镜和纳米定位器的聚焦离子束(FIB)装置中;将微线、纳米定位器和电路封装件带入用于FIB装置的工作区域中;使用纳米定位器将微线和电路封装件在用于附接的位置处结合在一起;将微线焊接到位;以及释放微线。
在又一方面,描述了制造微线的方法的实施例。该方法包括将一段预成形线悬浮在具有已知浓度和温度的蚀刻剂溶液中一段时间,以实现10微米或更小的直径,该预成形线包括导电金属;从蚀刻剂溶液中去除所蚀刻的线;以及冲洗所蚀刻的线。
附图说明
本说明书的实施例在附图的图中通过示例的方式而非通过限制的方式示出,其中相似的附图标记指示类似的元素。对“一”或“一个”实施例的不同引用不一定指相同的实施例,并且这样的引用可以表示至少一个。此外,当结合实施例描述特定特征、结构或特性时,认为结合其他实施例实现此类特征、结构或特性在本领域技术人员的知识范围内,无论是否明确描述。如本文所用,术语“耦合”或“耦接”表示间接或直接电连接,除非限定为可包括无线连接的“可通信耦合”。因此,如果第一器件耦合到第二器件,则该连接可以是通过直接电连接,或者通过经由其他器件和连接的间接电连接。
附图被并入说明书并形成说明书的一部分,以说明本说明书的一个或多个示例性实施例。本说明书的各种优点和特征将从以下结合所附权利要求并参考附图的具体实施方式中进行理解,其中:
图1描绘了根据实施例的制造导电微线的方法;
图1A描绘了根据实施例的正在被蚀刻以形成微线的一段预成形线;
图2描绘了根据实施例的制造电路封装件的方法;
图2A至图2F描绘了可以是图2的方法的一部分的附加元素;
图3A描绘了根据实施例的已经附接到纳米定位器的尖端的微线;
图3B描绘了根据实施例的附接到IC芯片的表面的微线;
图3C描绘了根据实施例的附接到电路封装件的两个微线;
图4A描绘了根据实施例的耦合被提供在IC芯片的表面处的两个嵌入式导电元件的微线;
图4B描绘了根据实施例的耦合被提供在IC芯片的层间电介质顶部上的两个导电元件的微线;
图4C描绘了根据实施例的耦合两个导电元件同时避免IC芯片上的第三导电元件的微线;
图4D描绘了根据实施例的耦合用于堆叠的第一IC芯片和第二IC芯片的接合焊盘的微线;
图4E描绘了根据实施例的已经被成形以形成天线并附接到IC芯片上的导电元件的微线;
图4F描绘了根据实施例的已经被成形以形成微电感器并附接到IC芯片上的导电元件的微线;
图5描绘了可以用于制造包含由金属制成的微线的IC芯片的双束FIB显微镜和SEM;
图6A描绘了图5的FIB可以执行的电路编辑的示例;并且
图6B描绘了图5的FIB不能执行的电路编辑的示例。
具体实施方式
现在将参考附图详细描述本发明的特定实施例。在本发明的实施例的以下详细描述中,阐述了许多具体细节,以便提供对本发明的更透彻的理解。然而,对于本领域的普通技术人员显而易见的是,可以在无这些具体细节的情况下实践本发明。在其他情况下,未详细描述众所周知的特征,以避免不必要地使描述复杂化。
IC电路编辑需要用以修改器件内部的小互连件而不会无意中影响附近的结构的精度。对当前开发芯片的电路编辑需要FIB显微镜,其具有精密电动载物台、高真空腔室、特定气体化学物质(即前体气体)和计算机辅助绘图(CAD)导航,以定位位于表面下且在暴露之前无法看到的目标互连件。使用前体气体和离子束扫描的组合,这些FIB显微镜能够进行选择性蚀刻和沉积。
现在参考图5,示出了操作中的FIB装置500的侧视图。FIB装置500的核心件是初级离子柱502,其从液态金属离子源(例如,镓)生成离子束504。带正电的镓离子(Ga+)506从场发射器点源引出并通过施加大电势(通常在30-50千伏(kV)范围内)加速。在静电透镜的帮助下,发射被聚焦成离子束504,其可以具有亚微米直径。离子束504可以用于铣削穿过可以是集成电路的样品508,如故障分析中可能需要的。样品508通常定位在真空腔室512内的载物台510上。
当离子束504碰撞样品508时,二次电子514、二次离子(I+或I-)516以及中性分子和原子518可以从样品表面520中喷出。带电粒子被拉向电偏置网格,并由通常与离子柱502成角度定位的检测器(未示出)收集。来自所喷出的粒子的信号可以被放大和显示,以提供感兴趣区域的实时图像。
双柱工具可以具有由可选电子柱522补充的离子柱502,该电子柱522可以从离子柱502倾斜45度至60度。电子柱522将大量电子524输送到局部区域,并且为FIB装置500执行SEM成像,提供通常优于单独由离子柱502形成的图像的图像并帮助提供增加的场深。由于铣削区域易于成像,电子柱522还可以有助于横截面和透射电子显微镜(TEM)样品制备。
离子束504通常以单向光栅(raster)或以用户定义的模式跨样品508移动。操作员已经控制各种参数,如束流、光斑尺寸、像素间距和停留时间。撞击样品表面的镓离子506的剂量或量通常是束流、扫描持续时间和扫描面积的函数。二次产率(即每个指向样品的镓离子506的二次离子516的数量)是正在被铣削的材料的函数。由离子束504溅射掉的样品508的表面材料的量是所有上面提到的参数的函数。
虽然离子束504可以对样品材料具有溅射影响,但是通常需要添加气体以帮助化学地去除材料,从而对材料去除过程进行增强。气体辅助蚀刻是现代FIB中的常见特征。可选气体注入柱526将局部沉积气体528输送到要铣削的区域。该沉积气体528可以与离子束504相互作用,以提供选择性气体辅助化学蚀刻。可替代地,初级离子束可以用于分解气体,以提供导电或绝缘材料在样品上的选择性沉积。
通过在要执行的修改的局部区域处引导离子束,FIB可以促进半导体器件修改。离子束去除局部区域中的材料,铣削穿过各个层。当到达感兴趣的层时,可以通过在期望位置中沉积新金属线或其他材料以建立连接,或者通过切断现有的导电线以断绝连接来执行电路编辑。在一些示例中,为了在FIB内部创建导电连接,将含有例如铂的有机金属前体注入瞄准目标区域(例如,两个或更多个导电接触点)处的腔室中,并且离子束扫描器件表面上的图案,导致前体气体分解并导致沉积到器件上。其他前体气体可以包括六羰基钨(W(CO)6),以及包括铝(Al)、铜(Cu)、钼(Mo)等有机金属气体。
FIB装置可以使用穿过基板的背面或穿过包围金属层的电介质层的方法在器件上执行电路编辑。最佳方法可以取决于器件的布局以及位于表面和期望导电元件之间的障碍物。图6A描绘了通过IC芯片600A的背面执行的电路编辑的示例,其中FIB装置提供新连接。IC芯片600A包括基板602和层间电介质(ILD)604。基板602包含导电区606,其是掺杂硅并且可以形成例如与电路相关联的源极、漏极或阱(well)。ILD 604包含可以通过通孔608连接的金属层M1至M6。
对于所示的电路编辑,正在基板中的导电区606A和作为金属层M5的一部分的导电元件610之间创建新连接。使用FIB装置,已经在基板602中铣削沟槽612,以暴露感兴趣区。另外,沟槽614A和沟槽614B已经被铣削,以分别接触导电元件610和导电区606A。因为这些沟槽穿过基板602的一部分,所以新连接需要与基板绝缘。这可以通过沉积可以填充沟槽614A和沟槽614B的电介质层(例如,氧化硅616)以及跨沟槽612的底部618的一部分延伸来完成。然后,FIB可以铣削穿过填充沟槽614A和沟槽614B的氧化硅616,同时在这些沟槽的壁上留下一层氧化硅。然后,FIB将导电材料200沉积到沟槽614A和沟槽614B中,以及在两个沟槽614A、614B之间形成导电连接。
虽然图6A中所示的电路编辑完全在当前FIB装置500的能力内,但是FIB目前不可能执行其他期望编辑,诸如在高于表面的两个导电元件之间形成导电连接,诸如在有源电路(BOAC)或顶部铜元件之上接合(bond)。图6B描绘了包含电介质层622、顶部铜元件624和顶部铜元件626的IC芯片600B。在这个示例中,期望在顶部铜元件624和顶部铜元件626之间形成新连接,而不首先在这两个顶部铜元件之间沉积电介质。然而,因为沉积物是由气体制成的并且导电元件624、626包含悬壁结构(overhangs),所以不可能跨过顶部铜元件624和顶部铜元件626之间的间隙提供连接。相反,尝试沉积连接将会导致如图所示的不连续段628A、628B和628C。
由于用于使金属导电元件挥发的方法,出现在FIB中形成的导电元件可能出现的另一个问题。用于在FIB中气相沉积连接的金属(例如铂、钨或钼)不易挥发,所以为了使用这些金属,可以将它们封闭在碳“笼”中,以增强挥发性。在一个实施例中,(三甲基环戊二烯)三甲基铂(C9H17Pt)是用于沉积铂的前体气体。所得到的沉积的铂包含大量的碳,这增加连接的电阻率。由FIB沉积的示例连接具有约20欧姆/微米的电阻率。这意味着具有长度为90μm和宽度为1μm的示例FIB连接可以具有约1800欧姆的电阻。通过将宽度增加到2μm,电阻可以降低到约900欧姆,但保持高。当需要新连接承载高电流时,这产生问题,因为电流可能烧毁连接。需要可以在FIB中执行的新操作来解决这些问题。
本申请描述了一种制造微线(例如具有几微米或甚至更小的直径)并且使用这些微线来耦合IC芯片上的导电元件的方法。电化学蚀刻是减小线的直径的已知方法,并且已经用于生产非常小的、锋利的尖端,以用于在许多过程,例如扫描隧道显微术。申请人已对线采用化学蚀刻,以提供具有10μm或更小的直径的微线。一旦准备好,这些微线就可以在对集成电路芯片执行电路编辑中使用。除了在解决现有FIB过程中已识别的缺点中使用之外,还识别了在IC芯片生产中使用所描述的微线的方法。另外,尽管所描述的概念是为在IC中使用而开发的,但是它们的使用不限于IC,如下文将进一步描述的。
图1描绘了用于制造可以在电路编辑中使用并且也可以在生产成品封装件中使用的微线的方法100的流程图。目前,该方法是一种已被示出提供均匀的线蚀刻的手动过程。本文描述了该手动方法,以提供概念的证明,但不是对该方法的限制。方法100开始于将一段预成形线悬浮105在具有已知浓度和温度的蚀刻剂溶液中。包括诸如钨、铜、铝等导电金属的预成形线保持在蚀刻剂溶液中一段时间,这将实现10微米或更小的直径。在一个实施例中,预成形线是钨并且具有1mil的初始直径。
执行测试,以确定用以实现期望结果的合适的浓度和时间段。然后,将具有1mil的直径的各种节段的钨线在110℃下的30%过氧化氢溶液中悬浮约30分钟(加一分钟或减一分钟),并且获得具有范围为1μm至6μm的相应直径的微线。实际所需的时间将取决于金属成分和预成形线的初始直径、蚀刻剂和蚀刻剂浓度以及溶液的温度。可以使用的其他金属和相应蚀刻剂的若干示例包括用于蚀刻铜线的稀硝酸和用于蚀刻铝线的稀盐酸。一旦确定的时间段已经逝去,该方法继续从蚀刻剂溶液中去除110所蚀刻的线。然后,冲洗115所蚀刻的线,以完全停止任何蚀刻动作。
图1A描绘了在蚀刻以形成微线期间的线的示例。该图未按比例绘制,并且仅用于示出总体思路而被提供。已使用未具体示出的保持器将预成形线122悬浮在蚀刻剂溶液124中。在蚀刻一段时间后,预成形线122包括两个节段:第一节段126保持在蚀刻剂溶液上方并且不受蚀刻影响,并且第二节段128浸入蚀刻剂溶液124中并且将具有随时间减小的直径。蚀刻剂溶液124维持在选定的温度,尽管再次未具体示出该装置。尽管第一节段126保持其直径和可见度,但是随着第二节段128接近10μm或更小的最终直径,第二节段128将不再对肉眼可见并且只能在放大情况下才能看到。由于微线将被运送到FIB腔室以供使用,因此节段126可以保持附接用于在运送期间处理线122。还可以期望的是,将预成形线122的长度限制为可以在FIB腔室内操纵的长度。当前FIB腔室通常具有可以以几百毫米测量的尺寸,使得可以提供具有几毫米长度的微线。
图2描绘了根据实施例的制造电路封装件的方法200的流程图。电路封装件可以包含单个IC芯片、附接在一起的多个IC芯片,例如多芯片模块。为了本申请的目的,对IC芯片的引用包括作为IC封装件或电路封装件的一部分的IC芯片。可以注意的是,IC封装件或电路封装件可以包括但不限于图3A至图3C和图4A至图4F中所示的元件。电路封装件还可以包含耦合到器件的芯片,其中该器件是非IC电气部件或电路,或耦合到器件的器件。电路封装件可以处于正在制造的过程中,或者可以处于设计的开发和/或调试的过程中,其中正在执行电路编辑。当正在执行电路编辑时,电路封装件的一个或多个区可以已经被预先暴露,例如使用FIB装置来去除材料并暴露一个或多个导电元件。导电元件可以包括但不限于接合焊盘、通孔、线、金属层、部件等。电路封装件也可以是研究应用的一部分,包括微机电(MEM)器件等。
方法200开始于安装205具有10μm或更小的直径的用于运送的微线。在一个实施例中,已经使用图1的方法100形成了微线。在一个实施例中,将微线安装到基板,该基板提供保持微线以引入FIB腔室中的稳定构件;该基板可以由适合于该目的的任何材料形成。在一个实施例中,微线被放置在容器(例如,在FIB内可以从其拾取微线的托架)内。在一个实施例中,整个线具有10微米或更小的直径。在一个实施例中,线的第一段具有10微米或更小的直径,并且线的第二段具有可以更容易固定的较大直径。
将所安装的微线和电路封装件引入210到FIB装置中,该FIB装置包括FIB显微镜和纳米定位器,该FIB显微镜可以是等离子FIB显微镜。在一些实施例中,FIB装置还包括扫描电子显微镜。虽然未要求,但是SEM提供了内部工作区域的单独视图,并改善了在FIB腔室的三个维度内定位物品(诸如微线)的能力。纳米定位器是能够以纳米准确度定位样品的高度精确运动器件。纳米定位器最初被引入FIB腔室中用于在TEM样品制备中使用,但是可以重新用于微线的操纵。为了本申请的目的,对纳米定位器的引用被解释为包括微型夹持器、MEMS器件、使用静电力的器件等,以及自组装或自对准的方法。FIB腔室被进一步耦合,以提供高真空,并且包括高能量源、用于可视化的检测器,以及可以用于执行如前所述的铣削或沉积的多种化学物质。
然后,将微线、电路封装件和纳米定位器带入215用于FIB装置的工作区域中,并且使用220纳米定位器将微线和电路封装件在用于附接的位置处结合在一起。在一个实施例中,微线可以保持静止,而电路封装件被操纵以使两者接触。在一个实施例中,微线可以由作为纳米定位器的一部分的微型夹持器拾取,并精确地放置在电路封装件上。还可以使用仅包括细长尖端的纳米定位器非常精确地放置微线;这个过程将在下面描述。一旦定位,就使用一个或多个焊点(welds)将微线段焊接225到位。在一个实施例中,使用前体气体(三甲基环戊二烯)三甲基铂来进行焊接,跨微线沉积短的铂带。一旦将微线紧固到位,就可以从保持或附接到微线的器件释放230该微线。
如上所述,在一个示例实施例中,纳米定位器包括细长尖端,其中微线必须首先附接到该细长尖端。用于此方法的附加元素在图2A中示出。纳米定位器的尖端被焊接到微线。在FIB装置的上下文中,术语焊接用于描述创建物理和/或电连接的过程,并且可以通过沉积少量的多种可用化学物质中的一种来实现,这些化学物质将粘附到纳米定位器和微线两者。可以定位焊点,使得附接位于微线的将放置在IC芯片上的适当位置中的一部分内。然后切下245一段微线以供使用。在完成定位220和焊接225之后,可以通过从纳米定位器的尖端切割掉250微线段释放230微线段。
图3A是展示图2A的方法的一部分的工作区域300A的离子束视图的图。在背景中看到带有所附接的微线312的基板310。纳米定位器尖端314最初被焊接到一段微线312,然后该段微线312被切割掉以形成微线段316。箭头313指向微线312和微线段316上进行切割的位置。图3中还示出的是作为气体注入系统的一部分的喷嘴318。为了比较,喷嘴318的直径约为一毫米。在一个实施例中,纳米定位器是牛津仪器纳米操纵器(Oxford InstrumentsNano-Manipulator)。
图3B是在已经完成方法200之后FIB腔室的工作区域300B的进一步图。如在工作区域300B中所见,IC芯片322包含接合焊盘324。已经使用铂焊点328A将微线段326附接到接合焊盘324。还已经添加了附加铂焊点328B、328C、328D,以进一步固定微线段326。微线段326长约500μm、并且直径约为1μm。尽管微线326未示出附接到第二导电元件,但是图3B清楚地展示了在IC芯片上放置和附接外部创建的微线的能力。在此实施例中,微线326上的电阻使用4点开尔文测量方法在90μm的长度上测量为1.6欧姆;该电阻比使用FIB沉积方法的电阻好两个数量级。
图2B至图2F各自示出了在方法200的元素上进一步扩展的元素或可以是方法200的一部分的附加元素。这些附加元素中的每一个都结合图4A至图4F进行描述,图4A至图4F描绘了其中可以利用所描述的微线在电路编辑期间形成新连接或作为生产电路封装件的常规部分的多种方式。在图2B中,扩展了将微线节段焊接225到位的元素,以阐明微线节段的第一端被焊接260到IC芯片上的第一导电元件并且微线节段的第二端被焊接到IC芯片上的第二导电元件。尽管在该示例中仅耦合了两个导电元件,但是可以使用一个或多个微线将多个导电元件耦合在一起。
元素260的最简单示例在图4A中示出,其描绘了IC芯片400A的横截面,该IC芯片400A包含通过导电焊点(未具体示出)附接到第一导电元件404和第二导电元件406的微线段408。第一导电元件404和第二导电元件406可以是例如均嵌入层间电介质402中的金属层的接合焊盘或节段。虽然这种类型的电路编辑在当前FIB技术的能力内,但是以所描述的方式附接的微线可以提供低得多的电阻,并且能够比使用例如沉积在FIB中的铂的连接传导更大的电流。在一个实施例中,该示例可以被保留用于需要较低电阻和载流能力的特定电路编辑。
另一个示例在图4B中示出,其描绘了IC芯片400B的横截面。IC芯片400B包括升高到IC芯片400B的表面411上方的第一导电元件414和第二导电元件416。第一导电元件414和第二导电元件416可以是在层间电介质412的顶部上形成的顶部铜层或BOAC层的一部分。第一导电元件414和第二导电元件416的高度和底切侧都使得在没有首先在两个导电元件之间沉积电介质的情况下不可能使用所沉积的金属形成连接,如图6B中所展示。然而,微线节段418足够坚硬以在第一导电元件414和第二导电元件416之间桥接。
已被添加以提供两个接合线和它们的相应接合焊盘之间的表面耦合和升高耦合的微线的示例在图3C中示出。在FIB腔室中已完成工作的进一步图中,IC芯片330包含接合焊盘332、334以及它们的相应接合线336、338。接合线336通过焊料接头(solder joint)340附接到接合焊盘332,并且接合线338通过焊料接头342附接到接合焊盘334。期望将接合线336和接合焊盘332耦合到接合线338和接合焊盘334。由于目标电阻,放置两个微线来形成耦合。在所示的实施例中,微线344通过焊点348附接到焊料接头340和焊料接头342。微线346被放置为空中耦合,并且通过焊点350附接到接合线336和接合线338。
第一导电元件和第二导电元件并不总是处于允许直线形成连接的位置。例如,第三导电元件可以位于第一导电元件和第二导电元件之间。使用FIB化学物质处理,只有通过首先在第三导电元件之上沉积一层电介质,然后沉积期望连接,才可以避免与第三导电元件的意外连接。然而,沉积在FIB中的电介质可能会发生泄漏,从而允许连接和第三导电元件之间的不希望的泄漏,并且花费大量时间。图2C描绘了在这种情况下可以添加到方法200的元素。在该实施例中,微线节段可以被成形265,以在第一导电元件和第二导电元件之间的第三导电元件之上拱起,而不触及第三导电元件。在一个实施例中,在定位微线之前,完成成形。在一个实施例中,可以将微线的第一端焊接就位,然后在焊接微线的第二端之前将微线弯曲或以其他方式成形为期望形状。
图4C描绘了IC芯片400C的横截面,其中第一导电元件434和第二导电元件436各自嵌入层间电介质432中,而第三导电元件437位于第一导电元件434和第二导电元件436之间的直接路径上。微线节段438已经弯曲或以其他方式成形以在第三导电元件437之上拱起,与第一导电元件434和第二导电元件436进行接触,而不与第三导电元件437进行任何接触。
值得注意的是,可能存在这样的情况,其中通过使用微线提供的新能力不仅可以在电路编辑期间使用,而且可以在芯片和芯片封装件的生产期间使用。微米尺寸的线可以用于与利用较大线完成的过程相同的过程中,但是具有更小的特征和更高的精度。例如,当前的接合焊盘通常在跨40微米至60微米的范围内,并且使用直径为25微米至40微米的接合线。如果接合焊盘为50微米×50微米,则微阵列的一侧将需要数百微米才能实现多个连接。相比之下,通过使用微线,可以使用更小的接合焊盘,从而潜在地允许更少的用于接合焊盘的基板面(real estate),或在相同尺寸的封装件中的更大数量的接合焊盘。
图2D描绘了当第二IC芯片被安装到第一IC芯片上或靠近第一IC芯片(例如,在多芯片模块中)时添加并阐明方法200的几个元素。再次,微线节段可以被成形270以用于附接在第一IC芯片上的第一接合焊盘和第二IC芯片上的第二接合焊盘之间。然后,扩展了将微线节段焊接225到位的元素,以阐明微线节段的第一端被焊接275到第一接合焊盘,并且微线节段的第二端被焊接到第二接合焊盘。
这种用法的一个示例在图4D中进行描绘。电路封装件400D包括具有第一接合焊盘443、444的第一IC芯片442。具有第二接合焊盘446、447的第二IC芯片445已经被安装在第一IC芯片442的顶部上。第二IC芯片445可以是例如电感器、电容器、一个或多个传感器、有源元件的微阵列、无源元件,或在制作期间或在制作后添加到第一IC芯片442的任何其他电路。微线448已经被成形和附接,以将第一接合焊盘443连接到第二接合焊盘446,并且微线449已经被成形和附接,以将第一接合焊盘444连接到第二接合焊盘447。
由于金属微线的延展性,这些微线可以被成形以形成可以添加到电路封装件(例如,IC芯片或IC封装件)的附加元件。图2E提供了用于方法200的附加元素,其中微线节段被成形280,以形成天线。一旦微线节段被成形和附接到电路封装件,就可以使用天线执行通信。
图4E描绘了包括嵌入ILD 452中的导电元件454的IC芯片400E的横截面。导电元件454再次可以是感兴趣的金属化层中的接合焊盘或触点等。微线456已经被成形以形成天线458,其附接到导电元件454,以提供通信能力。微线456的长度可以被调谐到期望频率。当然,天线458可以采用与图4E中所示的形状不同的许多形状。
图2F提供了可以添加到方法200的另一元素,其中微线节段被成形285以形成微电感器。电感器很难用半导体处理来制造,因为电感器形成大的且具有挑战性的结构。将微线成形为可以固定到IC芯片的微电感器提供了替代的制造方法。图4F描绘了IC芯片400F,其包括嵌入ILD 462中的第一导电元件466和第二导电元件468。微线463已经被成形以形成微电感器464,其附接到第一导电元件466和第二导电元件468。可以调节线圈的直径和线圈的紧密度,以实现期望电感。
所描述的微线的引入在IC芯片的制造中的当前能力与FIB的能力之间提供了一种桥接。微线的制造和使用可以提供以前在电路编辑技术中不可用的新能力,诸如在两个凸起元件之间进行桥接、在中间导电元件之上拱起以及提供能够承载更大电流的连接。微线还可以提供执行现有功能的新方法,这样实现更小的接合焊盘并提供天线和微电感器,现在可以以更小量级的尺寸制造天线和微电感器。随着IC芯片及其相关联的封装件继续在尺寸上缩小,所描述的微线的使用可以开辟进一步的可能性。
尽管已经详细示出和描述了各种实施例,但是权利要求不限于任何特定实施例或示例。以上具体实施方式均未暗示任何特定部件、元件、步骤、动作或功能是必不可少的,使得其必须被包括在权利要求的范围内。除非明确说明,否则以单数形式对元素的引用并不意味着“一个且只有一个”,而是“一个或多个”。本领域普通技术人员已知的上述实施例的元素的所有结构和功能等效物通过引用明确地并入本文,并且由本权利要求涵盖。因此,本领域的技术人员将认识到,在所附权利要求的精神和范围内,可以通过各种修改和改变实践本文描述的示例性实施例。
Claims (22)
1.一种集成电路封装件即IC封装件,其包括:
第一导电元件,其被制造为所述IC封装件的一部分;以及
微线,其具有耦合到所述第一导电元件的第一端,所述微线已经被异位制造并且包括具有10微米或更小的直径的金属。
2.根据权利要求1所述的IC封装件,其中所述微线形成天线。
3.根据权利要求1所述的IC封装件,还包括制造为所述IC封装件的一部分的第二导电元件,其中所述微线的第二端耦合到所述第二导电元件。
4.根据权利要求3所述的IC封装件,其中所述第一导电元件和所述第二导电元件各自被抬高到所述IC封装件的IC芯片的表面上方。
5.根据权利要求3所述的IC封装件,其中所述微线被成形以在所述第一导电元件和所述第二导电元件之间的第三导电元件之上延伸,而不触及所述第三导电元件。
6.根据权利要求3所述的IC封装件,其中所述第一导电元件包括在所述IC封装件的第一IC芯片上的第一接合焊盘,并且所述第二导电元件包括在所述IC封装件的第二IC芯片上的第二接合焊盘,所述第二IC芯片被安装在所述第一IC芯片上,并且进一步其中所述微线被成形以附接到所述第一接合焊盘和所述第二接合焊盘。
7.根据权利要求3所述的IC封装件,其中所述微线被成形以形成微电感器。
8.一种制造电路封装件的方法,所述方法包括:
安装用于运送的微线,所述微线由金属形成并具有10微米或更小的直径;
将所安装的微线和所述电路封装件引入聚焦离子束装置即FIB装置中,所述FIB装置包括FIB显微镜和纳米定位器;
将所述微线、所述纳米定位器和所述电路封装件带入用于所述FIB装置的工作区域中;
使用所述纳米定位器将所述微线和所述电路封装件在用于附接的位置处结合在一起;
将所述微线焊接到位;以及
释放所述微线。
9.根据权利要求8所述的方法,其中所述FIB装置还包括扫描电子显微镜(SEM)。
10.根据权利要求8所述的方法,其中所述纳米定位器包括从由下列项组成的组中选择的元件:细长尖端、微型夹持器、微机电(MEM)器件和使用静电力进行定位的器件。
11.根据权利要求8所述的方法,其中将所述微线焊接到位使用从一组有机金属前体中选择的前体气体,所述一组有机金属前体包括(三甲基环戊二烯)三甲基铂(C9H17Pt)和六羰基钨(W(CO)6)。
12.根据权利要求8所述的方法,其中所述电路封装件包括从由下列项组成的组中选择的元件:单个IC芯片、附接在一起的多个IC芯片、芯片到器件封装件和器件到器件封装件,其中所述器件是非IC电气部件或电路。
13.根据权利要求8所述的方法,还包括使所述微线成形以形成天线。
14.根据权利要求8所述的方法,还包括使所述微线成形以形成微电感器。
15.根据权利要求8所述的方法,其中将所述微线焊接到位包括:将所述微线的第一端焊接到所述电路封装件的第一IC芯片上的第一导电元件,以及将所述微线的第二端焊接到所述第一IC芯片上的第二导电元件。
16.根据权利要求15所述的方法,还包括使所述微线成形以在所述第一导电元件和所述第二导电元件之间的第三导电元件之上拱起。
17.根据权利要求8所述的方法,其中所述电路封装件包括第一IC芯片,在所述第一IC芯片上安装有第二IC芯片,所述方法还包括:
使所述微线成形以附接在所述第一IC芯片上的第一接合焊盘和所述第二IC芯片上的第二接合焊盘之间,
其中将所述微线焊接到位包括将所述微线的第一端焊接到所述第一接合焊盘以及将所述微线的第二端焊接到所述第二接合焊盘。
18.根据权利要求8所述的方法,其中使用所述纳米定位器将所述微线和所述电路封装件结合在一起包括:将所述纳米定位器的尖端焊接到所安装的微线;切断微线段;以及将所述微线段定位在用于附接的位置处,并且进一步其中释放所述微线包括:从所述纳米定位器的所述尖端切割掉所述微线段。
19.一种用于制造微线的方法,包括:
将一段预成形线悬浮在具有已知浓度和温度的蚀刻剂溶液中一段时间,以实现10微米或更小的直径,所述预成形线包括导电金属;
从所述蚀刻剂溶液中去除所蚀刻的线;以及
冲洗所蚀刻的线。
20.根据权利要求19所述的方法,其中所述导电金属是钨,并且所述蚀刻剂溶液是浓度为约30%且温度为约110℃的过氧化氢。
21.根据权利要求19所述的方法,其中所述导电金属是铜,并且所述蚀刻剂溶液是稀硝酸。
22.根据权利要求19所述的方法,其中所述导电金属是铝,并且所述蚀刻剂溶液是稀盐酸。
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US16/592,102 US11233017B2 (en) | 2019-10-03 | 2019-10-03 | Ex-situ manufacture of metal micro-wires and FIB placement in IC circuits |
PCT/US2020/054202 WO2021067908A1 (en) | 2019-10-03 | 2020-10-05 | Ex-situ manufacture of metal micro-wires and fib placement in 1c circuits |
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JPS61287133A (ja) * | 1985-06-13 | 1986-12-17 | Matsushita Electric Ind Co Ltd | 半導体装置の製造方法 |
KR100623099B1 (ko) * | 1994-11-15 | 2006-09-13 | 폼팩터, 인크. | 두 개의 전자부품 사이의 전기적 연결부 |
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US7262491B2 (en) * | 2005-09-06 | 2007-08-28 | Advanced Interconnect Technologies Limited | Die pad for semiconductor packages and methods of making and using same |
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US20130174900A1 (en) * | 2011-07-07 | 2013-07-11 | Stion Corporation | Nanowire enhanced transparent conductive oxide for thin film photovoltaic devices |
US20140338076A1 (en) * | 2012-02-04 | 2014-11-13 | NaugaNeedles, LLC | Methods and Apparatuses for Specimen Lift-Out and Circuit Edit Using Needle Arrays |
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