CN114765138A - 半导体装置 - Google Patents

半导体装置 Download PDF

Info

Publication number
CN114765138A
CN114765138A CN202210017267.6A CN202210017267A CN114765138A CN 114765138 A CN114765138 A CN 114765138A CN 202210017267 A CN202210017267 A CN 202210017267A CN 114765138 A CN114765138 A CN 114765138A
Authority
CN
China
Prior art keywords
low moisture
permeable sheet
semiconductor device
case
cover
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202210017267.6A
Other languages
English (en)
Inventor
川端大辅
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Publication of CN114765138A publication Critical patent/CN114765138A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/564—Details not otherwise provided for, e.g. protection against moisture
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/10—Containers; Seals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45147—Copper (Cu) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H01L2224/48139—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate with an intermediate bond, e.g. continuous wire daisy chain
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/072—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

减少半导体装置中的水分的侵入路径。半导体装置(100)具有：半导体元件(1)；壳体(2)，其收容有半导体元件(1)；封装材料(3)，其被填充于壳体(2)内；低透湿片(11)，其将封装材料(3)覆盖；以及盖(12)，其将壳体(2)的开口部堵塞。低透湿片(11)由透湿度小于或等于1g/m2×24Hr的低透湿性材料构成。低透湿片(11)的周缘部被壳体(2)与盖(12)夹持。

Description

半导体装置
技术领域
本发明涉及半导体装置。
背景技术
将半导体元件封装于壳体内这一构造的电力控制用半导体装置被广为知晓。作为壳体的材料，大多采用聚苯硫醚(PPS)等高耐热高绝缘工程塑料。作为被填充于壳体的封装材料，采用硅类凝胶或环氧树脂。另外，在壳体设置有保护封装材料的盖，通常，该盖的材料使用与壳体的材料相同的材料。以下，有时也将电力控制用的半导体元件及半导体装置分别称为“功率半导体元件”及“功率半导体装置”。
伴随功率半导体元件的SiC元件化、Si元件的温度特性的提高，市场对功率半导体装置的要求逐渐扩大，例如，作为使用保障而要求迄今为止被用于参考试验的吸湿耐量。作为吸湿耐量试验，在JEITA ED-4701 102A所规定的高温高湿偏置(Temperature HumidityBias；THB)试验中，在例如温度85℃、湿度85％的环境下，实施施加规定电压的保存试验。
如果功率半导体装置内的透湿加深，则有可能功率半导体元件的表面、搭载该功率半导体元件的绝缘基板等高绝缘部件的表面处的绝缘电阻下降，功率半导体装置的寿命变短。特别地，由SiC构成的功率半导体元件的终端部收缩，由于是施加高电场的部位，因此由于吸湿而使终端部的绝缘电阻下降的不良影响大。
具有上述构造的功率半导体装置的透湿及吸湿的主要路径是壳体、盖的粘接界面、嵌合部。例如，在下述的专利文献1中公开了如下技术，即，为了抑制由半导体装置的使用环境造成的气体、水分等的侵入，在半导体装置的封装材料之上配置片材。
专利文献1：日本特开2014-150204号公报
在专利文献1的技术中，担心由于在片材与壳体之间产生间隙而导致水分从该间隙侵入。
发明内容
本发明就是为了解决这样的问题而提出的，其目的在于抑制水分向半导体装置的侵入。
本发明涉及的半导体装置具有：半导体元件；壳体，其收容有所述半导体元件；封装材料，其被填充于收容有所述半导体元件的所述壳体内；第1低透湿片，其将所述封装材料覆盖，由透湿度小于或等于1g/m2×24Hr的低透湿性材料构成；以及盖，其将所述壳体的开口部堵塞，所述第1低透湿片的周缘部被所述壳体与所述盖夹持。
发明的效果
根据本发明，能够减少水分向半导体装置内的侵入路径，因此水分向半导体装置的侵入受到抑制。
附图说明
图1是实施方式1涉及的半导体装置的剖面示意图。
图2是实施方式1中的低透湿片的斜视图。
图3是表示实施方式1涉及的半导体装置的制造工序的剖面示意图。
图4是表示实施方式1涉及的半导体装置的制造工序的剖面示意图。
图5是表示实施方式1涉及的半导体装置的制造工序的剖面示意图。
图6是表示实施方式1涉及的半导体装置的制造工序的剖面示意图。
图7是实施方式2涉及的半导体装置的剖面示意图。
图8是实施方式2中的低透湿片的俯视图及剖面图。
图9是实施方式3涉及的半导体装置的剖面示意图。
图10是实施方式3中的低透湿片的俯视图。
图11是表示实施方式3涉及的半导体装置的制造工序的剖面示意图。
图12是表示实施方式3涉及的半导体装置的制造工序的剖面示意图。
图13是表示实施方式3涉及的半导体装置的制造工序的剖面示意图。
图14是表示实施方式3涉及的半导体装置的制造工序的剖面示意图。
图15是实施方式4涉及的半导体装置的剖面示意图。
图16是表示实施方式4涉及的半导体装置的制造工序的剖面示意图。
图17是表示实施方式4涉及的半导体装置的制造工序的剖面示意图。
图18是表示实施方式4涉及的半导体装置的制造工序的剖面示意图。
图19是表示实施方式4涉及的半导体装置的制造工序的剖面示意图。
具体实施方式
＜实施方式1＞
图1是实施方式1涉及的半导体装置100的剖面示意图。如图1所示，半导体装置100是具有功率半导体元件即半导体元件1被收容于壳体2而通过封装材料3进行了封装的构造的功率半导体装置。半导体元件1是使用硅(Si)、碳化硅(SiC)、氮化镓(GaN)等而形成的IGBT(Insulated Gate Bipolar Transistor)或MOSFET(Metal Oxide SemiconductorField Effect Transistor)等。
半导体元件1搭载于绝缘基板4，绝缘基板4搭载于基座板6。绝缘基板4由绝缘层4a、在绝缘层4a的上表面形成的电路图案4b和在绝缘层4a的下表面形成的电路图案4c构成。半导体元件1经由接合材料5而与电路图案4b接合，基座板6经由接合材料7而与电路图案4c接合。
绝缘层4a及电路图案4b、4c的材料不受限制。绝缘层4a例如可以由氧化铝(Al2O3)、氮化铝(AlN)、氮化硅(Si3N4)等无机陶瓷材料构成。电路图案4b、4c例如可以由铜或其合金、铝或其合金等构成。作为接合材料5及接合材料7，使用由铅(Pb)或锡(Sn)等构成的焊料或焊料合金、或由纳米银或纳米铜颗粒构成的烧结材料等。接合材料5的材料与接合材料7的材料可以彼此相同，也可以不同。
基座板6的材料可以是铜、铝、铜-钼合金(CuMo)等金属材料，也可以是碳化硅-铝复合材料(AlSiC)或碳化硅-镁复合材料(MgSiC)等复合材料料。
壳体2也搭载于基座板6，壳体2使用粘接剂8(第2粘接剂)而与基座板6粘接。
在壳体2组装有用于与外部之间的连接的电极9。半导体元件1、电路图案4b及电极9经由金属导线10连接或直接连接而构成电气电路。作为电极9的材料，例如大多使用以铜(Cu)或其合金等为主体的金属。另外，也可以在电极9的表面设置有Ni等镀层。作为金属导线10的材料，使用铝(Al)、铜(Cu)或它们的合金等。
封装材料3被填充于壳体2内，将半导体元件1及搭载有半导体元件1的绝缘基板4封装。封装材料3的材料例如是如硅树脂或环氧树脂等这样的绝缘性树脂。
并且，在壳体2内以将封装材料3覆盖的方式而设置有由低透湿性材料构成的低透湿片11(第1低透湿片)。在实施方式1中，使用图2所示的平板状的低透湿片11。构成低透湿片11的低透湿性材料例如是如聚四氟乙烯(PTFE)这样的氟类树脂等水分及气体的透过性低的材料，优选其透湿度小于或等于1g/m2×24Hr。此外，透湿度由JIS Z0208的“防湿包装材料的透过湿度试验方法”等进行定义。
另外，为了防止半导体装置100的大型化，优选低透湿片11的厚度小于或等于3mm，更优选小于或等于1mm。低透湿片11也可以与封装材料3的上表面接触。
壳体2的开口部被盖12堵塞，盖12使用粘接剂13(第1粘接剂)而与壳体2粘接。如图1所示，低透湿片11的周缘部被壳体2与盖12夹持。壳体2及盖12的材料只要具有电绝缘性即可，例如，可以由环氧树脂或聚苯硫醚(PPS)树脂等形成。另外，粘接剂8、13可以是通常的硅类粘接剂，也可以由丙烯酸类树脂等低透湿材料构成。
这里，对图1的半导体装置100的由壳体2、低透湿片11及盖12形成的构造详细地进行说明。盖12具有与壳体2的开口部嵌合的形状的凸部12a，壳体2在开口部的周缘具有锪孔部2a。因此，如果盖12的凸部12a与壳体2的开口部嵌合，则凸部12a与锪孔部2a相对。低透湿片11延伸至壳体2的锪孔部2a之上，低透湿片11的周缘部被凸部12a与锪孔部2a夹持。
将壳体2与盖12粘接的粘接剂13配置于未夹持有低透湿片11的部分(在图1中是锪孔部2a及凸部12a的外侧的部分)，粘接剂13的厚度方向与被壳体2与盖12夹持的部分处的低透湿片11的厚度方向相同。由此，在粘接剂13固化收缩时，壳体2的锪孔部2a与盖12的凸部12a彼此拉拽，因此得到锪孔部2a及凸部12a与被夹持在其间的低透湿片11之间的密接性增加这一效果。特别地，如果低透湿片11由氟树脂这样的具有弹性的材料形成，则低透湿片11弹性变形，与锪孔部2a及凸部12a之间得到高的密接性。
根据实施方式1涉及的半导体装置100，在壳体2内将半导体元件1封装的封装材料3被由低透湿性材料构成的低透湿片11覆盖，并且低透湿片11的周缘部被壳体2与盖12夹持，由此，在壳体2与低透湿片11之间难以产生间隙。因此，水分向壳体2内的侵入路径变少，防止水分向壳体2内侵入，半导体装置100的防湿性提高。例如，即使在作为将壳体2与盖12粘接的粘接剂13而使用了通常的硅类粘接剂(透湿度为10g/m2×24Hr～100g/m2×24Hr左右)的情况下，也得到足够的防湿效果。另外，通过低透湿片11而得到高的防湿效果，因此，通过使涂布粘接剂13的区域的宽度变窄，也能够有助于半导体装置100的小型化。特别地，在半导体元件1是SiC元件的情况下，其终端部收缩，是施加高电场的部位，由于吸湿而使终端部的绝缘电阻下降的不良影响大，因此，上述效果是有效的。
也可以在低透湿片11的表面设置凹凸而使低透湿片11的表面粗化。通过使低透湿片11的表面粗化，从而低透湿片11与封装材料3之间的密接性提高，能够期待进一步抑制水分的侵入路径。低透湿片11的粗化的方法可以是物理方法也可以是化学方法。例如，想到在用于使低透湿片11成型的模具的表面设置凹凸的方法等。
这里，对半导体装置100的制造方法进行说明。首先，将基座板6、接合材料7、绝缘基板4、接合材料5及半导体元件1依次堆叠，进行减压或还原气体氛围中的回流，给予大于或等于接合材料5及接合材料7的熔融温度的热履历，由此将各部件间接合。接下来，通过金属导线10的超声波接合而进行半导体元件1彼此间或半导体元件1与绝缘基板4之间的配线。
接下来，向基座板6的外周部(与壳体2之间的粘接部)线状地涂布粘接剂8，在粘接剂8之上载置壳体2，使粘接剂8热固化，由此将基座板6与壳体2粘接。然后，通过超声波接合而将组装于壳体2的电极9与绝缘基板4接合。
接下来，如图3所示，在壳体2内填充封装材料3，使用烤炉等使封装材料3热固化，由此将半导体元件1封装。然后，如图4所示，通过低透湿片11而将封装材料3覆盖。此时，低透湿片11的周缘部被载置于壳体2的锪孔部2a。
然后，如图5所示，向壳体2的缘部(与盖12之间的粘接部)线状或点状地涂布粘接剂13。然后，如图6所示，使盖12的凸部12a嵌合于壳体2的开口，并且通过盖12将壳体2的开口堵塞。此时，盖12的凸部12a抵接于低透湿片11的周缘部的上表面。然后，使粘接剂13热固化，将壳体2与盖12粘接。在粘接剂13固化收缩时，壳体2的锪孔部2a及盖12的凸部12a彼此拉拽，锪孔部2a及凸部12a与夹持在其间的低透湿片11之间的密接性增加。通过以上工序，完成图1所示的半导体装置100。
＜实施方式2＞
图7是实施方式2涉及的半导体装置的剖面示意图。另外，图8是实施方式2中的低透湿片11的俯视图及剖面图。在实施方式2中，低透湿片11在其周缘部即被壳体2与盖12夹持的部分具有凸部11a，在壳体2设置有供低透湿片11的凸部11a插入的槽2b。
另外，在本实施方式中，凸部11a设置于低透湿片11的端部，因此，低透湿片11的端部在剖视观察时呈L字型(如图8所示，如果以低透湿片11的剖面整体来观察，则呈“コ”字型)。另外，壳体2的槽2b设置于锪孔部2a。其它结构与实施方式1(图1)相同。
在低透湿片11设置凸部11a的方法可以是任意方法。例如，可以通过用于对低透湿片11进行成型的模具而形成凸部11a，也可以对图2所示这样的平板状的低透湿片11的下表面进行切削加工而形成凸部11a。
根据实施方式2的半导体装置100，除了与实施方式1相同的效果以外，还通过提高低透湿片11相对于壳体2的定位精度及低透湿片11的保持性，从而得到能够进一步提高半导体装置100的吸湿耐量的效果。
＜实施方式3＞
图9是实施方式3涉及的半导体装置100的剖面示意图。如图9所示，就实施方式3的半导体装置100而言，在壳体2与基座板6之间的粘接界面设置有低透湿片14(第2低透湿片)。低透湿片14的形状如图10所示在俯视观察时呈框状，以将封装材料3包围的方式在壳体2与基座板6之间的粘接界面延伸。构成低透湿片14的低透湿性材料可以与将封装材料3覆盖的低透湿片11相同，优选其透湿度小于或等于1g/m2×24Hr。
为了防止半导体装置100的大型化，优选低透湿片14的厚度小于或等于3mm，更优选小于或等于1mm。另外，也可以在壳体2与基座板6之间的粘接界面嵌套状地配置多个框状的低透湿片14。
另外，在本实施方式中，在壳体2的与基座板6之间的粘接界面形成有供低透湿片14的一部分插入的槽2c，在基座板6的与壳体2之间的粘接界面也形成有供低透湿片14的一部分插入的槽6a。因此，低透湿片14的厚度形成得比将壳体2与基座板6粘接的粘接剂8的厚度大。另外，低透湿片14在粘接剂8的内部延伸。即，粘接剂8设置于低透湿片14的两侧。其它结构与实施方式1(图1)相同。
对实施方式3的半导体装置100的制造方法进行说明。首先，将具有槽6a的基座板6、接合材料7、绝缘基板4、接合材料5及半导体元件1依次堆叠，进行减压或还原气体氛围中的回流，给予大于或等于接合材料5及接合材料7的熔融温度的热履历，由此将各部件间接合。接下来，通过金属导线10的超声波接合而进行半导体元件1彼此之间或半导体元件1与绝缘基板4之间的配线。其结果，得到图11的结构。
接下来，如图12所示，向基座板6的外周部(与壳体2之间的粘接部)处的槽6a的两侧线状地涂布粘接剂8。另外，如图13所示，在基座板6之上载置低透湿片14。此时，将低透湿片14的下部插入至槽6a。然后，如图14所示，在粘接剂8之上载置具有槽2c的壳体2。此时，将低透湿片14的上部插入至槽2c。然后，使粘接剂8热固化，由此将基座板6与壳体2粘接。
然后，与实施方式1同样地，将组装于壳体2的电极9与半导体元件1或绝缘基板4接合，通过封装材料3而将半导体元件1封装，通过低透湿片11将封装材料3覆盖，然后，将盖12粘接于壳体2。由此，完成图9所示的半导体装置100。
根据实施方式3的半导体装置100，除了与实施方式1相同的效果以外，还得到降低通过壳体2与基座板6之间的粘接剂8产生的吸湿，能够进一步提高半导体装置100的吸湿耐量的效果。
＜实施方式4＞
图15是实施方式4涉及的半导体装置100的剖面示意图。相对于实施方式3(图9)的结构，实施方式4涉及的半导体装置100的结构使在壳体2与基座板6之间的粘接界面设置的低透湿片14的厚度与粘接剂8的厚度相同。由于低透湿片14的厚度与粘接剂8的厚度相同，因此，不需要实施方式2中在壳体2设置的槽2c及在基座板6设置的槽6a，能够有助于生产率的提高及加工成本的降低。
对实施方式4的半导体装置100的制造方法进行说明。首先，将基座板6、接合材料7、绝缘基板4、接合材料5及半导体元件1依次堆叠，进行减压或还原气体氛围中的回流，给予大于或等于接合材料5及接合材料7的熔融温度的热履历，由此将各部件间接合。接下来，通过金属导线10的超声波接合而进行半导体元件1彼此之间或半导体元件1与绝缘基板4之间的配线。其结果，得到图16的结构。
接下来，如图17所示，向基座板6的外周部(与壳体2之间的粘接部)处的低透湿片14的设置位置的两侧线状地涂布粘接剂8。然后，如图18所示，在基座板6之上载置低透湿片14。与实施方式3不同，在基座板6不存在供低透湿片14插入的槽6a，但低透湿片14的位置通过膏状的粘接剂8而被固定。然后，如图19所示，在粘接剂8之上载置壳体2，使粘接剂8热固化，由此将基座板6与壳体2粘接。
然后，与实施方式1同样地，将组装于壳体2的电极9与半导体元件1或绝缘基板4接合，通过封装材料3将半导体元件1封装，通过低透湿片11而将封装材料3覆盖，然后，将盖12粘接于壳体2。由此，完成图15所示的半导体装置100。
此外，能够对各实施方式自由地进行组合，或对各实施方式适当地进行变形、省略。
标号的说明
1半导体元件，2壳体，2a锪孔部，2b槽，2c槽，3封装材料，4绝缘基板，4a绝缘层，4b电路图案，4c电路图案，5接合材料，6基座板，6a槽，7接合材料，8粘接剂，9电极，10金属导线，11低透湿片，11a凸部，12盖，12a凸部，13粘接剂，14低透湿片，100半导体装置。

Claims (10)

1.一种半导体装置，其具有：
半导体元件；
壳体，其收容有所述半导体元件；
封装材料，其被填充于收容有所述半导体元件的所述壳体内；
第1低透湿片，其将所述封装材料覆盖，由透湿度小于或等于1g/m2×24Hr的低透湿性材料构成；以及
盖，其将所述壳体的开口部堵塞，
所述第1低透湿片的周缘部被所述壳体与所述盖夹持。
2.根据权利要求1所述的半导体装置，其中，
所述壳体在所述开口部的周缘具有锪孔部，
所述盖具有与所述壳体的所述开口部嵌合的凸部，
所述第1低透湿片被所述壳体的所述锪孔部与所述盖的所述凸部夹持。
3.根据权利要求1或2所述的半导体装置，其中，
所述壳体与所述盖是在未夹持所述第1低透湿片的部分处使用第1粘接剂而粘接的，
所述第1粘接剂的厚度方向与被所述壳体与所述盖夹持的部分处的所述第1低透湿片的厚度方向相同。
4.根据权利要求1至3中任一项所述的半导体装置，其中，
所述第1低透湿片在被所述壳体与所述盖夹持的部分处具有凸部，
所述壳体具有供所述第1低透湿片的所述凸部插入的槽。
5.根据权利要求1至4中任一项所述的半导体装置，其中，
所述壳体被使用第2粘接剂而与搭载有所述半导体元件的基座板粘接，
还具有框状的第2低透湿片，该第2低透湿片在所述壳体与所述基座板之间的粘接界面延伸，该第2低透湿片由透湿度小于或等于1g/m2×24Hr的低透湿性材料构成。
6.根据权利要求5所述的半导体装置，其中，
在所述壳体与所述基座板之间的粘接界面处，所述第2粘接剂设置于所述第2低透湿片的两侧。
7.根据权利要求5或6所述的半导体装置，其中，
所述壳体及所述基座板具有供所述第2低透湿片的一部分插入的槽。
8.根据权利要求5或6所述的半导体装置，其中，
所述第2低透湿片的厚度与所述第2粘接剂的厚度相同。
9.根据权利要求1至8中任一项所述的半导体装置，其中，
在所述第1低透湿片的表面设置有凹凸。
10.根据权利要求1至9中任一项所述的半导体装置，其中，
所述低透湿性材料是氟类树脂。
CN202210017267.6A 2021-01-14 2022-01-07 半导体装置 Pending CN114765138A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2021-004053 2021-01-14
JP2021004053A JP7479307B2 (ja) 2021-01-14 2021-01-14 半導体装置

Publications (1)

Publication Number Publication Date
CN114765138A true CN114765138A (zh) 2022-07-19

Family

ID=82116338

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202210017267.6A Pending CN114765138A (zh) 2021-01-14 2022-01-07 半导体装置

Country Status (4)

Country Link
US (1) US20220223545A1 (zh)
JP (1) JP7479307B2 (zh)
CN (1) CN114765138A (zh)
DE (1) DE102021131049A1 (zh)

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6230895B1 (en) * 1999-08-20 2001-05-15 David P. Laube Container for transporting refurbished semiconductor processing equipment
WO2014034024A1 (ja) * 2012-08-30 2014-03-06 パナソニック株式会社 電子部品パッケージおよびその製造方法
WO2015111202A1 (ja) * 2014-01-27 2015-07-30 株式会社日立製作所 半導体モジュール
US11476170B2 (en) 2018-06-12 2022-10-18 Mitsubishi Electric Corporation Power semiconductor module and power conversion apparatus

Also Published As

Publication number Publication date
US20220223545A1 (en) 2022-07-14
JP7479307B2 (ja) 2024-05-08
DE102021131049A1 (de) 2022-07-14
JP2022108862A (ja) 2022-07-27

Similar Documents

Publication Publication Date Title
CN108292655B (zh) 功率模块
US9754855B2 (en) Semiconductor module having an embedded metal heat dissipation plate
JP6057926B2 (ja) 半導体装置
JP6676079B2 (ja) 半導体装置およびその製造方法
JP6057927B2 (ja) 半導体装置
JP2015198227A (ja) 半導体装置
JP6041795B2 (ja) 半導体装置
JP2019071392A (ja) 半導体装置
US20230197542A1 (en) Module with Gas Flow-Inhibiting Sealing at Module Interface to Mounting Base
US7868430B2 (en) Semiconductor device
JP6095303B2 (ja) 半導体装置および半導体装置の製造方法
CN114078790A (zh) 功率半导体模块装置及其制造方法
CN114765138A (zh) 半导体装置
US11626333B2 (en) Semiconductor device
CN115132669A (zh) 外壳、半导体模块及其生产方法
JP6811310B2 (ja) パワーモジュール
US11581229B2 (en) Power semiconductor module with adhesive filled tapered portion
US11616024B2 (en) Storage device including semiconductor chips sealed with resin on metal plate
JP2013135161A (ja) 半導体装置およびその製造方法
JP7157783B2 (ja) 半導体モジュールの製造方法及び半導体モジュール
US20220157673A1 (en) Module-type semiconductor device and method of manufacturing module-type semiconductor device
CN115411002A (zh) 半导体装置及半导体装置的制造方法
JP2023182178A (ja) 半導体装置
CN115116865A (zh) 半导体装置的制造方法
CN116564903A (zh) 半导体装置和半导体装置的制造方法

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination