CN114765129A - 半导体装置结构 - Google Patents

半导体装置结构 Download PDF

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Publication number
CN114765129A
CN114765129A CN202210171561.2A CN202210171561A CN114765129A CN 114765129 A CN114765129 A CN 114765129A CN 202210171561 A CN202210171561 A CN 202210171561A CN 114765129 A CN114765129 A CN 114765129A
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layer
gate
self
aligned contact
source
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王圣璁
黄麟淯
庄正吉
王志豪
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明实施例提供一种半导体装置结构。半导体装置结构包括栅极介电层、栅极层、第一自对准接点层、隔离层以及第一侧壁间隔物。栅极层接触栅极介电层；第一自对准接点层位于栅极层上；隔离层位于栅极层与第一自对准接点层之间；第一侧壁间隔物接触栅极介电层、隔离层以及第一自对准接点层。

Description

半导体装置结构
技术领域
本发明实施例涉及半导体装置结构，尤其涉及隔离层位于自对准接点层与栅极层之间以阻挡氧扩散至栅极层的结构。
背景技术
集成电路通常包含多个半导体装置如场效晶体管与内连线层形成于半导体基板上。由于持续改善多种电子构件(比如切换源极与漏极之间的电流所用的栅极)的效能，半导体产业已经历持续的快速成长。然而在集成电路的工艺时可能损伤栅极与其效能。因此目前亟需改善处理与制造集成电路的方法。
发明内容
本发明一些实施例提供半导体装置结构。半导体装置结构包括栅极介电层；栅极层，接触栅极介电层；第一自对准接点层，位于栅极层上；隔离层，位于栅极层与第一自对准接点层之间；以及第一侧壁间隔物，接触栅极介电层、隔离层以及第一自对准接点层。
本发明一些实施例提供半导体装置结构。半导体装置结构包括第一源极/漏极结构与第二源极/漏极结构；以及通道层，位于第一源极/漏极结构与第二源极/漏极结构之间并接触第一源极/漏极结构与第二源极/漏极结构，其中通道层的组成为半导体层。半导体装置结构包括栅极介电层，围绕通道层的至少一表面；栅极层，围绕栅极介电层的至少一表面；以及第一自对准接点层，位于栅极层上，其中第一自对准接点层包括介电材料。半导体装结构还包括隔离层，位于栅极层与第一自对准接点层之间；以及第一侧壁间隔物，接触栅极介电层、第一自对准接点层、与隔离层。
本发明一些实施例提供半导体装置结构的形成方法。方法包括形成鳍状结构，其具有多个通道层位于其上；形成牺牲栅极结构于鳍状结构的一部分上；形成侧壁间隔物于牺牲栅极结构的两侧上；移除牺牲栅极结构以露出通道层的部分；形成栅极介电层于通道层的露出部分上；形成栅极层于栅极介电层上；移除栅极层与栅极介电层的部分，使栅极层与栅极介电层的上表面低于侧壁间隔物的上表面；形成隔离层于栅极层与栅极介电层上，其中隔离层包括不含氧原子的介电材料；以及形成自对准接点层于隔离层上。
附图说明
图1至图4为一些实施例中，制造半导体装置结构的多种阶段的透视图。
图5至图14为本发明实施例中，半导体装置结构在多种制作阶段中沿着图4的剖线A-A的剖视图。
图15为一些实施例中，半导体装置结构沿着图4的剖线B-B的剖视图。
图16为一些实施例中，半导体装置结构沿着图4的剖线C-C的剖视图。
附图标记如下：
A-A,B-B,C-C:剖线
H1,H2,H3,H4:高度
T1,T2:厚度
10:基板
12,14:半导体层
16,28:垫层
18:硬掩模
20:鳍状结构
22,45:隔离层
24:牺牲栅极介电层
26:牺牲栅极层
30:掩模层
32:牺牲栅极结构
33,34:侧壁间隔物
35:内侧间隔物
36:源极/漏极结构
38:接点蚀刻停止层
40:层间介电层
41:衬垫层
42:栅极介电层
43:金属层
44:栅极层
46:沟槽
50:第一自对准接点层
50a:底部
50b:顶部
51:接点孔
52:硅化物层
54:阻挡层
56:源极/漏极金属接点
58:隔离孔
60:第二自对准接点层
100:半导体装置结构
具体实施方式
下述详细描述可搭配附图说明，以利理解本发明的各方面。值得注意的是，各种结构仅用于说明目的而未按比例绘制，如本业常态。实际上为了清楚说明，可任意增加或减少各种结构的尺寸。
下述内容提供的不同实施例或实例可实施本发明的不同结构。下述特定构件与排列的实施例用以简化本发明内容而非局限本发明。举例来说，形成第一构件于第二构件上的叙述包含两者直接接触的实施例，或两者之间隔有其他额外构件而非直接接触的实施例。此外，本发明的多个实例可重复采用相同标号以求简洁，但多种实施例及/或设置中具有相同标号的元件并不必然具有相同的对应关系。
此外，空间性的相对用语如“下方”、“其下”、“较下方”、“上方”、“较上方”或类似用语可用于简化说明某一元件与另一元件在图示中的相对关系。空间性的相对用语可延伸至以其他方向使用的元件，而非局限于图示方向。元件亦可转动64°或其他角度，因此方向性用语仅用以说明图示中的方向。
虽然本发明实施例以纳米片通道场效晶体管作说明，但本发明实施例亦可实施于其他工艺及/或其他装置，比如平面场效晶体管、鳍状场效晶体管、水平全绕式栅极场效晶体管、垂直全绕式栅极场效晶体管或其他合适装置。本技术领域中技术人员应理解其他调整亦属于本发明实施例的范畴。
图1至图16为本发明实施例中，制造半导体装置结构100的例示性工艺。可以理解的是，可在图1至图16所示的工艺之前、之中、与之后提供额外步骤，且方法的额外实施例可置换或省略一些下述步骤。步骤及/或工艺的顺序不限于所述顺序而可交换。
图1至图4为一些实施例中，制造半导体装置结构100的多种阶段的透视图。如图1所示，形成鳍状结构20于半导体的基板10上。提供基板10以形成半导体装置结构100于其上。基板10可包含单晶半导体材料，比如但不限于硅、锗、硅锗、砷化镓、锑化铟、磷化镓、锑化镓、砷化铝铟、砷化镓铟、磷化镓锑、砷化镓锑或磷化铟。基板10可包含多种掺杂设置，端视电路设计而定。举例来说，可形成不同的掺杂轮廓如n型井或p型井于基板10的区域中。而这些区域设计为用于不同的装置型态如n型场效晶体管或p型场效晶体管。在一些实施例中，基板10可为绝缘层上硅基板，其包括绝缘结构(如氧化物)位于两个硅层之间以增进效能。
为了形成鳍状结构20，可形成一或多对的半导体层12与半导体层14于基板10上。半导体层12及14的形成方法可为分子束外延工艺、有机金属化学气相沉积工艺及/或其他合适的外延成长工艺。在一些实施例中，半导体层14与基板10包括相同材料。在一些实施例中，半导体层12及14包括的材料与基板10不同。在一些实施例中，半导体层12及14的材料具有不同晶格常数。最终移除通道区中的半导体层12，以定义之后形成的多栅极装置的相邻通道区之间的垂直距离。在一些实施例中，半导体层12包括外延成长的硅锗层，而半导体层14包括外延成长的硅层。在一些其他实施例中，半导体层12及14可包含其他材料如锗、半导体化合物(如碳化硅、砷化锗、磷化镓、磷化铟、砷化铟及/或锑化铟)、半导体合金(如硅锗、磷砷化镓、砷化铝铟、砷化铝镓、砷化镓铟、磷化镓铟及/或磷砷化镓铟)或上述的组合。
鳍状结构20的形成方法可为图案化成对的半导体层12及14上的垫层16与硬掩模18，接着蚀刻穿过成对的半导体层12及14与基板10的一部分。
如图2所示，形成鳍状结构20之后，形成隔离层22于鳍状结构20之间的沟槽中。形成隔离层22于基板10上，接着回蚀刻隔离层22以露出成对的半导体层12及14。隔离层22的上表面可与接触基板10的最底部的半导体层12的表面等高，或与最底部的半导体层12的表面齐平。在一些实施例中，隔离层22可包含氧化硅、氮化硅、氮氧化硅、氟硅酸盐玻璃、低介电常数的介电层或上述的组合。
接着形成牺牲栅极结构32于鳍状结构20上，并形成侧壁间隔物33及34于牺牲栅极结构32的侧部上。牺牲栅极结构32可包含牺牲栅极介电层24、牺牲栅极层26、垫层28、与掩模层30。牺牲栅极介电层24可包含一或多层的介电材料，比如氧化硅、氮化硅、高介电常数的介电材料及/或其他合适的介电材料。牺牲栅极层26可包含硅如多晶硅或非晶硅。垫层28可包含氮化硅。掩模层30可包含氧化硅。接着可在掩模层30、垫层28、牺牲栅极层26、与牺牲栅极介电层24上进行图案化步骤，以形成牺牲栅极结构32。
侧壁间隔物33及34形成于每一牺牲栅极结构32的侧壁上。侧壁间隔物33及34的组成可为任何合适的介电材料。在一些实施例中，侧壁间隔物33可包含或可为介电材料，比如氮化硅、锆硅化物、碳氮化硅、氧化锆铝、氧化钛、氧化钽、氧化锆、氧化镧、氮化锆、碳化硅、氧化锌、碳氧化硅、氧化铪、氧化镧、氧化铝、碳氮氧化硅、铪硅化物、氮氧化铝、氧化钇、碳氮化钽、氧化硅或任何上述的组合。侧壁间隔物33的厚度T1可为约1nm至约10nm。类似地，侧壁间隔物34与侧壁间隔物33可包含或可为相同材料。侧壁间隔物34的厚度T2可为约1nm至约10nm。在一些实施例中，侧壁间隔物33与侧壁间隔物34的组成为不同材料。举例来说，侧壁间隔物33的组成可为氧化硅为主的材料如氧化硅，而侧壁间隔物34的组成可为氮化硅为主的材料如氮化硅。虽然图2显示侧壁间隔物33及34，一些实施例可省略侧壁间隔物33及34的任一者。
如图3所示，源极/漏极结构36形成于牺牲栅极结构32的两侧上。源极/漏极结构36的形成方法可为回蚀刻牺牲栅极结构32未覆盖的鳍状结构20的部分(或鳍状结构20露出的部分)、自侧壁间隔物33及34之下回蚀刻半导体层12以形成内侧间隔物空洞、形成内侧间隔物35(如图5所示)于内侧间隔物空洞中以及自第二半导体层14与基板10的露出表面外延成长源极/漏极结构36。
内侧间隔物35的组成可为介电材料，比如氧化硅、氮化硅、碳化硅、碳氮化硅、碳氧化硅、氮氧化硅、碳氮氧化硅或上述的组合。在一些实施例中，内侧间隔物35可包含氮化硅、氧化硅、碳氮氧化硅或上述的组合。
源极/漏极结构36可包含一或多种半导体材料，端视装置型态而定。源极/漏极结构36可为外延材料，其厚度可介于约0.5nm至约30nm之间。
对n型装置而言，源极/漏极结构36可包含一或多层的硅、磷化硅、碳化硅、碳磷化硅或III-V族材料(如磷化铟、砷化镓、砷化铝、砷化铟、砷化铝铟或砷化镓铟)。在一些实施例中，源极/漏极结构36可掺杂n型掺质如磷、砷或类似物以用于n型装置。
对p型装置而言，源极/漏极结构36可包含一或多层的硅、硅锗、硼化硅锗、锗或III-V族材料(如锑化铟、锑化镓或锑化铟镓)。在一些实施例中，源极/漏极结构36可掺杂p型掺质如硼。
如图4所示，形成接点蚀刻停止层38与层间介电层40于露出的表面上。在一实施例中，接点蚀刻停止层38形成于源极/漏极结构36、侧壁间隔物33及34、与隔离层22上。接点蚀刻停止层38可包含或可为任何合适材料，比如氮化硅、氮氧化硅、锆硅化物、碳氮化硅、氧化锆铝、氧化钛、氧化钽、氧化锆、氧化镧、氮化锆、碳化硅、氧化锌、碳氧化硅、氧化铪、氧化镧、氧化铝、碳氮氧化硅、硅、铪硅化物、钽氧化铝、氧化钇、碳氮化钽、氧化硅或任何上述的组合，且其形成方法可为化学气相沉积、物理气相沉积或原子层沉积。接点蚀刻停止层38的厚度可为约1nm至约10nm。在一些实施例中，接点蚀刻停止层38的材料不同于侧壁间隔物33及34，因此后续工艺可选择性回蚀刻侧壁间隔物33及34以形成第一自对准接点层。
层间介电层40形成于接点蚀刻停止层38上。层间介电层40所用的材料可包括含硅、氧、碳及/或氢的化合物，比如氧化硅、碳氢氧化硅或碳氧化硅。层间介电层40可采用有机材料如聚合物。在移除牺牲栅极结构32时，层间介电层40可保护源极/漏极结构36。可进行平坦化步骤如化学机械研磨以露出牺牲栅极层26，用于之后移除牺牲栅极结构32。
图5至图14为本发明实施例中，半导体装置结构100在多种制作阶段中沿着图4的剖线A-A的剖视图。图15为一些实施例中，半导体装置结构100沿着图4的剖线B-B的剖视图。图16为一些实施例中，半导体装置结构100沿着图4的剖线C-C的剖视图。
如图5所示，进行置换栅极步骤以形成栅极介电层42与栅极层44。置换栅极步骤可包含移除牺牲栅极层26与牺牲栅极介电层24以露出牺牲栅极结构32之下的鳍状结构20。接着移除半导体层12以形成半导体层14的纳米片。相邻的源极/漏极结构的源极结构及/或端点与漏极结构及/或端点可由通道层(比如半导体层14的纳米片)相连。
接着沉积栅极介电层42于半导体层14的每一纳米片的露出表面、内侧间隔物35的露出表面、与侧壁间隔物33的露出表面上。栅极介电层42可包含一或多层的介电材料，比如氧化硅、氮化硅、高介电常数的介电材料、其他合适的介电材料及/或上述的组合。高介电常数的介电材料的例子包含氧化铪、氧化铪硅、氮氧化和硅、氧化铪钽、氧化铪钛、氧化铪锆、氧化锆、氧化铝、氧化钛、氧化铪-氧化铝合金、其他合适的高介电常数的介电材料及/或上述的组合。
接着形成栅极层44于栅极介电层42上。栅极层44包括一或多层的导电材料(如功函数金属)，比如多晶硅、铝、铜、钛、钽、钨、钴、钼、氮化钽、镍硅化物、钴硅化物、氮化钛、氮化钨、钛铝、氮化钛铝、碳氮化钽、碳化钽、氮化钽硅、金属合金、其他合适材料及/或上述的组合。在形成栅极层44之后，可进行平坦化工艺如化学机械研磨工艺以移除多余的栅极材料，并露出层间介电层40的上表面。
图5亦显示一或多个半导体层14连接半导体层14的两侧上的源极/漏极结构36，以形成多通道晶体管。一或多个半导体层14作为多通道晶体管的源极/漏极结构36之间的一或多个通道区。可由施加至栅极层44的电压控制源极/漏极结构36之间的连接。在其他实施例中，通道区可为单一通道晶体管的通道，其可为单一通道的鳍状通道区或平面通道区。
如图6所示，进行金属栅极回蚀刻工艺以移除栅极介电层42与栅极层44的部分。沟槽46可形成于保留的栅极介电层42与栅极层44之上的区域中。金属栅极回蚀刻工艺可为等离子体蚀刻工艺，其可采用一或多种蚀刻剂如含氯气体、含溴气体及/或含氟气体。蚀刻工艺可选择性蚀刻栅极介电层42与栅极层44，而实质上不影响侧壁间隔物33及34、层间介电层40、与接点蚀刻停止层38。
在一些实施例中，亦回蚀刻侧壁间隔物33及34，使侧壁间隔物33及34的上表面高于栅极介电层42与栅极层44的上表面。栅极介电层42与栅极层44的上表面实质上共平面。可采用两道或更多道蚀刻工艺以蚀刻栅极介电层42、栅极层44、与侧壁间隔物33及34。举例来说，可采用第一蚀刻工艺以回蚀刻栅极介电层42与栅极层44至第一高度，接着采用第二蚀刻工艺以回蚀刻侧壁间隔物33及34至第二高度，且第二高度与第一高度实质上相同。接着采用第三蚀刻工艺以进一步回蚀刻栅极介电层42与栅极层44至第三高度，且第三高度低于第二高度。在其他实施例中，可采用第一蚀刻工艺以回蚀刻栅极介电层42与栅极层44至第一高度，接着回蚀刻侧壁间隔物33及34至第二高度，且第二高度大于第一高度。在这些状况中，可向下蚀刻侧壁间隔物33及34至低于接点蚀刻停止层38并高于栅极介电层42与栅极层44，如图6所示。
通过蚀刻接点蚀刻停止层38之下的侧壁间隔物33及34，在形成源极/漏极金属接点时，后续形成的自对准接点层可覆盖并保护侧壁间隔物33及34。此外，侧壁间隔物33及34的高度仍高于栅极介电层42与栅极层44，使侧壁间隔物33及34仍可保护栅极层44。
如图7所示，选择性形成金属层43于栅极层44上。在一些实施例中，金属层43可延伸覆盖栅极介电层42的整个上表面或上表面的一部分。由于栅极层44可包括多个功函数金属层，形成金属层43的步骤可使隔离层(如图8中的隔离层45)之后形成于栅极层44上而不需考虑成长选择性的问题。若金属层43不存在，则栅极层44的不同功函数金属与后续形成的隔离层之间可能产生所谓的成长选择性的问题。金属层43可包含或可为钨、钌、钼、钴、氮化钽、铜、钛、钽、氮化钛或类似物。金属层43的厚度可为约0.5nm至约10nm。若金属层43比0.5nm薄，则无法调整上述的成长选择性。另一方面，若金属层43的厚度大于10nm，则会增加制造成本而无明显好处。金属层43的形成方法可为物理气相沉积、化学气相沉积、原子层沉积或其他合适工艺。栅极层44的功函数金属的多层金属表面，可促进选择性成长金属层43于栅极层44上，但不成长金属层43于侧壁间隔物33及34、接点蚀刻停止层38、与层间介电层40的介电材料上。因此可由下至上的方式形成金属层43。在一些实施例中，可视情况形成金属层43，且金属层43可不存在。
如图8所示，形成隔离层45于金属层43上。隔离层45可作为保护层，以在后续工艺(比如沉积自对准接点如图9中的第一自对准接点层50)时避免氧化金属层43与栅极层44。选择隔离层45的材料，使其不氧化金属层43与栅极层44。在多种实施例中，隔离层45的组成为不含氧原子的介电材料。隔离层45的例示性材料可包含但不限于氮化锆、碳化硅、氮化硅、碳氮化硅、碳氮化钽、类似物或任何上述的组合。在一些实施例中，隔离层45的材料不同于侧壁间隔物33及34与接点蚀刻停止层38的材料。隔离层45可选择性地形成于金属层43上，且其形成方法可为任何合适的选择性沉积工艺如原子层沉积。可控制形成隔离层45所用的前驱物与温度，以选择性或优先成长隔离层45于金属层43的金属表面上，而非侧壁间隔物33及34、接点蚀刻停止层38、与层间介电层40的介电表面上。在其他实施例中，可顺应性地形成隔离层45于金属层43与半导体装置结构100的露出表面上，接着可进行一或多道选择性蚀刻工艺(如原子层蚀刻)以自半导体装置结构100的露出表面移除隔离层45，而不损伤金属层43上的隔离层45。隔离层45的厚度可为约0.5nm至约10nm。若隔离层45比0.5nm薄，则无法做为保护层。另一方面，若隔离层45的厚度大于10nm，则会增加制造成本而无明显好处。
如图9所示，将第一自对准接点层50填入隔离层45上的沟槽46(见图8)中。第一自对准接点层50在后续图案化金属接点所用的沟槽与通孔时，可作为蚀刻停止层。沟槽46的轮廓会造成第一自对准接点层50具有底部50a与自底部50a延伸的顶部50b。底部50a接触隔离层45与侧壁间隔物33，而顶部50b接触侧壁间隔物33及34与接点蚀刻停止层38。底部50a的高度H1介于约1nm至约40nm之间。顶部50b的高度H2介于约1nm至约20nm之间。若第一自对准接点层50比高度H1与高度H2的总和薄，则无法在后续工艺中作为蚀刻停止层。另一方面，若第一自对准接点层50的厚度大于高度H1与高度H2的总和，则会增加装置尺寸而无额外优点。
第一自对准接点层50可为介电材料，且其蚀刻选择性可不同于接点蚀刻停止层38与后续形成的源极/漏极金属接点(比如图12中的源极/漏极金属接点56)。在一些实施例中，第一自对准接点层50可为高介电常数的介电层，其介电常数大于或等于约3.9，比如大于或等于约7。在一些实施例中，第一自对准接点层50的材料与隔离层45所用的材料不同。第一自对准接点层50所用的合适材料可包含但不限于氧化硅、铪硅化物、碳氧化硅、氧化铝、锆硅化物、氮氧化铝、氧化锆、氧化铪、氧化钛、氧化锆铝、氧化锌、氧化钽、氧化镧、氧化钇、碳氮化钽、氮化硅、碳氮氧化硅、氮化锆、碳氮化硅或任何上述的组合。第一自对准接点层50的形成方法可为合适的沉积工艺，比如化学气相沉积、可流动的化学气相沉积、物理气相沉积或原子层沉积。
虽然一些实施例的第一自对准接点层50可含氧，形成隔离层45于第一自对准接点层50与栅极层44之间，可阻挡氧扩散至栅极层44中。如此一来，若隔离层45不存在而氧化栅极层44的现象可最小化或消除，进而避免金属功函数偏移与装置效能劣化。
在一些实施例中，可视情况形成第一自对准接点层50，且第一自对准接点层50可不存在。在这些例子中，可回蚀刻栅极层44与栅极介电层42，接着形成金属层43与隔离层45于栅极层44与栅极介电层42上。隔离层45的上表面可与侧壁间隔物33及34与接点蚀刻停止层38的上表面共平面。
在第一自对准接点层50填入沟槽46之后，可进行平坦化工艺如化学机械研磨工艺以移除多余的第一自对准接点层50，以露出层间介电层40的上表面。
在图10所示的一些其他实施例中，在金属栅极回蚀刻工艺之后，可省略金属层43。相反地，在形成隔离层45与将第一自对准接点层50填入沟槽46之前，可先沉积衬垫层41于沟槽46的露出表面上。衬垫层41可作为栅极层44所用的扩散阻挡层，且在后续工艺时避免氧化栅极层44。衬垫层41为顺应性的层状物并接触隔离层45、栅极层44、栅极介电层42、侧壁间隔物33及34、接点蚀刻停止层38、与第一自对准接点层50，如图10所示。在一些实施例中，可省略隔离层45。衬垫层41的组成可为不含氧原子的介电层，因此其不氧化栅极层44。衬垫层41所用的合适材料可包含但不限于氮化硅、碳化硅、碳氮化硅、氮化锆、类似物或任何上述的组合。衬垫层41的形成方法可为合适的沉积工艺，比如原子层沉积、化学气相沉积或物理气相沉积。
如图11及图12所示，形成源极/漏极金属接点56。可形成接点孔51穿过层间介电层40与接点蚀刻停止层38，接着将导电材料填入接点孔51以形成源极/漏极金属接点56。可采用合适的光刻与蚀刻技术以形成接点孔51穿过多种层状物，以露出源极/漏极结构36的上表面。在一些实施例中，接点孔51可形成于所有的源极/漏极结构36上，以形成源极/漏极金属接点56于其上而达到结构平衡。在其他实施例中，接点孔51只形成于选定的源极/漏极结构36上，其自顶侧连接至电源或信号线。
在形成接点孔51之后，可选择性形成硅化物层52于接点孔51所露出的源极/漏极结构36的上表面上，如图11所示。硅化物层52可电性耦接源极/漏极结构36至后续形成的源极/漏极金属接点56。硅化物层52的形成方法可为沉积金属源层以覆盖露出表面(包含源极/漏极结构36的露出表面)，并进行快速热退火工艺。在一些实施例中，金属源层包括的金属层择自但不限于钛、钛硅化物、钴、钴硅化物、镍、镍硅化物、镍钴、铂、镍铂、铱、铂铱、铒、镱、钯、铑、铌、钨硅化物或氮化钛硅。在形成金属源层之后，可进行快速热退火工艺，比如温度介于约700℃至约900℃之间的快速退火。在快速热退火工艺时，源极/漏极结构36上的金属源层的部分可与源极/漏极结构36中的硅反应形成硅化物层52。接着移除金属源层的未反应部分。在一些实施例中，硅化物层52的厚度可介于约0.5nm至10nm之间。
在形成硅化物层52之后，沉积导电材料以填入接点孔51并形成源极/漏极金属接点56，如图12所示。在一些实施例中，再填入源极/漏极金属接点56之前，形成阻挡层54于硅化物层52与接点蚀刻停止层38的露出表面上。在一些实施例中，阻挡层54的组成可为钛、钽、氮化钛、氮化钽、钨、钴、钌或类似物。阻挡层54的厚度可小于约10nm。源极/漏极金属接点56的组成可为导电材料。在一些实施例中，源极/漏极金属接点56所用的导电材料包括但不限于钨、钴、钌、钛、镍、铜、金、银、铂、钯、铱、锇、铑、铝、钼、氮化钽或类似物。
在一些实施例中，源极/漏极金属接点56的形成方法可为合适的沉积工艺，比如化学气相沉积、物理气相沉积、电镀、原子层沉积或其他合适技术。之后可进行化学机械研磨工艺以移除高于第一自对准接点层50的上表面的导电材料层的一部分。
如图13、图14、图15及图16所示，回蚀刻源极/漏极金属接点56以形成隔离孔58，并形成第二自对准接点层60于隔离孔58中。隔离孔58的形成方法可为等离子体蚀刻工艺，其采用一或多种蚀刻剂如含氯气体、含溴气体及/或含氟气体。蚀刻工艺可选择性蚀刻源极/漏极金属接点56，且实质上不影响第一自对准接点层50、阻挡层54、接点蚀刻停止层38、与层间介电层40。回蚀刻后的源极/漏极金属接点56具有高度H3。在一些实施例中，高度H3介于约0.5nm至约90nm之间，比如约5nm至约40nm。
在一些实施例中，第二自对准接点层60的材料与第一自对准接点层50所用的材料不同，因此在后续工艺中相对于第一自对准接点层50可选择性地移除第二自对准接点层60。第二自对准接点层60所用的合适材料可包含但不限于氧化硅、铪硅化物、碳氧化硅、氧化铝、锆硅化物、氮氧化铝、氧化锆、氧化铪、氧化钛、氧化锆铝、氧化锌、氧化钽、氧化镧、氧化钇、碳氮化钽、氮化硅、硅、碳氮氧化硅、氮化锆、碳氮化硅或上述的组合。第二自对准接点层60的形成方法可为合适的沉积工艺，比如化学气相沉积、物理气相沉积、电镀、原子层沉积或其他合适技术。在一些实施例中，可视情况形成第二自对准接点层60，或第二自对准接点层60可不存在。在此状况下，不回蚀刻阻挡层54与源极/漏极金属接点56。后续工艺可移除第二自对准接点层60，其可作为连接至源极/漏极金属接点56的接点孔所用的自对准结构。
之后进行化学机械研磨工艺，以移除高于第一自对准接点层50的上表面的第二自对准接点层60的一部分。在一些实施例中，第二自对准接点层60的高度H4可介于约1nm至约50nm之间。
应理解的是，半导体装置结构100可进行后续的互补式金属氧化物半导体及/或后段工艺，以形成多种结构如晶体管、接点及/或通孔、内连线金属层、介电层、钝化层或类似物。此外，半导体装置结构100亦可包含背侧接点(未图示)于基板10的背侧上，使源极/漏极结构36的源极或漏极经由背侧接点连接至背侧电源轨(如正电压VDD或负电压VSS)。
本发明实施例以金属层以及金属层上的隔离层覆盖栅极层的上表面，以避免氧化半导体装置中的栅极层。隔离层形成于第一自对准接点层与栅极层之间，以避免氧自第一自对准接点层扩散至栅极层中。如此一来，若隔离层不存在而氧化栅极层的现象可最小化或消除，进而避免金属功函数偏移与装置效能劣化。
本发明一些实施例提供半导体装置结构。半导体装置结构包括栅极介电层；栅极层，接触栅极介电层；第一自对准接点层，位于栅极层上；隔离层，位于栅极层与第一自对准接点层之间；以及第一侧壁间隔物，接触栅极介电层、隔离层以及第一自对准接点层。
在一些实施例中，隔离层的组成为不含氧原子的介电材料。
在一些实施例中，隔离层接触第一自对准接点层。
在一些实施例中，半导体装置结构还包括金属层，位于栅极层与隔离层之间并接触栅极层与隔离层。
在一些实施例中，金属层更接触栅极介电层。
在一些实施例中，第一侧壁间隔物接触金属层。
在一些实施例中，半导体装置结构还包括第二侧壁间隔物接触第一侧壁间隔物。
在一些实施例中，半导体装置结构还包括接点蚀刻停止层接触第二侧壁间隔物与第一自对准接点层。
本发明一些实施例提供半导体装置结构。半导体装置结构包括第一源极/漏极结构与第二源极/漏极结构；以及通道层，位于第一源极/漏极结构与第二源极/漏极结构之间并接触第一源极/漏极结构与第二源极/漏极结构，其中通道层的组成为半导体层。半导体装置结构包括栅极介电层，围绕通道层的至少一表面；栅极层，围绕栅极介电层的至少一表面；以及第一自对准接点层，位于栅极层上，其中第一自对准接点层包括介电材料。半导体装结构还包括隔离层，位于栅极层与第一自对准接点层之间；以及第一侧壁间隔物，接触栅极介电层、第一自对准接点层、与隔离层。
在一些实施例中，隔离层的组成为不含氧原子的介电材料。
在一些实施例中，半导体装置结构还包括金属层位于栅极层与隔离层之间并接触栅极层与隔离层。
在一些实施例中，半导体装置结构还包括第二侧壁间隔物，接触第一侧壁间隔物与第一自对准接点层。
在一些实施例中，半导体装置结构还包括：源极/漏极金属接点，位于第一源极/漏极结构与第二源极/漏极结构上；第二自对准接点层，接触源极/漏极金属接点；以及接点蚀刻停止层，位于第二自对准接点层与第一自对准接点层之间并接触第二自对准接点层与第一自对准接点层。
在一些实施例中，半导体装置结构还包括：衬垫层，接触栅极层、栅极介电层、隔离层、第一侧壁间隔物、与第一自对准接点层。
在一些实施例中，衬垫层的组成为不含氧原子的介电材料。
在一些实施例中，半导体装置结构还包括：第二侧壁间隔物，接触第一侧壁间隔物与衬垫层；以及接点蚀刻停止层，接触衬垫层与第二侧壁间隔物。
在一些实施例中，半导体装置结构还包括：源极/漏极金属接点，位于第一源极/漏极结构与第二源极/漏极结构上；以及第二自对准接点层，接触源极/漏极金属接点。
本发明一些实施例提供半导体装置结构的形成方法。方法包括形成鳍状结构，其具有多个通道层位于其上；形成牺牲栅极结构于鳍状结构的一部分上；形成侧壁间隔物于牺牲栅极结构的两侧上；移除牺牲栅极结构以露出通道层的部分；形成栅极介电层于通道层的露出部分上；形成栅极层于栅极介电层上；移除栅极层与栅极介电层的部分，使栅极层与栅极介电层的上表面低于侧壁间隔物的上表面；形成隔离层于栅极层与栅极介电层上，其中隔离层包括不含氧原子的介电材料；以及形成自对准接点层于隔离层上。
在一些实施例中，方法还包括形成金属层于隔离层与栅极层之间。
上述实施例的特征有利于本技术领域中技术人员理解本发明。本技术领域中技术人员应理解可采用本发明作基础，设计并变化其他工艺与结构以完成上述实施例的相同目的及/或相同优点。本技术领域中技术人员亦应理解，这些等效置换并未脱离本发明精神与范畴，并可在未脱离本发明的精神与范畴的前提下进行改变、替换或更动。

Claims (1)

1.一种半导体装置结构，包括：
一栅极介电层；
一栅极层，接触该栅极介电层；
一第一自对准接点层，位于该栅极层上；
一隔离层，位于该栅极层与该第一自对准接点层之间；以及
一第一侧壁间隔物，接触该栅极介电层、该隔离层以及该第一自对准接点层。
CN202210171561.2A 2021-02-25 2022-02-24 半导体装置结构 Pending CN114765129A (zh)

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