CN115394715A - 半导体装置 - Google Patents
半导体装置 Download PDFInfo
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- CN115394715A CN115394715A CN202210729659.5A CN202210729659A CN115394715A CN 115394715 A CN115394715 A CN 115394715A CN 202210729659 A CN202210729659 A CN 202210729659A CN 115394715 A CN115394715 A CN 115394715A
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
- H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
- H01L21/28185—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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Abstract
一种半导体装置,包括基板;第一半导体通道位于基板上;第二半导体通道位于基板上且横向偏离第一半导体通道;以及第三半导体通道位于基板上并横向偏离第二半导体通道。第一、第二及第三栅极结构,分别位于第一、第二及第三半导体通道上并分别横向围绕第一、第二及第三半导体通道。第一非有源鳍状物位于第一与第二栅极结构之间;以及第二非有源鳍状物位于第二与第三栅极结构之间。桥导体层位于第一、第二、与第三栅极结构及第一与第二非有源鳍状物上。介电插塞自第二非有源鳍状物的上表面延伸穿过桥导体层至桥导体层的至少上表面。
Description
技术领域
本发明实施例涉及半导体装置,尤其涉及场效晶体管如平面场效晶体管、三为鳍状场效晶体管、或全绕式栅极装置。
背景技术
半导体集成电路产业已经历指数成长。集成电路材料与设计的技术进展,使每一代的集成电路比前一代具有更小且更复杂的电路。在集成电路演进中,功能密度(比如单位芯片面积的内连线装置数目)通常随着几何尺寸(比如采用的制作工艺所能产生的最小构件或线路)缩小而增加。尺寸缩小的工艺通常有利于增加产能与降低相关成本。尺寸缩小亦增加处理与制造集成电路的复杂度。
发明内容
在至少一实施例中,半导体装置包括基板;第一半导体通道,位于基板上;第二半导体通道,位于基板上且横向偏离第一半导体通道;第三半导体通道,位于基板上并横向偏离第二半导体通道;第一栅极结构,位于第一半导体通道上并横向围绕第一半导体通道;第二栅极结构,位于第二半导体通道上并横向围绕第二半导体通道;第三栅极结构,位于第三半导体通道上并横向围绕第三半导体通道;第一非有源鳍状物,位于第一栅极结构与第二栅极结构之间;第二非有源鳍状物,位于第二栅极结构与第三栅极结构之间;桥导体层,位于第一栅极结构、第二栅极结构、第三栅极结构、第一非有源鳍状物、与第二非有源鳍状物上;以及介电插塞,自第二非有源鳍状物的上表面延伸穿过桥导体层至桥导体层的至少上表面。
在至少一些实施例中,半导体装置包括:基板;第一晶体管,位于基板上且具有延伸于第一方向中的第一栅极结构;第二晶体管,位于基板上且具有延伸于第一方向中且对准第一栅极结构的第二栅极结构,且第二栅极结构与第一栅极结构电性隔离;隔离区,位于基板上且在第一方向中位于第一晶体管与第二晶体管之间;栅极隔离结构,接触第一栅极结构、第二栅极结构、与隔离区。栅极隔离结构包括:第一部分,自隔离区的上表面延伸至第一栅极结构的上表面与第二栅极结构的上表面;以及第二部分,自第一部分的上表面延伸至高于第一栅极结构与第二栅极结构的上表面的高度。
在至少一实施例中,半导体装置的形成方法包括形成第一鳍状物堆叠与第二鳍状物堆叠;以自对准工艺形成非有源鳍状物于第一鳍状物堆叠与第二鳍状物堆叠之间的第一开口中;形成第一栅极结构于第一鳍状物堆叠上,并形成第二栅极结构于第二鳍状物堆叠上,其中非有源鳍状物隔离第一栅极结构与第二栅极结构;在形成第一栅极结构与第二栅极结构之后,形成介电插塞于非有源鳍状物上;以及形成桥导体层于第一栅极结构与第二栅极结构上,其中桥导体层延伸的垂直高度低于介电插塞的上表面。
附图说明
图1A至图1H为本发明实施例中,集成电路装置的一部分的俯视图与剖视图。
图2至图16、图17A、图17B、图18至图21、图22A至图22C、图23A至图23C、图24A至图24C及图25至图28为本发明多种实施例中,集成电路于多种制作阶段的附图。
图29为本发明多种实施例中,制作半导体装置的方法的流程图。
附图标记如下:
F-F’,H-H’:剖线
H1:高度
W1:宽度
10:集成电路装置
20A,20B,20C,20D,20E:全绕式栅极装置
21,21A,21B,21C:第一半导体层
22,24:纳米结构
22A1,22A2,22A3,22A4,22A5,22B1,22B2,22B3,22B4,22B5,22C1,22C2,22C3,22C4,22C5:通道
23,23A,23B,23C:第二半导体层
25:多层堆叠
26:鳍状物堆叠
28,95:氧化物层
29,182:硬掩模层
40:虚置栅极结构
41:栅极间隔物
42:间隔物层
43:衬垫介电层
44,600:栅极介电层
45:虚置栅极层
46:填充介电层
47:掩模层
48:介电隔离结构
49:第二间隔物层
50:覆层
51,183,250:开口
52,53:气隙
74:内侧间隔物
82:源极/漏极结构
90:介电层
92:非有源区块
93:介电衬垫层
94:非有源鳍状结构
97:非有源鳍状物盖
99:栅极隔离结构
110:基板
120:源极/漏极接点
130:层间介电层
131:蚀刻停止层
132:第二蚀刻停止层
170:区域
181:第一掩模层
200:置换栅极
200A,200B,200C,200D,200E:栅极结构
204:桥导体层
210:界面层
240:第二界面层
260:粘着层
270:盖层
290:金属填充层
321,322,323,324,325:鳍状物
361,362,363,364:隔离结构
510:缝隙
700:功函数阻挡层
900:功函数金属层
1000:方法
1100,1200,1300,1400,1500,1600,1700,1800:步骤
具体实施方式
下述详细描述可搭配附图说明,以利理解本发明的各方面。值得注意的是,各种结构仅用于说明目的而未按比例绘制,如本业常态。实际上为了清楚说明,可任意增加或减少各种结构的尺寸。
下述内容提供的不同实施例或实例可实施本发明的不同结构。下述特定构件与排列的实施例用以简化本发明内容而非局限本发明。举例来说,形成第一构件于第二构件上的叙述包含两者直接接触的实施例,或两者之间隔有其他额外构件而非直接接触的实施例。此外,本发明的多个实例可重复采用相同标号以求简洁,但多种实施例及/或设置中具有相同标号的元件并不必然具有相同的对应关系。
此外,空间相对用语如“在…下方”、“下方”、“较低的”、“上方”、“较高的”、或类似用词,用于描述附图中一些元件或结构与另一元件或结构之间的关系。这些空间相对用语包括使用中或操作中的装置的不同方向,以及附图中所描述的方向。当装置转向不同方向时(旋转90度或其他方向),则使用的空间相对形容词也将依转向后的方向来解释。
相对程度的用语如“大约”、“实质上”、或类似用语,应解释成本技术领域中技术人员依据的目前技术规范。一般而言,用语“实质上”比用语“大约”的容许范围更窄。举例来说,“大约100个单位”的厚度将包括更大范围如70个单位到130个单位(+/-30%),而“实质上100个单位”的厚度将包括更小的范围如,95个单位到105个单位(+/-5%)。同样,此类容许范围(+/-30%、+/-5%、或类似范围)可能取决于工艺及/或设备,并且不应解释为大于或小于本技术领域中技术人员所承认的技术规范,除了相对用语“大约”在类似说明中不如“实质上”那样严格。
本发明实施例通常关于半导体装置,更特别关于场效晶体管如平面场效晶体管、三为鳍状场效晶体管、或全绕式栅极装置。在高级的技术节点中,栅极隔离结构(切割金属栅极结构)以及相邻半导体鳍状物之间的空间(与重叠及关键尺寸相关)的布局限制,将局限单位高度的尺寸缩小。此处所述的栅极隔离结构可采用自对准的制作工艺以改善空间限制。
可由任何合适方法图案化全绕式栅极晶体管结构。举例来说,可采用一或多到光刻工艺图案化结构,包括双重图案化或多重图案化工艺。一般而言,双重图案化或多重图案化结合光刻与自对准工艺,其产生的图案间距小于采用单一的直接光刻工艺所得的图案间距。举例来说,一实施例形成牺牲层于基板上,并采用光刻工艺图案化牺牲层。采用自对准工艺以沿着图案化的牺牲层侧部形成间隔物。接着移除牺牲层,而保留的间隔物之后可用于图案化全绕式栅极装置的结构。
图1A至图1H为本发明实施例中,集成电路装置10的一部分的俯视图与剖视图,其中集成电路装置10包括全绕式栅极装置20A至20E。图1A、图1C、图1E及图1G为含有全绕式栅极装置20A至20E的集成电路装置10的部分俯视图。为了简化附图,在图1A、图1C、图1E及图1G的俯视图中省略这些结构。在一些实施例中,全绕式栅极装置20A至20E可包括至少一n型场效晶体管或p型场效晶体管。集成电路装置如集成电路装置10通常包括不同临界电压的晶体管,端视其于集成电路装置中的功能而定。举例来说,输入/输出晶体管通常具有最高的临界电压,核心逻辑晶体管通常具有最低的临界电压,而其他功能的晶体管如静态随机存取存储器晶体管的临界电压在输入/输出晶体管与核心逻辑晶体管的临界电压之间。集成电路装置10中的一些电路区块包括两种或更多种不同临界电压的两个或更多个n型场效晶体管及/或p型场效晶体管。
全绕式栅极装置20A至20E形成于基板110之上及/或之中,且通常包含栅极结构200A至200E以跨过自隔离结构361至364凸起且隔有隔离结构361至364的半导体鳍状物321至325之上的半导体通道(可改视作纳米结构)。通道标示为22AX至22CX,其中X为1至5的整数,以分别对应五个晶体管如全绕式栅极装置20A至20E。栅极结构200A至200E各自控制流经通道22A1至22C5的电流。
在许多集成电路装置中,两个或更多个相邻的全绕式栅极装置的栅极结构之间较佳具有电性连接。在一般工艺中,栅极结构的材料层形成于大量的相邻半导体鳍状物上,且在形成材料层之前或之后形成隔离结构以切割材料层,并使材料层的这些部分彼此隔离。材料层的每一部分可为一或多个栅极结构以对应一或多个全绕式栅极装置。为了说明目的,图1A至图1H所示的设置中,两个栅极隔离结构99隔离五个栅极结构200A至200E,因此电性连接栅极结构200B及200C,电性连接栅极结构200D及200E,且栅极结构200A、栅极结构200B及200C、与栅极结构200D及200E彼此电性隔离。栅极隔离结构99可改视作介电插塞。桥导体层204亦可达到电性连接,且可覆盖栅极结构200A至200E。栅极隔离结构99延伸穿过桥导体层204以及介电盖层270与粘着层260(其亦覆盖栅极结构200A至200E)。栅极隔离结构99更接触非有源区块92的非有源鳍状物盖97或非有源鳍状结构94。非有源鳍状结构94与非有源区块92自栅极结构200A至200E的上表面延伸至隔离结构361至364,使栅极结构200A至200E可彼此横向隔离,比如以非有源鳍状结构94的一者横向隔离栅极结构200B与栅极结构200C。在一些实施例中,非有源鳍状结构94延伸高于通道22A1、22A2、22A3、22A4及22A5的上表面约5nm至约25nm。
本发明多种实施例在形成栅极结构200A至200E之前以自对准工艺形成非有源鳍状结构94,且在形成栅极结构200A至200E之后以另一自对准工艺形成栅极隔离结构99。如此一来,相邻的全绕式栅极装置如全绕式栅极装置200B及200C之间的物理分隔,与其他栅极隔离工艺相比可缩小至少5%。非有源鳍状结构94与非有源区块92的其他内容将搭配图1E至图1H说明如下。
图1C至图1D为图1D中的集成电路装置10沿着X-Z平面的剖视图,其中X方向为水平方向,而Z方向为垂直方向。图1D的剖视图显示全绕式栅极装置20A至20E的单一全绕式栅极装置20B以简化附图,而相关说明可通用于其他全绕式栅极装置20A及20C至20E。通道22A2至22C2横向邻接源极/漏极结构82,且栅极结构200B覆盖并围绕通道22A2至22C2。栅极结构200B可依据施加至栅极结构200B与源极/漏极结构82的电压,控制自源极/漏极结构82穿过通道22A2至22C2到另一源极/漏极结构82的电流。
在一些实施例中,鳍状物322包括硅。在一些实施例中,全绕式栅极装置20B为n型场效晶体管,其源极/漏极结构82包括磷化硅。在一些实施例中,全绕式栅极装置20B为p型场效晶体管,其源极/漏极结构82包括硅锗。
通道22A2至22C2各自包括半导体材料如硅或硅化合物(其尺寸为几纳米),且各自具有伸长的形状并延伸于X方向中。在一些实施例中,通道22A2至22C2各自具有纳米线状、纳米片状、纳米管状、或其他合适的纳米尺寸形状。通道22A2至22C2的剖面轮廓可为矩形、圆形、方向、椭圆形、六角形、或上述的组合。
在一些实施例中,通道22A2至22C2的长度(在X方向中)可彼此不同,因为锥形的鳍状物蚀刻工艺。在一些实施例中,通道22A1的长度可小于通道22B1的长度,而通道22B1的长度可小于通道22C1的长度。由于扩展通道22A2至22C2之间的空间(在Z方向中)以增加栅极结构的制作工艺容许范围所用的通道修整工艺,通道22A2至22C2可各自具有不一致的厚度。举例来说,每一通道22A2至22C2的中间部分可比两端部分薄。此形状可一起视作狗骨头状。
在一些实施例中,通道22A至22C2之间的空间(比如通道22B2与通道22A2之间,或通道22B2与通道22C2之间)可介于约8nm至约12nm之间。在一些实施例中,通道22A2至22C2各自的厚度(在Z方向中)介于约5nm至约8nm之间。在一些实施例中,通道22A2至22C2各自的宽度(在Y方向中,垂直于X-Z平面且未图示于图1D)为至少约8nm。
栅极结构200B位于通道22A2至22C2之上与之间。在一些实施例中,栅极结构200B位于通道22A2至22C2之上与之间,而通道22A2至22C2为n型装置所用的硅通道或p型装置所用的硅锗通道。在一些实施例中,栅极结构200B包括界面层210、一或多个栅极介电层600、一或多个功函数金属层900、与金属填充层290。
界面层210如通道22A2至22C2的材料的氧化物,可形成于通道22A2至22C2的露出区域与鳍状物322的上表面上。界面层210可促进栅极介电层600与通道22A2至22C2的粘着性。在一些实施例中,界面层210的厚度为约至约在一些实施例中,界面层210的厚度为约界面层210过薄则可能存在空洞或粘着性不足。界面层210过厚则消耗栅极填充的容许范围,其有关于调整临界电压与电阻如上述。在一些实施例中,界面层210掺杂偶极掺质如镧以调整临界电压。
在一些实施例中,栅极介电层600包括至少一高介电常数的栅极介电材料,其可视作介电常数大于氧化硅的介电常数(约3.9)的介电材料。例示性的高介电常数的介电材料包括氧化铪、氧化铪硅、氮氧化铪硅、氧化铪钽、氧化铪钛、氧化铪锆、氧化锆、氧化钽、或上述的组合。在一些实施例中,栅极介电层600的厚度为约至约
在一些实施例中,栅极介电层600可包括掺质,比如自氧化镧、氧化镁、氧化钇、氧化钛、氧化铝、氧化铌、或类似物驱入高介电常数的栅极介电层中的金属离子,或自氧化硼驱入的硼离子。上述离子的浓度可达调整临界电压的效果。在一例中,对n型晶体管装置而言,较高浓度的镧离子比较低浓度的镧离子或无镧离子更能降低临界电压。对p型装置而言,上述现象相反。在一些实施例中,这些晶体管装置(如n型输入/输出晶体管)的栅极介电层600不含其他晶体管装置(比如n型核心逻辑晶体管或p型输入/输出晶体管)中存在的掺质。举例来说,n型输入/输出晶体管需要较高的临界电压,因此输入/输出晶体管的高介电常数的介电层较佳不含镧离子,因镧离子会降低临界电压。
在一些实施例中,栅极结构200B还包括一或多个功函数金属层,其可一起视作功函数金属层900。在全绕式栅极装置20B设置为n型场效晶体管时,其功函数金属层900可包含至少一n型功函数金属层、原位盖层、与氧阻挡层。在一些实施例中,n型功函数金属层可为或包括n型金属材料,比如碳化钛铝、钛铝、碳化钽铝、钽铝、或类似物。原位盖层形成于n型功函数金属层上,且可包含氮化钛、氮化钛硅、氮化钽、或另一合适材料。氧阻挡层形成于原位盖层上,以避免氧扩散至n型功函数金属层中。氧扩散会造成临界电压产生不想要的偏移。氧阻挡层的组成可为介电材料,其可阻止氧穿透至n型功函数金属层,且可保护n型功函数金属层免于进一步氧化。氧阻挡层可包含硅、锗、硅锗、或另一合适材料的氧化物。在一些实施例中,功函数金属层900可比所述内容含有更多或更少的层状物。
功函数金属层900可进一步包括一或多个阻挡层如金属氮化物(比如氮化钛、氮化钨、氮化钼、氮化钽、或类似物)。一或多个阻挡层各自的厚度为约至约包含一或多个阻挡层可提供额外的临界电压调整弹性。一般而言,额外的阻挡层各自增加临界电压。如此一来,对n型场效晶体管而言,较高临界电压装置(如输入/输出晶体管装置)可具有至少一个额外阻挡层或超过两个额外阻挡层,而较低临界电压装置(如核心逻辑晶体管装置)可具有较少额外阻挡层或不具有额外阻挡层。对p型场效晶体管而言,较高临界电压装置(如输入/输出晶体管装置)可具有较少额外阻挡层或不具有额外阻挡层,而较低临界电压装置(如核心逻辑晶体管装置)可具有至少一个额外阻挡层或超过两个额外阻挡层。在下述内容中,以绝对值说明临界电压。在一例中,n型场效晶体管的输入/输出晶体管与p型场效晶体管的输入/输出晶体管可具有类似的临界电压绝对值但相反的极性,比如n型场效晶体管输入/输出晶体管所用的+1V与p型场效晶体管的输入/输出晶体管所用的-1V。如此一来,由于额外阻挡层各自增加临界电压的绝对值(如0.1V/层),增加额外阻挡层将增加n型场效晶体管的临界电压并降低p型场效晶体管的临界电压。
栅极结构200B亦包括金属填充层290。金属填充层290可包括导电材料如钨、钴、钌、铱、钼、铜、铝、或上述的组合。在通道22A2至22C2之间,一或多个功函数金属层900可围绕金属填充层290,而栅极介电层600可围绕功函数金属层900(在剖视图中)。栅极结构200B亦可包含粘着层,其形成于一或多个功函数金属层900与金属填充层290之间以增加粘着力。粘着层未图示于图1A至图1H以简化附图。
全绕式栅极装置20A至20E亦包括栅极间隔物41与内侧间隔物74位于栅极介电层600与界面层210的侧壁上。内侧间隔物74亦位于通道22A2至22C2之间。栅极间隔物41与内侧间隔物74可包含介电材料如低介电常数的介电材料(比如碳氮氧化硅、氮氧化硅、氮化硅、或碳氧化硅)。
全绕式栅极装置20A至20E可进一步包括源极/漏极接点120(如图1F及图1H所示),其可形成于源极/漏极结构82上。源极/漏极接点120可包含导电材料如钨、钴、钌、铱、钼、铜、铝、或上述的组合。阻挡层(未图示)如氮化硅或氮化钛可围绕源极/漏极接点120,以帮助避免或降低自源极/漏极接点120扩散材料及/或扩散材料至源极/漏极接点120中。硅化物层亦可形成于源极/漏极结构82与源极/漏极接点120之间,以降低源极/漏极接点电组。硅化物层可含金属硅化物材料如一些实施例的钴硅化物,或一些其他实施例的钛硅化物。
全绕式栅极装置20A至20E还包括层间介电层130。层间介电层130提供电性隔离于全绕式栅极装置20A至20E的上述多种构件之间,比如栅极结构200B与源极/漏极接点120之间。在形成层间介电层130之前可形成蚀刻停止层131,其可横向地位于层间介电层130与栅极间隔物41之间并垂直地位于层间介电层130与源极/漏极结构82之间。
图1F及图1H分别为沿着图1E及图1G所示的剖线F-F'及H-H'的剖视图。图1F及图1H所示的剖视图垂直于半导体鳍状物321至325并平行于栅极结构200A至200E,且沿着源极/漏极结构82。介电隔离结构48邻接非有源鳍状结构94与非有源区块92。如图1F所示的一些实施例,介电隔离结构48各自包括间隔物层42与衬垫介电层43。在一些实施例中,间隔物层42可为或包括多晶硅或低介电常数的介电层如氮化硅、碳氮化硅、碳氮氧化硅、碳氧化硅、或类似物。在一些实施例中,衬垫介电层43为高介电常数的介电层,其包括氧化铪、氧化锆、氧化铪铝、氧化铪硅、氧化铝、或类似物。在一些实施例中,非有源鳍状结构94亦包括低介电常数的介电材料如氮化硅、碳氮化硅、碳氮氧化硅、碳氧化硅、或类似物。在一些实施例中,介电隔离结构48各自的宽度W1为约2nm至约13nm。
如图1H所示的一些实施例,介电隔离结构48各自包括衬垫介电层43与填充介电层46。在一些实施例中,衬垫介电层43为高介电常数的介电层,其包括氧化铪、氧化锆、氧化铪铝、氧化铪硅、氧化铝、或类似物。在一些实施例中,填充介电层46为低介电常数的介电层,其包括氮化硅、碳氮化硅、碳氮氧化硅、碳氧化硅、或类似物。一般而言,两种设置(图1F及图1H)包括衬垫介电层43,其为高介电常数的介电层以用于结构稳定性与增进抗扩散性。然而为了降低寄生电容,介电隔离结构48还包括间隔物层42或第三介电层如填充介电层46,其为低介电常数的介电层。由于图2至图22C与图24A至27所示的全绕式栅极装置20A至20E所用的制作工艺不同,两种设置之间的高介电常数与低介电常数的介电层的相对形状与位置不同。具体而言,图11至图13显示的工艺步骤与图1F的介电隔离结构48的形成方法相关,而图24A至图25显示的工艺步骤与图1H的介电隔离结构48的形成方法相关。
制作全绕式栅极装置的额外细节,可参考美国专利号10164012(发明名称为半导体装置与其制造方法,获证日为2018/12/25)以及美国专利号10361278(发明名称为制造半导体装置的方法与半导体装置,获证日为2019/7/23)。
图29显示本发明一或多个实施例中,自工件形成集成电路装置或其部分的方法1000的流程图。方法1000仅为举例,而非局限本发明实施例至方法1000实际记载的内容。在方法1000之前、之中、与之后可提供额外步骤,且方法的额外实施例可置换、省略、或调换一些所述步骤。此处不详述所有步骤以简化说明。方法1000将搭配工件于方法1000的不同制作阶段的部分透视图及/或剖视图(如图2至图28所示)说明如下。为了避免疑问,附图中的X方向垂直于Y方向,且Z方向垂直于X方向与Y方向。值得注意的是,由于工件将制作成半导体装置,工件亦可依内容需求而视作半导体装置。
在图2中,提供基板110。基板110可为半导体基板如半导体基体或类似物,其可掺杂(如掺杂p型或n型掺质)或未掺杂。基板110的半导体材料可包含硅、锗、半导体化合物(如碳化硅、砷化镓、磷化镓、磷化铟、砷化铟及/或锑化铟)、半导体合金(如硅锗、磷砷化镓、砷化铝铟、砷化铝镓、砷化镓铟、磷化镓铟及/或磷砷化镓铟)、或上述的组合。亦可采用其他基板如单层基板、多层基板、或组成渐变基板。
在图2中,多层堆叠25(或晶格)形成于基板110上,其包括交错的第一半导体层21A至21C(一起视作第一半导体层21)与第二半导体层23A至23C(一起视作第二半导体层23)。在一些实施例中,第一半导体层21的组成可为适用于n型纳米场效晶体管的第一半导体材料,比如硅、碳化硅、或类似物。第二半导体层23的组成可为适用于p型纳米场效晶体管的第二半导体材料,比如硅锗或类似物。多层堆叠25的每一层的外延成长工艺可采用化学气相沉积、原子层沉积、气相外延、分子束外延、或类似工艺。如图3所示,氧化物层28与硬掩模层29形成于顶部的第一半导体层21A上。在一些实施例中,氧化物层28为垫氧化物层,且硬掩模层29可包含硅。
附图中的第一半导体层21与第二半导体层23各自为三层。在一些实施例中,多层堆叠25可包含一层、两层、四层、或更多层的第一半导体层21与一层、两层、四层、或更多层的第二半导体层23。虽然附图中的多层堆叠25其最底层为第二半导体层23C,但一些实施例中的多层堆叠25的最底层可为第一半导体层21。
由于第一半导体材料与第二半导体材料之间的高蚀刻选择性,可移除第二半导体材料的第二半导体层23,而不明显移除第一半导体材料的第一半导体层21,使第一半导体层21之后可图案化以形成纳米场效晶体管的通道区。在一些实施例中,移除第一半导体层21并图案化第二半导体层以形成通道区。高蚀刻选择性可移除第一半导体材料的第一半导体层21,而不明显移除第二半导体材料的第二半导体层23,因此可图案化第二半导体层23以形成纳米场效晶体管的通道区。
图3显示鳍状物321至325形成于基板110中,而纳米结构22及24形成于多层堆叠25中,如图29的步骤1100所示。在一些实施例中,纳米结构22及24与鳍状物321至325的形成方法可为蚀刻沟槽于多层堆叠25与基板110中。蚀刻可为任何可接受的蚀刻工艺,比如反应性离子蚀刻、中性束蚀刻、类似制成、或上述的组合。蚀刻可为非等向。纳米结构22如通道22A1至22C可由第一半导体层21形成,而纳米结构24可由第二半导体层23形成。相邻鳍状物321至325与纳米结构22及24之间在Y方向中的距离可为约18nm至约100nm。
鳍状物321至325与纳米结构22及24的图案化方法可为任何合适方法。举例来说,可采用一或多道光刻工艺形成鳍状物321至325与纳米结构22及24,包括双重图案化或多重图案化工艺。一般而言,双重图案化或多重图案化工艺结合光刻与自对准工艺,其产生的图案间距小于采用单一的直接光刻工艺所得的图案间距。以多重图案化工艺为例,可形成牺牲层于基板上,并采用光刻工艺图案化牺牲层。可采用自对准工艺以沿着图案化的牺牲层侧部形成间隔物。接着移除牺牲层,而保留的间隔物之后可用于图案化鳍状物321至325。在一些实施例中,可由光刻工艺图案化硬掩模层29,接着以蚀刻工艺转移图案以形成鳍状物321至325与纳米结构22及24。鳍状物321至325与其上方的纳米结构22及24可一起视作鳍状物堆叠。鳍状物堆叠26包括鳍状物321、纳米结构如通道22A1、22B1及22C1、与纳米结构24,如图3中的虚线所示。图3显示五个鳍状物堆叠26,但亦可采用图案化工艺以形成较多或较少的鳍状物堆叠。
图3所示的鳍状物321至325具有垂直的平直侧壁。在一些实施例中,侧壁实质上垂直(非锥形),使鳍状物321至325与纳米结构22及24的宽度实质上类似,且纳米结构22及24各自为矩形。在一些实施例中,鳍状物321至325具有锥形侧壁,使鳍状物321至325及/或纳米结构22及24各自的宽度在朝基板110的方向中持续增加。在这些实施例中,纳米结构22及24可各自具有不同的宽度且为梯形。
在图4中,隔离结构361至364可为浅沟槽隔离区,其可与鳍状物321至325相邻并位于鳍状物321至325之间。隔离结构361至364的形成方法可为沉积绝缘材料于基板110、鳍状物321至325、与纳米结构22及24之上,以及相邻的鳍状物321至325与纳米结构22及24之间。绝缘材料可为氧化物如氧化硅、氮化物、类似物、或上述的组合,且其形成方法可为高密度等离子体化学气相沉积、可流动的化学气相沉积、类似方法、或上述的组合。在一些实施例中,可先沿着基板110、鳍状物321至325、与纳米结构22及24的表面形成衬垫层(未图示)。之后可形成上述的填充材料于衬垫层上。
对绝缘材料进行移除工艺如化学机械研磨、回蚀刻工艺、上述的组合、或类似工艺,以移除纳米结构22及24上的多余绝缘材料。在一些实施例中,完成移除工艺之后,可露出纳米结构22及24的上表面,且纳米结构22及24的上表面可与绝缘材料齐平。在图4所示的一些实施例中,移除工艺之后可保留硬掩模层29与氧化物层28于纳米结构22上。
接着可使绝缘材料凹陷以形成隔离结构361至364。在凹陷之后,纳米结构22及24与鳍状物321至325的上侧部分可自相邻的隔离结构361至364之间凸起。隔离结构361至364的上表面可为平坦(如图示)、凸出、凹入、或上述的组合。在一些实施例中,使隔离结构361至364凹陷的方法可为可接受的蚀刻工艺,比如采用稀氢氟酸的氧化物移除工艺,其对绝缘材料具有选择性,且鳍状物32与纳米结构22及24维持实质上不变。
图2至图4所示的一实施例中,形成鳍状物321至325与纳米结构22及24(如最后蚀刻的工艺)。在一些实施例中,鳍状物321至325及/或纳米结构22及24可外延成长于介电层中的沟槽中(如蚀刻优先的工艺)。外延结构可包括交错的上述半导体材料,比如第一半导体材料与第二半导体材料。
如图4所示,可形成合适的井区(未图示)于鳍状物321至325、纳米结构22及24及/或隔离结构361至364中。采用掩模,以对基板110的p型区进行n型杂质注入,并对基板110的n型区进行p型杂质注入。例示性的n型杂质可包含磷、砷、锑、或类似物。例示性的p型杂质可包含硼、氟化硼、铟、或类似物。在注入之后可进行退火,以修复注入损伤并活化p型及/或n型杂质。在一些实施例中,可在外延成长鳍状物321至325与纳米结构22及24时进行原位掺杂,以省略分开的注入步骤。不过原位掺杂与注入掺杂可搭配使用。
在图5中,覆层50形成于纳米结构22及24、鳍状物321至325的上侧部分、与隔离结构361至364的周边部分之上与周围。覆层50的组成可为半导体材料(比如基板110所用的半导体材料选择之一),其成长的工艺可为气相外延或分子束外延,且其沉积的工艺可为化学气相沉积、原子层沉积、或类似工艺。在一些实施例中,覆层50包括硅锗。在沉积覆层50的材料之后,可进行非等向蚀刻以露出隔离结构361至365。一般而言,覆层50为暂时结构,在形成栅极结构200A至200E之前可移除覆层50与纳米结构24,且覆层50与纳米结构24可包括相同材料。
图6至图8显示非有源鳍状结构94与非有源区块92的形成方法,如图29的步骤1200所示。在图6中,非有源鳍状结构94与非有源区块92所用的介电层90,形成于覆层50之间与隔离结构361至365之上。介电层90的组成可为低介电常数的介电材料(如非有源鳍状结构94的介电材料选择之一)。介电层90的厚度可为约6nm至约30nm。如图6所示,可采用覆层50进行自对准工艺,以形成介电层90于隔离结构362至364上。自对准工艺可使个别鳍状物322至325之间的空间,比采用一般工艺沉积介电层90以形成非有源鳍状结构94所得的空间更紧密。一般工艺在形成与蚀刻栅极结构200A至200E之后,可沉积介电层90。由于工艺限制(特别是层叠与对准规则的限制),蚀刻栅极结构200A至200E的工艺(有时可是做切割栅极工艺)需要较大的空间于鳍状物321至325之间,以避免蚀刻太靠近蚀刻所形成的开口两侧的纳米结构22。通过沉积介电层90于纳米结构22及24的侧壁上的覆层50的垂直部分之间的开口中,不只确保对准还可减少空间,使面积较小的电路功能区块的设计与制作具有相同或更好的效能。
在图7中,氧化物层95形成于隔离结构361之上,以及隔离结构361上的介电层90的部分的上表面之上与侧壁之间。在一些实施例中,氧化物层95包括氧化硅。
在图8中,进行移除工艺使覆层50、介电层90、与氧化物层95的多余材料凹陷至与硬掩模层29的上表面实质上共平面。在一些实施例中,移除工艺可为化学机械研磨工艺,其可形成非有源鳍状结构94与非有源区块92的介电衬垫层93与氧化物层95。在一些实施例中,使氧化物层95进一步凹陷至低于介电层90与覆层50的上表面,且非有源鳍状物盖97形成于介电层90的侧壁之间的氧化物层95上。在一些实施例中,非有源鳍状物盖97包括低介电常数的介电材料。在一些实施例中,非有源鳍状物盖97与介电衬垫层93包括相同材料。在一些实施例中,氧化物层95的材料不同于介电衬垫层93的材料与非有源鳍状物盖97的材料。
图9为一些实施例中,形成集成电路装置10的中间阶段的透视图。在形成非有源鳍状物盖97之后,可形成虚置栅极结构40于鳍状物321至325及/或纳米结构22及24上。图9显示单一的虚置栅极结构40,但可同时形成实质上平行于虚置栅极结构40的许多其他虚置栅极结构40。在形成虚置栅极结构40时,虚置栅极层45形成于鳍状物321至325及/或纳米结构22及24上。虚置栅极层45的材料组成对隔离结构361至364具有高蚀刻选择性。虚置栅极层45可为导电材料、半导体、或非导电材料,且其可为非晶硅、多晶硅、多晶硅锗、金属氮化物、金属硅化物、金属氧化物、或金属。虚置栅极层45的沉积方法可为物理气相沉积、化学气相沉积、溅镀沉积、或其他技术以用于沉积选定材料。掩模层47形成于虚置栅极层45上,且可包含氮化硅、氮氧化硅、或类似物。一些实施例在形成虚置栅极层45之前,形成栅极介电层44于虚置栅极层45与鳍状物321至325(及/或纳米结构22及24)之间。
在图10中,进行多重移除工艺以移除硬掩模层29、氧化物层28、非有源鳍状结构94、介电衬垫层93、非有源鳍状物盖97、与覆层50的露出部分,而移除工艺采用虚置栅极结构40作为掩模。采用可接受的蚀刻工艺修整覆层50,比如对覆层50具有选择性的蚀刻工艺,其选择性蚀刻覆层50的材料的速率大于蚀刻纳米结构如通道22A1至22C5、纳米结构24、与非有源鳍状结构94的材料的速率。凹陷及修整步骤可移除一些纳米结构24。
图11至图13显示形成介电隔离结构48以邻接非有源鳍状结构94与非有源区块92,如图29的步骤1300所示。在图11中,间隔物层42亦可视作间隔物层,其形成于掩模层47的侧壁、虚置栅极层45、栅极介电层44、硬掩模层29、氧化物层28、纳米结构22及24、非有源鳍状结构94、非有源区块92、与隔离结构361至364上,且其形成方法可为顺应性沉积工艺。间隔物层42的组成可为绝缘材料如氮化硅、氧化硅、碳氮化硅、氮氧化硅、碳氮氧化硅、或类似物。
在图12中,衬垫介电层43形成于间隔物层42的相邻侧壁之间的空间中。衬垫介电层43包括高介电常数的介电材料,其可视作介电常数大于氧化硅的介电常数(约3.9)的介电材料。例示性的高介电常数的介电材料包括氧化铪、氧化铪硅、但氧化铪硅、氧化铪钽、氧化铪钛、氧化铪锆、氧化锆、氧化钽、或上述的组合。衬垫介电层43填入空间,使衬垫介电层43的上表面与纳米结构22及24与非有源鳍状结构94上的间隔物层42的上表面实质上共平面。在一些实施例中,衬垫介电层43的形成方法为沉积工艺如化学气相沉积、原子层沉积、或另一合适工艺。沉积工艺之后可为蚀刻工艺如等向蚀刻工艺,以移除空间之外的衬垫介电层43的多余材料,比如间隔物层42的上侧侧壁与上侧表面上的衬垫介电层43。
在图13中,形成第二间隔物层49于掩模层47、虚置栅极层45、栅极介电层44、硬掩模层29、氧化物层28、纳米结构22及24、非有源鳍状结构94、非有源区块92、衬垫介电层43、与隔离结构361至364之上,且形成方法可为顺应性的沉积工艺。第二间隔物层49可为或包括绝缘材料如氮化硅、氧化硅、碳氮化硅、氮氧化硅、碳氮氧化硅、或类似物。在一些实施例中,第二间隔物层49与间隔物层42的组成为相同材料。在一些实施例中,间隔物层42与第二间隔物层49可为或包括多晶硅。
在沉积第二间隔物层49之后,可移除第二间隔物层49的水平表面(如X-Y平面),接着进行一或多道蚀刻工艺以蚀刻虚置栅极结构40、间隔物层42、与第二间隔物层49未覆盖的鳍状物321至325及/或纳米结构22及24的凸出部分,最后形成图示的结构。蚀刻可为非等向,因此保护且不蚀刻直接位于虚置栅极结构40与栅极间隔物41之下的鳍状物321至325的部分。在一些实施例中,凹陷的鳍状物321至325的上表面可与隔离结构361至364的上表面实质上共平面,或稍微低于隔离结构361至364的上表面,如图所示。
可进行后续蚀刻工艺,使介电隔离结构48、非有源鳍状结构94、间隔物层42、衬垫介电层43、与非有源区块92凹陷。后续蚀刻工艺可完全移除非有源鳍状物盖97的露出部分。后续蚀刻工艺亦可使氧化物层95与介电衬垫层93的露出部分凹陷。
图14显示内侧间隔物74的形成方法。进行选择性蚀刻工艺使纳米结构24其露出的末端部分凹陷,且实质上不攻击纳米结构22。在选择性蚀刻工艺之后,可形成凹陷于纳米结构中,其位于移除的末端部分原本的位置。接着形成内侧间隔物层以填入纳米结构22之间的凹陷,而凹陷的形成方法为之前的选择性蚀刻工艺。内侧间隔物层可为合适的介电材料,比如碳氮化硅、碳氮氧化硅、或类似物,且其形成方法可为合适的沉积方法如物理气相沉积、化学气相沉积、原子层沉积、或类似方法。可进行蚀刻工艺如非等向蚀刻工艺,以移除纳米结构24中的凹陷之外的内侧间隔物层的部分。内侧间隔物层的保留部分(如纳米结构24中的凹陷内的部分)可形成内侧间隔物74。最终结构如图14所示。
图15显示源极/漏极结构82形成于介电隔离结构48之间,如图29的步骤1400所示。在所述实施例中,源极/漏极结构82可自外延材料外延成长。在一些实施例中,由于非有源鳍状结构94之间的空间因含有介电隔离结构48而减少,源极/漏极结构82实质上不横向成长。在一些实施例中,源极/漏极结构82可施加应力于个别的通道22A1至22C5中以改善效能。源极/漏极结构82可使虚置栅极结构40各自位于个别的相邻成对的源极/漏极结构82之间。在一些实施例中,间隔物层42、第二间隔物层49及内侧间隔物74可使源极/漏极结构82与虚置栅极层45隔有合适的横向距离,以避免源极/漏极结构82电性桥接至最终装置中后续形成的栅极。
源极/漏极结构82可包含任何可接受的材料,比如适用于n型或p型装置的材料。在一些实施例中,对n型装置而言,源极/漏极结构82包括的材料可施加拉伸应力于通道区中,比如硅、碳化硅、碳磷化硅、磷化硅、或类似物。在特定实施例形成p型装置时,源极/漏极结构82包括的材料可施加压缩应力于通道区中,比如硅锗、硼化硅锗、锗、锗锡、或类似物。源极/漏极结构82的表面可自鳍状物的个别表面隆起,且可具有晶面。在一些实施例中,相邻的源极/漏极结构82可合并以形成单一的源极/漏极结构82以与两个相邻的鳍状物321至325相邻。
将掺质注入至源极/漏极结构82之后进行退火。源极/漏极区的杂质浓度可介于约1019cm-3至约1021cm-3之间。源极/漏极结构82所用的n型杂质及/或p型杂质可为任何前述杂质。在一些实施例中,可在成长时原位掺杂源极/漏极结构82。接着可形成接点蚀刻停止层与层间介电层(未图示以简化附图),以覆盖虚置栅极结构40与源极/漏极结构82。
在图16中,移除纳米结构24、掩模层47、与虚置栅极层45以释放鳍状物的通道22A1至22C5,如图29的步骤1500所示。在释放步骤之前可进行平坦化工艺如化学机械研磨,使虚置栅极层45与栅极间隔物41的上表面齐平。平坦化工艺亦可移除虚置栅极层45上的掩模层47,以及沿着掩模层47的侧壁的栅极间隔物41的部分。综上所述,露出虚置栅极层45的上表面。
接着由蚀刻工艺移除虚置栅极层45,以形成凹陷。在一些实施例中,可由非等向干蚀刻工艺移除虚置栅极层45。举例来说,蚀刻工艺可包括干蚀刻工艺,其采用反应气体以选择性蚀刻虚置栅极层45而不蚀刻栅极间隔物41。栅极介电层44若存在,则可在蚀刻虚置栅极层45时作为蚀刻停止层。在移除虚置栅极层45之后,可移除栅极介电层44。
移除纳米结构24以释放纳米结构22。在移除纳米结构24之后,纳米结构22可形成水平延伸(比如平行于基板110的主要上表面)的多个纳米片。纳米片可一起视作全绕式栅极装置20A至20E的通道如纳米结构22。
在一些实施例中,可由选择性蚀刻工艺移除纳米结构24,其采用的蚀刻剂对纳米结构24的材料具有选择性,因此可移除纳米结构24而实质上不攻击纳米结构22。在一些实施例中,蚀刻至成为等向蚀刻工艺,其可采用蚀刻气体且可视情况采用载气。蚀刻气体可包括氟气或氢氟酸,而载气可为惰气如氩气、氦气、氮气、上述的组合、或类似物。
在一些实施例中,可移除纳米结构24并图案化纳米结构22,以形成p型场效晶体管与n型场效晶体管的通道区。在一些其他实施例中,可移除纳米结构22并图案化纳米结构24,以形成p型场效晶体管与n型场效晶体管的通道区。
在一些实施例中,全绕式栅极装置20A至20E的纳米片如纳米结构22可由后续的蚀刻工艺重塑(如薄化),以改善栅极填充的容许范围。重塑步骤可为对纳米片如纳米结构22具有选择性的等向蚀刻工艺。在重塑之后,纳米片如纳米结构22可具有狗骨头状,其中间部分沿着X方向的厚度小于其周边部分沿着X方向的厚度。
虽然未图示于图15及图16以简化附图,但在移除纳米结构24、掩模层47、与虚置栅极层45之前,可沉积层间介电层130于源极/漏极结构82、非有源鳍状结构94、介电衬垫层93、氧化物层95、与介电隔离结构48上。亦可在沉积层间介电层130之前形成蚀刻停止层131(见图22A)。在沉积层间介电层130之后,可使层间介电层130稍微凹陷,且可形成第二蚀刻停止层132于凹陷中的层间介电层130上。接着可进行化学机械研磨步骤或类似步骤,以移除第二蚀刻停止层132的多余材料,使第二蚀刻停止层132的上表面与蚀刻停止层131及栅极间隔物41的上表面实质上共平面。
接着在图17A及图17B中,形成置换栅极200如栅极结构200A至200E,如图29的步骤1600所示。图17B为图17A的区域170对应栅极结构200B的一部分的细节图。每一置换栅极200如图17B所示的栅极结构200B通常包含界面层210、至少一栅极介电层600、功函数金属层900、与金属填充层290。在一些实施例中,每一置换栅极200还包括至少一第二界面层240或功函数阻挡层700。
如图17B所示,栅极介电层600形成于界面层210上。在一些实施例中,采用原子层沉积工艺形成栅极介电层600,以精准控制栅极介电层600的沉积厚度。在一些实施例中,采用约40次至80次的循环进行原子层沉积工艺,且其温度可介于约200℃至约300℃之间。在一些实施例中,原子层沉积工艺采用氯化铪及/或水作为前驱物。此原子层沉积工艺可形成栅极介电层600,其厚度可介于约至约之间。
在一些实施例中,栅极介电层600包括高介电常数的介电材料,其可视作介电常数大于氧化硅的介电常数(约3.9)的介电材料。例示性的高介电常数的介电材料包括氧化铪、氧化铪硅、氮氧化铪硅、氧化铪钽、氧化铪钛、氧化铪锆、氧化锆、氧化钽、或上述的组合。在其他实施例中,栅极介电层600可包含非高介电常数的介电材料如氧化硅。在一些实施例中,栅极介电层600包括超过一个高介电常数的介电层,其中至少一者含有掺质如镧、镁、钇、或类似物,其可由退火工艺驱入栅极介电层600以调整全绕式栅极装置20B的临界电压。
如图17B所示,形成第二界面层240于栅极介电层600上,并形成功函数阻挡层700于第二界面层240上。第二界面层240可促进较佳的金属栅极粘着性于栅极介电层600上。在许多实施例中,第二界面层240可改善栅极结构200B的热稳定性,以限制金属杂质自功函数金属层900及/或功函数阻挡层700扩散至栅极介电层600中。在一些实施例中,形成第二界面层240的方法可为先沉积高介电常数的盖层(未图示)于栅极介电层600上。在多种实施例中,高介电常数的盖层包括氮氧化铪硅、氧化铪钽、氧化铪钛、氮氧化铪铝、氧化铪锆、与其他合适材料的一或多者。在具体实施例中,高介电常数的盖层包括氮化钛硅。在一些实施例中,高介电常数的盖层的沉积方法可为原子层沉积,其采用40次至约100次的循环,且温度可为约400℃至约450℃。在一些实施例中,接着进行热退火以形成第二界面层240,其可为或包括氮氧化钛硅。在以热退火形成第二界面层240之后,可进行人工智能控制的原子层蚀刻的多个循环,以移除高介电常数的盖层而实质上不移除第二界面层240。每一循环可包含进行氯化钨的第一脉冲、接着进行氩气净化、接着进行氧气的第二脉冲、以及接着进行另一氩气净化。移除高介电常数的盖层,以增加栅极填充的容许范围。栅极填充可用于金属栅极图案化以进一步调整多重临界电压。
如图17B所示的一些实施例,形成第二界面层240与移除高介电常数的盖层之后,可视情况形成功函数阻挡层700于栅极结构200B上。功函数阻挡层700可为或包括金属氮化物,比如氮化钛、氮化钨、氮化钼、氮化钽、或类似物。在具体实施例中,功函数阻挡层700为氮化钛。功函数阻挡层700的厚度可为约至约含有功函数阻挡层700,可提供额外的临界电压调整弹性。一般而言,功函数阻挡层700可增加n型场效晶体管装置所用的临界电压,并降低p型场效晶体管装置所用的临界电压。
在一些实施例中,功函数金属层900可包括n型功函数金属层、原位盖层、与氧阻挡层的至少一者,且形成于功函数阻挡层700上。n型功函数金属层可为或包括n型金属材料,比如碳化钛铝、钛铝、碳化钽铝、钽铝、或类似物。n型功函数金属层的形成方法可为一或多种沉积方法,比如化学气相沉积、物理气相沉积、原子层沉积、镀制法及/或其他合适方法,其且厚度可介于约至之间。原位盖层形成于n型功函数金属层上。在一些实施例中,原位盖层可为或包括氮化钛、氮化钛硅、氮化钽、或另一合适材料,且其厚度可介于约至之间。氧阻挡层形成于原位盖层上,以避免氧扩散至n型功函数金属层中,而氧扩散可能造成临界电压产生不想要的偏移。氧阻挡层的组成可为介电材料,其可阻止氧穿透至n型功函数金属层,且可保护n型功函数金属层免于进一步氧化。氧阻挡层可包含硅、锗、硅锗、或另一合适材料的氧化物。在一些实施例中,氧阻挡层的形成方法可采用原子层沉积,且其厚度可介于约至约之间。
图17B亦显示金属填充层290。在一些实施例中,可形成粘着层(未图示)于功函数金属层的氧阻挡层与金属填充层290之间。粘着层可促进及/或增进金属填充层290与功函数金属层900之间的粘着性。在一些实施例中,粘着层的组成可为金属氮化物如氮化钛、氮化钽、氮化钼、氮化钨、或另一合适材料,且其形成方法可采用原子层沉积。在一些实施例中,粘着层的厚度可介于约至约之间。金属填充层290可形成于粘着层上,且可包含导电材料如钨、钴、钌、铱、钼、铜、铝、或上述的组合。在一些实施例中,金属填充层290的沉积方法可采用化学气相沉积、物理气相沉积、镀制法及/或其他合适工艺。在一些实施例中,缝隙510如气隙形成于垂直地位于通道22A2及22B2之间的金属填充层290中。在一些实施例中,金属填充层290顺应性地沉积于功函数金属层900上。顺应性沉积于侧壁的膜可能合并,因此形成缝隙510。在一些实施例中,缝隙510不存在于相邻的通道22A2及22B2之间。
此时可使所有的栅极结构200A至200E彼此电性隔离。图18至图23C显示一些实施例中,电性连接一些栅极结构200A至200E的工艺,并电性隔离其他的栅极结构200A至200E。
图18至图21显示形成介电插塞如栅极隔离结构99于非有源鳍状结构94及/或非有源区块92之上的方法,如图29的步骤1700所示。在图18中,形成第一掩模层181与硬掩模层182于栅极结构200A至200E、非有源鳍状结构94、介电衬垫层93、与非有源鳍状物盖97上。第一掩模层181包括硅,比如多晶硅或非晶硅。在一些实施例中,第一掩模层181的厚度可为约100nm至约200nm。在一些实施例中,对第一掩模层181进行平坦化步骤。第一掩模层181与硬掩模层182的沉积方法可采用任何合适工艺,包括旋转涂布、低压化学气相沉积、等离子体辅助化学气相沉积、物理气相沉积、原子层沉积、或其他合适工艺。在一些实施例中,硬掩模层182包括一或多层的氮化硅、碳氧化硅、或类似物。
在图19中,蚀刻硬掩模层182与第一掩模层181以形成开口183于非有源鳍状结构94与非有源鳍状物盖97上并露出鳍状结构94与非有源鳍状物盖97。如图19所示,开口183的一者形成于隔离结构363上的非有源鳍状物盖97上,并露出非有源鳍状物盖97。在形成开口183于非有源鳍状结构94的一者之上时,开口183的宽度(在Y方向中)实质上等于非有源鳍状结构94的宽度,但较大或较小的宽度亦适用。非有源鳍状结构94上的开口183通常亦实质上对准非有源鳍状结构94,但可能因对准偏移而发生一些对不准。
在一些实施例中,为了形成开口183,可形成光刻胶图案(未图示)于硬掩模层182上,且先由对硬掩模层182的材料具有选择性的非等向蚀刻工艺蚀刻硬掩模层182,以形成自硬掩模层182的上表面延伸的开口183的上侧部分,其露出非有源鳍状结构94与非有源鳍状物盖97上的第一掩模层181的上表面。在蚀刻硬掩模层182之后可移除光刻胶图案,且在形成自第一掩模层181的上表面延伸的开口183的下侧部分(其露出非有源鳍状结构94与非有源鳍状物盖97的上表面)时的硬掩模层182可作为掩模。下侧部分的形成方法可为蚀刻第一掩模层181,且蚀刻方法可为对第一掩模层181的材料具有选择性的非等向蚀刻工艺。
在图20中,形成开口183之后可形成介电插塞如栅极隔离结构99于开口183中。在一些实施例中,介电插塞如栅极隔离结构99可为或包括氮化硅、氧化硅、氧化铝、氧化锆、或另一合适材料。沉积介电插塞如栅极隔离结构99于开口183中的合适工艺,可为化学气相沉积及/或其他合适技术。在沉积介电插塞如栅极隔离结构99之后,可进行移除工艺如化学机械研磨或另一合适工艺,以自第一掩模层181上移除介电插塞如栅极隔离结构99的多余材料,使介电插塞如栅极隔离结构99的上表面与第一掩模层181的上表面实质上齐平。介电插塞如栅极隔离结构99通常延续开口183的形状,使非有源鳍状结构94上的介电插塞如栅极隔离结构99实质上对准非有源鳍状结构94,且介电插塞如栅极隔离结构99与非有源鳍状结构94具有类似宽度。非有源鳍状物盖97上的介电插塞如栅极隔离结构99其宽度可为约1/100至1/2的非有源鳍状物盖97的宽度,且可对准(在Y方向中)非有源鳍状物盖97的中心。在一些实施例中,非有源鳍状物盖97上的介电插塞如栅极隔离结构99可部分覆盖介电衬垫层93。
在形成介电插塞如栅极隔离结构99之后可移除第一掩模层181,以保留介电插塞如栅极隔离结构99于非有源鳍状结构94与非有源鳍状物盖97上。在一些实施例中,可由反应性离子蚀刻或其他合适工艺移除第一掩模层181。最终结构如图21所示。此时所有的栅极结构200A至200E彼此维持电性隔离。
图22A至图22C为沿着X-Z平面的附图,其与图1D类似。图22A至22C显示相邻栅极结构200A至200E的电性连接,比如栅极结构200B及200C或者栅极结构200D及200E,如图29的步骤1800所示。虽然附图中的栅极结构200A至200E中的两个相邻栅极结构电性连接,但应理解一些实施例的介电插塞如栅极隔离结构99的适当位置可使三个或更多个相邻的栅极结构电性连接。
在图22A中,形成粘着层260。在形成粘着层260之前,可形成第二蚀刻停止层132于层间介电层130上。粘着层260形成于第二蚀刻停止层132、蚀刻停止层131、栅极间隔物41、与栅极结构200A至200E上。粘着层260可为或包括避免金属及/或氟扩散于桥导体层204(见图22C)与周围的层状物或结构(如金属填充层290)之间的材料,亦可促进桥导体层204粘着到栅极结构200A至200E。在一些实施例中,粘着层260可为或包括金属氮化物如氮化钛或其他合适材料。在一些实施例中,粘着层260的形成方法为沉积工艺如物理气相沉积或其他合适工艺。在一些实施例中,粘着层260在水平表面上的厚度(实质上在X-Y平面上的厚度,或水平厚度)大于在垂直表面上的厚度(实质上在Y-Z平面上的厚度,或垂直厚度)。举例来说,水平厚度可视作金属填充层290的上表面上的粘着层260的厚度,而垂直厚度可视作间隔物层42及/或第二间隔物层49的侧壁上的粘着层260的厚度。在一些实施例中,水平厚度比垂直厚度大了约1nm。在一些实施例中,水平厚度与垂直厚度的比例为至少约1.5。在一些实施例中,水平厚度为约2nm,而垂直厚度小于约1nm。
在图22B中,采用蚀刻工艺使粘着层260凹陷以形成成核区,而桥导体层204可沉积于成核区中。一些实施例在蚀刻之前将抗反射材料层(未图示以简化附图)填入粘着层260上的开口250中,接着回蚀刻抗反射材料层至比金属填充层290高出高度H1。在回蚀刻抗反射材料层(不同于粘着层260的材料)之后,可由蚀刻工艺移除高于高度H1的粘着层260的部分。接着可移除低于高度H1的抗反射材料层的保留材料,留下图22B所示的粘着层260。在一些实施例中,粘着层260的垂直侧壁达到高度H1,其低于间隔物层42的上表面。
在图22C中,以由下至上的工艺沉积桥导体层204,使导电材料如金属可选择性地沉积于粘着层260上,而不沉积于集成电路装置10的其他结构上。在一些实施例中,导电材料为钨、钴、钌、或其他合适的导电材料。在一些实施例中,导电材料为无氟钨。在一些实施例中,桥导体层204的导电材料的沉积方法为化学气相沉积工艺或其他合适工艺。由于粘着层260可作为成长桥导体层204所用的籽晶层,因此可由良好控制的方式沉积桥导体层204,并建立电性连接于栅极结构200A至200E中未隔有非有源鳍状结构94与介电插塞如栅极隔离结构99(或隔有非有源区块92与介电插塞如栅极隔离结构99)的相邻栅极结构之间。
图23A显示粘着层260上的桥导体层204。桥导体层204与粘着层260在栅极结构200A至200E、非有源鳍状结构94、与非有源区块92的上表面上不连续,因为介电插塞如栅极隔离结构99的存在。如此一来,非有源鳍状结构94可横向隔离栅极结构200B与栅极结构200C,而覆盖并物理接触栅极结构200B、200C、与非有源鳍状结构94的粘着层260与桥导体层204可电性连接栅极结构200B及200C。栅极结构200D及200E彼此电性连接的方式与前述方式类似。
如图23A及图23C所示,盖层270沉积于桥导体层204之上的开口250中。在一些实施例中,盖层270可为或包括介电材料,比如氮化硅、氧化硅、氮氧化硅、碳化硅、碳氧化硅、碳氮氧化硅、或另一合适材料。在一些实施例中,盖层270的介电材料的沉积方法可为物理气相沉积、化学气相沉积、原子层沉积、或另一合适工艺。在一些实施例中,盖层270的介电材料可与介电插塞如栅极隔离结构99的介电材料相同。在一些实施例中,盖层270与每一介电插塞如栅极隔离结构99之间存在可见界面,虽然一些其他实施例中的盖层270与介电插塞如栅极隔离结构99可为连续材料层而不具有界面。在形成盖层270之后,可进行移除工艺如化学机械研磨,以平坦化并研磨覆层270与介电插塞如栅极隔离结构99的上表面。
在图23B中,形成源极/漏极接点120以穿过层间介电层130与蚀刻停止层131,并接触源极/漏极结构82。在一些实施例中,进行蚀刻工艺以形成开口于层间介电层130中,接着进行另一蚀刻工艺延伸开口穿过蚀刻停止层131以露出源极/漏极结构82的上表面。在一些实施例中,金属硅化物层(未图示以简化附图)形成于每一源极/漏极结构82的露出上表面。接着沉积导电材料于源极/漏极结构82上的开口中,以形成源极/漏极接点120。在一些实施例中,导电材料可为或包括铜、钨、钌、钴、或另一合适材料。在一些实施例中,导电材料的沉积方法为物理气相沉积、无电镀、或另一合适工艺。在沉积导电材料于开口中之后,可进行移除工艺如化学机械研磨以移除层间介电层130上的多余导电材料,使源极/漏极接点120的上表面与层间介电层130的上表面实质上齐平。
图24A至图28显示形成图1H的集成电路装置10所用的另一工艺。图2至图10所示的步骤,与形成图1F及1H的集成电路装置所用的步骤实质上相同。
图24A至图24C显示介电隔离结构48的形成方法,如图29的步骤1300所示。在图24A中,形成图10的工件之后,可形成介电隔离结构48于纳米结构22及24与非有源鳍状结构94及/或非有源区块92之间的开口51中。较佳以介电隔离结构48提供电性隔离、结构支撑、与低电阻电容延迟。顺应性地沉积衬垫介电层43于开口51中。在一些实施例中,衬垫介电层43可为或包括高介电常数的介电材料,比如氧化铪、氧化锆、氧化铪铝、氧化铪硅、氧化铝、或另一合适的高介电常数的介电材料,其通常可比较低介电常数的介电材料提供更多结构支撑。在一些实施例中,衬垫介电层43的沉积方法为物理气相沉积、化学气相沉积、原子层沉积、或另一合适工艺。在一些实施例中,衬垫介电层43的厚度大于约若厚度小于则结构支撑可能不足。
在形成衬垫介电层43之后,可形成填充介电层46于衬垫介电层43的侧壁之间的开口51之中以及衬垫介电层43的上表面之上。在一些实施例中,填充介电层46可为或包括低介电常数的介电材料,比如氮化硅、碳氮化硅、碳氮氧化硅、碳氧化硅、或另一合适材料。填充介电层46可降低纳米结构22及24与非有源鳍状结构94及/或非有源区块92之间的总介电常数。在一些实施例中,填充介电层46的厚度可为约至约在一些实施例中,填充介电层46比衬垫介电层43厚。在一些实施例中,填充介电层46与衬垫介电层43的厚度比例大于约1.5。比例小于约1.5可能造成不能接受的寄生电容,因为介电隔离结构48的总介电常数过高。
图24A显示一些实施例中,介电隔离结构48所用的设置。在图24B所示的一些其他实施例中,气隙52可存在于介电隔离结构48中而非填充介电层46中。一些实施例在沉积衬垫介电层43时,衬垫介电层43的上侧区域可合并而留下气隙52(或空洞)于衬垫介电层43中。气隙的介电常数极低,可降低介电隔离结构48的总介电常数,并维持衬垫介电层43所提供的结构支撑。
在图24C所示的另一设置中,气隙53存在于填充介电层46中。与上述内容类似,沉积填充介电层46的步骤在完全填入开口51之前,填充介电层46的上侧区域合并以形成气隙53。
图25与图13类似,形成间隔物层42于掩模层47、虚置栅极层45、栅极介电层44、与硬掩模层29的上表面与侧壁上。间隔物层42更形成于氧化物层28上。在一些实施例中,间隔物层42的形成方法为顺应性的沉积工艺。间隔物层42的组成为绝缘材料,比如氮化硅、氧化硅、碳氮化硅、氮氧化硅、碳氮氧化硅、或类似物。在一些实施例中,间隔物层42包括多晶硅。图25所示的设置与图13所示的设置之间的差异在于形成介电隔离结构48之后,以分开步骤形成间隔物层42。如此一来,间隔物层42可形成为单层,但一些实施例的图25中的间隔物层42亦可形成为多层。
在沉积间隔物层42之后,移除间隔物层42的水平(X-Y平面)表面,接着进行一或多道蚀刻工艺以蚀刻虚置栅极结构40与间隔物层42未覆盖的凸起鳍状物321至325及/或纳米结构22及24的部分,以形成图25所示的结构。蚀刻可为非等向,因此可保护而实质上不蚀刻直接位于虚置栅极结构40与间隔物层42之下的鳍状物321至325与纳米结构22及24的部分。在一些实施例中,凹陷的鳍状物321至325的上表面可与隔离结构361至364的上表面实质上共平面(如图示),或稍微低于隔离结构361至364的上表面。
可进行后续的蚀刻工艺使介电隔离结构48、非有源鳍状结构94、衬垫介电层43、与非有源区块92凹陷。后续的蚀刻工艺可完全移除非有源鳍状物盖97的露出部分。后续的蚀刻工艺亦使氧化物层92与介电衬垫层93的露出部分凹陷。
图26与图14类似,形成内侧间隔物74。进行选择性蚀刻工艺使纳米结构24其露出的末端部分凹陷,而实质上不攻击纳米结构22。在选择性蚀刻工艺之后,凹陷形成于纳米结构24中,其位于纳米结构24被移除的末端部分原本的位置。接着形成内侧间隔物层以填入纳米结构22之间的凹陷,而凹陷的形成方法为之前的选择性蚀刻工艺。内侧间隔物层可为合适的介电材料如碳氮化硅、碳氮氧化硅、或类似物,且其形成方法为合适的沉积法如物理气相沉积、化学气相沉积、原子层沉积、或类似方法。进行蚀刻工艺如非等向蚀刻工艺,以移除纳米结构24中的凹陷之外的内侧间隔物层的部分。内侧间隔物层的保留部分(比如位于纳米结构24中的凹陷之内的部分)可形成内侧间隔物74。最终结构如图26所示。
图27与图15类似,形成源极/漏极结构82,如图29的步骤1400所示。在所述实施例中,自外延材料外延成长源极/漏极结构82。在一些实施例中,由于含有介电隔离结构48的非有源鳍状结构94之间的空间减少,源极/漏极结构82的成长实质上不横向成长。在一些实施例中,源极/漏极结构82施加应力于个别的通道22A1至22C5中以改善效能。形成源极/漏极结构82,使虚置栅极结构40各自位于个别的相邻成对源极/漏极结构82之间。在一些实施例中,间隔物层42与内侧间隔物74使源极/漏极结构82与虚置栅极结构40隔有合适的横向距离,以避免源极/漏极结构82桥接至最终装置中后续形成的栅极。接着可形成接点蚀刻停止层与层间介电层(未图示以简化附图)以覆盖虚置栅极结构40与源极/漏极结构82。
在形成源极/漏极结构82之后,可进行图16至图22C所示的步骤以释放纳米结构22(步骤1500)、形成栅极结构200A至200E于纳米结构周围与之上(步骤1600)、形成介电插塞如栅极隔离结构99于非有源鳍状结构94及/或非有源区块92之上(步骤1700)、并由栅极结构200A至200E之上与介电插塞如栅极隔离结构99之间的桥导体层204电性连接栅极结构200A至200E中的相邻栅极结构(步骤1800)。
在图28中,形成源极/漏极接点120以穿过层间介电层130与蚀刻停止层131,并接触源极/漏极结构82。在一些实施例中,进行蚀刻工艺以形成开口于层间介电层130中,接着进行另一蚀刻工艺以延伸开口穿过蚀刻停止层131而露出源极/漏极结构82的上表面。在一些实施例中,金属硅化物层(未图示以简化附图)形成于每一源极/漏极结构82露出的上表面。接着沉积导电材料于源极/漏极结构82上的开口中,以形成源极/漏极接点120。在一些实施例中,导电材料可为或包括铜、钨、钌、钴、或另一合适材料。在一些实施例中,导电材料的沉积方法可为物理气相沉积、无电镀、或另一合适工艺。在沉积导电材料于开口中之后,可进行移除工艺如化学机械研磨以移除层间介电层130上的多余导电材料,使源极/漏极接点120的上表面与层间介电层130的上表面实质上齐平。
可进行额外工艺以完成制作全绕式栅极装置20A至20E。举例来说,可形成栅极接点(未图示以简化附图)以电性耦接至栅极结构200A至200E。接着可形成内连线结构于源极/漏极接点120与栅极接点上。内连线结构可包括多个介电层以围绕金属结构,而金属结构包括导电线路与导电通孔以形成电性连接于基板110上的装置如全绕式栅极装置20A至20E之间,并电性连接至集成电路装置10外部的集成电路装置。
实施例可提供一些优点。在形成栅极结构200A至200E之前以自对准工艺形成非有源鳍状结构94与非有源区块92,栅极结构200A至200E之间的空间尺寸缩小的程度超出之前技术可能达到的程度。此外,采用介电隔离结构48缩小源极/漏极结构82的宽度,单元电容可减少5%。
在至少一实施例中,半导体装置包括基板;第一半导体通道,位于基板上;第二半导体通道,位于基板上且横向偏离第一半导体通道;第三半导体通道,位于基板上并横向偏离第二半导体通道;第一栅极结构,位于第一半导体通道上并横向围绕第一半导体通道;第二栅极结构,位于第二半导体通道上并横向围绕第二半导体通道;第三栅极结构,位于第三半导体通道上并横向围绕第三半导体通道;第一非有源鳍状物,位于第一栅极结构与第二栅极结构之间;第二非有源鳍状物,位于第二栅极结构与第三栅极结构之间;桥导体层,位于第一栅极结构、第二栅极结构、第三栅极结构、第一非有源鳍状物、与第二非有源鳍状物上;以及介电插塞,自第二非有源鳍状物的上表面延伸穿过桥导体层至桥导体层的至少上表面。
在一些实施例中,半导体装置还包括:第一介电隔离结构,位于第一非有源鳍状物的第一侧壁上;第二介电隔离结构,位于第二非有源鳍状物的第二侧壁上,且第二侧壁面对第一侧壁;以及源极/漏极结构,自第一侧壁延伸至第二侧壁。
在一些实施例中,第一介电隔离结构包括:第一介电层,具有第一介电常数;以及衬垫层,位于第一介电层与第一侧壁之间。
在一些实施例中,衬垫层与第三栅极结构的栅极间隔物层为连续的相同层。
在一些实施例中,衬垫层包括多晶硅。
在一些实施例中,衬垫层包括具有第二介电常数的介电材料,且第二介电常数低于第一介电常数。
在一些实施例中,第一介电隔离结构包括:衬垫层,位于第一侧壁、隔离结构的上表面、与源极/漏极结构的第三侧壁上;以及第二介电层,横向位于衬垫层的垂直部分之间。
在一些实施例中,衬垫层的介电常数大于第二介电层的介电常数。
在一些实施例中,第一介电隔离结构包括:衬垫层,位于第一侧壁、隔离结构的上表面、与源极/漏极结构的第三侧壁上,且衬垫层的介电常数大于约3.9;以及衬垫层所密封的气体。
在至少一些实施例中,半导体装置包括:基板;第一晶体管,位于基板上且具有延伸于第一方向中的第一栅极结构;第二晶体管,位于基板上且具有延伸于第一方向中且对准第一栅极结构的第二栅极结构,且第二栅极结构与第一栅极结构电性隔离;隔离区,位于基板上且在第一方向中位于第一晶体管与第二晶体管之间;栅极隔离结构,接触第一栅极结构、第二栅极结构、与隔离区。栅极隔离结构包括:第一部分,自隔离区的上表面延伸至第一栅极结构的上表面与第二栅极结构的上表面;以及第二部分,自第一部分的上表面延伸至高于第一栅极结构与第二栅极结构的上表面的高度。
在一些实施例中,半导体装置还包括:粘着层,位于第一栅极结构与第二栅极结构上,其中粘着层包括金属氮化物;以及导电层,位于粘着层上,且导电层包括无氟钨。
在一些实施例中,半导体装置还包括:第三晶体管,具有延伸于第一方向中且对准第一栅极结构的第三栅极结构,且第三栅极结构与第一栅极结构电性隔离;非有源区块,位于第一晶体管与第三晶体管之间;以及第二介电插塞,自非有源区块延伸穿过粘着层与导电层至导电层的至少上表面。
在一些实施例中,半导体装置还包括:介电盖层,位于第一栅极结构与第二栅极结构上,其中第二部分延伸穿过介电盖层,且第二部分的上表面与介电盖层的上表面实质上共平面。
在至少一实施例中,半导体装置的形成方法包括形成第一鳍状物堆叠与第二鳍状物堆叠;以自对准工艺形成非有源鳍状物于第一鳍状物堆叠与第二鳍状物堆叠之间的第一开口中;形成第一栅极结构于第一鳍状物堆叠上,并形成第二栅极结构于第二鳍状物堆叠上,其中非有源鳍状物隔离第一栅极结构与第二栅极结构;在形成第一栅极结构与第二栅极结构之后,形成介电插塞于非有源鳍状物上;以及形成桥导体层于第一栅极结构与第二栅极结构上,其中桥导体层延伸的垂直高度低于介电插塞的上表面。
在一些实施例中,方法还包括:形成介电隔离结构于非有源鳍状物与第一鳍状物堆叠之间;使横向位于介电隔离结构与相邻的介电结构之间的第一鳍状物堆叠的一部分凹陷,以形成第二开口;以及形成源极/漏极区于第二开口中,以接触介电隔离结构并接触第一鳍状物堆叠。
在一些实施例中,形成介电隔离结构的步骤包括:形成衬垫层于第一鳍状物堆叠、第二鳍状物堆叠、与非有源鳍状物的表面上;以及形成具有第一介电常数的第一介电层于衬垫层上,且第一介电层横向位于第一鳍状物堆叠与非有源鳍状物之间,以及第二鳍状物堆叠与非有源鳍状物之间。
在一些实施例中,衬垫层更形成于第一鳍状物堆叠与第二鳍状物堆叠上的虚置栅极结构的侧壁上。
在一些实施例中,衬垫层的介电常数大于第一介电层的介电常数。
在一些实施例中,方法还包括:形成粘着层于第一栅极结构与第二栅极结构上,以延伸至实质上的垂直高度,其中桥导体层的形成方法采用粘着层作为选择性沉积工艺中的籽晶层。
在一些实施例中,方法还包括:以桥导体层电性连接第一栅极结构至第三栅极结构。
上述实施例的特征有利于本技术领域中技术人员理解本发明。本技术领域中技术人员应理解可采用本发明作基础,设计并变化其他工艺与结构以完成上述实施例的相同目的及/或相同优点。本技术领域中技术人员亦应理解,这些等效置换并未脱离本发明精神与范畴,并可在未脱离本发明的精神与范畴的前提下进行改变、替换、或更动。
Claims (1)
1.一种半导体装置,包括:
一基板;
一第一半导体通道,位于该基板上;
一第二半导体通道,位于该基板上且横向偏离该第一半导体通道;
一第三半导体通道,位于该基板上并横向偏离该第二半导体通道;
一第一栅极结构,位于该第一半导体通道上并横向围绕该第一半导体通道;
一第二栅极结构,位于该第二半导体通道上并横向围绕该第二半导体通道;
一第三栅极结构,位于该第三半导体通道上并横向围绕该第三半导体通道;
一第一非有源鳍状物,位于该第一栅极结构与该第二栅极结构之间;
一第二非有源鳍状物,位于该第二栅极结构与该第三栅极结构之间;
一桥导体层,位于该第一栅极结构、该第二栅极结构、该第三栅极结构、该第一非有源鳍状物、与该第二非有源鳍状物上;以及
一介电插塞,自该第二非有源鳍状物的上表面延伸穿过该桥导体层至该桥导体层的至少上表面。
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