CN114759095A - Homotype heterojunction composite channel TFT device and preparation method thereof - Google Patents
Homotype heterojunction composite channel TFT device and preparation method thereof Download PDFInfo
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- 238000002360 preparation method Methods 0.000 title claims abstract description 11
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- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 claims description 21
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- 229910004205 SiNX Inorganic materials 0.000 claims description 13
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- 229910052906 cristobalite Inorganic materials 0.000 claims description 7
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- 229910052682 stishovite Inorganic materials 0.000 claims description 7
- 229910052905 tridymite Inorganic materials 0.000 claims description 7
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 claims description 6
- 238000000151 deposition Methods 0.000 claims description 6
- 229910052733 gallium Inorganic materials 0.000 claims description 6
- 229910052738 indium Inorganic materials 0.000 claims description 6
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
- H01L29/78693—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate the semiconducting oxide being amorphous
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Abstract
The invention discloses a homotype heterojunction composite channel TFT device and a preparation method thereof. Aiming at the key problems of current carrying capacity reduction, reliability degradation and the like of a TFT (thin film transistor) device caused by high-density oxygen vacancy related defect states at an amorphous IGZO material and a channel interface, the invention innovatively adopts a method of nN type a-IGZO, N/ITO and N type heterojunction channel structure design and nitrogen doping to effectively inhibit the trapping effect of defects and realize the high-performance and high-reliability application of the TFT device.
Description
Technical Field
The invention relates to a homotype heterojunction composite channel TFT device and a preparation method thereof, in particular to an nN-type a-IGZO (indium gallium zinc oxide) N/ITO (indium tin oxide) N homotype heterojunction composite channel TFT device structure and a preparation method thereof, belonging to the technical field of information materials and devices.
Background
In recent years, a technique for manufacturing a metal oxide Thin Film Transistor (TFT) represented by a novel transparent amorphous InGaZnO-based thin film transistor (a-IGZO) has been proposed because of its high field-effect electron mobility (a-IGZO)>10cm2Vs), high optical transmittance (E)g>3.0eV), low power consumption, low cost and the like, and has remarkable application prospect in the technologies of active matrix organic light emitting diode display (AM-OLED), active matrix liquid crystal display (AM-LCD) and System-on-panel (SoP); meanwhile, the a-IGZO TFT prepared at room temperature still has good device performance, so that the TFT device can be compatible with a flexible substrate, and further has a certain application prospect in transparent electronic paper and transparent display technologies. Although the a-IGZO TFT has excellent device performance, the electrical performance and reliability of the device are seriously influenced by the distribution of high-density band tail states and sub-band states in a material system due to the inherent amorphous characteristic of the a-IGZO material. Research shows that the high-density sub-band state existing in the band gap of the a-IGZO material is mainly composed of oxygen vacancies (V)o) The relevant defects are induced and fully occupied by electrons in the energy range of-1.5 eV at the top of the valence band. When the device is excited by sub-band light, electrons in an occupied state are excited to a conduction band, so that oxygen vacancies lose electrons and are converted into monovalent oxygen vacancy ions (V)o +) Divalent oxygen vacancy ion (V)o 2+) And adjacent metal atoms are caused to generate lattice relaxation during the conversion process, and new oxygen vacancy related defect states are generated in the middle of a band gap and at the bottom of a conduction band, thereby causing the degradation of the electrical performance and reliability of the a-IGZO TFT. In addition, the defect characteristics of the a-IGZO material system have a complex influence on the interface characteristics between the gate dielectric layer and the channel layer of the TFT device. Studies have demonstrated that the high density of defects present at the a-IGZO TFT interface also originate primarily from oxygen vacancy related defects, which trap electrons/holes in the channel from oxygen vacancy related defects at the interface when the device is operated under gate voltage stress, causing the threshold voltage of the device to drift. In summary, the degradation mechanism of the reliability of the a-IGZO TFT device is related to the oxygen vacancy related defects at the a-IGZO material system and the device interfaceAccordingly, effectively suppressing the generation of oxygen vacancy related defects at the interface of the a-IGZO material system and the device will significantly improve the reliability of the a-IGZO TFT device.
At present, a method for regulating and controlling oxygen vacancy defects by doping N in an a-IGZO channel layer is widely researched, the regulation and control mechanism is that the ion radius of N is close to that of O, and N atoms are easy to replace O atoms in a lattice structure, so that the generation of oxygen vacancy defects in the a-IGZO material is effectively inhibited; meanwhile, the valence band of the a-IGZO material can be reformed due to the hybridization effect of the N2 p electron orbit and the O2 p electron orbit, so that oxygen vacancy defect failure is caused, the oxygen vacancy related defect density of the valence band top to 1.5eV is reduced, and the electrical reliability of the TFT under the irradiation of sub-band light is obviously improved. But at the same time the oxygen vacancies, as intrinsic donors in the a-IGZO material system, are the primary source of channel carriers for the TFT device (i.e., each oxygen vacancy provides two electrons). Therefore, the N doping technology inhibits the concentration of donor oxygen vacancy defects in the a-IGZO material, so that the concentration of current carriers in a channel of the TFT device is reduced, and the electrical performance of the a-IGZO TFT device is further influenced.
As can be seen from the extended exponential function model of the a-IGZO TFT device, the electrical reliability of the TFT device is influenced by the average effective potential barrier (E) at the channel layer and the interfaceτ) High influence. Under gate compressive stress, carriers in the TFT channel need to overcome the interface mean effective barrier to be captured by defects in the interface or dielectric layer.
ΔVth＝ΔVth0{1-exp[-(t/τ)β]}，τ＝τ0exp(Eτ/kBT) (1)
Research shows that the interface quality can be effectively improved and the interface quality can be effectively improved by introducing the ultrathin N-doped a-IGZO into the a-IGZO TFT interfaceτSignificantly reduces the TFT device threshold voltage drift. Based on this, as known from the semiconductor heterojunction energy band theory-Anderson model, at the nN homotype semiconductor heterojunction interface, an energy valley is formed on the narrow-band (N) semiconductor side and a peak is formed on the wide-band (N) semiconductor side due to the discontinuity of the energy band on the interface, so that a higher energy band barrier is formed at the interface. The potential barrier can inhibit channel carriers from being interfacedOr the defects in the dielectric layer are captured, so that the limit of oxygen vacancy defects on the performance and reliability of the a-IGZO TFT device can be broken through. It is known that a transparent Indium Tin Oxide (ITO) thin film has a wide band gap (3.8eV to 4.3eV) and high conductivity (30 cm)2Vs), and the like, and the n-type heterojunction is formed by combining the a-IGZO thin film material (3.0 eV-3.5 eV). The nN type a-IGZO/ITO homotype heterojunction is used as a TFT channel layer, and the limitation of the defects of an a-IGZO material system on the performance and reliability of a device is broken through by the formation of a heterojunction energy band barrier and an N doping method. Namely, a nitrogen-doped ITO/N insertion layer is introduced at the interface of the a-IGZO/N TFT device to form a high potential barrier at the a-IGZO/N/ITO/N heterojunction to inhibit channel carriers from being captured by defects in the interface or the dielectric layer. Meanwhile, based on the high conductivity of the ITO N thin film material, when the TFT is in an on state, the ITO N insertion layer can compensate the channel carrier concentration, and the on-state current and the field effect mobility of the device are increased; the back channel layer a-IGZO: N still has a high resistance in the off-state of the TFT, enabling the device to have a low off-state current. In addition, due to the introduction of nitrogen doping, the regulation and control of oxygen vacancy related defects at the interface of a thin film material and a device can be realized, and the realization of a high-performance and high-reliability a-IGZO TFT device is further ensured.
Disclosure of Invention
In order to solve the problems in the prior art, the invention provides a homotype heterojunction composite channel TFT device and a preparation method thereof.
In order to achieve the purpose, the invention adopts the technical scheme that: a homotype heterojunction composite channel TFT device comprises a substrate, a gate electrode layer, a gate dielectric layer, ultrathin ITO (indium tin oxide), an N active layer, a-IGZO, an N active layer, a passivation layer and a source/drain metal electrode layer;
the gate electrode layer is divided into a bottom gate structure and a top gate structure by the position of the gate electrode layer, the bottom of the bottom gate structure is a substrate, and the gate electrode layer, a gate dielectric layer, ultrathin ITO (indium tin oxide), an N active layer, a-IGZO (indium tin oxide), the N active layer and a source/drain metal electrode layer are sequentially stacked above the substrate from bottom to top as required; the upper surface of the a-IGZO N active layer is also covered with a passivation layer;
the bottom of the top gate structure is also a substrate, and a-IGZO are sequentially stacked from bottom to top above the substrate according to requirements: an N active layer, an ultrathin ITO, an N active layer, a source/drain metal electrode layer, a gate dielectric layer and a gate electrode layer.
Further, the substrate is a glass substrate; the thickness of the gate electrode layer is 50-300 nanometers; the thickness of the gate dielectric layer is 50-400 nanometers; the thickness of the ultrathin ITO N active layer is 2-5 nanometers, and the thickness of the a-IGZO N active layer is 25-60 nanometers; the thickness of the passivation layer is 100-350 nanometers; the thickness of the source/drain metal electrode layer is 50-300 nanometers.
A method for preparing a homotype heterojunction composite channel TFT device comprises the following steps,
and 2, preparing a top gate structure.
Further, the preparation method of the bottom gate structure comprises the following steps:
step 1.1, obtaining a substrate;
step 1.2, manufacturing a gate metal electrode layer on the substrate by adopting a photoetching process and an electron beam evaporation process;
step 1.3, preparing gate dielectric layer SiO by adopting PECVD process2、SiNxEtc.;
step 1.4, depositing nitrogen-doped ultrathin ITO (indium tin oxide) as an N active layer and a-IGZO as an N active layer on the gate dielectric layer in sequence by adopting a sputtering system;
step 1.5, realizing device isolation on the ultrathin ITO (indium tin oxide) N active layer and the a-IGZO N active layer by adopting a photoetching process and a wet etching process or a dry etching process;
step 1.6, preparing metal source and drain electrode layers by adopting photoetching and electron beam evaporation processes;
step 1.7, preparing a channel by adopting a stripping technology after the preparation of the source electrode and the drain electrode;
step 1.8, preparing SiO by adopting PECVD process2Or SiNxAn equal passivation layer;
and step 1.9, etching the passivation layer by adopting a photoetching process and a wet or dry etching process to expose the source/drain electrode.
Further, the specific preparation steps of the top gate structure are as follows:
step 2.1, obtaining a substrate;
2.2, sequentially depositing nitrogen-doped a-IGZO (indium gallium zinc oxide) active layer and ultrathin ITO (indium tin oxide) active layer on the substrate by adopting a sputtering system;
step 2.3, realizing device isolation on the active layers of the a-IGZO, N and the ultrathin ITO, N by adopting a photoetching process and a wet or dry etching process;
step 2.4, preparing a metal source electrode and a metal drain electrode by adopting a photoetching process and an electron beam evaporation process after the device is isolated by etching;
step 2.5, preparing the SiO of the gate dielectric layer by adopting a PECVD process2、SiNxEtc.;
and 2.6, etching to expose the source/drain electrode by adopting a photoetching process and a wet etching process or a dry etching process.
And 2.7, preparing a gate metal electrode by adopting a photoetching process and an electron beam evaporation process.
Furthermore, the gate electrode layer is made of conductive metal, and is manufactured by adopting an electron beam evaporation process, and the thickness of the gate electrode layer is about 50-300 nanometers.
Further, the gate dielectric layer is made of SiO2、SiNxAnd the thickness is about 50-400 nm by adopting a PECVD process during manufacturing.
Further, the ultrathin nitrogen-doped ITO and a-IGZO active layer are formed by performing magnetron sputtering on the ITO and the a-IGZO active layers in Ar + O2+N2And growing the ultrathin ITO under the condition of mixed sputtering atmosphere, wherein the thickness of the N active layer of the ultrathin ITO is 2-5 nanometers, and the thickness of the a-IGZO N active layer of the ultrathin ITO is 25-60 nanometers.
Furthermore, the source/drain electrodes are made of conductive metal, and the thickness of the source/drain electrodes is 50-300 nanometers by adopting an electron beam evaporation process during manufacturing.
Further, the passivation layer is made of SiO2Or SiNxAnd the thickness is 100-350 nm by adopting a PECVD process during manufacturing.
Compared with the prior art, the invention has the beneficial effects that:
n-type a-IGZO, N/ITO and N-type heterojunction are used as a TFT channel layer, namely a nitrogen-doped ultrathin interface ITO and an N insertion layer are introduced into the interface of an a-IGZO and N TFT device to form a high potential barrier at the N-type heterojunction to inhibit channel carriers from being captured by defects in the interface or the dielectric layer; meanwhile, based on the high conductivity of the ITO and N thin film materials, when the TFT is in an on state, the ultrathin ITO and N insertion layer can compensate the channel carrier concentration, and the on-state current and the field effect electron mobility of the device are increased; and when the TFT is in an off state, the back channel layer a-IGZO: N still has high resistance, so that the device can have low off-state current. In addition, due to the introduction of nitrogen doping, the regulation and control of oxygen vacancy related defects at the interface of the thin film material and the device can be realized, and the realization of the high-performance and high-reliability a-IGZO TFT device is further ensured.
Drawings
FIG. 1 is a bottom gate structure schematic diagram of an nN type a-IGZO: N/ITO: N homotype heterojunction composite channel TFT device of the invention.
FIG. 2 is a schematic diagram of a top gate structure of an nN type a-IGZO/N/ITO/N homotype heterojunction composite channel TFT device.
Fig. 3 is a flow chart of a bottom gate structure and a top gate structure in the present invention.
FIG. 4 is a flow chart of a method for fabricating a bottom gate structure according to the present invention.
FIG. 5 is a flow chart of a method for fabricating a top gate structure according to the present invention.
Description of the bottom gate structure figures: the thin film transistor comprises a substrate 1, a gate electrode layer 2, a gate dielectric layer 3, an ultrathin ITO (indium tin oxide) N active layer 4, an A-IGZO N active layer 5, a source/drain metal electrode layer 6 and a passivation layer 7.
Description of the top gate structure figures: the thin film transistor comprises a 1-substrate, a 2-IGZO (indium gallium zinc oxide) N active layer, a 3-ultrathin ITO (indium tin oxide) N active layer, a 4-source/drain metal electrode layer, a 5-gate dielectric layer and a 6-gate electrode layer.
Detailed Description
Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings. The embodiments described below with reference to the accompanying drawings are illustrative only for the purpose of explaining the present invention, and are not to be construed as limiting the present invention.
The invention discloses an nN type a-IGZO (indium tin oxide)/ITO (indium tin oxide) and N type heterojunction composite channel TFT (thin film transistor) device structure. The structure is divided into a bottom gate structure and a top gate structure according to the position of the gate electrode layer.
The bottom gate structure is shown in fig. 1, and comprises a substrate 1, a gate electrode layer 2, a gate dielectric layer 3, an ultrathin ITO (indium tin oxide), an N active layer 4, an a-IGZO, an N active layer 5, a source/drain metal electrode layer 6 and a passivation layer 7 which are sequentially stacked according to needs, and the bottom gate structure comprises the following steps:
and S001, obtaining the substrate.
The substrate may be a rigid substrate (e.g., glass) or a flexible substrate as is known in the art. In this embodiment, the substrate is Corning glass (Corning glass) glass.
And S002, manufacturing a gate electrode layer on the substrate by adopting a photoetching process and an electron beam evaporation process.
In the present embodiment, the gate electrode layer is made of conductive metal and has a thickness of about 50 to 300 nm.
And S003, forming a gate dielectric layer on the gate electrode layer through a PECVD process.
In this embodiment, the gate dielectric layer is made of SiO2、SiNxAnd the thickness is about 50 to 400 nanometers.
S004, depositing an ultrathin ITO: N active layer and an a-IGZO: N active layer in sequence through a sputtering system.
In this example, the ultra-thin ITO: N active layer and the a-IGZO: N active layer both use a magnetron sputtering system at Ar + O2+N2And growing under the condition of mixed sputtering atmosphere. The thickness of the N active layer of the ultrathin ITO is about 2-5 nanometers, and the thickness of the N active layer of the a-IGZO is about 25-60 nanometers.
And S005, forming a source electrode on one side of the N active layer of the a-IGZO, and forming a drain electrode on the other side of the N active layer of the a-IGZO.
In this embodiment, an electron beam evaporation process is used to prepare the metal source and drain, and the source and drain are made of conductive metal and have a thickness of about 50-300 nm.
And S006, forming a passivation layer on the a-IGZO: N active layer through a PECVD process.
In this embodiment, the passivation layer is made of SiO2Or SiNxThe thickness is about 100 to 350 nm.
And S007, etching the passivation layer by adopting a photoetching process and a wet etching process or a dry etching process to expose the source/drain electrodes.
The top gate structure is shown in fig. 2, and comprises a glass substrate 1, an a-IGZO (indium gallium zinc oxide) N active layer 2, an ultrathin ITO (indium tin oxide) N active layer 3, a source/drain metal electrode layer 4, a gate dielectric layer 5 and a gate electrode layer 6 which are sequentially stacked according to needs, and comprises the following steps:
s001, obtaining the substrate.
The substrate may be a rigid substrate (e.g., glass) or a flexible substrate as is known in the art. In this embodiment, the substrate is Corning glass (Corning glass) glass.
S002, depositing an a-IGZO N active layer and an ultrathin ITO N active layer in sequence through a sputtering system.
In this example, the ultra-thin ITO: N active layer and the a-IGZO: N active layer were both formed using a magnetron sputtering system at Ar + O2+N2And growing under the condition of mixed sputtering atmosphere. The thickness of the N active layer of the ultrathin ITO is about 2-5 nanometers, and the thickness of the N active layer of the a-IGZO is about 25-60 nanometers.
And S003, forming a source electrode on one side of the ultrathin ITO-N active layer and forming a drain electrode on the other side of the ultrathin ITO-N active layer.
In this embodiment, an electron beam evaporation process is used to prepare the metal source and drain, and the source and drain are made of conductive metal and have a thickness of about 50-300 nm.
And S004, preparing the gate dielectric layer by a PECVD process.
In this embodiment, the passivation layer is made of SiO2Or SiNxThe thickness is about 100 to 350 nm.
And S005, etching to expose the source/drain electrode by adopting a photoetching process and a wet or dry etching process.
And S006, forming a gate electrode layer on the gate dielectric layer by an electron beam evaporation method.
In the present embodiment, the gate electrode layer is made of conductive metal and has a thickness of about 50 to 300 nm.
Compared with the prior art, the technical scheme adopted by the invention has the following technical effects: n-type a-IGZO, N/ITO and N-type heterojunction are used as a TFT channel layer, namely a nitrogen-doped ultrathin interface ITO and an N insertion layer are introduced into the interface of an a-IGZO and N TFT device to form a high potential barrier at the N-type heterojunction to inhibit channel carriers from being captured by defects in the interface or the dielectric layer; meanwhile, based on the high conductivity of the ITO and N thin film materials, when the TFT is in an on state, the ultrathin ITO and N insertion layer can compensate the channel carrier concentration, and the on-state current and the field effect electron mobility of the device are increased; and when the TFT is in an off state, the back channel layer a-IGZO: N still has high resistance, so that the device can have low off-state current. In addition, due to the introduction of nitrogen doping, the regulation and control of oxygen vacancy related defects at the interface of a thin film material and a device can be realized, and the realization of a-IGZO TFT device with high performance and high reliability is further ensured.
The invention has various embodiments, and all technical solutions formed by adopting equivalent transformation or equivalent transformation are within the protection scope of the invention.
It should be noted that the above-mentioned embodiments illustrate rather than limit the invention, and that those skilled in the art will be able to design alternative embodiments without departing from the scope of the appended claims.
Claims (10)
1. A homotype heterojunction composite channel TFT device is characterized in that: the thin film transistor comprises a substrate, a gate electrode layer, a gate dielectric layer, ultrathin ITO (indium tin oxide), an N active layer, a-IGZO, an N active layer, a passivation layer and a source/drain metal electrode layer;
the gate electrode layer is divided into a bottom gate structure and a top gate structure by the position of the gate electrode layer, the bottom of the bottom gate structure is a substrate, and the gate electrode layer, a gate dielectric layer, ultrathin ITO (indium tin oxide), an N active layer, a-IGZO (indium tin oxide), the N active layer and a source/drain metal electrode layer are sequentially stacked above the substrate from bottom to top as required; the upper surface of the a-IGZO N active layer is also covered with a passivation layer;
the bottom of the top gate structure is also a substrate, and an a-IGZO (indium gallium zinc oxide) N active layer, an ultrathin ITO (indium tin oxide) N active layer, a source/drain metal electrode layer, a gate dielectric layer and a gate electrode layer are sequentially stacked on the substrate from bottom to top as required.
2. The homotype heterojunction composite channel TFT device of claim 1, wherein: the substrate is a glass substrate; the thickness of the gate electrode layer is 50-300 nanometers; the thickness of the gate dielectric layer is 50-400 nanometers; the thickness of the ultrathin ITO N active layer is 2-5 nanometers, and the thickness of the a-IGZO N active layer is 25-60 nanometers; the thickness of the passivation layer is 100-350 nanometers; the thickness of the source/drain metal electrode layer is 50-300 nanometers.
3. A method for fabricating a homotype heterojunction composite channel TFT device according to claim 1, wherein: comprises the following specific steps of (a) preparing,
step 1, preparing a bottom gate structure;
and 2, preparing a top gate structure.
4. The method of fabricating a homotype heterojunction composite channel TFT device according to claim 3, wherein: the preparation method of the bottom gate structure comprises the following steps:
step 1.1, obtaining a substrate;
step 1.2, manufacturing a gate metal electrode layer on the substrate by adopting a photoetching process and an electron beam evaporation process;
step 1.3, preparing gate dielectric layer SiO by adopting PECVD process2、SiNxEtc.;
step 1.4, depositing nitrogen-doped ultrathin ITO (indium tin oxide) as an N active layer and a-IGZO as an N active layer on the gate dielectric layer in sequence by adopting a sputtering system;
step 1.5, realizing device isolation on the ultrathin ITO, N active layer and the a-IGZO, N active layer by adopting a photoetching process and a wet or dry etching process;
step 1.6, preparing metal source and drain electrode layers by adopting photoetching and electron beam evaporation processes;
step 1.7, preparing a channel by adopting a stripping technology after the preparation of the source electrode and the drain electrode;
step 1.8, preparing SiO by adopting PECVD process2Or SiNxAn equal passivation layer;
and step 1.9, etching the passivation layer by adopting a photoetching process and a wet etching process or a dry etching process to expose the source/drain electrode.
5. The method of fabricating a homotype heterojunction composite channel TFT device according to claim 3, wherein: the top gate structure is prepared by the following specific steps:
step 2.1, obtaining a substrate;
2.2, sequentially depositing a nitrogen-doped a-IGZO (indium gallium zinc oxide) N active layer and an ultrathin ITO (indium tin oxide) N active layer on the substrate by adopting a sputtering system;
step 2.3, realizing device isolation on the active layers of the a-IGZO, N and the ultrathin ITO, N by adopting a photoetching process and a wet or dry etching process;
step 2.4, preparing a metal source electrode and a metal drain electrode by adopting a photoetching process and an electron beam evaporation process after the device is isolated by etching;
step 2.5, preparing the SiO of the gate dielectric layer by adopting a PECVD process2、SiNxEtc.;
and 2.6, etching to expose the source/drain electrode by adopting a photoetching process and a wet etching process or a dry etching process.
And 2.7, preparing the gate metal electrode by adopting a photoetching process and an electron beam evaporation process.
6. The method of fabricating a homotype heterojunction composite channel TFT device according to claim 3, wherein: the gate electrode layer is made of conductive metal, an electron beam evaporation process is adopted during manufacturing, and the thickness is about 50-300 nanometers.
7. The method of fabricating a homotype heterojunction composite channel TFT device according to claim 3, wherein: the gate dielectric layer is made of SiO2、SiNxAnd the thickness is about 50-400 nm by adopting a PECVD process during manufacturing.
8. The method of fabricating a homotype heterojunction composite channel TFT device according to claim 3, wherein: the ultrathin nitrogen-doped ITO (indium tin oxide) N active layer and the a-IGZO N active layer are formed in an Ar + O (argon-oxygen) atmosphere by a magnetron sputtering system2+N2And growing the ultrathin ITO under the condition of mixed sputtering atmosphere, wherein the thickness of the N active layer of the ultrathin ITO is 2-5 nanometers, and the thickness of the N active layer of the a-IGZO is 25-60 nanometers.
9. The method for preparing a homotype heterojunction composite channel TFT device according to claim 3, wherein: the source/drain electrodes are made of conductive metal, and the thickness of the source/drain electrodes is 50-300 nanometers by adopting an electron beam evaporation process during manufacturing.
10. The method for preparing a homotype heterojunction composite channel TFT device according to claim 3, wherein: the passivation layer is made of SiO2Or SiNxAnd the manufacturing process adopts a PECVD process, and the thickness is 100-350 nanometers.
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