CN102723367B - Oxide semiconductor thin film transistor - Google Patents
Oxide semiconductor thin film transistor Download PDFInfo
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- CN102723367B CN102723367B CN201210223163.7A CN201210223163A CN102723367B CN 102723367 B CN102723367 B CN 102723367B CN 201210223163 A CN201210223163 A CN 201210223163A CN 102723367 B CN102723367 B CN 102723367B
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- oxide semiconductor
- channel layer
- source electrode
- semiconductor thin
- drain electrode
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Abstract
The invention provides an oxide semiconductor thin film transistor which comprises a substrate, a gate electrode, an insulation dielectric layer and an oxide semiconductor channel layer, wherein the gate electrode, the insulation dielectric layer and the oxide semiconductor channel layer are sequentially arranged on the substrate, the insulation dielectric layer enables the gate electrode and the oxide semiconductor channel layer to be insulted, a drain electrode and a source electrode are arranged on the upper surface of the oxide semiconductor channel layer, a gap between the drain electrode and the source electrode is d1, the length of an overlapping region of the source electrode and the gate electrode in the horizontal direction is d2, contact between the source electrode and the oxide semiconductor channel layer is schottky contact, and the contact between the drain electrode and the oxide semiconductor channel layer is ohmic contact. The short-channel effect on the oxide semiconductor thin film transistor is small due to new geometrical characteristics and operating principles, and the oxide semiconductor thin film transistor is favorable for improvement of consistency.
Description
Technical field
The present invention relates to a kind of oxide semiconductor thin-film transistor, belong to flat display field.
Background technology
Thin-film transistor (thin-film transistor), as the active driving device of flat-panel monitor, becomes the key technology of flat display field.Oxide semiconductor is (as IGZO, AZO, GZO, ZnO etc.) thin-film transistor is with advantages such as its high transparent, high mobility, high current switching ratio, low technological temperature and simple manufacturing process, have good development prospect, can be used on high performance TFT-LCD or AMOLED display screen.
But, current oxide semiconductor thin-film transistor at work (as under constant voltage or constant current mode) its threshold voltage passing in time easily produces drift, thus have impact on the stability of threshold voltage, and then cause the harmful effect to display picture element light levels.
Research finds, the concentration of charge carrier is very large on the impact of threshold voltage, traditional oxide semiconductor source electrode is all ohmic contact with drain electrode and contacting of oxide semiconductor channel layer, what oxide semiconductor (normally n-type semiconductor) surface was formed is negative space charge region, direction of an electric field points in body by surface, sheet electron concentration is than much bigger in body, so source electrode barrier region is a high conductance region.During the work of this thin-film transistor, saturation current is determined by the pinch off (pinch-off) of drain terminal conduction, and carrier concentration is large, thus increases the impact on threshold voltage, and then have impact on the job stability of oxide semiconductor thin-film transistor.
Summary of the invention
Therefore, the technical problem to be solved in the present invention is to provide a kind of oxide semiconductor thin-film transistor being improved job stability by carrier concentration during reduction work.
Another technical problem that the present invention will solve is the oxide semiconductor thin-film transistor providing a kind of consistency higher.
For this reason, the invention provides a kind of oxide semiconductor thin-film transistor, comprise substrate and gate electrode, insulating medium layer and oxide semiconductor channel layer is on the substrate set in turn, described insulating medium layer makes described gate electrode and the insulation of described oxide semiconductor channel layer, the upper surface of described oxide semiconductor channel layer arranges drain electrode and source electrode, and the gap between described drain electrode and described source electrode is d
1, the length of described source electrode and described grid overlapping region is in the horizontal direction d
2, the contact between described source electrode and described oxide semiconductor channel layer is Schottky contacts, and the contact between described drain electrode and described oxide semiconductor channel layer is ohmic contact.
Gap d between described drain electrode and described source electrode
1scope be 1 ~ 20 μm.
The position be positioned between described source electrode and described drain electrode on described oxide semiconductor channel layer arranges the etching barrier layer of fitting with described conductor oxidate channel layer, and the length of described etching barrier layer (301) is than the gap d between described source electrode and described drain electrode
1large 1 ~ 5um.
Described etching barrier layer is the one of carrying on the back channel-etch type structure or stopping in etching type structure.
The another side that described etching barrier layer and described oxide semiconductor channel layer are fitted arranges passivation layer.
The thickness of described passivation layer is 100-400nm.
Described substrate is made up of monocrystalline silicon, glass or flexible substrate.
One deck resilient coating is set between described substrate and described grid.
The thickness of described resilient coating is 100-400nm.
Described resilient coating is by SiO
2and/or Si
3n
4composition.
Described gate electrode is made up of any one in Mo, MoW, n++Si, T, Al or ITO.
Described insulating medium layer is by SiO
2, Si
3n
4or Al
2o
3in one or more make.
Described oxide semiconductor channel layer is by IGZO, IGO, ZTO, GZO, ZnO, In
2o
3, Cu
2o or SnO
2in one or more make.
Described etching barrier layer is by SiO
2, Si
3n
4, TiO
2, Al
2o
3or one or more in ZTSO are made.
The length d of described source electrode and described grid overlapping region in the horizontal direction
2scope be 3-20 μm.
The length range of described drain electrode and described gate electrode overlapping region is in the horizontal direction 0-3 μm.
Described oxide semiconductor channel layer can be N-shaped raceway groove or p-type raceway groove.The selection of source, drain electrode is according to shown in table 1.And if N-shaped oxide semiconductor form ohmic contact, need to select the work function metal lower than N-shaped oxide semiconductor as drain electrode; Select the work function metal higher than semiconductor as source electrode, thus and form Schottky contacts between semiconductor.For p-type oxide semiconductor, source, the leakage selection of metal electrode and the contrary of N-shaped.
In the present invention, the I in chemical formula represents In element, and G represents Ga element, and Z represents Zn element, and O represents oxygen element, and T represents Sn element.
Oxide semiconductor thin-film transistor provided by the invention has the following advantages:
1. oxide semiconductor thin-film transistor provided by the invention, comprise substrate and gate electrode, insulating medium layer and oxide semiconductor channel layer is on the substrate set in turn, described insulating medium layer makes described gate electrode and the insulation of described oxide semiconductor channel layer, the upper surface of described oxide semiconductor channel layer arranges drain electrode and source electrode, and the gap between described drain electrode and described source electrode is d
1, the length of described source electrode and described gate electrode overlapping region is in the horizontal direction d
2, the contact between described source electrode and described oxide semiconductor channel layer is Schottky contacts, and the contact between described drain electrode and described oxide semiconductor channel layer is ohmic contact.Carrier transport in thin-film transistor, open electric current and saturation current and control primarily of the source electrode potential barrier of reverse biased.In the present invention, because the contact between described source electrode and described oxide semiconductor (normally N-shaped) channel layer is Schottky contacts, a positive space charge region is formed at semiconductor surface, wherein direction of an electric field points to surface by body, it makes semiconductor surface electron energy higher than in body, can be bent upwards by band, namely surface potential barrier is formed, in barrier region, space charge is formed primarily of ionized donor, electron concentration is than much little in body, therefore be a high resistance region, during the work of this thin-film transistor, carrier concentration is than source/raceway groove, leakage/raceway groove is that the transistor of ohmic contact is much lower entirely, therefore the stability of oxide semiconductor thin-film transistor provided by the invention is higher.
2. oxide semiconductor thin-film transistor provided by the invention, due to geometric properties and the operation principle of new construction, oxide semiconductor thin-film transistor provided by the invention can work under short channel and thick gate dielectric layer condition, make the transmission current of described oxide semiconductor thin-film transistor little by short-channel effects, thus make the consistency of oxide semiconductor thin-film transistor provided by the invention higher.
Accompanying drawing explanation
Fig. 1 is the structural representation without the oxide semiconductor thin-film transistor of etching barrier layer provided by the invention;
Fig. 2 is the structural representation with the oxide semiconductor thin-film transistor of etching barrier layer provided by the invention.
In figure, Reference numeral is expressed as:
101-substrate; 102-grid; 103-insulating medium layer; 104-oxide semiconductor channel layer; 201-drain electrode; 202-source electrode; 301-etching barrier layer.
Embodiment
Core object of the present invention is to provide a kind of oxide semiconductor thin-film transistor being improved job stability by regulation and control carrier concentration.
Fig. 1 is the structural representation without the oxide semiconductor thin-film transistor of etching barrier layer provided by the invention, Fig. 2 is the structural representation with the oxide semiconductor thin-film transistor of etching barrier layer provided by the invention, embodiment will be provided below, and specific explanations technical scheme of the present invention by reference to the accompanying drawings, the condition forming ohmic contact (anti-drag barrier) or Schottky contacts (barrier layer) in embodiment between oxide semiconductor (N-shaped and p-type) and metal electrode is as shown in table 1, wherein W
mand W
sthe work function of metal and semiconductor respectively.Work function such as the table 2 of various metallic element provides.
Embodiment 1
As shown in Figure 2, the present embodiment provides a kind of oxide semiconductor thin-film transistor, comprise substrate 101 and be arranged on gate electrode 102, insulating medium layer 103 and the oxide semiconductor channel layer 104 on described substrate 101 in turn, described insulating medium layer 103 makes described gate electrode 102 and described oxide semiconductor channel layer 104 insulate, the upper surface of described oxide semiconductor channel layer 104 arranges drain electrode 201 and source electrode 202, and the gap between described drain electrode 201 and described source electrode 202 is d
1, described source electrode 202 is d with the length of described grid 102 overlapping region in the horizontal direction
2, the contact between described source electrode 202 and described oxide semiconductor channel layer 104 is Schottky contacts, and the contact between described drain electrode 201 and described oxide semiconductor channel layer 104 is ohmic contact.
For the ease of forming electric field between grid 102 and source electrode 202, thus be beneficial to carrier transport, the length d of described source electrode 202 and described grid 102 overlapping region in the horizontal direction
2scope be 3-20 μm, in the present embodiment, d
2it is 3 μm.
In the present invention, the gap d between described drain electrode 201 and described source electrode 202
1scope be 1 ~ 20 μm, in the present embodiment, the gap d between described drain electrode 201 and described source electrode 202
1it is 1 μm.
In the present embodiment, the position be positioned between described source electrode 202 and described drain electrode 201 on described oxide semiconductor channel layer 104 arranges the etching barrier layer 301 of fitting with described conductor oxidate channel layer 104, and the length of described etching barrier layer 301 is than the gap d between source electrode 202 and described drain electrode 201
1large 1 μm, namely the length of described etching barrier layer 301 is 2 μm.In order to meet core object of the present invention, the length of described etching barrier layer 301 is than the gap d between source electrode 202 and described drain electrode 201
1during large 1-5 μm, can designing requirement of the present invention.
In the present embodiment, described oxide semiconductor thin-film transistor is etch stopper type structure.
In the present embodiment, described etching barrier layer 301 is by SiO
2make, it should be noted that, for realizing core object of the present invention, the material of described etching barrier layer 301 is not construed as limiting, and described etching barrier layer 301 can also by Si
3n
4, TiO
2or Al
2o
3in one or more make.
In the present embodiment, the another side that described etching barrier layer 301 and described oxide semiconductor channel layer 104 are fitted arranges passivation layer, the thickness of described passivation layer is 100nm, for realizing core object of the present invention, can meet design requirement when the thickness of described passivation layer is 100-400nm.
It should be noted that, in the present embodiment, in order to realize core object of the present invention, described etching barrier layer 301 is optional, and oxide semiconductor thin-film transistor as shown in Figure 1 does not just have described etching barrier layer 301.
In the present embodiment, described substrate 101 is made up of silicon, certainly, described substrate 101 can also adopt glass or flexible substrate to make, and flexible substrate can be polyimide(polyimides in the present invention), PET(PETG), PEN(PEN), PES(is poly-to benzene diethyl sulfone) or Parylene(xylylene po1ymer) etc.
In the present embodiment, between described substrate 101 and described grid 102, arrange one deck resilient coating, the thickness of described resilient coating is 100nm, certainly, for meeting core object of the present invention, can meet design requirement when the thickness of described resilient coating is arranged between 100-400nm.In the present embodiment, described resilient coating SiO
2make separately, described resilient coating can also by Si
3n
4make separately, or by SiO
2and Si
3n
4jointly make.
In the present embodiment, described gate electrode 102 is made up of Mo, and it can also be made up of any one in MoW, n++Si, T, Al or ITO.
In the present embodiment, described insulating medium layer 103 is by SiO
2make, it can also by ZTSO, Si
3n
4or Al
2o
3in one or more make, be prepared from by the method for PECVD, sputtering or ALD (ald).
In the present embodiment, described oxide semiconductor channel layer 104 is made up of IGOZ, and it can also by IGO, ZTO, GZO, ZnO, In
2o
3, Cu
2o or SnO
2in one or more make.Described oxide semiconductor channel layer 104 is N-shaped raceway groove.Described oxide semiconductor channel layer 104 generally adopts the mode of sputtering to be formed.
In the present embodiment, described drain electrode 201 is 3 μm with the length of described gate electrode 102 overlapping region in the horizontal direction, and for the present invention, described drain electrode 201 is 0-3 μm with the length range of described gate electrode 102 overlapping region in the horizontal direction.
Embodiment 2
As shown in Figure 2, the present embodiment provides a kind of oxide semiconductor thin-film transistor, comprise substrate 101 and be arranged on gate electrode 102, insulating medium layer 103 and the oxide semiconductor channel layer 104 on described substrate 101 in turn, described insulating medium layer 103 makes described gate electrode 102 and described oxide semiconductor channel layer 104 insulate, the upper surface of described oxide semiconductor channel layer 104 arranges drain electrode 201 and source electrode 202, and the gap between described drain electrode 201 and described source electrode 202 is d
1, described source electrode 202 is d with the length of described grid 102 overlapping region in the horizontal direction
2, the contact between described source electrode 202 and described oxide semiconductor channel layer 104 is Schottky contacts, and the contact between described drain electrode 201 and described oxide semiconductor channel layer 104 is ohmic contact.
For the ease of forming electric field between grid 102 and source electrode 202, thus be beneficial to carrier transport, the length d of described source electrode 202 and described grid 102 overlapping region in the horizontal direction
2scope be 3-20 μm, in the present embodiment, d
2it is 20 μm.
In the present invention, the gap d between described drain electrode 201 and described source electrode 202
1scope be 1 ~ 20 μm, in the present embodiment, the gap d between described drain electrode 201 and described source electrode 202
1it is 20 μm.
In the present embodiment, the position be positioned between described source electrode 202 and described drain electrode 201 on described oxide semiconductor channel layer 104 arranges the etching barrier layer 301 of fitting with described conductor oxidate channel layer 104, and the length of described etching barrier layer 301 is than the gap d between source electrode 202 and described drain electrode 201
1large 5 μm, namely the length of described etching barrier layer 301 is 25 μm.In order to meet core object of the present invention, the length of described etching barrier layer 301 is than the gap d between source electrode 202 and described drain electrode 201
1during large 1-5 μm, can designing requirement of the present invention.
In the present embodiment, described oxide semiconductor thin-film transistor is etch stopper type structure.
In the present embodiment, described etching barrier layer 301 is by Si
3n
4make, it should be noted that, for realizing core object of the present invention, the material of described etching barrier layer 301 is not construed as limiting, and described etching barrier layer 301 can also by SiO
2, TiO
2or Al
2o
3in one or more make.
In the present embodiment, the another side that described etching barrier layer 301 and described oxide semiconductor channel layer 104 are fitted arranges passivation layer, the thickness of described passivation layer is 400nm, for realizing core object of the present invention, can meet design requirement when the thickness of described passivation layer is 100-400nm.
It should be noted that, in the present embodiment, in order to realize core object of the present invention, described etching barrier layer 301 is optional, and oxide semiconductor thin-film transistor as shown in Figure 1 does not just have described etching barrier layer 301.
In the present embodiment, described substrate 101 is made up of glass, certainly, described substrate 101 can also adopt silicon or flexible substrate to make, and flexible substrate can be polyimide(polyimides in the present invention), PET(PETG), PEN(PEN), PES(is poly-to benzene diethyl sulfone) or Parylene(xylylene po1ymer) etc.
In the present embodiment, between described substrate 101 and described grid 102, arrange one deck resilient coating, the thickness of described resilient coating is 400nm, certainly, for meeting core object of the present invention, can meet design requirement when the thickness of described resilient coating is arranged between 100-400nm.In the present embodiment, described resilient coating Si
3n
4make separately, described resilient coating can also by SiO
2make separately, or by SiO
2and Si
3n
4jointly make.
In the present embodiment, described gate electrode 102 is made up of Al, and it can also be made up of any one in Mo, MoW, n++Si, T or ITO.
In the present embodiment, described insulating medium layer 103 is by Si
3n
4make, it can also by ZTSO, SiO
2or Al
2o
3in one or more make, be prepared from by the method for PECVD, sputtering or ALD (ald).
In the present embodiment, described oxide semiconductor channel layer 104 is made up of ZnO, and it can also by IGO, ZTO, GZO, IGOZ, In
2o
3, Cu
2o or SnO
2in one or more make.Described oxide semiconductor channel layer 104 is N-shaped raceway groove.Described oxide semiconductor channel layer 104 generally adopts the mode of sputtering to be formed.
In the present embodiment, described drain electrode 201 is 1.5 μm with the length of described gate electrode 102 overlapping region in the horizontal direction, for the present invention, described drain electrode 201 is 0-3 μm with the length range of described gate electrode 102 overlapping region in the horizontal direction.
Embodiment 3
As shown in Figure 2, the present embodiment provides a kind of oxide semiconductor thin-film transistor, comprise substrate 101 and be arranged on gate electrode 102, insulating medium layer 103 and the oxide semiconductor channel layer 104 on described substrate 101 in turn, described insulating medium layer 103 makes described gate electrode 102 and described oxide semiconductor channel layer 104 insulate, the upper surface of described oxide semiconductor channel layer 104 arranges drain electrode 201 and source electrode 202, and the gap between described drain electrode 201 and described source electrode 202 is d
1, described source electrode 202 is d with the length of described grid 102 overlapping region in the horizontal direction
2, the contact between described source electrode 202 and described oxide semiconductor channel layer 104 is Schottky contacts, and the contact between described drain electrode 201 and described oxide semiconductor channel layer 104 is ohmic contact.
For the ease of forming electric field between grid 102 and source electrode 202, thus be beneficial to carrier transport, the length d of described source electrode 202 and described grid 102 overlapping region in the horizontal direction
2scope be 3-20 μm, in the present embodiment, d
2it is 10 μm.
In the present invention, the gap d between described drain electrode 201 and described source electrode 202
1scope be 1 ~ 20 μm, in the present embodiment, the gap d between described drain electrode 201 and described source electrode 202
1it is 15 μm.
In the present embodiment, the position be positioned between described source electrode 202 and described drain electrode 201 on described oxide semiconductor channel layer 104 arranges the etching barrier layer 301 of fitting with described conductor oxidate channel layer 104, and the length of described etching barrier layer 301 is than the gap d between source electrode 202 and described drain electrode 201
1large 3 μm, namely the length of described etching barrier layer 301 is 18 μm.In order to meet core object of the present invention, the length of described etching barrier layer 301 is than the gap d between source electrode 202 and described drain electrode 201
1during large 1-5 μm, can designing requirement of the present invention.
In the present embodiment, described oxide semiconductor thin-film transistor is etch stopper type structure.
In the present embodiment, described etching barrier layer 301 is by TiO
2make, it should be noted that, for realizing core object of the present invention, the material of described etching barrier layer 301 is not construed as limiting, and described etching barrier layer 301 can also by SiO
2, Si
3n
4or Al
2o
3in one or more make.
In the present embodiment, the another side that described etching barrier layer 301 and described oxide semiconductor channel layer 104 are fitted arranges passivation layer, the thickness of described passivation layer is 200nm, for realizing core object of the present invention, can meet design requirement when the thickness of described passivation layer is 100-400nm.
It should be noted that, in the present embodiment, in order to realize core object of the present invention, described etching barrier layer 301 is optional, and oxide semiconductor thin-film transistor as shown in Figure 1 does not just have described etching barrier layer 301.
In the present embodiment, described substrate 101 is made up of PET, certainly, described substrate 101 can also adopt silicon, glass or other flexible substrate to make, and other flexible substrate can be polyimide(polyimides in the present invention), PET(PETG), PEN(PEN), PES(is poly-to benzene diethyl sulfone) or Parylene(xylylene po1ymer) etc.
In the present embodiment, between described substrate 101 and described grid 102, arrange one deck resilient coating, the thickness of described resilient coating is 200nm, certainly, for meeting core object of the present invention, can meet design requirement when the thickness of described resilient coating is arranged between 100-400nm.In the present embodiment, described resilient coating is by SiO
2and Si
3n
4jointly make, described resilient coating can also by SiO
2or Si
3n
4make separately.
In the present embodiment, described gate electrode 102 is made up of ITO, and it can also be made up of any one in Mo, MoW, n++Si, T or Al.
In the present embodiment, described insulating medium layer 103 is by Al
2o
3make, it can also by ZTSO, SiO
2or Si
3n
4in one or more make, be prepared from by the method for PECVD, sputtering or ALD (ald).
In the present embodiment, described oxide semiconductor channel layer 104 is by SnO
2make, it can also by IGO, ZTO, GZO, IGOZ, In
2o
3, Cu
2one or more in O or ZnO are made.Described oxide semiconductor channel layer 104 is N-shaped raceway groove.Described oxide semiconductor channel layer 104 is generally prepared from by the method sputtered.
In the present embodiment, described drain electrode 201 is 0 μm with the length of described gate electrode 102 overlapping region in the horizontal direction, and for the present invention, described drain electrode 201 is 0-3 μm with the length range of described gate electrode 102 overlapping region in the horizontal direction.
Embodiment 4
As shown in Figure 1, the present embodiment provides a kind of oxide semiconductor thin-film transistor, comprise substrate 101 and be arranged on gate electrode 102, insulating medium layer 103 and the oxide semiconductor channel layer 104 on described substrate 101 in turn, described insulating medium layer 103 makes described gate electrode 102 and described oxide semiconductor channel layer 104 insulate, the upper surface of described oxide semiconductor channel layer 104 arranges drain electrode 201 and source electrode 202, and the gap between described drain electrode 201 and described source electrode 202 is d
1, described source electrode 202 is d with the length of described grid 102 overlapping region in the horizontal direction
2, the contact between described source electrode 202 and described oxide semiconductor channel layer 104 is Schottky contacts, and the contact between described drain electrode 201 and described oxide semiconductor channel layer 104 is ohmic contact.
For the ease of forming electric field between grid 102 and source electrode 202, thus be beneficial to carrier transport, the length d of described source electrode 202 and described grid 102 overlapping region in the horizontal direction
2scope be 3-20 μm, in the present embodiment, d
2it is 3 μm.
In the present invention, the gap d between described drain electrode 201 and described source electrode 202
1scope be 1 ~ 20 μm, in the present embodiment, the gap d X between described drain electrode 201 and described source electrode 202 is 1 μm.
In the present embodiment, described substrate 101 is made up of silicon, certainly, described substrate 101 can also adopt glass or flexible substrate to make, and flexible substrate can be polyimide(polyimides in the present invention), PET(PETG), PEN(PEN), PES(is poly-to benzene diethyl sulfone) or Parylene(xylylene po1ymer) etc.
In the present embodiment, between described substrate 101 and described grid 102, arrange one deck resilient coating, the thickness of described resilient coating is 100nm, certainly, for meeting core object of the present invention, can meet design requirement when the thickness of described resilient coating is arranged between 100-400nm.In the present embodiment, described resilient coating SiO
2make separately, described resilient coating can also by Si
3n
4make separately, or by SiO
2and Si
3n
4jointly make.
In the present embodiment, described gate electrode 102 is made up of Mo, and it can also be made up of any one in MoW, n++Si, T, Al or ITO.
In the present embodiment, described insulating medium layer 103 is by SiO
2make, it can also by ZTSO, Si
3n
4or Al
2o
3in one or more make, be prepared from by the method for PECVD, sputtering or ALD (ald).
In the present embodiment, described oxide semiconductor channel layer 104 is made up of IGOZ, and it can also by IGO, ZTO, GZO, ZnO, In
2o
3, Cu
2o or SnO
2in one or more make.Described oxide semiconductor channel layer 104 is N-shaped raceway groove.Described oxide semiconductor channel layer 104 generally adopts the mode of sputtering to be formed.
In the present embodiment, described drain electrode 201 is 3 μm with the length of described gate electrode 102 overlapping region in the horizontal direction, and for the present invention, described drain electrode 201 is 0-3 μm with the length range of described gate electrode 102 overlapping region in the horizontal direction.
Embodiment 5
As shown in Figure 1, the present embodiment provides a kind of oxide semiconductor thin-film transistor, comprise substrate 101 and be arranged on gate electrode 102, insulating medium layer 103 and the oxide semiconductor channel layer 104 on described substrate 101 in turn, described insulating medium layer 103 makes described gate electrode 102 and described oxide semiconductor channel layer 104 insulate, the upper surface of described oxide semiconductor channel layer 104 arranges drain electrode 201 and source electrode 202, and the gap between described drain electrode 201 and described source electrode 202 is d
1, described source electrode 202 is d with the length of described grid 102 overlapping region in the horizontal direction
2, the contact between described source electrode 202 and described oxide semiconductor channel layer 104 is Schottky contacts, and the contact between described drain electrode 201 and described oxide semiconductor channel layer 104 is ohmic contact.
For the ease of forming electric field between grid 102 and source electrode 202, thus be beneficial to carrier transport, the length d of described source electrode 202 and described grid 102 overlapping region in the horizontal direction
2scope be 3-20 μm, in the present embodiment, d
2it is 20 μm.
In the present invention, the gap d between described drain electrode 201 and described source electrode 202
1scope be 1 ~ 20 μm, in the present embodiment, the gap d between described drain electrode 201 and described source electrode 202
1it is 20 μm.
In the present embodiment, described substrate 101 is made up of glass, certainly, described substrate 101 can also adopt silicon or flexible substrate to make, and flexible substrate can be polyimide(polyimides in the present invention), PET(PETG), PEN(PEN), PES(is poly-to benzene diethyl sulfone) or Parylene(xylylene po1ymer) etc.
In the present embodiment, between described substrate 101 and described grid 102, arrange one deck resilient coating, the thickness of described resilient coating is 400nm, certainly, for meeting core object of the present invention, can meet design requirement when the thickness of described resilient coating is arranged between 100-400nm.In the present embodiment, described resilient coating Si
3n
4make separately, described resilient coating can also by SiO
2make separately, or by SiO
2and Si
3n
4jointly make.
In the present embodiment, described gate electrode 102 is made up of Al, and it can also be made up of any one in Mo, MoW, n++Si, T or ITO.
In the present embodiment, described insulating medium layer 103 is by Si
3n
4make, it can also by ZTSO, SiO
2or Al
2o
3in one or more make, be prepared from by the method for PECVD, sputtering or ALD (ald).
In the present embodiment, described oxide semiconductor channel layer 104 is made up of ZnO, and it can also by IGO, ZTO, GZO, IGOZ, In
2o
3, Cu
2o or SnO
2in one or more make.Described oxide semiconductor channel layer 104 is N-shaped raceway groove.Described oxide semiconductor channel layer 104 generally adopts the mode of sputtering to be formed.
In the present embodiment, described drain electrode 201 is 1.5 μm with the length of described gate electrode 102 overlapping region in the horizontal direction, for the present invention, described drain electrode 201 is 0-3 μm with the length range of described gate electrode 102 overlapping region in the horizontal direction.
Embodiment 6
As shown in Figure 1, the present embodiment provides a kind of oxide semiconductor thin-film transistor, comprise substrate 101 and be arranged on gate electrode 102, insulating medium layer 103 and the oxide semiconductor channel layer 104 on described substrate 101 in turn, described insulating medium layer 103 makes described gate electrode 102 and described oxide semiconductor channel layer 104 insulate, the upper surface of described oxide semiconductor channel layer 104 arranges drain electrode 201 and source electrode 202, and the gap between described drain electrode 201 and described source electrode 202 is d
1, described source electrode 202 is d with the length of described grid 102 overlapping region in the horizontal direction
2, the contact between described source electrode 202 and described oxide semiconductor channel layer 104 is Schottky contacts, and the contact between described drain electrode 201 and described oxide semiconductor channel layer 104 is ohmic contact.
For the ease of forming electric field between grid 102 and source electrode 202, thus be beneficial to carrier transport, the length d of described source electrode 202 and described grid 102 overlapping region in the horizontal direction
2scope be 3-20 μm, in the present embodiment, d
2it is 10 μm.
In the present invention, the gap d between described drain electrode 201 and described source electrode 202
1scope be 1 ~ 20 μm, in the present embodiment, the gap d between described drain electrode 201 and described source electrode 202
1it is 15 μm.
In the present embodiment, described substrate 101 is made up of PET, certainly, described substrate 101 can also adopt silicon, glass or other flexible substrate to make, and other flexible substrate can be polyimide(polyimides in the present invention), PET(PETG), PEN(PEN), PES(is poly-to benzene diethyl sulfone) or Parylene(xylylene po1ymer) etc.
In the present embodiment, between described substrate 101 and described grid 102, arrange one deck resilient coating, the thickness of described resilient coating is 200nm, certainly, for meeting core object of the present invention, can meet design requirement when the thickness of described resilient coating is arranged between 100-400nm.In the present embodiment, described resilient coating is by SiO
2and Si
3n
4jointly make, described resilient coating can also by SiO
2or Si
3n
4make separately.
In the present embodiment, described gate electrode 102 is made up of ITO, and it can also be made up of any one in Mo, MoW, n++Si, T or Al.
In the present embodiment, described insulating medium layer 103 is by Al
2o
3make, it can also by ZTSO, SiO
2or Si
3n
4in one or more make, be prepared from by the method for PECVD, sputtering or ALD (ald).
In the present embodiment, described oxide semiconductor channel layer 104 is by SnO
2make, it can also by IGO, ZTO, GZO, IGOZ, In
2o
3, Cu
2one or more in O or ZnO are made.Described oxide semiconductor channel layer 104 is N-shaped raceway groove.Described oxide semiconductor channel layer 104 is generally prepared from by the method sputtered.
In the present embodiment, described drain electrode 201 is 0 μm with the length of described gate electrode 102 overlapping region in the horizontal direction, and for the present invention, described drain electrode 201 is 0-3 μm with the length range of described gate electrode 102 overlapping region in the horizontal direction.
The formation condition of the way of contact of the present invention is described for N-shaped tunnel oxide semiconductor IGZO thin-film transistor below.Gate electrode can be the one in Mo, MoW, Ti, Al etc.Drain electrode and raceway groove form ohmic contact, drain electrode material select work function lower than N-shaped oxide semiconductor [IGZO work function is about 4.57eV, in table 2, drain electrode/the channel interface formed can be as Ti/Al/Ti/IGZO, Al/AZO/IGZO, Au/Ti/IGZO, Al/IGZO, Ti/IGZO etc.And source electrode and raceway groove form Schottky contacts, work function can be selected higher than N-shaped oxide semiconductor, such as Mo/IGZO, Au/IGZO, Pt/IGZO, Ni/IGZO, ITO/IGZO etc.Source, drain electrode are generally prepared from by sputtering method.
The present invention is also applicable to the oxide semiconductor of p-type raceway groove, as the ZnO of p-type, Cu
2o, and SnO
2deng, when making the present invention's structure thin-film transistor as shown in Figure 1 or 2, the selection of source, drain electrode is contrary with N-shaped.
Table 1 forms the condition on N-shaped and p-type barrier layer
| Work function compares | N-type semiconductor | P-type semiconductor |
| W m>W s | Barrier layer | Anti-drag barrier |
| W m<W s | Anti-drag barrier | Barrier layer |
W
m---the work function of metal; W
s---the work function of semiconductor
The work function (unit: eV) of the various metallic element of table 2
| Metal | Work function | Metal | Work function | Metal | Work function | Metal | Work function | Metal | Work function | Metal | Work function |
| Ag | 4.26 | Al | 4.28 | As | 3.75 | Au | 5.1 | B | 4.45 | Ba | 2.7 |
| Be | 4.98 | Bi | 4.22 | C | 5 | Ca | 2.87 | Cd | 4.22 | Ce | 2.9 |
| Co | 5 | Cr | 4.5 | Cs | 2.14 | Cu | 4.65 | Eu | 2.5 | Fe | 4.5 |
| Ga | 4.2 | Gd | 3.1 | Hf | 3.9 | Hg | 4.49 | In | 4.12 | Ir | 5.27 |
| K | 2.3 | La | 3.5 | Li | 2.9 | Lu | 3.3 | Mg | 3.66 | Mn | 4.1 |
| Mo | 4.6 | Na | 2.75 | Nb | 4.3 | Nd | 3.2 | Ni | 5.15 | Os | 4.83 |
| Pb | 4.25 | Pt | 5.65 | Rb | 2.16 | Re | 4.96 | Rh | 4.98 | Ru | 4.71 |
| Sb | 4.55 | Sc | 3.5 | Se | 5.9 | Si | 4.85 | Sm | 2.7 | Sn | 4.42 |
| Sr | 2.59 | Ta | 4.25 | Tb | 3 | Te | 4.95 | Th | 3.4 | Ti | 4.33 |
| Tl | 3.84 | U | 3.63 | V | 4.3 | W | 4.55 | Y | 3.1 | Zn | 4.33 |
Obviously, above embodiment is only in order to illustrate technical scheme of the present invention, and the restriction not to execution mode, although with reference to preferred embodiment to invention has been detailed description, those of ordinary skill in any art, can also make other changes in different forms on the basis of the above description, also exhaustive without the need to also giving all execution modes here.Therefore protection scope of the present invention is when being as the criterion depending on the claim scope person of defining.
Claims (24)
1. an oxide semiconductor thin-film transistor, comprise substrate (101) and be arranged on gate electrode (102), insulating medium layer (103) and the oxide semiconductor channel layer (104) on described substrate (101) in turn, described insulating medium layer (103) makes described gate electrode (102) and described oxide semiconductor channel layer (104) insulation, the upper surface of described oxide semiconductor channel layer (104) arranges drain electrode (201) and source electrode (202), and the gap between described drain electrode (201) and described source electrode (202) is d
1, described source electrode (202) is d with the length of described gate electrode (102) overlapping region in the horizontal direction
2, the length d of described source electrode (202) and described gate electrode (102) overlapping region in the horizontal direction
2scope be 3-20 μm; Described drain electrode (201) is 0-3 μm with the length range of described gate electrode (102) overlapping region in the horizontal direction; Contact between described source electrode (202) and described oxide semiconductor channel layer (104) is Schottky contacts, and the contact between described drain electrode (201) and described oxide semiconductor channel layer (104) is ohmic contact; Described gate electrode (102) is made up of any one in Mo, MoW, n++ Si, Ti, Al or ITO; Described oxide semiconductor channel layer (104) is by IGZO, IGO, ZTO, GZO, ZnO, In
2o
3,cu
2o or SnO
2in one or more make; Described oxide semiconductor channel layer (104) is N-shaped raceway groove, and described drain electrode material selects the work function metal lower than N-shaped oxide semiconductor to make, and the metal that described source electrode Material selec-tion work function is higher than N-shaped oxide semiconductor is made.
2. oxide semiconductor thin-film transistor according to claim 1, is characterized in that: the scope of the gap d 1 between described drain electrode (201) and described source electrode (202) is 1 ~ 20 μm.
3. oxide semiconductor thin-film transistor according to claim 2, it is characterized in that: the position be positioned between described source electrode (202) and described drain electrode (201) on described oxide semiconductor channel layer (104) arranges the etching barrier layer (301) of fitting with described conductor oxidate channel layer (104), and the length of described etching barrier layer (301) is than the gap d between described source electrode (202) and described drain electrode (201)
1large 1 ~ 5 μm.
4. oxide semiconductor thin-film transistor according to claim 3, is characterized in that: described etching barrier layer (301) is the one of carrying on the back channel-etch type structure or stopping in etching type structure.
5. oxide semiconductor thin-film transistor according to claim 4, is characterized in that: the another side that described etching barrier layer (301) and described oxide semiconductor channel layer (104) are fitted arranges passivation layer.
6. oxide semiconductor thin-film transistor according to claim 5, is characterized in that: the thickness of described passivation layer is 100-400nm.
7. oxide semiconductor thin-film transistor according to any one of claim 1-6, is characterized in that: described substrate (101) is made up of monocrystalline silicon, glass or flexible substrate.
8. oxide semiconductor thin-film transistor according to claim 7, is characterized in that:
Between described substrate (101) and described gate electrode (102), one deck resilient coating is set.
9. oxide semiconductor thin-film transistor according to claim 8, is characterized in that: the thickness of described resilient coating is 100-400nm.
10. oxide semiconductor thin-film transistor according to claim 9, is characterized in that: described resilient coating is by SiO
2and/or Si
3n
4composition.
11. oxide semiconductor thin-film transistors according to any one of claim 1-6, is characterized in that: described insulating medium layer (103) is by SiO
2, Si
3n
4or Al
2o
3in one or more make.
12. oxide semiconductor thin-film transistors according to any one of claim 3-6, is characterized in that: described etching barrier layer (301) is by SiO
2, Si
3n
4, TiO
2, Al
2o
3or one or more in ZTSO are made.
13. 1 kinds of oxide semiconductor thin-film transistors, comprise substrate (101) and be arranged on gate electrode (102), insulating medium layer (103) and the oxide semiconductor channel layer (104) on described substrate (101) in turn, described insulating medium layer (103) makes described gate electrode (102) and described oxide semiconductor channel layer (104) insulation, the upper surface of described oxide semiconductor channel layer (104) arranges drain electrode (201) and source electrode (202), and the gap between described drain electrode (201) and described source electrode (202) is d
1, described source electrode (202) is d with the length of described gate electrode (102) overlapping region in the horizontal direction
2, the length d of described source electrode (202) and described gate electrode (102) overlapping region in the horizontal direction
2scope be 3-20 μm; Described drain electrode (201) is 0-3 μm with the length range of described gate electrode (102) overlapping region in the horizontal direction; Contact between described source electrode (202) and described oxide semiconductor channel layer (104) is Schottky contacts, and the contact between described drain electrode (201) and described oxide semiconductor channel layer (104) is ohmic contact; Described gate electrode (102) is made up of any one in Mo, MoW, n++ Si, Ti, Al or ITO; Described oxide semiconductor channel layer (104) is by IGZO, IGO, ZTO, GZO, ZnO, In
2o
3,cu
2o or SnO
2in one or more make; Described oxide semiconductor channel layer (104) is p-type raceway groove, and described drain electrode material selects the work function metal higher than p-type oxide semiconductor to make, and the metal that described source electrode Material selec-tion work function is lower than p-type oxide semiconductor is made.
14. oxide semiconductor thin-film transistors according to claim 13, is characterized in that: the scope of the gap d 1 between described drain electrode (201) and described source electrode (202) is 1 ~ 20 μm.
15. oxide semiconductor thin-film transistors according to claim 14, it is characterized in that: the position be positioned between described source electrode (202) and described drain electrode (201) on described oxide semiconductor channel layer (104) arranges the etching barrier layer (301) of fitting with described conductor oxidate channel layer (104), and the length of described etching barrier layer (301) is than the gap d between described source electrode (202) and described drain electrode (201)
1large 1 ~ 5 μm.
16. oxide semiconductor thin-film transistors according to claim 15, is characterized in that: described etching barrier layer (301) is the one of carrying on the back channel-etch type structure or stopping in etching type structure.
17. oxide semiconductor thin-film transistors according to claim 16, is characterized in that: the another side that described etching barrier layer (301) and described oxide semiconductor channel layer (104) are fitted arranges passivation layer.
18. oxide semiconductor thin-film transistors according to claim 17, is characterized in that: the thickness of described passivation layer is 100-400nm.
19. according to any one of claim 13-18 oxide semiconductor thin-film transistor, it is characterized in that: described substrate (101) is made up of monocrystalline silicon, glass or flexible substrate.
20. oxide semiconductor thin-film transistors according to claim 19, is characterized in that: between described substrate (101) and described gate electrode (102), arrange one deck resilient coating.
21. oxide semiconductor thin-film transistors according to claim 20, is characterized in that: the thickness of described resilient coating is 100-400nm.
22. oxide semiconductor thin-film transistors according to claim 21, is characterized in that: described resilient coating is by SiO
2and/or Si
3n
4composition.
23. oxide semiconductor thin-film transistors according to any one of claim 13-18, is characterized in that: described insulating medium layer (103) is by SiO
2, Si
3n
4or Al
2o
3in one or more make.
24. oxide semiconductor thin-film transistors according to any one of claim 15-18, is characterized in that: described etching barrier layer (301) is by SiO
2, Si
3n
4, TiO
2, Al
2o
3or one or more in ZTSO are made.
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| CN103606563B (en) * | 2013-10-22 | 2016-06-01 | 清华大学 | Without knot type tunneling field-effect transistor and forming method thereof |
| CN104167365A (en) | 2014-08-06 | 2014-11-26 | 京东方科技集团股份有限公司 | Metal oxide thin-film transistor, array substrate, manufacturing method of metal oxide thin-film transistor and display device |
| CN104332500A (en) * | 2014-09-04 | 2015-02-04 | 北京大学 | Resistive gate tunneling field effect transistor and preparation method thereof |
| CN104576749A (en) * | 2014-10-31 | 2015-04-29 | 京东方科技集团股份有限公司 | Thin film transistor and manufacturing method thereof as well as array substrate and display device |
| CN104766880A (en) * | 2015-04-07 | 2015-07-08 | 中国科学院合肥物质科学研究院 | P-type bismuth strontium cobalt oxide semiconductor channel thin film transistor and preparation method thereof |
| JP6366828B2 (en) * | 2015-04-28 | 2018-08-01 | 三菱電機株式会社 | Transistor, thin film transistor substrate, and liquid crystal display device |
| GB2571351A (en) * | 2018-02-27 | 2019-08-28 | Univ Manchester | Device and method |
| CN109166941B (en) * | 2018-04-26 | 2020-07-24 | 湖南大学 | Energy conversion device |
| GB201821084D0 (en) * | 2018-12-21 | 2019-02-06 | Univ Manchester | Device and method |
| CN109728098B (en) * | 2019-01-03 | 2022-05-17 | 合肥鑫晟光电科技有限公司 | Thin film transistor, sensor, detection method, detection device and detection system |
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| US6303479B1 (en) * | 1999-12-16 | 2001-10-16 | Spinnaker Semiconductor, Inc. | Method of manufacturing a short-channel FET with Schottky-barrier source and drain contacts |
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