CN102723367A - Oxide semiconductor thin film transistor - Google Patents
Oxide semiconductor thin film transistor Download PDFInfo
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- CN102723367A CN102723367A CN2012102231637A CN201210223163A CN102723367A CN 102723367 A CN102723367 A CN 102723367A CN 2012102231637 A CN2012102231637 A CN 2012102231637A CN 201210223163 A CN201210223163 A CN 201210223163A CN 102723367 A CN102723367 A CN 102723367A
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Abstract
The invention provides an oxide semiconductor thin film transistor which comprises a substrate, a gate electrode, an insulation dielectric layer and an oxide semiconductor channel layer, wherein the gate electrode, the insulation dielectric layer and the oxide semiconductor channel layer are sequentially arranged on the substrate, the insulation dielectric layer enables the gate electrode and the oxide semiconductor channel layer to be insulted, a drain electrode and a source electrode are arranged on the upper surface of the oxide semiconductor channel layer, a gap between the drain electrode and the source electrode is d1, the length of an overlapping region of the source electrode and the gate electrode in the horizontal direction is d2, contact between the source electrode and the oxide semiconductor channel layer is schottky contact, and the contact between the drain electrode and the oxide semiconductor channel layer is ohmic contact. The short-channel effect on the oxide semiconductor thin film transistor is small due to new geometrical characteristics and operating principles, and the oxide semiconductor thin film transistor is favorable for improvement of consistency.
Description
Technical field
The present invention relates to a kind of oxide semiconductor thin-film transistor, belong to the flat panel display field.
Background technology
Thin-film transistor (thin-film transistor) becomes the key technology in flat panel display field as the active driving element of flat-panel monitor.Oxide semiconductor is (like IGZO; AZO, GZO, ZnO etc.) thin-film transistor with its high transparent, high mobility, high current switching than advantages such as, low technological temperature and simple manufacturing process; Have good development prospect, can be used on high performance TFT-LCD or the AMOLED display screen.
Yet; Present oxide semiconductor thin-film transistor (under constant voltage or constant current mode) its threshold voltage passing in time at work is easy to generate drift; Thereby influenced the stability of threshold voltage, and then caused harmful effect the bright degree of display picture element.
Discover; The concentration of charge carrier is very big to the influence of threshold voltage; Traditional oxide semiconductor source electrode all is ohmic contact with drain electrode with contacting of oxide semiconductor channel layer, and what oxide semiconductor (normally n N-type semiconductor N) surface formed is the space charge region of bearing, and direction of an electric field is pointed in the body by the surface; Much bigger in the surface electronic concentration ratio body, so being a high electricity, the source electrode barrier region leads the zone.Saturation current is by pinch off (pinch-off) decision of drain terminal conduction during this thin-film transistor work, and carrier concentration is big, thereby has increased the influence to threshold voltage, and then has influenced the job stability of oxide semiconductor thin-film transistor.
Summary of the invention
Therefore, the present invention's technical problem that will solve be to provide a kind of when reducing work carrier concentration improve the oxide semiconductor thin-film transistor of job stability.
Another technical problem that the present invention will solve is the oxide semiconductor thin-film transistor that provides a kind of consistency higher.
For this reason; The present invention provides a kind of oxide semiconductor thin-film transistor; Comprise substrate and be arranged on gate electrode, insulating medium layer and the oxide semiconductor channel layer on the said substrate in order; Said insulating medium layer makes said gate electrode and said oxide semiconductor channel layer insulate, and the upper surface of said oxide semiconductor channel layer is provided with drain electrode and source electrode, and said drain electrode and said source gaps between electrodes are d
1, the length of said source electrode and said grid overlapping region in the horizontal direction is d
2, contacting between said source electrode and said oxide semiconductor channel layer is Schottky contacts, contacting between said drain electrode and said oxide semiconductor channel layer is ohmic contact.
Said drain electrode and said source gaps between electrodes d
1Scope be 1～20 μ m.
Position being positioned between said source electrode and the said drain electrode on the said oxide semiconductor channel layer is provided with the etching barrier layer of fitting with said conductor oxidate channel layer, and the length of said etching barrier layer (301) is than the gap d between said source electrode and the said drain electrode
1Big 1～5um.
Said etching barrier layer is for back of the body channel-etch type structure or stop a kind of in the etching type structure.
The another side that said etching barrier layer and said oxide semiconductor channel layer are fitted is provided with passivation layer.
The thickness of said passivation layer is 100-400nm.
Said substrate is processed by monocrystalline silicon, glass or flexible substrate.
Between said substrate and said grid, one deck resilient coating is set.
The thickness of said resilient coating is 100-400nm.
Said resilient coating is by SiO
2And/or Si
3N
4Form.
Said gate electrode is processed by among Mo, MoW, n++Si, T, Al or the ITO any.
Said insulating medium layer is by SiO
2, Si
3N
4Or Al
2O
3In one or more process.
Said oxide semiconductor channel layer is by IGZO, IGO, ZTO, GZO, ZnO, In
2O
3, Cu
2O or SnO
2In one or more process.
Said etching barrier layer is by SiO
2, Si
3N
4, TiO
2, Al
2O
3Or among the ZTSO one or more are processed.
The length d of said source electrode and said grid overlapping region in the horizontal direction
2Scope be 3-20 μ m.
The length range of said drain electrode and said gate electrode overlapping region in the horizontal direction is 0-3 μ m.
Said oxide semiconductor channel layer can be n type raceway groove or p type raceway groove.The selection of source, drain electrode is according to shown in the table 1.If form ohmic contact with n type oxide semiconductor, need to select work function than the low metal of n type oxide semiconductor as drain electrode; Select work function than the high metal of semiconductor as the source electrode, thereby and form Schottky contacts between the semiconductor.As far as p type oxide semiconductor, source, the selection of leaking metal electrode and n type opposite.
Among the present invention, the I in the chemical formula representes the In element, and G representes the Ga element, and Z representes the Zn element, and O representes oxygen element, and T representes the Sn element.
Oxide semiconductor thin-film transistor provided by the invention has the following advantages:
1. oxide semiconductor thin-film transistor provided by the invention; Comprise substrate and be arranged on gate electrode, insulating medium layer and the oxide semiconductor channel layer on the said substrate in order; Said insulating medium layer makes said gate electrode and said oxide semiconductor channel layer insulate; The upper surface of said oxide semiconductor channel layer is provided with drain electrode and source electrode, and said drain electrode and said source gaps between electrodes are d
1, the length of said source electrode and said gate electrode overlapping region in the horizontal direction is d
2, contacting between said source electrode and said oxide semiconductor channel layer is Schottky contacts, contacting between said drain electrode and said oxide semiconductor channel layer is ohmic contact.Carrier transport in the thin-film transistor, open electric current and saturation current mainly by the source electrode potential barrier control of reverse biased.Among the present invention, because contacting between said source electrode and said oxide semiconductor (normally n type) channel layer is Schottky contacts, in positive space charge region of semiconductor surface formation; Wherein direction of an electric field is by pointing to the surface in the body; It is higher than in the body semiconductor surface electron energy, can be with to be bent upwards, and promptly forms surface potential barrier; In the barrier region; Space charge is mainly formed by ionized donor, and therefore electron concentration is a high resistant zone than little a lot of in the body; Carrier concentration is that the transistor of ohmic contact is much lower than source/raceway groove, leakage/raceway groove entirely during the work of this thin-film transistor, and therefore oxide semiconductor thin-film transistor provided by the invention is stable higher.
2. oxide semiconductor thin-film transistor provided by the invention; Because the geometric properties and the operation principle of new construction; Oxide semiconductor thin-film transistor provided by the invention can be worked under short channel and thick gate dielectric layer condition; Make the transmission current of said oxide semiconductor thin-film transistor receive short-channel effects little, thereby make that the consistency of oxide semiconductor thin-film transistor provided by the invention is higher.
Description of drawings
Fig. 1 is the structural representation that does not have the oxide semiconductor thin-film transistor of etching barrier layer provided by the invention;
Fig. 2 is the structural representation with oxide semiconductor thin-film transistor of etching barrier layer provided by the invention.
Reference numeral is expressed as among the figure:
The 101-substrate; The 102-grid; The 103-insulating medium layer; 104-oxide semiconductor channel layer; The 201-drain electrode; 202-source electrode; The 301-etching barrier layer.
Embodiment
Core purpose of the present invention is to provide a kind of oxide semiconductor thin-film transistor that improves job stability through the regulation and control carrier concentration.
Fig. 1 is the structural representation that does not have the oxide semiconductor thin-film transistor of etching barrier layer provided by the invention; Fig. 2 is the structural representation with oxide semiconductor thin-film transistor of etching barrier layer provided by the invention; To provide embodiment below; And combine accompanying drawing specific explanations technical scheme of the present invention; The condition that forms ohmic contact (anti-barrier layer) or Schottky contacts (barrier layer) between oxide semiconductor among the embodiment (n type and p type) and the metal electrode is as shown in table 1, wherein W
mAnd W
sBe respectively metal and semi-conductive work function.The work function such as the table 2 of various metallic elements provide.
Embodiment 1
As shown in Figure 2; Present embodiment provides a kind of oxide semiconductor thin-film transistor; Comprise substrate 101 and be arranged on gate electrode 102, insulating medium layer 103 and the oxide semiconductor channel layer 104 on the said substrate 101 in order; Said insulating medium layer 103 makes said gate electrode 102 and said oxide semiconductor channel layer 104 insulate; The upper surface of said oxide semiconductor channel layer 104 is provided with drain electrode 201 and source electrode 202, and the gap between said drain electrode 201 and the said source electrode 202 is d
1, said source electrode 202 is d with the length of said grid 102 overlapping region in the horizontal direction
2, said source electrode 202 is a Schottky contacts with contacting of 104 of said oxide semiconductor channel layers, said drain electrode 201 is an ohmic contact with contacting of 104 of said oxide semiconductor channel layers.
For the ease of between grid 102 and source electrode 202, forming electric field, thereby be beneficial to carrier transport, the length d of said source electrode 202 and said grid 102 overlapping region in the horizontal direction
2Scope be 3-20 μ m, in the present embodiment, d
2Be 3 μ m.
Among the present invention, the gap d between said drain electrode 201 and the said source electrode 202
1Scope be 1～20 μ m, in the present embodiment, the gap d between said drain electrode 201 and the said source electrode 202
1Be 1 μ m.
In the present embodiment; Position being positioned between said source electrode 202 and the said drain electrode 201 on the said oxide semiconductor channel layer 104 is provided with the etching barrier layer 301 of fitting with said conductor oxidate channel layer 104, and the length of said etching barrier layer 301 is than the gap d between source electrode 202 and the said drain electrode 201
1Big 1 μ m, the length of promptly said etching barrier layer 301 is 2 μ m.In order to satisfy core purpose of the present invention, the length of said etching barrier layer 301 is than the gap d between source electrode 202 and the said drain electrode 201
1During big 1-5 μ m, can both designing requirement of the present invention.
In the present embodiment, said oxide semiconductor thin-film transistor is an etching barrier type structure.
In the present embodiment, said etching barrier layer 301 is by SiO
2Process, need to prove, for realizing core purpose of the present invention, the material of said etching barrier layer 301 does not constitute restriction, and said etching barrier layer 301 can also be by Si
3N
4, TiO
2Or Al
2O
3In one or more process.
In the present embodiment; Said etching barrier layer 301 is provided with passivation layer with the another side that said oxide semiconductor channel layer 104 is fitted; The thickness of said passivation layer is 100nm, and for realizing core purpose of the present invention, the thickness of said passivation layer can both meet design requirement during for 100-400nm.
Need to prove that in the present embodiment, in order to realize core purpose of the present invention, said etching barrier layer 301 is optional, oxide semiconductor thin-film transistor as shown in Figure 1 does not just have said etching barrier layer 301.
In the present embodiment; Said substrate 101 is processed by silicon; Certainly; Said substrate 101 can also adopt glass or flexible substrate to process, and flexible substrate can be polyimide (polyimides), PET (PETG), PEN (PEN), PES (gathering benzene diethyl sulfone) or Parylene (xylylene po1ymer) etc. in the present invention.
In the present embodiment; Between said substrate 101 and said grid 102, one deck resilient coating is set, the thickness of said resilient coating is 100nm, certainly; For satisfying core purpose of the present invention, when being arranged between the 100-400nm, the thickness of said resilient coating can both meet design requirement.In the present embodiment, said resilient coating SiO
2Process separately, said resilient coating can also be by Si
3N
4Process separately, perhaps by SiO
2And Si
3N
4Process jointly.
In the present embodiment, said gate electrode 102 is processed by Mo, and it can also be processed by among MoW, n++Si, T, Al or the ITO any.
In the present embodiment, said insulating medium layer 103 is by SiO
2Process, it can also be by ZTSO, Si
3N
4Or Al
2O
3In one or more process, be prepared from the method for PECVD, sputter or ALD (ald).
In the present embodiment, said oxide semiconductor channel layer 104 is processed by IGOZ, and it can also be by IGO, ZTO, GZO, ZnO, In
2O
3, Cu
2O or SnO
2In one or more process.Said oxide semiconductor channel layer 104 is a n type raceway groove.The said oxide semiconductor channel layer 104 general modes of sputter that adopt form.
In the present embodiment, said drain electrode 201 is 3 μ m with the length of said gate electrode 102 overlapping region in the horizontal direction, and for the present invention, said drain electrode 201 is 0-3 μ m with the length range of said gate electrode 102 overlapping region in the horizontal direction.
Embodiment 2
As shown in Figure 2; Present embodiment provides a kind of oxide semiconductor thin-film transistor; Comprise substrate 101 and be arranged on gate electrode 102, insulating medium layer 103 and the oxide semiconductor channel layer 104 on the said substrate 101 in order; Said insulating medium layer 103 makes said gate electrode 102 and said oxide semiconductor channel layer 104 insulate; The upper surface of said oxide semiconductor channel layer 104 is provided with drain electrode 201 and source electrode 202, and the gap between said drain electrode 201 and the said source electrode 202 is d
1, said source electrode 202 is d with the length of said grid 102 overlapping region in the horizontal direction
2, said source electrode 202 is a Schottky contacts with contacting of 104 of said oxide semiconductor channel layers, said drain electrode 201 is an ohmic contact with contacting of 104 of said oxide semiconductor channel layers.
For the ease of between grid 102 and source electrode 202, forming electric field, thereby be beneficial to carrier transport, the length d of said source electrode 202 and said grid 102 overlapping region in the horizontal direction
2Scope be 3-20 μ m, in the present embodiment, d
2Be 20 μ m.
Among the present invention, the gap d between said drain electrode 201 and the said source electrode 202
1Scope be 1～20 μ m, in the present embodiment, the gap d between said drain electrode 201 and the said source electrode 202
1Be 20 μ m.
In the present embodiment; Position being positioned between said source electrode 202 and the said drain electrode 201 on the said oxide semiconductor channel layer 104 is provided with the etching barrier layer 301 of fitting with said conductor oxidate channel layer 104, and the length of said etching barrier layer 301 is than the gap d between source electrode 202 and the said drain electrode 201
1Big 5 μ m, the length of promptly said etching barrier layer 301 is 25 μ m.In order to satisfy core purpose of the present invention, the length of said etching barrier layer 301 is than the gap d between source electrode 202 and the said drain electrode 201
1During big 1-5 μ m, can both designing requirement of the present invention.
In the present embodiment, said oxide semiconductor thin-film transistor is an etching barrier type structure.
In the present embodiment, said etching barrier layer 301 is by Si
3N
4Process, need to prove, for realizing core purpose of the present invention, the material of said etching barrier layer 301 does not constitute restriction, and said etching barrier layer 301 can also be by SiO
2, TiO
2Or Al
2O
3In one or more process.
In the present embodiment; Said etching barrier layer 301 is provided with passivation layer with the another side that said oxide semiconductor channel layer 104 is fitted; The thickness of said passivation layer is 400nm, and for realizing core purpose of the present invention, the thickness of said passivation layer can both meet design requirement during for 100-400nm.
Need to prove that in the present embodiment, in order to realize core purpose of the present invention, said etching barrier layer 301 is optional, oxide semiconductor thin-film transistor as shown in Figure 1 does not just have said etching barrier layer 301.
In the present embodiment; Said substrate 101 is processed by glass; Certainly; Said substrate 101 can also adopt silicon or flexible substrate to process, and flexible substrate can be polyimide (polyimides), PET (PETG), PEN (PEN), PES (gathering benzene diethyl sulfone) or Parylene (xylylene po1ymer) etc. in the present invention.
In the present embodiment; Between said substrate 101 and said grid 102, one deck resilient coating is set, the thickness of said resilient coating is 400nm, certainly; For satisfying core purpose of the present invention, when being arranged between the 100-400nm, the thickness of said resilient coating can both meet design requirement.In the present embodiment, said resilient coating Si
3N
4Process separately, said resilient coating can also be by SiO
2Process separately, perhaps by SiO
2And Si
3N
4Process jointly.
In the present embodiment, said gate electrode 102 is processed by Al, and it can also be processed by among Mo, MoW, n++Si, T or the ITO any.
In the present embodiment, said insulating medium layer 103 is by Si
3N
4Process, it can also be by ZTSO, SiO
2Or Al
2O
3In one or more process, be prepared from the method for PECVD, sputter or ALD (ald).
In the present embodiment, said oxide semiconductor channel layer 104 is processed by ZnO, and it can also be by IGO, ZTO, GZO, IGOZ, In
2O
3, Cu
2O or SnO
2In one or more process.Said oxide semiconductor channel layer 104 is a n type raceway groove.The said oxide semiconductor channel layer 104 general modes of sputter that adopt form.
In the present embodiment; Said drain electrode 201 is 1.5 μ m with the length of said gate electrode 102 overlapping region in the horizontal direction; For the present invention, said drain electrode 201 is 0-3 μ m with the length range of said gate electrode 102 overlapping region in the horizontal direction.
Embodiment 3
As shown in Figure 2; Present embodiment provides a kind of oxide semiconductor thin-film transistor; Comprise substrate 101 and be arranged on gate electrode 102, insulating medium layer 103 and the oxide semiconductor channel layer 104 on the said substrate 101 in order; Said insulating medium layer 103 makes said gate electrode 102 and said oxide semiconductor channel layer 104 insulate; The upper surface of said oxide semiconductor channel layer 104 is provided with drain electrode 201 and source electrode 202, and the gap between said drain electrode 201 and the said source electrode 202 is d
1, said source electrode 202 is d with the length of said grid 102 overlapping region in the horizontal direction
2, said source electrode 202 is a Schottky contacts with contacting of 104 of said oxide semiconductor channel layers, said drain electrode 201 is an ohmic contact with contacting of 104 of said oxide semiconductor channel layers.
For the ease of between grid 102 and source electrode 202, forming electric field, thereby be beneficial to carrier transport, the length d of said source electrode 202 and said grid 102 overlapping region in the horizontal direction
2Scope be 3-20 μ m, in the present embodiment, d
2Be 10 μ m.
Among the present invention, the gap d between said drain electrode 201 and the said source electrode 202
1Scope be 1～20 μ m, in the present embodiment, the gap d between said drain electrode 201 and the said source electrode 202
1Be 15 μ m.
In the present embodiment; Position being positioned between said source electrode 202 and the said drain electrode 201 on the said oxide semiconductor channel layer 104 is provided with the etching barrier layer 301 of fitting with said conductor oxidate channel layer 104, and the length of said etching barrier layer 301 is than the gap d between source electrode 202 and the said drain electrode 201
1Big 3 μ m, the length of promptly said etching barrier layer 301 is 18 μ m.In order to satisfy core purpose of the present invention, the length of said etching barrier layer 301 is than the gap d between source electrode 202 and the said drain electrode 201
1During big 1-5 μ m, can both designing requirement of the present invention.
In the present embodiment, said oxide semiconductor thin-film transistor is an etching barrier type structure.
In the present embodiment, said etching barrier layer 301 is by TiO
2Process, need to prove, for realizing core purpose of the present invention, the material of said etching barrier layer 301 does not constitute restriction, and said etching barrier layer 301 can also be by SiO
2, Si
3N
4Or Al
2O
3In one or more process.
In the present embodiment; Said etching barrier layer 301 is provided with passivation layer with the another side that said oxide semiconductor channel layer 104 is fitted; The thickness of said passivation layer is 200nm, and for realizing core purpose of the present invention, the thickness of said passivation layer can both meet design requirement during for 100-400nm.
Need to prove that in the present embodiment, in order to realize core purpose of the present invention, said etching barrier layer 301 is optional, oxide semiconductor thin-film transistor as shown in Figure 1 does not just have said etching barrier layer 301.
In the present embodiment; Said substrate 101 is processed by PET; Certainly; Said substrate 101 can also adopt silicon, glass or other flexible substrate to process, and other flexible substrate can be polyimide (polyimides), PET (PETG), PEN (PEN), PES (gathering benzene diethyl sulfone) or Parylene (xylylene po1ymer) etc. in the present invention.
In the present embodiment; Between said substrate 101 and said grid 102, one deck resilient coating is set, the thickness of said resilient coating is 200nm, certainly; For satisfying core purpose of the present invention, when being arranged between the 100-400nm, the thickness of said resilient coating can both meet design requirement.In the present embodiment, said resilient coating is by SiO
2And Si
3N
4Process jointly, said resilient coating can also be by SiO
2Or Si
3N
4Process separately.
In the present embodiment, said gate electrode 102 is processed by ITO, and it can also be processed by among Mo, MoW, n++Si, T or the Al any.
In the present embodiment, said insulating medium layer 103 is by Al
2O
3Process, it can also be by ZTSO, SiO
2Or Si
3N
4In one or more process, be prepared from the method for PECVD, sputter or ALD (ald).
In the present embodiment, said oxide semiconductor channel layer 104 is by SnO
2Process, it can also be by IGO, ZTO, GZO, IGOZ, In
2O
3, Cu
2Among O or the ZnO one or more are processed.Said oxide semiconductor channel layer 104 is a n type raceway groove.Said oxide semiconductor channel layer 104 generally is prepared from the method for sputter.
In the present embodiment, said drain electrode 201 is 0 μ m with the length of said gate electrode 102 overlapping region in the horizontal direction, and for the present invention, said drain electrode 201 is 0-3 μ m with the length range of said gate electrode 102 overlapping region in the horizontal direction.
Embodiment 4
As shown in Figure 1; Present embodiment provides a kind of oxide semiconductor thin-film transistor; Comprise substrate 101 and be arranged on gate electrode 102, insulating medium layer 103 and the oxide semiconductor channel layer 104 on the said substrate 101 in order; Said insulating medium layer 103 makes said gate electrode 102 and said oxide semiconductor channel layer 104 insulate; The upper surface of said oxide semiconductor channel layer 104 is provided with drain electrode 201 and source electrode 202, and the gap between said drain electrode 201 and the said source electrode 202 is d
1, said source electrode 202 is d with the length of said grid 102 overlapping region in the horizontal direction
2, said source electrode 202 is a Schottky contacts with contacting of 104 of said oxide semiconductor channel layers, said drain electrode 201 is an ohmic contact with contacting of 104 of said oxide semiconductor channel layers.
For the ease of between grid 102 and source electrode 202, forming electric field, thereby be beneficial to carrier transport, the length d of said source electrode 202 and said grid 102 overlapping region in the horizontal direction
2Scope be 3-20 μ m, in the present embodiment, d
2Be 3 μ m.
Among the present invention, the gap d between said drain electrode 201 and the said source electrode 202
1Scope be 1～20 μ m, in the present embodiment, the gap d X between said drain electrode 201 and the said source electrode 202 is 1 μ m.
In the present embodiment; Said substrate 101 is processed by silicon; Certainly; Said substrate 101 can also adopt glass or flexible substrate to process, and flexible substrate can be polyimide (polyimides), PET (PETG), PEN (PEN), PES (gathering benzene diethyl sulfone) or Parylene (xylylene po1ymer) etc. in the present invention.
In the present embodiment; Between said substrate 101 and said grid 102, one deck resilient coating is set, the thickness of said resilient coating is 100nm, certainly; For satisfying core purpose of the present invention, when being arranged between the 100-400nm, the thickness of said resilient coating can both meet design requirement.In the present embodiment, said resilient coating SiO
2Process separately, said resilient coating can also be by Si
3N
4Process separately, perhaps by SiO
2And Si
3N
4Process jointly.
In the present embodiment, said gate electrode 102 is processed by Mo, and it can also be processed by among MoW, n++Si, T, Al or the ITO any.
In the present embodiment, said insulating medium layer 103 is by SiO
2Process, it can also be by ZTSO, Si
3N
4Or Al
2O
3In one or more process, be prepared from the method for PECVD, sputter or ALD (ald).
In the present embodiment, said oxide semiconductor channel layer 104 is processed by IGOZ, and it can also be by IGO, ZTO, GZO, ZnO, In
2O
3, Cu
2O or SnO
2In one or more process.Said oxide semiconductor channel layer 104 is a n type raceway groove.The said oxide semiconductor channel layer 104 general modes of sputter that adopt form.
In the present embodiment, said drain electrode 201 is 3 μ m with the length of said gate electrode 102 overlapping region in the horizontal direction, and for the present invention, said drain electrode 201 is 0-3 μ m with the length range of said gate electrode 102 overlapping region in the horizontal direction.
Embodiment 5
As shown in Figure 1; Present embodiment provides a kind of oxide semiconductor thin-film transistor; Comprise substrate 101 and be arranged on gate electrode 102, insulating medium layer 103 and the oxide semiconductor channel layer 104 on the said substrate 101 in order; Said insulating medium layer 103 makes said gate electrode 102 and said oxide semiconductor channel layer 104 insulate; The upper surface of said oxide semiconductor channel layer 104 is provided with drain electrode 201 and source electrode 202, and the gap between said drain electrode 201 and the said source electrode 202 is d
1, said source electrode 202 is d with the length of said grid 102 overlapping region in the horizontal direction
2, said source electrode 202 is a Schottky contacts with contacting of 104 of said oxide semiconductor channel layers, said drain electrode 201 is an ohmic contact with contacting of 104 of said oxide semiconductor channel layers.
For the ease of between grid 102 and source electrode 202, forming electric field, thereby be beneficial to carrier transport, the length d of said source electrode 202 and said grid 102 overlapping region in the horizontal direction
2Scope be 3-20 μ m, in the present embodiment, d
2Be 20 μ m.
Among the present invention, the gap d between said drain electrode 201 and the said source electrode 202
1Scope be 1～20 μ m, in the present embodiment, the gap d between said drain electrode 201 and the said source electrode 202
1Be 20 μ m.
In the present embodiment; Said substrate 101 is processed by glass; Certainly; Said substrate 101 can also adopt silicon or flexible substrate to process, and flexible substrate can be polyimide (polyimides), PET (PETG), PEN (PEN), PES (gathering benzene diethyl sulfone) or Parylene (xylylene po1ymer) etc. in the present invention.
In the present embodiment; Between said substrate 101 and said grid 102, one deck resilient coating is set, the thickness of said resilient coating is 400nm, certainly; For satisfying core purpose of the present invention, when being arranged between the 100-400nm, the thickness of said resilient coating can both meet design requirement.In the present embodiment, said resilient coating Si
3N
4Process separately, said resilient coating can also be by SiO
2Process separately, perhaps by SiO
2And Si
3N
4Process jointly.
In the present embodiment, said gate electrode 102 is processed by Al, and it can also be processed by among Mo, MoW, n++Si, T or the ITO any.
In the present embodiment, said insulating medium layer 103 is by Si
3N
4Process, it can also be by ZTSO, SiO
2Or Al
2O
3In one or more process, be prepared from the method for PECVD, sputter or ALD (ald).
In the present embodiment, said oxide semiconductor channel layer 104 is processed by ZnO, and it can also be by IGO, ZTO, GZO, IGOZ, In
2O
3, Cu
2O or SnO
2In one or more process.Said oxide semiconductor channel layer 104 is a n type raceway groove.The said oxide semiconductor channel layer 104 general modes of sputter that adopt form.
In the present embodiment; Said drain electrode 201 is 1.5 μ m with the length of said gate electrode 102 overlapping region in the horizontal direction; For the present invention, said drain electrode 201 is 0-3 μ m with the length range of said gate electrode 102 overlapping region in the horizontal direction.
Embodiment 6
As shown in Figure 1; Present embodiment provides a kind of oxide semiconductor thin-film transistor; Comprise substrate 101 and be arranged on gate electrode 102, insulating medium layer 103 and the oxide semiconductor channel layer 104 on the said substrate 101 in order; Said insulating medium layer 103 makes said gate electrode 102 and said oxide semiconductor channel layer 104 insulate; The upper surface of said oxide semiconductor channel layer 104 is provided with drain electrode 201 and source electrode 202, and the gap between said drain electrode 201 and the said source electrode 202 is d
1, said source electrode 202 is d with the length of said grid 102 overlapping region in the horizontal direction
2, said source electrode 202 is a Schottky contacts with contacting of 104 of said oxide semiconductor channel layers, said drain electrode 201 is an ohmic contact with contacting of 104 of said oxide semiconductor channel layers.
For the ease of between grid 102 and source electrode 202, forming electric field, thereby be beneficial to carrier transport, the length d of said source electrode 202 and said grid 102 overlapping region in the horizontal direction
2Scope be 3-20 μ m, in the present embodiment, d
2Be 10 μ m.
Among the present invention, the gap d between said drain electrode 201 and the said source electrode 202
1Scope be 1～20 μ m, in the present embodiment, the gap d between said drain electrode 201 and the said source electrode 202
1Be 15 μ m.
In the present embodiment; Said substrate 101 is processed by PET; Certainly; Said substrate 101 can also adopt silicon, glass or other flexible substrate to process, and other flexible substrate can be polyimide (polyimides), PET (PETG), PEN (PEN), PES (gathering benzene diethyl sulfone) or Parylene (xylylene po1ymer) etc. in the present invention.
In the present embodiment; Between said substrate 101 and said grid 102, one deck resilient coating is set, the thickness of said resilient coating is 200nm, certainly; For satisfying core purpose of the present invention, when being arranged between the 100-400nm, the thickness of said resilient coating can both meet design requirement.In the present embodiment, said resilient coating is by SiO
2And Si
3N
4Process jointly, said resilient coating can also be by SiO
2Or Si
3N
4Process separately.
In the present embodiment, said gate electrode 102 is processed by ITO, and it can also be processed by among Mo, MoW, n++Si, T or the Al any.
In the present embodiment, said insulating medium layer 103 is by Al
2O
3Process, it can also be by ZTSO, SiO
2Or Si
3N
4In one or more process, be prepared from the method for PECVD, sputter or ALD (ald).
In the present embodiment, said oxide semiconductor channel layer 104 is by SnO
2Process, it can also be by IGO, ZTO, GZO, IGOZ, In
2O
3, Cu
2Among O or the ZnO one or more are processed.Said oxide semiconductor channel layer 104 is a n type raceway groove.Said oxide semiconductor channel layer 104 generally is prepared from the method for sputter.
In the present embodiment, said drain electrode 201 is 0 μ m with the length of said gate electrode 102 overlapping region in the horizontal direction, and for the present invention, said drain electrode 201 is 0-3 μ m with the length range of said gate electrode 102 overlapping region in the horizontal direction.
Be the formation condition that example is explained the way of contact of the present invention with n type tunnel oxide semiconductor IGZO thin-film transistor below.Gate electrode can be Mo, MoW, Ti, a kind of among the Al etc.Drain electrode and raceway groove form ohmic contact, the drain electrode material select work function than n type oxide semiconductor low [the IGZO work function is about 4.57eV, sees table 2; Drain electrode/the channel interface that forms can be like Ti/Al/Ti/IGZO, Al/AZO/IGZO, Au/Ti/IGZO; Al/IGZO, Ti/IGZO etc.And source electrode and raceway groove form Schottky contacts, can select work function higher than n type oxide semiconductor, such as Mo/IGZO, and Au/IGZO, Pt/IGZO, Ni/IGZO, ITO/IGZO etc.Source, drain electrode generally are prepared from sputtering method.
The present invention also is applicable to the oxide semiconductor of p type raceway groove, like the ZnO of p type, Cu
2O, and SnO
2Deng, the selection of source, drain electrode is opposite with the n type when making the present invention's structure like Fig. 1 or thin-film transistor shown in Figure 2.
Table 1 forms the condition on n type and p type barrier layer
| Work function relatively | The n N-type semiconductor N | The p N-type semiconductor N |
| W m>;W s | The barrier layer | Anti-barrier layer |
| W m<W s | Anti-barrier layer | The barrier layer |
W
m---the work function of metal; W
s---semi-conductive work function
Work function (the unit: eV) of the various metallic elements of table 2
| Metal | Work function | Metal | Work function | Metal | Work function | Metal | Work function | Metal | Work function | Metal | Work function |
| Ag | 4.26 | Al | 4.28 | As | 3.75 | Au | 5.1 | B | 4.45 | Ba | 2.7 |
| Be | 4.98 | Bi | 4.22 | C | 5 | Ca | 2.87 | Cd | 4.22 | Ce | 2.9 |
| Co | 5 | Cr | 4.5 | Cs | 2.14 | Cu | 4.65 | Eu | 2.5 | Fe | 4.5 |
| Ga | 4.2 | Gd | 3.1 | Hf | 3.9 | Hg | 4.49 | In | 4.12 | Ir | 5.27 |
| K | 2.3 | La | 3.5 | Li | 2.9 | Lu | 3.3 | Mg | 3.66 | Mn | 4.1 |
| Mo | 4.6 | Na | 2.75 | Nb | 4.3 | Nd | 3.2 | Ni | 5.15 | Os | 4.83 |
| Pb | 4.25 | Pt | 5.65 | Rb | 2.16 | Re | 4.96 | Rh | 4.98 | Ru | 4.71 |
| Sb | 4.55 | Sc | 3.5 | Se | 5.9 | Si | 4.85 | Sm | 2.7 | Sn | 4.42 |
| Sr | 2.59 | Ta | 4.25 | Tb | 3 | Te | 4.95 | Th | 3.4 | Ti | 4.33 |
| Tl | 3.84 | U | 3.63 | V | 4.3 | W | 4.55 | Y | 3.1 | Zn | 4.33 |
Obviously; Above embodiment is only in order to explain technical scheme of the present invention; And be not the qualification to execution mode, although the present invention is specified with reference to preferred embodiment, the those of ordinary skill in any affiliated technical field; On the basis of above-mentioned explanation, can also make other multi-form variation or change, also need not here also can't give exhaustive all execution modes.Therefore protection scope of the present invention is as the criterion when looking the claim scope person of defining.
Claims (17)
1. oxide semiconductor thin-film transistor; Comprise substrate (101) and be arranged on gate electrode (102), insulating medium layer (103) and the oxide semiconductor channel layer (104) on the said substrate (101) in order; Said insulating medium layer (103) makes said gate electrode (102) and said oxide semiconductor channel layer (104) insulate; The upper surface of said oxide semiconductor channel layer (104) is provided with drain electrode (201) and source electrode (202), and the gap between said drain electrode (201) and the said source electrode (202) is d
1, said source electrode (202) is d with the length of said grid (102) overlapping region in the horizontal direction
2, contacting between said source electrode (202) and said oxide semiconductor channel layer (104) is Schottky contacts, contacting between said drain electrode (201) and said oxide semiconductor channel layer (104) is ohmic contact.
2. oxide semiconductor thin-film transistor according to claim 1 is characterized in that: the gap d between said drain electrode (201) and the said source electrode (202)
1Scope be 1～20 μ m.
3. oxide semiconductor thin-film transistor according to claim 1 and 2; It is characterized in that: the position that between said source electrode (202) and said drain electrode (201), is positioned on the said oxide semiconductor channel layer (104) is provided with the etching barrier layer (301) of fitting with said conductor oxidate channel layer (104), and the length of said etching barrier layer (301) is than the gap d between said source electrode (202) and the said drain electrode (201)
1Big 1～5 μ m.
4. oxide semiconductor thin-film transistor according to claim 3 is characterized in that: said etching barrier layer (301) is for back of the body channel-etch type structure or stop a kind of in the etching type structure.
5. oxide semiconductor thin-film transistor according to claim 4 is characterized in that: said etching barrier layer (301) is provided with passivation layer with the another side that said oxide semiconductor channel layer (104) is fitted.
6. oxide semiconductor thin-film transistor according to claim 5 is characterized in that: the thickness of said passivation layer is 100-400nm.
7. according to each said oxide semiconductor thin-film transistor among the claim 1-6, it is characterized in that: said substrate (101) is processed by monocrystalline silicon, glass or flexible substrate.
8. according to each described oxide semiconductor thin-film transistor among the claim 1-7, it is characterized in that:
Between said substrate (101) and said grid (102), one deck resilient coating is set.
9. oxide semiconductor thin-film transistor according to claim 8 is characterized in that: the thickness of said resilient coating is 100-400nm.
10. according to Claim 8 or 9 described oxide semiconductor thin-film transistors, it is characterized in that: said resilient coating is by SiO
2And/or Si
3N
4Form.
11. according to each described oxide semiconductor thin-film transistor among the claim 1-10, it is characterized in that: said gate electrode (102) is processed by among Mo, MoW, n++Si, T, Al or the ITO any.
12. according to each described oxide semiconductor thin-film transistor among the claim 1-11, it is characterized in that: said insulating medium layer (103) is by SiO
2, Si
3N
4Or Al
2O
3In one or more process.
13. according to each described oxide semiconductor thin-film transistor among the claim 1-12, it is characterized in that: said oxide semiconductor channel layer (104) is by IGZO, IGO, ZTO, GZO, ZnO, In
2O
3, Cu
2O or SnO
2In one or more process.
14. according to each described oxide semiconductor thin-film transistor among the claim 3-13, it is characterized in that: said etching barrier layer (301) is by SiO
2, Si
3N
4, TiO
2, Al
2O
3Or among the ZTSO one or more are processed.
15., it is characterized in that: the length d of said source electrode (202) and said grid (102) overlapping region in the horizontal direction according to each described oxide semiconductor thin-film transistor among the claim 1-14
2Scope be 3-20 μ m.
16. according to each described oxide semiconductor thin-film transistor among the claim 1-15, it is characterized in that: said drain electrode (201) is 0-3 μ m with the length range of said gate electrode (102) overlapping region in the horizontal direction.
17. according to each described oxide semiconductor thin-film transistor among the claim 3-16, it is characterized in that: said oxide semiconductor channel layer (104) is n type raceway groove or p type raceway groove.
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