TW201431069A - Metal oxynitride based heterojunction field effect transistor - Google Patents

Abstract

Embodiments of the present invention generally relate to an HFET having one or more metal oxynitride or metal oxide channel semiconductor layers with source and drain electrodes, and a gate which contacts the semiconductor layer though a junction or junctions formed between the gate and channel semiconductor. The junction can be formed by inserting a different type of semiconductor material, for example, an amorphous silicon semiconductor material, a different metal oxynitride, a p-type metal oxide semiconductor or a low work function metal oxide conductor, between the gate and channel material. The junction can be also formed by using a metal which forms a Schottky barrier as in a Schottky diode between the metal and semiconductor.

Description

Heterojunction field effect transistor based on metal oxynitride

Embodiments of the present invention generally relate to a heterojunction field effect transistor (HFET) having a one or more metal oxynitride channel semiconductor layers and a gate. The heterojunction field effect transistor has one or more metal oxynitride channel semiconductor layers. The metal oxynitride channel semiconductor layer has a source and a drain, and the gate contacts the semiconductor layer via one or more junctions formed between the gate and the channel semiconductor.

At present, the focus on thin film transistors (TFTs) is particularly high, because such devices can be used in devices such as liquid crystal active matrix displays (LCDs), and devices such as liquid crystal active matrix displays are often used. On the computer and TV tablet. The LCDs may also include light emitting diodes (LEDs), such as organic light emitting diodes (OLEDs) for backlighting. LEDs and OLEDs require TFTs for control to address the activity of the display screen.

The current (ie, on-current) driven by the TFTs is limited by the channel material (often meant active material, semiconductor material or semiconductor active material) and channel width and length. In addition, the turn-on voltage is determined The carrier is accumulated in the channel region of the semiconductor layer, and the threshold voltage is offset after bias temperature stress or current temperature stress, and when semiconductor or dielectric When the fixed charge drifts or charges in the electrical material are trapped in the interface, the carrier packing changes.

Helium as a semiconductor material has its limitations. Amorphous germanium has a low mobility. Although polycrystalline germanium has a higher mobility than amorphous germanium, it is expensive to manufacture and must be subjected to an annealing process.

Therefore, TFTs having high mobility but which can be manufactured at low cost are required in the field, and TFTs are formed of semiconductor materials.

Embodiments of the present invention generally relate to an HFET having a channel semiconductor layer having one or more metal oxynitrides or metal oxides having a source and a drain, and a gate connected via one or several connections The surface contacts the semiconductor layer, and the junction is formed between the gate and the channel semiconductor. The junction can be formed by interposing different forms of semiconductor material, different metal oxynitrides, p-type metal oxide semiconductors or low work function metal oxide conductors between the gate and the channel material, examples of semiconductor materials It is an amorphous germanium semiconductor material. The junction can also be formed by the use of a metal that is typically formed between the metal and the semiconductor as in the Schottky transistor.

In one embodiment, a heterojunction field effect transistor includes: a first semiconductor layer; a source disposed on at least a portion of the first semiconductor layer; and a drain disposed on at least a portion of the first semiconductor layer Upper; a gate dielectric layer, Placed over the source, drain and at least a portion of the first semiconductor layer, the gate dielectric layer has a junction therethrough to expose at least a portion of the first semiconductor layer; a second semiconductor layer disposed on the gate Above the electrical layer and the junction; and a gate disposed above the junction and the junction of the second semiconductor layer. The second semiconductor layer has a lower Fermi level than the first semiconductor layer, or the gate metal has a work function which is lower than the Fermi level of the connected semiconductor to form a Schottky barrier to the metal and Between semiconductors. In order to better understand the above and other aspects of the present invention, the preferred embodiments are described below, and in conjunction with the drawings, the detailed description is as follows:

100‧‧‧ cavity

102, 202‧‧‧ substrate

104‧‧‧ Target

106‧‧‧Base

108‧‧‧Tip

110‧‧‧ Grounding belt

112‧‧‧Actuator

114‧‧‧vacuum pump

116‧‧‧ Backplane

118‧‧‧Magnetron

120‧‧‧ Dark area cover

122‧‧‧ cavity cover

124‧‧‧Anode

126‧‧‧ gas guiding tube

128‧‧‧ couplings

130‧‧‧ ‧ body

132‧‧‧ gas control panel

200, 220, 230, 300, 400, 500‧‧‧ HFET

204‧‧‧Dielectric layer

206A, 206B, 206C, 302, 304, 402, 502‧‧ ‧ semiconductor layer

208‧‧‧ source

210‧‧‧汲polar

212‧‧‧gate dielectric layer

214, 306‧‧ ‧ gate

216‧‧‧ joint

A, AA, B, C, D, E, F‧‧‧ arrows

N, S‧‧‧ magnetic pole

For a more detailed description of the present invention, reference should be made to the preferred embodiments of the invention. However, it is to be understood that the appended claims are not intended to limit the scope of the invention.

1 is a cross-sectional view of a cavity of a PVD in accordance with an embodiment of the present invention.

2A-2C are cross-sectional views of HFETs in accordance with several embodiments.

FIG. 3 is a cross-sectional view of an HFET according to another embodiment.

4 is a cross-sectional view of an HFET in accordance with another embodiment.

FIG. 5 is a cross-sectional view of an HFET according to another embodiment.

For ease of understanding, the same reference numbers are used wherever practicable. It is used to indicate the same components that are common to these figures. It is contemplated that elements disclosed in one embodiment may be used in other embodiments without departing from the scope of the invention.

Embodiments of the present invention generally relate to a metal oxynitride HFET having a one or more channel semiconductor layers having a source and a drain, and a gate formed via one or more The junction between the gate and the channel semiconductor contacts the semiconductor layer. The junction can be formed by interposing different forms of semiconductor material, different metal oxynitrides, p-type metal oxide semiconductors or low work function metal oxide conductors between the gate and the channel material, in different forms. The semiconductor material is exemplified by an amorphous germanium semiconductor material. The junction can also be formed by the use of a metal that forms a Schottky barrier between the metal and the semiconductor as is typical in Schottky diodes.

The present invention is illustratively described and can be used in a PVD cavity to process a large area substrate, such as a 4300 PVD cavity, taken from AKT ^® , located in Santa Clara, California. A subsidiary of Applied Materials, Inc., Santa Clara, California. However, it should be understood that the sputter target may have utility in other system architectures, including systems configured to process large area circular substrates and systems produced by other manufacturers.

1 is a cross-sectional view of a cavity 100 of a PVD in accordance with an embodiment of the present invention. The cavity 100 can be vented by the vacuum pump 114. In the cavity 100, the substrate 102 can be disposed relative to the target 104. The substrate can be disposed in the cavity 100 On the susceptor 106. The base 106 can be lifted or lowered by the actuator 112 as indicated by the arrow "A". The pedestal 106 can be lifted to lift the substrate 102 to a processing position and lowered such that the substrate 102 can be removed from the cavity 100. When the pedestal 106 is in the lower position, the lift pin 108 lifts the substrate 102 onto the pedestal 106. Ground strap 110 can ground base 106 during processing. The pedestal 106 can be lifted during processing to aid in uniform deposition.

Target 104 may include one or more targets 104. The target 104 can be bonded to the backing plate 116 by a bonding layer. To control the temperature of the target 104, a cooling passage can be located in the backing plate 116. One or more magnetrons 118 may be disposed behind the backing plate 116. The magnetron 118 can be scanned across the backing plate 116 in a linear or two dimensional path. The walls of the cavity can be shielded by the dark space shield 120 and the cavity shield 122 to avoid deposition.

In order to help provide uniform sputtering deposition throughout the substrate 102, the anode 124 can be placed between the target 104 and the substrate 102. In one embodiment, the anode 124 can be a bead-treated stainless steel plated with arc sprayed aluminum. In one embodiment, one end of the anode 124 can be fixed to the cavity wall by the frame body 130. The anode 124 provides a charge relative to the target 104 such that charged ions will be attracted thereto rather than a cavity wall that is typically a ground potential. By providing the anode 124 between the target 104 and the substrate 102, the plasma can be more uniform and contribute to deposition.

For reactive sputtering, it is helpful to provide a reactive gas into the chamber 100. One or more gas guiding tubes 126 may also be at the target 104 and the substrate 102 The distance between the entire cavity 100 is between. The gas guiding tube 126 can guide a sputtering gas such as an inert gas or a reactive gas, the inert gas includes argon, and the reactive gas is, for example, oxygen, nitrogen, or the like. Gas may be supplied from gas control plate 132 to gas guiding tube 126, which may direct one or more gases, such as argon, oxygen, and nitrogen. The gas guiding tube 126 can be disposed at a position below the substrate 102 of the one or more anodes 124 and the target 104. The anode 124 can shield the gas guiding tube 126 during processing to avoid deposition. Masking the gas guiding tube 126 with the anode 124 reduces the total amount of deposition that may cover or block the gas vent. The gas guiding tube 126 can be coupled to the anode 124 by one or more coupling members 128.

As described herein, the TFT is formed using a combination of one or more metal oxynitride layers or a metal oxynitride layer having another semiconductor material as the active channel material, more particularly an HFET. A two dimensional electron gas can be formed in the transistor via an interface confined between the two layers, rather than from an external electric field provided to the transistor. The transistor has a gate that directly contacts the active channel material or contacts the active channel material via a thin dielectric layer or other semiconductor layer. The source and drain are separated by a region that is covered by a gate that can directly contact the via or contact the via via other layers or dielectric layers of the semiconductor material. The region covered by the gate and the source and drain can also be processed in different ways via annealing or conversion.

2A-2C are cross-sectional views of HFETs in accordance with several embodiments. In the embodiment shown in Figures 2A-2C, the HFET includes a substrate 202. Suitable materials for the substrate 202 include bismuth, bismuth, bismuth, soda lime glass (soda lime) Glass), glass, semiconductor, plastic, steel or stainless steel substrates, but not limited to these materials.

There may be a dielectric layer 204 on the substrate 202. Suitable materials that can be used for the dielectric layer 204 include hafnium oxide, hafnium oxynitride, tantalum nitride, aluminum oxide, or combinations thereof. Dielectric layer 204 can be deposited by suitable deposition techniques, including plasma enhanced chemical vapor deposition (PECVD).

A plurality of semiconductor layers 206A-206C are then formed over dielectric layer 204. In practical applications, the semiconductor layers 206A-206C are often referred to as channel layers, active layers, or semiconductor active layers.

Source 208 and drain 210 are formed over semiconductor layers 206A-206C. The exposed portions of the semiconductor layers 206A-206C between the source 208 and the drain 210 are used as active channels. Suitable materials for source 208 and drain 210 include chromium, copper, aluminum, tantalum, titanium, molybdenum, and combinations thereof, or transparent conductive oxides (TCOs). Source 208 and drain 210 may be formed by a suitable deposition technique, such as physical vapor deposition (PVD), followed by PVD as a patterning by etching.

A gate dielectric layer 212 can be deposited over the exposed active channel and source 208 and drain 210. Suitable materials that can be used for the gate dielectric layer 212 include hafnium oxide, hafnium oxynitride, tantalum nitride, aluminum oxide, or combinations thereof. Gate dielectric layer 212 can be deposited by suitable deposition techniques, including plasma assisted chemical vapor deposition (PECVD). The gate dielectric layer 212 can then be etched to form the junction 216 and exposed to active The uppermost semiconductor layer 206C of the channel.

Gate 214 can then be formed by filling at least a portion of gate 214 into junction 216. Suitable materials for the gate 204 include chromium, copper, aluminum, tantalum, titanium, molybdenum, and combinations thereof, or transparent conductive oxide (TCO), but are not limited to such materials, and transparent conductive oxides are commonly used, for example. Indium tin oxide (ITO) or fluorine doped zinc oxide (ZnO: F) as a transparent electrode. Gate 214 can be deposited by suitable deposition techniques such as PVD, metalorganic chemical vapor deposition (MOCVD), spin-on process, and printing processes.

As shown in FIG. 2A, the HFET 200 can have a junction 216 that is formed equidistant from the source 208 and the drain 210, as indicated by arrows "A" and "B". As shown in FIG. 2B, HFET 220 can have a junction 216 that is formed closer to source 208 or drain 210. The arrows "C" and "D" indicate that the junction 216 is closer to one of the source 208 and the drain 210. As shown in FIG. 2C, not only the junction 216 of the HFET 230 is formed closer to the source 208 or the drain 210 as indicated by arrows "E" and "F", but the gate 214 may be located only at the source. Above one of the pole 208 and the drain 210.

The semiconductor layers 206A-206C can include oxygen, nitrogen, and one or more elements selected from the group consisting of zinc, gallium, cadmium, indium, tin, and combinations thereof. In one embodiment, the semiconductor layers 206A-206C can include oxygen, nitrogen, and one or more elements having a filled s rail domain and a filled d rail domain. In another embodiment, the semiconductor layers 206A-206C can include oxygen, nitrogen, and one or more have filled rails The elements of the domain. In another embodiment, the semiconductor layers 206A-206C can include oxygen, nitrogen, and one or more divalent elements. In another embodiment, the semiconductor layers 206A-206C can include oxygen, nitrogen, and one or more trivalent elements. In another embodiment, the semiconductor layers 206A-206C can include oxygen, nitrogen, and one or more tetravalent elements.

Semiconductor layers 206A-206C may also include dopants. Suitable dopants that can be used include Al, Sn, Ga, Ca, Si, Ti, Cu, Ge, In, Ni, Mn, Cr, V, Mg, Si _x N _y , Al _x O _y , and SiC. The dopant may also be non-metallic, such as H, C, S, F, and the like. In one embodiment, the dopant comprises aluminum. In another embodiment, the dopant comprises tin.

Examples of the semiconductor layers 206A-206C include the following: ZnO _x N _y , SnO _x N _y , InO _x N _y , CdO _x N _y , GaO _x N _y , ZnSnO _x N _y , ZnInO _x N _y , ZnCdO _x N _{y , ZnGaO x N y, SnInO x} N y, SnCdO x N y, SnGaO x N y, InCdO x N y, InGaO x N y, CdGaO x N y, ZnSnInO x N y, ZnSnCdO x N y, ZnSnGaO x N y ZnInCdO _x N _y , ZnInGaO _x N _y , ZnCdGaO _x N _y , SnInCdO _x N _y , SnInGaO _x N _y , SnCdGaO _x N _y , InCdGaO _x N _y , ZnSnInCdO _x N _y , ZnSnInGaO _x N _y , ZnInCdGaO _x N _y And SnInCdGaO _x N _y . Examples of the semiconductor layers 206A-206C include doping materials: ZnO _x N _y : Al, ZnO _x N _y : Sn, SnO _x N _y : Al, InO _x N _y : Al, InO _x N _y : Sn, CdO _x N _y : Al, CdO _x N _y : Sn, GaO _x N _y : Al, GaO _x N _y : Sn, ZnSnO _x N _y : Al, ZnInO _x N _y : Al, ZnInO _x N _y : Sn, ZnCdO _x N _y : Al, ZnCdO _x N _y : Sn, ZnGaO _x N _y : Al, ZnGaO _x N _y : Sn, SnInO _x N _y : Al, SnCdO _x N _y : Al, SnGaO _x N _y : Al, InCdO _{x N y: Al, InCdO x N} y: Sn, InGaO x N y: Al, InGaO x N y: Sn, CdGaO x N y: Al, CdGaO x N y: Sn, ZnSnInO x N y: Al, ZnSnCdO x N _y : Al, ZnSnGaO _x N _y : Al, ZnInCdO _x N _y : Al, ZnInCdO _x N _y : Sn, ZnInGaO _x N _y : Al, ZnInGaO _x N _y : Sn, ZnCdGaO _x N _y : Al, ZnCdGaO _x N _y :Sn, SnInCdO _x N _y : Al, SnInGaO _x N _y : Al, SnCdGaO _x N _y : Al, InCdGaO _x N _y : Al, InCdGaO _x N _y : Sn, ZnSnInCdO _x N _y : Al, ZnSnInGaO _x N _y : Al, ZnInCdGaO _x N _y : Al, ZnInCdGaO _x N _y :Sn, and SnInCdGaO _x N _y :Al.

The semiconductor layers 206A-206C can be deposited by sputtering. In one embodiment, the sputter target comprises a metal such as zinc, gallium, tin, cadmium, indium, or a combination thereof. The sputter target may additionally include a dopant. An oxygen-containing gas and a nitrogen-containing system are introduced into the cavity to deposit the semiconductor layers 206A-206C by reactive sputtering. In one embodiment, the nitrogen containing gas comprises N ₂ . In another embodiment, the nitrogen containing gas comprises N ₂ O, NH ₃ , or a combination thereof. In one embodiment, the oxygen containing gas comprises O ₂ . In another embodiment, the oxygen containing gas comprises N ₂ O. The nitrogen containing nitrogen gas and the oxygen containing oxygen gas react with the metal from the sputtering target to form a semiconductor material on the substrate, the semiconductor material including metal, oxygen, nitrogen, and selective dopants. In one embodiment, the nitrogen-containing gas and oxygen-containing system are individual gases. In another embodiment, the nitrogen-containing gas and the oxygen-containing gas comprise the same gas. Additional additives such as B ₂ H ₆ , CO ₂ , CO, CH ₄ , and combinations thereof may also be provided to the cavity during sputtering.

Furthermore, the semiconductor layers 206A-206C may comprise a multi-component metal oxide (in other words a polycationic metal oxide such as IGZO), a single cationic metal oxide (in other words zinc oxide), or comprise at least two anions and a single cation. A multi-anionic compound of the system. The cation may be N, O, S, P, C, F, I, As, Se or the like. Additionally, the semiconductor layers 206A-206C can be selected from other semiconductor materials such as metal oxides or metal nitrides.

Each of the semiconductor layers 206A-206C can be different. Alternatively, the first semiconductor layer 206A and the third semiconductor layer 206C may be substantially identical, and the second semiconductor layer 206B may be different therefrom. For example, such layers may differ in composition. Having different semiconductor layers 206A-206C produces higher mobility. Higher mobility can be achieved with graphene and other layered semiconductor materials. However, mobility can be achieved by using quantum confinement by combining quantum oxide semiconductors having different energy gaps, carrier concentrations or Fermi levels with metal oxide semiconductors.

When the electron system is confined to a steep canyon called a quantum well, electrons can move quickly without colliding with other impurities. Quantum well systems using AlGaAs/GaAs structures are known. A heterojunction of two different metal oxynitrides or metal nitrides or metal oxides or a metal oxynitride and other semiconductor materials can be created to produce quantum wells. With the formation of quantum wells, high mobility can be achieved to produce high mobility TFTs and other thin film electronic devices. The film from the metal oxynitride may have one or more quantum wells to form a superlattice.

Each of the semiconductor layers 206A-206C will have various characteristics to facilitate interaction with other layers, respectively. Each of the semiconductor layers 206A-206C will have an energy level (Ev) of the vacuum, an energy level (ECB) at the bottom of the conduction band, an electrical intermediate order (ECNL), a Fermi level (EF), and an energy level at the top of the valence band ( EVB). By controlling the Fermi level and the electrical performance level, the amount The subwell can be formed and the mobility can be improved.

By controlling the Fermi level, the position of the quantum well can be pre-selected. Quantum wells can form interfaces that limit electrons to these layers, if desired. Alternatively, a quantum well can be formed to capture electrons in the second semiconductor layer 206B. Electronic limitations are achieved through dramatic changes in the composition of the different membranes in contact. This limitation is caused by an energy barrier formed when charge transfer crosses such interfaces, and charge transfer across these interfaces is due to differences in Fermi level and differences in electrical performance steps. The gate in Figure 2A-2C is a metal with a work function which is lower than the Fermi level of the connected semiconductor.

FIG. 3 is a cross-sectional view of the HFET 300 in accordance with another embodiment. It will be understood that although the HFET 300 illustrated in FIG. 3 has a junction 216 equidistant between the source 208 and the drain 210, other HFET layouts are applicable. For example, HFETs having a plurality of junctions can be expected as HFETs having a junction that is closer to one of source 208 or drain 210. Again, for example, the HFETs in Figure 2C are contemplated.

In the embodiment shown in FIG. 3, a plurality of semiconductor layers 302, 304 are disposed on the gate dielectric layer 212 and in the junction 216. The gate 306 is disposed on the semiconductor layer 304. Suitable materials for the gate 306 include chromium, copper, aluminum, tantalum, titanium, molybdenum, and combinations thereof, or transparent conductive oxide (TCO), but are not limited to such materials, and transparent conductive oxides are commonly used, for example. Indium tin oxide (ITO) or fluorine-doped zinc oxide (ZnO: F) as a transparent electrode.

In the embodiment shown in FIG. 3, two semiconductor layers are shown 302, 304. The two semiconductor layers 302, 304 comprise different compositions and/or characteristics. In one embodiment, the semiconductor layers 302, 304 may each comprise an amorphous germanium, wherein the first semiconductor layer 302 comprises intrinsic amorphous silicon and the second semiconductor layer 304 comprises p-type amorphous germanium. The first semiconductor layer 302 is in contact with the semiconductor layer 206A of the active channel. The distinct first and second semiconductor layers 302, 304 can also be different from the active layers of the semiconductor layers 206A-206C. In particular, it is contemplated that semiconductor layer 302 and semiconductor layer 206A have different compositions or properties such that the Fermi level of different semiconductor layers can induce electrons to be pushed from one semiconductor layer to another, or, if desired, Captured in a specific semiconductor layer. In addition, the semiconductor layers 302, 304 may also have different Fermi or electrical performance steps.

FIG. 4 is a cross-sectional view of an HFET 400 in accordance with another embodiment. It will be appreciated that while the HFET 400 illustrated in FIG. 4 has a junction 216 equidistant between the source 208 and the drain 210, other HFET designs are applicable. For example, HFETs having a plurality of junctions can be expected as HFETs having a junction that is closer to one of source 208 or drain 210. Again, for example, the HFETs in Figure 2C are contemplated.

In the embodiment shown in FIG. 4, a single semiconductor layer 402 is formed in junction 216 in the case where gate 306 is formed thereon. The semiconductor layer 402 may comprise a metal oxide or a metal oxynitride, which is different from the semiconductor material used for the semiconductor layer 206A. The semiconductor layer 402 may be different from the semiconductor layer 206A in a composition, a Fermi level, an electrical performance step, and the like. Suitable examples for the semiconductor layer 402 include zinc oxynitride rich in oxygen and zinc oxide rich Oxygen, tin oxynitride, indium oxynitride, tin dioxide, or a combination thereof.

FIG. 5 is a cross-sectional view of a HFET 500 in accordance with another embodiment. It will be appreciated that while the HFET 500 illustrated in Figure 5 has a junction 216 equidistant between the source 208 and the drain 210, other HFET designs are applicable. For example, HFETs having a plurality of junctions can be expected as HFETs having a junction that is closer to one of source 208 or drain 210. Again, for example, the HFETs in Figure 2C are contemplated.

In the embodiment shown in FIG. 5, a single semiconductor layer 502 is formed in the junction 216 in the case where the gate 306 is formed thereon. The semiconductor layer 502 includes a material different from the semiconductor layer 206A. The semiconductor layer 502 may be different from the semiconductor layer 206A in a composition, a Fermi level, an electrical performance step, and the like. Semiconductor layer 502 can include a p-type metal oxide or an oxynitride or a low work function metal oxide conductor. Tin oxide is an example of the semiconductor layer 502.

The mobility of the structure can be improved by having a gate that is in direct contact or in contact with the active channel material via a thin dielectric layer or other semiconductor layer.

In conclusion, the present invention has been disclosed in the above preferred embodiments, and is not intended to limit the present invention. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

202‧‧‧Substrate

204‧‧‧Dielectric layer

206A, 206B, 206C‧‧‧ semiconductor layer

208‧‧‧ source

210‧‧‧汲polar

212‧‧‧gate dielectric layer

214‧‧‧ gate

216‧‧‧ joint

230‧‧‧HFET

E, F‧‧‧ arrows

Claims (19)

A heterojunction field effect transistor, comprising: a first semiconductor layer; a source disposed on at least a portion of the first semiconductor layer; a drain disposed on at least a portion of the first semiconductor layer; a gate dielectric layer disposed over the source, the drain, and at least a portion of the first semiconductor layer, the gate dielectric layer having a junction therethrough to expose at least a portion of the first semiconductor layer; a second semiconductor layer is disposed over the gate dielectric layer and the junction; and a gate is disposed over the second semiconductor layer and the junction. The heterojunction field effect transistor of claim 1, wherein the second semiconductor layer comprises a plurality of semiconductor layers. The heterojunction field effect transistor of claim 2, wherein the second semiconductor layers comprise: a first second semiconductor layer comprising a first semiconductor material; and a second second semiconductor layer The second semiconductor material is different from the first semiconductor material. The heterojunction field effect transistor of claim 3, wherein the first semiconductor material comprises an intrinsic germanium. The heterojunction field effect transistor of claim 4, wherein the second semiconductor material comprises p-type germanium. The heterojunction field effect transistor of claim 5, wherein the first semiconductor material and the second semiconductor material are amorphous germanium. The heterojunction field effect transistor of claim 6, wherein the first semiconductor material and the second semiconductor material are different from the material including the first semiconductor layer. The heterojunction field effect transistor of claim 7, wherein the first semiconductor layer comprises a plurality of layers. The heterojunction field effect transistor of claim 8, wherein the first semiconductor layers have different Fermi energy levels. The heterojunction field effect transistor of claim 1, wherein the second semiconductor layer comprises a metal oxynitride or a metal oxide. The heterojunction field effect transistor of claim 10, wherein the first semiconductor layer comprises another metal oxynitride different from the metal oxynitride of the second semiconductor layer or another metal oxide Things. The heterojunction field effect transistor according to claim 11, wherein the second semiconductor layer comprises a material selected from the group consisting of zinc oxynitride rich in oxygen, zinc oxide, tin oxynitride, indium oxynitride, and dioxide. a group of tin, and combinations thereof. The heterojunction field effect transistor of claim 12, wherein the first semiconductor layer comprises a plurality of layers. The heterojunction field effect transistor of claim 13, wherein the first semiconductor layers have different Fermi energy levels. Such as the heterojunction field effect transistor described in claim 1 of the patent scope, The second semiconductor layer includes a p-type metal oxide, a p-type metal oxynitride, or a low work function metal oxide conductor. The heterojunction field effect transistor of claim 15, wherein the second semiconductor layer comprises tin oxide. The heterojunction field effect transistor of claim 16, wherein the first semiconductor layer comprises a plurality of layers. The heterojunction field effect transistor of claim 17, wherein the first semiconductor layers have different Fermi energy levels. The heterojunction field effect transistor of claim 18, wherein the first semiconductor layers comprise a plurality of metal oxynitrides.