CN114709254B - High-voltage parallel diode structure with composite buried layer and preparation method thereof - Google Patents
High-voltage parallel diode structure with composite buried layer and preparation method thereof Download PDFInfo
- Publication number
- CN114709254B CN114709254B CN202210337815.3A CN202210337815A CN114709254B CN 114709254 B CN114709254 B CN 114709254B CN 202210337815 A CN202210337815 A CN 202210337815A CN 114709254 B CN114709254 B CN 114709254B
- Authority
- CN
- China
- Prior art keywords
- region
- active
- layer
- regions
- active region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000002131 composite material Substances 0.000 title claims abstract description 11
- 238000002360 preparation method Methods 0.000 title description 12
- 239000000758 substrate Substances 0.000 claims abstract description 24
- 238000009792 diffusion process Methods 0.000 claims description 82
- 238000002347 injection Methods 0.000 claims description 71
- 239000007924 injection Substances 0.000 claims description 71
- 229910052751 metal Inorganic materials 0.000 claims description 43
- 239000002184 metal Substances 0.000 claims description 43
- 230000003647 oxidation Effects 0.000 claims description 17
- 238000007254 oxidation reaction Methods 0.000 claims description 17
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 15
- 230000001360 synchronised effect Effects 0.000 claims description 14
- 229920005591 polysilicon Polymers 0.000 claims description 13
- 238000001259 photo etching Methods 0.000 claims description 12
- 238000012545 processing Methods 0.000 claims description 12
- 229910052787 antimony Inorganic materials 0.000 claims description 11
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 claims description 11
- 238000000137 annealing Methods 0.000 claims description 8
- 239000012535 impurity Substances 0.000 claims description 8
- 238000002955 isolation Methods 0.000 claims description 7
- 229910052785 arsenic Inorganic materials 0.000 claims description 6
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims description 6
- 238000000034 method Methods 0.000 claims description 6
- 238000000151 deposition Methods 0.000 claims description 4
- 238000005530 etching Methods 0.000 claims description 4
- 238000004519 manufacturing process Methods 0.000 claims description 4
- 150000001875 compounds Chemical class 0.000 claims 1
- 230000003071 parasitic effect Effects 0.000 abstract description 16
- 230000015556 catabolic process Effects 0.000 abstract description 12
- 230000000694 effects Effects 0.000 abstract description 7
- 238000002513 implantation Methods 0.000 description 6
- 239000004065 semiconductor Substances 0.000 description 6
- 230000003321 amplification Effects 0.000 description 5
- 238000003199 nucleic acid amplification method Methods 0.000 description 5
- 238000013461 design Methods 0.000 description 3
- 238000002474 experimental method Methods 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000007943 implant Substances 0.000 description 2
- 238000011160 research Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/0814—Diodes only
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
- H01L29/0623—Buried supplementary region, e.g. buried guard ring
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
Abstract
The invention relates to a high-voltage parallel diode structure with a composite buried layer, which comprises a P-type substrate, wherein a P-type epitaxial layer is arranged above the P-type substrate, a first N-type buried layer and a second N-type buried layer are sequentially arranged in the P-type substrate from top to bottom, and the upper part of the first N-type buried layer is positioned in the P-type epitaxial layer; in the P type epitaxial layer, a plurality of active areas and field regions are arranged at intervals and are positioned above the first N type buried layer. The invention can realize high reverse breakdown voltage and has small parasitic PNP effect to the ground.
Description
Technical Field
The invention relates to the technical field of semiconductor manufacturing, in particular to a high-voltage parallel diode structure with a composite buried layer and a preparation method thereof.
Background
With the rapid development of power supply technologies such as AC-DC and DC-DC, the use occasions of high-voltage diodes are more and more. The high reverse voltage resistance and the good thermal stability of the high-voltage power supply are key technologies of high-voltage integrated circuits and power integrated circuits, and the high-voltage power supply is widely applied to various power supply circuits, synchronous control circuits, interface bus control systems and the like. Therefore, the structure of the high voltage diode is always the focus and hot spot of research of all the major semiconductor manufacturers and scientific research institutes.
As is well known, in a semiconductor integrated circuit structure, devices such as a diode and other MOS transistors are integrated on the same epitaxial layer or substrate material, and these devices are generally isolated from each other by a P-type ground ring. Therefore, the PN junction of the diode and its surrounding P-type or N-type layer form a parasitic PNP or NPN transistor. The parasitic PNP and NPN tubes can cause that a large part of the current which should originally flow through the diode is shunted to other branches by the parasitic tubes, and only a small part of the current can pass through the diode. As a result, the circuit performance may deviate from the design value, and the circuit may even fail to function. In order to reduce the parasitic effect of the diode on a P-type ground ring and the like, in practical use, an NPN tube with a short-circuited collector and base is generally used instead of the diode. The collector and base of the NPN tube are short-circuited to be used as the anode (P) of the diode, and the emitter is used as the cathode (N) of the diode. In the diode structure, the cathode N-terminal emitter is wrapped by the base and the collector which are used as anodes, so that when the diode is conducted in the forward direction, the diode cannot form a parasitic tube with a surrounding P-type ground ring or other devices. Therefore, when the diode with the structure is conducted, current is basically not shunted, and the performance is good. However, since the cathode N-terminal emitter of this diode is wrapped inside the anode P-terminal, the concentration of the emitter cannot be made very low, and therefore the reverse breakdown voltage of this diode cannot be made high, up to about 40V. However, in the actual power supply and synchronous rectification circuit, a diode with reverse withstand voltage of 100 to 200V is often needed to prevent reverse bias, and such a high-voltage diode cannot be made into an NPN tube structure with a short-circuited collector and base, so that the shunt to the P-type ground is large; meanwhile, because the diode structure is only a pure diode structure, under the condition of forward conduction and high-current use, the forward voltage drop of the diode structure is also large, so that the power loss is increased, and the energy is wasted. Therefore, how to realize the diode with high reverse voltage resistance, and simultaneously, the current of the diode is enabled to be extremely small, and the forward voltage drop is not too large when the diode is used with large forward current, which is a technical problem to be solved urgently.
Disclosure of Invention
The invention aims to provide a high-voltage parallel diode structure with a composite buried layer and a preparation method thereof, which can realize high reverse breakdown voltage and have small parasitic PNP effect on the ground.
Based on the same inventive concept, the invention has two independent technical schemes:
1. a high-voltage parallel diode structure with a composite buried layer comprises a P-type substrate, wherein a P-type epitaxial layer is arranged above the P-type substrate, a first N-type buried layer and a second N-type buried layer are sequentially arranged in the P-type substrate from top to bottom, and the upper part of the first N-type buried layer is positioned in the P-type epitaxial layer;
in the P type epitaxial layer, a plurality of active areas and field regions are arranged at intervals and are positioned above the first N type buried layer.
Further, the second N-type buried layer is an N-type antimony buried layer.
Further, the P-type epitaxial layer is provided with 9 active areas, 9 active areas are arranged at intervals, the first to ninth active areas are sequentially arranged from left to right, a field area is arranged between every two adjacent active areas, and a field oxide layer is arranged above the field area.
Furthermore, a P + injection diffusion region, a P well and a deep P well region are arranged at the first, third, fifth, seventh and ninth active regions of the P-type epitaxial layer, and the P + injection diffusion region, the P well and the deep P well region are sequentially arranged from top to bottom.
And N + injection diffusion regions, N wells and deep N well regions are arranged at the second, fourth, sixth and eighth active region positions of the P-type epitaxial layer, and are sequentially arranged from top to bottom.
Further, an outer oxidation layer is arranged above the P + injection diffusion area and the N + injection diffusion area, contact through holes are formed in the outer oxidation layer, contact through holes are formed in the positions, corresponding to the P + injection diffusion area and the N + injection diffusion area, above the P + injection diffusion area and the N + injection diffusion area, metal wiring penetrates through the contact through holes, the bottom end of the metal wiring is connected with the P + injection diffusion area or the N + injection diffusion area, and the top end of the metal wiring is used as a lead end of the high-voltage parallel diode structure.
Furthermore, the P + injection diffusion region metal wiring lead terminals of the first active region and the ninth active region are used as lead-out terminals of the high-voltage parallel diode isolation ground terminal;
the N + injection diffusion region metal wiring lead terminals of the second active region and the eighth active region are used as lead terminals of the diode cathode in the high-voltage parallel diode;
the P + injection diffusion region metal wiring lead terminals of the third active region and the seventh active region are used as leading-out terminals of PNP tube collecting electrodes in the high-voltage parallel diode;
the N + injection diffusion region metal wiring lead terminals of the fourth active region and the sixth active region are used as lead-out terminals of PNP tube base electrodes in the high-voltage parallel diode;
the lead end of the collector of the PNP tube in the high-voltage parallel diode is connected with the lead end of the base of the PNP tube in the high-voltage parallel diode, and the lead end of the base of the PNP tube in the high-voltage parallel diode is connected with the lead end of the cathode of the diode in the high-voltage parallel diode to serve as the cathode leading-out end of the whole high-voltage parallel diode.
And the P + of the fifth active region is injected into the metal wiring lead terminal of the diffusion region and serves as an anode lead-out terminal of the whole high-voltage parallel diode.
Further, above the field oxide layer between the first and second active areas, above the field oxide layer between the fourth and fifth active areas, above the field oxide layer between the fifth and sixth active areas, above the field oxide layer between the eighth and ninth active areas, all provided with a polysilicon layer, which is located in the outer oxide layer.
2. A preparation method of the high-voltage parallel diode structure with the composite buried layer,
photoetching and etching a buried layer window on the upper part of a P-type substrate, and in the buried layer window, firstly injecting and annealing N-type antimony impurities, and then injecting and annealing N-type arsenic impurities to form a first N-type buried layer and a second N-type buried layer;
growing a P-type epitaxial layer above a P-type substrate, and photoetching 9 active regions on the upper part of the P-type epitaxial layer, wherein the 9 active regions are arranged at intervals and are a first active region, a second active region and a ninth active region in sequence from left to right; a field region is arranged between every two active regions, and a field oxide layer is grown on the upper portion of each field region.
Further, a P + injection diffusion region, a P well and a deep P well region are formed below the first, third, fifth, seventh and ninth active regions, the P + injection diffusion region, the P well and the deep P well region are sequentially arranged from top to bottom, the synchronous processing operation of the plurality of P + injection diffusion regions is completed, the synchronous processing operation of the plurality of P wells is completed, and the synchronous processing operation of the plurality of deep P well regions is completed;
and N + injection diffusion regions, N wells and deep N well regions are formed below the second active region, the fourth active region, the sixth active region and the eighth active region, the N + injection diffusion regions, the N wells and the deep N well regions are sequentially arranged from top to bottom, a plurality of N + injection diffusion regions are synchronously processed, a plurality of N wells are synchronously processed, and a plurality of deep N well regions are synchronously processed.
Further, the method also comprises the following steps:
polysilicon layers are formed above field oxide layers between the first active area and the second active area, above field oxide layers between the fourth active area and the fifth active area, above field oxide layers between the fifth active area and the sixth active area, and above field oxide layers between the eighth active area and the ninth active area, and the polysilicon layers are processed synchronously;
an outer oxidation layer is formed above the P-type epitaxial layer, the outer oxidation layer is positioned at the middle part of each active area, and meanwhile, the outer oxidation layer is removed by photoetching to form a plurality of contact through holes; and depositing metal wiring in each contact through hole, wherein the bottom end of the metal wiring is connected with the active region, and the top end of the metal wiring is used as a lead terminal of the high-voltage parallel diode.
The invention has the following beneficial effects:
the invention comprises a P-type substrate, a P-type epitaxial layer is arranged above the P-type substrate, and in the P-type substrate, a first N-type buried layer and a second N-type buried layer are sequentially arranged from top to bottom, wherein the upper part of the first N-type buried layer is positioned in the P-type epitaxial layer; in the P type epitaxial layer, a plurality of active areas and field regions are arranged at intervals and are positioned above the first N type buried layer. According to the invention, by additionally arranging the second N-type buried layer, the concentration and the width of the base region of the ground parasitic PNP tube can be effectively increased when the high-voltage parallel diode is conducted in the forward direction, so that the amplification factor of the ground parasitic PNP tube is reduced, the shunt to the ground when the diode is conducted in the forward direction is reduced, the high reverse breakdown voltage can be realized, and the ground parasitic PNP effect is small. Experiments prove that under the same diode area and forward conducting current, the high-voltage parallel diode shunts the current of the P-type ground, which is about 30 percent smaller than that of a conventional high-voltage diode, so that the current requirement of an output end on a power supply end can be effectively reduced, namely the diode area can be effectively reduced, the whole chip area is reduced, and the design cost is reduced. The second N-type buried layer is an N-type antimony buried layer, so that high reverse breakdown voltage can be further effectively guaranteed, and the parasitic PNP effect to the ground can be small.
The P-type epitaxial layer is provided with 9 active regions, the 9 active regions are arranged at intervals and sequentially comprise a first active region, a second active region, a third active region, a fourth active region, a fifth active region, a sixth active region, a field oxide layer and a fifth active region from left to right, a field oxide layer is arranged between every two adjacent active regions, and the field oxide layer is arranged above the field oxide layer. The first, third, fifth, seventh and ninth active regions of the P-type epitaxial layer are respectively provided with a P + injection diffusion region, a P well and a deep P well region, and the P + injection diffusion region, the P well and the deep P well region are sequentially arranged from top to bottom; and N + injection diffusion regions, N wells and deep N well regions are arranged at the second, fourth, sixth and eighth active region positions of the P-type epitaxial layer, and are sequentially arranged from top to bottom. An outer oxidation layer is arranged above the P + injection diffusion region and the N + injection diffusion region, contact through holes are formed in the outer oxidation layer, the contact through holes are formed in the positions, corresponding to the P + injection diffusion region and the N + injection diffusion region, above the N + injection diffusion region and above the P + injection diffusion region, metal wiring penetrates through the contact through holes, the bottom end of the metal wiring is connected with the P + injection diffusion region or the N + injection diffusion region, and the top end of the metal wiring is used as a lead end of a high-voltage parallel diode structure. P + injection diffusion region metal wiring lead terminals of the first and ninth active regions are used as lead-out terminals of the isolation ground terminal of the high-voltage parallel diode; the N + injection diffusion region metal wiring lead terminals of the second active region and the eighth active region are used as lead terminals of the diode cathode in the high-voltage parallel diode; p + injection diffusion region metal wiring lead terminals of the third and seventh active regions are used as leading-out terminals of PNP tube collectors in the high-voltage parallel diode; the N + injection diffusion region metal wiring lead terminals of the fourth active region and the sixth active region are used as lead-out terminals of PNP tube base electrodes in the high-voltage parallel diode; the lead end of the collector of the PNP tube in the high-voltage parallel diode is connected with the lead end of the base of the PNP tube in the high-voltage parallel diode, and the lead end of the base of the PNP tube in the high-voltage parallel diode is connected with the lead end of the cathode of the diode in the high-voltage parallel diode to serve as the cathode leading-out end of the whole high-voltage parallel diode. And the P + of the fifth active region is injected into the metal wiring lead terminal of the diffusion region and serves as an anode lead-out terminal of the whole high-voltage parallel diode. The invention effectively reduces the forward conduction voltage drop under the large current through the structural design of the high-voltage parallel diode. Experiments prove that when the high-voltage parallel diode is used by conducting large current in the forward direction, the forward voltage drop of the high-voltage parallel diode is about 20% less than that of a conventional high-voltage diode, so that the power loss of the diode in the voltage transmission process is greatly reduced. Therefore, the high-voltage parallel diode has obvious effects on improving the output efficiency and reducing the power consumption.
The preparation method comprises the steps of photoetching and etching a buried layer window on the upper part of a P-type substrate, and in the buried layer window, firstly injecting and annealing N-type antimony impurities, and then injecting and annealing N-type arsenic impurities to form a first N-type buried layer and a second N-type buried layer; growing a P-type epitaxial layer above a P-type substrate, and photoetching 9 active regions on the upper part of the P-type epitaxial layer, wherein the 9 active regions are arranged at intervals and are sequentially a first active region to a ninth active region from left to right; a field region is arranged between every two active regions, and a field oxide layer is grown on the upper portion of each field region. A P + injection diffusion region, a P well and a deep P well region are formed below the first active region, the third active region, the fifth active region, the seventh active region and the ninth active region respectively, the P + injection diffusion region, the P well and the deep P well region are sequentially arranged from top to bottom, a plurality of P + injection diffusion regions are synchronously processed, a plurality of P wells are synchronously processed, and a plurality of deep P well regions are synchronously processed; and N + injection diffusion regions, N wells and deep N well regions are formed below the second active region, the fourth active region, the sixth active region and the eighth active region, the N + injection diffusion regions, the N wells and the deep N well regions are sequentially arranged from top to bottom, a plurality of N + injection diffusion regions are synchronously processed, a plurality of N wells are synchronously processed, and a plurality of deep N well regions are synchronously processed. The preparation method can effectively improve the preparation efficiency, does not need to change the existing production equipment, and is favorable for saving the cost.
The preparation method of the invention, on the field oxide of field between the first and second active areas, on the field oxide of field between the fourth and fifth active areas, on the field oxide of field between the fifth and sixth active areas, on the field oxide of field between the eighth and ninth active areas, there are polysilicon layers formed, the said polysilicon layer is processed synchronously; an outer oxidation layer is formed above the P-type epitaxial layer, the outer oxidation layer is positioned at the middle part of each active area, and meanwhile, the outer oxidation layer is removed by photoetching to form a plurality of contact through holes; and depositing metal wiring in each contact through hole, wherein the bottom end of the metal wiring is connected with the active region, and the top end of the metal wiring is used as a lead terminal of the high-voltage parallel diode. The preparation method further ensures that the preparation efficiency is effectively improved.
Drawings
FIG. 1 is a longitudinal structure of a high voltage parallel diode fabricated according to the present invention;
wherein: 1. P-type substrate, 2. Second N-type buried layer, 3. First N-type buried layer, 4. P-type epitaxial layer, 5. First active region, 6. Second active region, 7. Third active region, 8. Fourth active region, 9. Fifth active region, 10. Sixth active region, 11. Seventh active region, 12. Eighth active region, 13. Ninth active region, 14. Field oxide layer, 15. Deep P well region 16.P well, 17.P + implant diffusion region, 18. Deep N well region, 19.N well, 20.N + implant diffusion region, 21. Polysilicon layer, 22. External oxide layer, 23. Metal wiring, 100. Diode anode, 200. Diode cathode, 300.Pnp transistor emitter, 400.Pnp transistor base, 400.Pnp transistor collector, 600. Isolated ground terminal.
Fig. 2 is an equivalent circuit diagram of a vertical structure of a high-voltage parallel diode manufactured by the invention.
Detailed Description
The present invention is described in detail with reference to the embodiments shown in the drawings, but it should be understood that these embodiments are not intended to limit the present invention, and those skilled in the art should understand that functional, methodological, or structural equivalents or substitutions made by these embodiments are within the scope of the present invention.
The first embodiment is as follows:
high-voltage parallel diode structure with composite buried layer
As shown in fig. 1, a P-type epitaxial layer 4 is disposed above a P-type substrate 1, and a high voltage parallel diode is formed in the P-type epitaxial layer. A second N-type buried layer 2 and a first N-type buried layer 3 added in the invention are sequentially arranged between a P-type substrate 1 and a P-type epitaxial layer 4. The second N-type buried layer is an N-type antimony buried layer, and the first N-type buried layer 3 is a conventional N-type arsenic buried layer.
On the surface of the P-type epitaxial layer, a first active region 5, a second active region 6, a third active region 7, a fourth active region 8, a fifth active region 9, a sixth active region 10, a seventh active region 11, an eighth active region 12 and a ninth active region 13 are sequentially arranged from left to right. Two sides of each active area are provided with field areas, and field oxide layers 14 with the thickness of 3000-5500 angstroms are arranged on the field areas and used for isolating the active areas.
As shown in fig. 1 and fig. 2, in the present embodiment, in the first active region 5 and the ninth active region 13, a deep P well region 15 is provided as an isolation ground 600 for the high-voltage parallel diode and other devices. Inside the deep P well 15, a P + implantation diffusion region 17 and a P well 16 are disposed to increase the doping concentration there, and a good ohmic contact is formed through the contact via and the metal wiring as the leading-out terminal of the isolated ground terminal 600. At both the second active region 6 and the eighth active region 12, a deep N-well region 18 is provided. The deep N well region 18 diffuses 4-6 microns downwards from the P-type epitaxial surface, is communicated with the first N-type buried layer 3 and serves as a cathode 200 of a diode part in the high-voltage parallel diode. Inside the deep N well 18, an N + implantation diffusion region 20 and an N well 19 are provided to increase the doping concentration there, and a good ohmic contact is formed through a contact via and a metal wiring as a leading-out terminal of the cathode of the diode portion in the high voltage parallel diode.
In this embodiment, the third active region 7 and the seventh active region 11 are both provided with deep P well regions 15 as collectors 500 of PNP transistors in high voltage parallel diodes. Inside the deep P well 15, a P + implantation diffusion region 17 and a P well 16 are provided to increase the doping concentration there, and a good ohmic contact is formed through a contact via and a metal wiring as the leading-out terminal of the PNP transistor collector 500 in the high voltage parallel diode. At the fourth active region 8 and at the sixth active region 10, a deep N-well region 18 is provided. The deep N well region 18 diffuses 4-6 microns downwards from the P-type epitaxial surface, is communicated with the first N-type buried layer 3 and serves as a base 400 of a PNP tube in a high-voltage parallel diode. And an N + injection diffusion region 20 and an N well 19 are arranged in the deep N well 18 to increase the doping concentration of the deep N well, and a good ohmic contact is formed through a contact through hole and a metal wiring and is used as a leading-out terminal of a base electrode of a PNP (plug-and-play) tube in a high-voltage parallel diode.
In this embodiment, a deep P well region 15 is disposed in the fifth active region 9, and the deep P well region 15 is used as an emitter 300 of the PNP transistor in the high-voltage parallel diode, and also as an anode 100 of the diode in the high-voltage parallel diode, that is, an anode of the entire high-voltage parallel diode. Inside the deep P well 15, a P + implantation diffusion region 17 and a P well 16 are provided to increase the doping concentration there, and a good ohmic contact is formed through a contact via and a metal wiring as a leading-out terminal of the high voltage parallel diode anode 100. The anode deep P well 15, the base 400 of the PNP tube in the high-voltage parallel diode, the deep N well region 18 and the second N-type buried layer 3 jointly realize the high reverse breakdown voltage of the parallel diode, and the value of the high reverse breakdown voltage can reach 100-280V.
As shown in fig. 1 and fig. 2, in this embodiment, the metal wiring terminals of the third active region 7, the fourth active region 8, the sixth active region 10, and the seventh active region 11 are connected to serve as the collector 500 and base 400 shorting terminals of the PNP transistor in the high voltage parallel diode. The collector 500 of the PNP transistor is connected to the metal wiring terminals of the second active region 6 and the eighth active region 12 as the cathode terminals of the whole high-voltage parallel diode.
In this embodiment, the polysilicon layer 21 is disposed on the field oxide layer 14 between the first active region 5 and the second active region 6, and on the field oxide layer 14 between the eighth active region 12 and the ninth active region 13, and the thickness of the polysilicon layer is 2000 to 3000 angstroms, so as to increase the breakdown voltage from the high voltage parallel diode to the isolation ground. A polysilicon layer 21 with a thickness of 2000-3000 angstroms is also provided on the field oxide layer 14 between the fourth active region 8 and the fifth active region 9 and on the field oxide layer 14 between the fifth active region 9 and the sixth active region 10, so as to improve the reverse breakdown voltage from the cathode to the anode of the high voltage parallel diode. And an outer oxide layer 22 covering the whole wafer surface is arranged above all the field oxide layers and the active region, the thickness is 6000-9000 angstroms, the outer oxide layer above the field oxide layers is thin, and the outer oxide layer above the active region is thick. The external oxide layer 22 is removed at the corresponding positions of the P + implantation diffusion regions 17 of the first active region 5, the third active region 7, the fifth active region 9, the seventh active region 11 and the ninth active region 13 and the N + implantation diffusion regions 20 of the second active region 6, the fourth active region 8, the sixth active region 10 and the eighth active region 12 to form a contact through hole reaching the silicon surface; and a metal wiring 23 is arranged at the position of the contact through hole and is in contact with the silicon surface, and the anode, the cathode and the isolation ground end of the high-voltage parallel diode are respectively led out to form a complete high-voltage parallel diode structure.
The conventional high-voltage diode cannot be made into an NPN (negative-positive-negative) tube structure with a short-circuited base and emitter in order to realize reverse high-voltage breakdown, so that the current shunt to the ground is large when the conventional high-voltage diode is conducted in the forward direction. In the high-voltage parallel diode adopting the structure of the invention, an N-type antimony buried layer is added in addition to a conventional N-type arsenic buried layer and is arranged in front of all the working procedures, so that the concentration of the N-type antimony buried layer can be very concentrated, and the performance of other devices is not influenced. As is known, when a diode is conducted in the forward direction, the current shunting to the ground is caused by the conduction of a parasitic PNP transistor of the diode to the ground, and the amplification factor of the parasitic PNP transistor directly determines the magnitude of the current shunting to the ground. The larger the amplification factor is, the larger the shunt to the ground when the diode is in forward conduction is, and the smaller the shunt is. The amplification factor of the parasitic PNP transistor is mainly determined by the concentration and width of the base region (i.e., the N-type buried layer). In the high-voltage parallel diode with the structure, because a layer of thick N-type antimony buried layer is added, the concentration of the base region of the parasitic PNP tube is concentrated, and the width of the base region is widened, so that the amplification factor of the parasitic PNP tube is reduced, and the shunt to the ground when the diode is conducted in the forward direction is reduced. In addition, the high-voltage parallel diode with the structure of the invention has an advantage compared with the conventional high-voltage diode. The conventional high-voltage diode is formed by splicing an anode semiconductor region and a cathode semiconductor region, the voltage drop during forward conduction is the product of the sum of the body resistances of the two semiconductors and the product of the product multiplied by forward current, and the result is that when certain forward current flows through the diode, the generated forward voltage drop is larger, so that the power consumption consumed on the diode body is larger, and more energy is wasted. In the high-voltage parallel diode, a PNP tube with a short-circuited collector and base is connected with a conventional diode in parallel. The emitter of the PNP tube is reused as the anode of the conventional diode, namely as the anode of the whole high-voltage parallel diode. The collector and base short-circuit terminal of PNP tube are connected with cathode of conventional diode, and used as cathode of whole high-voltage parallel diode. The effect of this is that when the high voltage parallel diode is conducted in the forward direction and a certain forward current flows, the forward current mainly flows through the PNP part of the high voltage parallel diode, and the current flowing through the diode part is very small because the PNP part has an amplifying effect, and the voltage drop between the emitter and the collector generated when the current flows through the two ends of the emitter and the collector is very small. Therefore, the forward current of the same diode flows, the forward conduction voltage drop of the high-voltage parallel diode adopting the structure of the invention is definitely smaller than that of the conventional high-voltage diode, and the power loss on the body when the diode is conducted can be effectively reduced.
Through experiments, a high-voltage diode with a conventional structure and a high-voltage parallel diode of the invention are compared on the same process platform. The same diode forward current is fed at the same diode area and reverse breakdown voltage and the high voltage parallel diode of the present invention is found to have a ground current draw about 30% less than that of the conventional structure. The specific data are as follows: the area of each diode is 425 square microns, the reverse breakdown voltage is 160 volts, and the forward inflow current of each diode is 1 ampere. The current flowing out of a diode is 0.564 ampere, the shunt current to the ground is 0.436 ampere, and the shunt proportion is 43.6 percent by adopting a conventional structure; by adopting the high-voltage parallel diode structure, the current flowing out of the diode is 0.883 ampere, the shunt current to the ground is 0.117 ampere, and the shunt proportion is 11.7%. Therefore, under the same current at the diode outlet end, the current at the current inlet end required by adopting the high-voltage parallel diode structure of the invention is about 30 percent less than that of the conventional structure, namely the diode area can be correspondingly reduced by about 30 percent. In addition, the forward conduction voltage drop of the high-voltage parallel diode is about 20 percent smaller than that of the conventional structure when the same diode area flows through the same diode current. The specific data are as follows: the area of each diode is 425 square microns, and the current flowing through each diode is 0.5 ampere. The conventional structure is adopted, and the forward conduction voltage drop of a diode is 0.96 volt; by adopting the high-voltage parallel diode structure, the forward conduction voltage drop of the diode is 0.77 volt. Therefore, under the same diode current, the power loss of the high-voltage parallel diode structure is about 20% less than that of the diode with the conventional structure.
Example two:
preparation method of high-voltage parallel diode structure with composite buried layer
Photoetching and etching a buried layer window on the upper part of a P-type substrate, and in the buried layer window, firstly injecting and annealing N-type antimony impurities, and then injecting and annealing N-type arsenic impurities to form a first N-type buried layer 2 and a second N-type buried layer 3;
growing a P-type epitaxial layer 4 above a P-type substrate, and photoetching 9 active regions on the upper part of the P-type epitaxial layer, wherein the 9 active regions are arranged at intervals and are sequentially a first active region, a second active region and a ninth active region from left to right; a field region is arranged between every two active regions, and a field oxide layer is grown on the upper portion of each field region.
A P + injection diffusion region 17, a P well 16 and a deep P well region 15 are formed below the first, third, fifth, seventh and ninth active regions 5, 7, 9 and 11, the P + injection diffusion region 17, the P well 16 and the deep P well region 15 are sequentially arranged from top to bottom, the synchronous processing operation of the plurality of P + injection diffusion regions 17 is completed, the synchronous processing operation of the plurality of P wells 16 is completed, and the synchronous processing operation of the plurality of deep P well regions 15 is completed;
under the second, fourth, sixth and eighth active regions 6, 8, 10, 12, N + injection diffusion regions 20, N wells 19, deep N well regions 18 are formed, the N + injection diffusion regions 20, the N wells 19 and the deep N well regions 18 are sequentially arranged from top to bottom, the synchronous processing operation of the plurality of N + injection diffusion regions 20 is completed, the synchronous processing operation of the plurality of N wells 19 is completed, and the synchronous processing operation of the plurality of deep N well regions 18 is completed.
Further comprising the steps of:
a polysilicon layer 21 is formed above the field oxide layer of the field between the first active region 5 and the second active region 6, above the field oxide layer of the field between the fourth active region 8 and the fifth active region 9, above the field oxide layer of the field between the fifth active region 9 and the sixth active region 10, and above the field oxide layer of the field between the eighth active region 12 and the ninth active region 13, and the polysilicon layer is synchronously processed;
forming an outer oxidation layer 22 above the P-type epitaxial layer 4, and removing the outer oxidation layer 22 at the middle part of each active region by photoetching to form a plurality of contact through holes; and depositing a metal wiring 23 in each contact through hole, contacting with the P + injection diffusion region and the N + injection diffusion region, and leading the anode, the cathode and the isolation ground end of the high-voltage parallel diode to the surface respectively to form a complete high-voltage parallel diode structure.
The above-listed detailed description is only a specific description of a possible embodiment of the present invention, and they are not intended to limit the scope of the present invention, and equivalent embodiments or modifications made without departing from the technical spirit of the present invention should be included in the scope of the present invention.
It will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential attributes thereof. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein.
Claims (5)
1. The utility model provides a high-pressure diode structure that connects in parallel with compound buried layer, includes P type substrate, be equipped with P type epitaxial layer on the P type substrate, its characterized in that:
a first N-type buried layer and a second N-type buried layer are sequentially arranged in the P-type substrate from top to bottom, wherein the upper part of the first N-type buried layer is positioned in the P-type epitaxial layer;
a plurality of active regions and field regions are arranged in the P-type epitaxial layer at intervals, and the active regions and the field regions are positioned above the first N-type buried layer;
the second N-type buried layer is an N-type antimony buried layer;
the P-type epitaxial layer is provided with 9 active regions, the 9 active regions are arranged at intervals and are sequentially a first active region, a second active region, a third active region, a fourth active region, a fifth active region and a ninth active region from left to right, a field region is arranged between every two adjacent active regions, and a field oxide layer is arranged above the field regions;
the first, third, fifth, seventh and ninth active regions of the P-type epitaxial layer are respectively provided with a P + injection diffusion region, a P well and a deep P well region, and the P + injection diffusion region, the P well and the deep P well region are sequentially arranged from top to bottom;
the second, fourth, sixth and eighth active regions of the P-type epitaxial layer are respectively provided with an N + injection diffusion region, an N well and a deep N well region, and the N + injection diffusion region, the N well and the deep N well region are sequentially arranged from top to bottom;
an outer oxidation layer is arranged above the P + injection diffusion region and the N + injection diffusion region, a contact through hole is arranged in the outer oxidation layer, a contact through hole is arranged above each P + injection diffusion region and each N + injection diffusion region, a metal wiring penetrates through the contact through holes, the bottom end of the metal wiring is connected with the P + injection diffusion region or the N + injection diffusion region, and the top end of the metal wiring is used as a lead end of the high-voltage parallel diode structure;
the field oxide layer between the first and second active areas, the field oxide layer between the fourth and fifth active areas, the field oxide layer between the fifth and sixth active areas, the field oxide layer between the eighth and ninth active areas, all being equipped with the polycrystalline silicon layer, the polycrystalline silicon layer is located in the outer oxide layer.
2. The high voltage parallel diode structure with the buried composite layer of claim 1, wherein:
p + injection diffusion region metal wiring lead terminals of the first and ninth active regions are used as lead-out terminals of the isolation ground terminal of the high-voltage parallel diode;
the N + injection diffusion region metal wiring lead terminals of the second active region and the eighth active region are used as lead terminals of the diode cathode in the high-voltage parallel diode;
p + injection diffusion region metal wiring lead terminals of the third and seventh active regions are used as leading-out terminals of PNP tube collectors in the high-voltage parallel diode;
the N + injection diffusion region metal wiring lead terminals of the fourth active region and the sixth active region are used as lead-out terminals of PNP tube base electrodes in the high-voltage parallel diode;
the lead end of the collector of the PNP tube in the high-voltage parallel diode is connected with the lead end of the base of the PNP tube in the high-voltage parallel diode, and the lead end of the base of the PNP tube in the high-voltage parallel diode is connected with the lead end of the cathode of the diode in the high-voltage parallel diode to be used as the cathode leading-out end of the whole high-voltage parallel diode;
and the P + of the fifth active region is injected into the metal wiring lead terminal of the diffusion region and serves as an anode lead-out terminal of the whole high-voltage parallel diode.
3. A method for manufacturing a high-voltage parallel diode structure with a composite buried layer according to claim 1, wherein the method comprises the following steps:
photoetching and etching a buried layer window on the upper part of a P-type substrate, and in the buried layer window, firstly injecting and annealing N-type antimony impurities, and then injecting and annealing N-type arsenic impurities to form a first N-type buried layer and a second N-type buried layer;
growing a P-type epitaxial layer above a P-type substrate, and photoetching 9 active regions on the upper part of the P-type epitaxial layer, wherein the 9 active regions are arranged at intervals and are a first active region, a second active region and a ninth active region in sequence from left to right; a field region is arranged between every two active regions, and a field oxide layer is grown on the upper portion of each field region.
4. The production method according to claim 3, characterized in that: a P + injection diffusion region, a P well and a deep P well region are formed below the first active region, the third active region, the fifth active region, the seventh active region and the ninth active region respectively, the P + injection diffusion region, the P well and the deep P well region are sequentially arranged from top to bottom, a plurality of P + injection diffusion regions are synchronously processed, a plurality of P wells are synchronously processed, and a plurality of deep P well regions are synchronously processed;
and N + injection diffusion regions, N wells and deep N well regions are formed below the second active region, the fourth active region, the sixth active region and the eighth active region, the N + injection diffusion regions, the N wells and the deep N well regions are sequentially arranged from top to bottom, the synchronous processing operation of the plurality of N + injection diffusion regions is completed, the synchronous processing operation of the plurality of N wells is completed, and the synchronous processing operation of the plurality of deep N well regions is completed.
5. The method of claim 3, further comprising the steps of:
polysilicon layers are formed above field oxide layers between the first active area and the second active area, above field oxide layers between the fourth active area and the fifth active area, above field oxide layers between the fifth active area and the sixth active area, and above field oxide layers between the eighth active area and the ninth active area, and the polysilicon layers are processed synchronously;
an outer oxidation layer is formed above the P-type epitaxial layer, the outer oxidation layer is positioned at the middle part of each active area, and meanwhile, the outer oxidation layer is removed by photoetching to form a plurality of contact through holes; and depositing metal wiring in each contact through hole, wherein the bottom end of the metal wiring is connected with the active region, and the top end of the metal wiring is used as a lead terminal of the high-voltage parallel diode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210337815.3A CN114709254B (en) | 2022-04-01 | 2022-04-01 | High-voltage parallel diode structure with composite buried layer and preparation method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210337815.3A CN114709254B (en) | 2022-04-01 | 2022-04-01 | High-voltage parallel diode structure with composite buried layer and preparation method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN114709254A CN114709254A (en) | 2022-07-05 |
| CN114709254B true CN114709254B (en) | 2023-03-21 |
Family
ID=82172356
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210337815.3A Active CN114709254B (en) | 2022-04-01 | 2022-04-01 | High-voltage parallel diode structure with composite buried layer and preparation method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN114709254B (en) |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| IT1186490B (en) * | 1985-12-23 | 1987-11-26 | Sgs Microelettronica Spa | INTEGRATED SCHOTTKY DIODE |
| US7045830B1 (en) * | 2004-12-07 | 2006-05-16 | Fairchild Semiconductor Corporation | High-voltage diodes formed in advanced power integrated circuit devices |
| CN100524810C (en) * | 2006-10-23 | 2009-08-05 | 上海华虹Nec电子有限公司 | Horizontal PNP type audion and its making method |
| CN102130119B (en) * | 2010-01-18 | 2013-03-13 | 上海华虹Nec电子有限公司 | Diode and preparation method thereof |
| CN103456732B (en) * | 2012-05-30 | 2016-06-15 | 旺宏电子股份有限公司 | There is the Schottky diode strengthening breakdown voltage |
| CN209216985U (en) * | 2019-01-25 | 2019-08-06 | 无锡固电半导体股份有限公司 | High voltage Schottky diode |
-
2022
- 2022-04-01 CN CN202210337815.3A patent/CN114709254B/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| CN114709254A (en) | 2022-07-05 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN104576720B (en) | Semiconductor devices and inverse lead IGBT | |
| US9246410B2 (en) | Integrated power semiconductor component, production method and chopper circuit comprising integrated semiconductor component | |
| US8368167B1 (en) | Schottky diode with extended forward current capability | |
| US20160241232A1 (en) | Methods of Operating a Double-Base-Contact Bidirectional Bipolar Junction Transistor | |
| CN101599508B (en) | Semiconductor device | |
| CN113035841A (en) | Integrated chip with junction isolation structure and manufacturing method thereof | |
| CN113140566A (en) | Integrated chip with isolation structure and manufacturing method thereof | |
| CN101431073A (en) | Zener integrated circuit structure and manufacturing method thereof | |
| CN114709254B (en) | High-voltage parallel diode structure with composite buried layer and preparation method thereof | |
| CN212750894U (en) | Ultra-low voltage trigger device | |
| CN103579307A (en) | Novel diode component structure | |
| CN210092081U (en) | Constant current device | |
| CN102027594B (en) | Regenerative building block and diode bridge rectifier and methods | |
| CN114512477B (en) | Breakdown voltage adjustable SCR type ESD protection structure | |
| CN214848631U (en) | Low-voltage grid unidirectional silicon controlled electrostatic protection device | |
| JPH0654796B2 (en) | Composite semiconductor device | |
| CN111710674A (en) | Ultra-low voltage trigger device and manufacturing method thereof | |
| CN213026136U (en) | Semiconductor device with a plurality of transistors | |
| CN213988893U (en) | FRD chip | |
| CN112635546B (en) | High-reliability NMOS array structure and preparation method thereof | |
| CN216818345U (en) | NLDMOS device integrated with overvoltage protection diode | |
| CN215815878U (en) | Integrated chip with isolation structure | |
| CN215220713U (en) | Integrated chip with junction isolation structure | |
| CN212485325U (en) | Asymmetric grid bidirectional thyristor electrostatic protection device | |
| CN109216435A (en) | Inverse conductivity type insulated gate bipolar transistor and preparation method thereof is isolated in a kind of collector |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |