CN212750894U - Ultra-low voltage trigger device - Google Patents

Abstract

The ultra-low voltage trigger device comprises a back metal electrode, a P + substrate layer, an N-type epitaxial layer, an insulating dielectric layer and a front metal layer which are sequentially arranged from bottom to top, wherein a P + isolation layer, N + polycrystalline silicon and a P-type base region are sequentially arranged from one side to the other side of the end face of the N-type epitaxial layer; the P + isolation layer penetrates to the P + substrate layer; and a P + source region and an N + source region are arranged in the N + polysilicon region and the P type base region. The manufacturing method of the ultra-low voltage trigger device comprises the following steps: depositing an N-type epitaxial layer; forming a P + isolation layer by high-temperature propulsion; depositing N + polysilicon to expose the N-type epitaxial layer; forming a P-type base region by pushing; forming a P + source region in the N + polysilicon and P type base region, and then photoetching and injecting high-concentration N type impurities to form an N + source region; depositing an insulating medium layer to complete a front metal layer; and depositing a back metal electrode. The invention effectively reduces the cost and the trigger voltage, and has the capabilities of ultra-low trigger voltage and strong discharge charge.

Description

Ultra-low voltage trigger device

Technical Field

The utility model belongs to the technical field of electronic science and technology, concretely relates to ultra low voltage trigger device and manufacturing method thereof.

Background

The electrostatic discharge (ESD) phenomenon is widely present in daily environments, and is a real fatal threat to precise integrated circuits, and is one of the important causes for damage and even failure of integrated circuit products. Integrated circuit products are highly susceptible to ESD during their manufacture, fabrication, assembly, and operation, resulting in internal damage and reduced reliability. And the application environment of the device also has corresponding requirements on parameters such as capacitance, breakdown voltage, clamping characteristics and the like.

Nowadays, an era of combining artificial intelligence with the internet of things is coming formally, and smart homes also play an increasingly important role in life. With the continuous development of the technology, chips required by the internet of things are further developed towards high integration level and lower power consumption, which requires that the line width of the manufacturing process is further reduced. The narrow line width and low power consumption also make the chip more vulnerable and sensitive when subjected to the electrostatic discharge effect, so that the electrostatic discharge test is more and more rigorous. As the power consumption is further reduced, the power supply voltage is further reduced, and as the low trigger voltage, the ESD device with strong discharge capability is also required.

According to the low operating voltage characteristic of the low power consumption system. The requirements of low-voltage ESD protection devices with voltage levels of 1.2V, 1.8V, 2V, 2.5V, 2.8V, 3.3V and the like exist. In most existing ESD protection devices of low-voltage systems at the present stage, breakdown voltage is between 5V and 10V, and low-voltage ESD protection is not realized in the real sense. Devices commonly used for ESD protection include diodes, GGNMOS (gate grounded NMOS), BJT (triode), SCR (silicon controlled rectifier), etc., and low-voltage ESD protection devices often use SCR to obtain strong discharge capability. However, as the size of the ESD device is more and more required, it is more and more important to increase the ESD discharging capability in a certain size.

SUMMERY OF THE UTILITY MODEL

The utility model aims at providing a trigger device and manufacturing method are triggered to the ultralow pressure of low trigger voltage, high bleeder current ability to the not enough in the current vertical SCR product structure. The fold-back voltage of the SCR is reduced by injecting a trigger current into the SCR base region. The trigger current is provided by the forward biased PN strings, and the trigger voltage can be adjusted to be high or low by adjusting the number of the forward biased PN strings. And the current of the diode path is limited by the integrated polysilicon resistor, so that the phenomenon that the trigger area is burnt out due to overcurrent and loses the low trigger characteristic is prevented.

The ultra-low voltage trigger device comprises a back metal electrode, wherein a P + substrate layer is arranged on the back metal electrode, an N-type epitaxial layer is deposited on the P + substrate layer, the end face of the N-type epitaxial layer is sequentially pushed at high temperature from one side to the other side to form a P + isolation layer, N + polycrystalline silicon is deposited, and a P-type base region is formed by pushing a knot; the P + isolation layer penetrates to the P + substrate layer; p + source regions are arranged in the two regions of the N + polycrystalline silicon and the P type base region, and then N type impurities are injected between the P + isolation layer and the N + polycrystalline silicon and at the sides of the N + source regions in the N + polycrystalline silicon and the P type base region to form the N + source regions; and depositing an insulating medium layer on the N-type epitaxial layer, and etching the front metal layer on the insulating medium layer.

Furthermore, a thermal oxidation layer is arranged between the N + polysilicon and the N type epitaxial layer.

Furthermore, the insulating medium layer is positioned between the N-type epitaxial layer and the front metal layer.

Further, the P + substrate layer and the N-type epitaxial layer form D1, the P + source region and the N + source region form D2, and D1 and D2 form a diode string.

Furthermore, a PNPN type thyristor is formed by the P + substrate layer, the N type epitaxial layer, the P type base region, the N + source region between the P + isolation layer and the N + polysilicon.

The utility model has the advantages as follows:

the forward biased diode string with the small current triggering function utilizes the diodes and the polysilicon diodes formed in four corner regions, effectively improves the utilization rate of the chip and reduces the chip cost.

And secondly, forming effective electrical isolation after the N + polysilicon is positioned on the thermal oxide layer grown after pit etching, and performing CMP planarization treatment after the deposition of the N + polysilicon is finished. The formation of structures in the polysilicon is compatible with subsequent conventional processes. And the current of the trigger area is introduced into the P-type base area from the first layer, and the trigger current flows into the base area trigger area through the shortest path. A series of ultra-low trigger voltage devices were fabricated with minimal area loss.

Thirdly, the utility model discloses a forward biased diode cluster can reduce SCR's flyback current to 1.5V, through adjusting the regional forward biased diode figure of polycrystalline silicon, can realize that trigger voltage is voltage such as 1.4V, 2.1V, 2.8V, 3.5V. The ultra-low voltage trigger device can realize the voltage levels of 1.2V, 1.8V, 2V, 2.5V, 2.8V, 3.3V and the like.

Drawings

Fig. 1 is a layout schematic diagram of the low-voltage ESD protection device based on the vertical SCR structure of the present invention.

Fig. 2 is an equivalent circuit diagram of the low-voltage ESD protection device based on the vertical SCR structure of the present invention.

Fig. 3 is a schematic diagram of a-a' cross-sectional position of the low-voltage ESD protection device based on the vertical SCR structure of the present invention.

Fig. 4 is a schematic diagram of a longitudinal structure of a section a-a' of the low-voltage ESD protection device based on the longitudinal SCR structure of the present invention.

Fig. 5 is another embodiment of the low-voltage ESD protection device based on the vertical SCR structure of the present invention.

FIG. 6 shows the first process step of the A-A' cross section of the present invention, P + substrate material and N-type epitaxial layer growth.

Fig. 7 shows the second process step of the cross section a-a' of the present invention, which is to inject and push through the P + isolation layer.

Fig. 8 shows a third process step of the cross section a-a' of the present invention, which is to etch the isolation trench and grow the isolation oxide layer, deposit the polysilicon, and planarize the surface CMP, thereby finally leaking the silicon material surface.

Fig. 9 shows a fourth process step of the cross section a-a' of the present invention, which is to perform the injection and junction-pushing of the P-type base region.

Fig. 10 shows a fifth process step of the cross section a-a', the implantation and junction push of the N + source region and the P + source region.

Fig. 11 shows a sixth process step of the cross section a-a' of the present invention, in which the insulating dielectric layer and the top front metal layer are formed by photolithography.

Fig. 12 shows a seventh process step of the cross section a-a', thinning of the back P + substrate layer and metallization of the back metal electrode.

Fig. 13 is a TLP test result chart of the present invention.

In the figure, 101, a P + substrate layer, 102, an N type epitaxial layer, 103, a P + isolation layer, 104, a thermal oxidation layer, 105, N + polysilicon, 106, a P type base region, 107, a P + source region, 108, an N + source region, 109, an insulating medium layer, 110, a front metal layer, 111 and a back metal electrode.

Detailed Description

The present invention will be described in further detail with reference to the accompanying drawings and embodiments. The details are described by taking a P-type substrate material and a voltage level of 1.2V as an example. Technical scheme only the utility model discloses a some embodiment, based on the utility model provides a vertical SCR's the low pressure ESD protection device that introduces forward biased diode cluster in the region of isolation and control SCR's flyback voltage, the number of diode cluster can be in the middle of 1 to 10, forms through a technology, all belongs to the utility model discloses a protection range.

The layout diagram of the present invention as shown in fig. 1 is that the gray area is the metal layer, the most marginal circle is the isolation potential contact area, and the central area is the GND electrode area.

As the equivalent circuit diagram shown in fig. 2, the ESD current releasing direction of the present invention is: CH to GND, the channel includes a small current path L1 through forward biased diodes D1, D2 and resistor R2, resistor R1, and the SCR large current bleeding path L2 of PNPN. When the two current paths are independent, the starting voltage of the small current path is 1.4V of the forward bias voltage of the two diodes. The starting voltage of the large-current path PNPN tube is mainly determined by the base region PN junction, and the avalanche withstand voltage BV of the large-current path PNPN tube is more than 6V. When a voltage pulse impacts the CH port, a current I1 first passes through a path L1 due to the low on-voltage of the small current path, and a current I1 is injected into the P-base region of the NPN transistor and flows through a base short-circuit resistor R1. When I1 & R1 is greater than 0.7V, NPN in SCR is conducted, current I2 is injected into N-type base region of PNP tube, and SCR is started to rapidly discharge pulse charge. Wherein R2 is the series resistance integrated on the L1 route, prevents this route's reposition of redundant personnel too big under the heavy current, causes the route to burn out.

As shown in fig. 3 and 4, the ultra-low voltage trigger device includes a back metal electrode 111, a P + substrate layer 101 is disposed on the back metal electrode 111, an N-type epitaxial layer 102 is deposited on the P + substrate layer 101, an end surface of the N-type epitaxial layer 102 is sequentially advanced from left to right at a high temperature to form a P + isolation layer 103, N + polysilicon 105 and a P-type base region 106; the P + isolation layer 103 penetrates to the P + substrate layer 101; p + source regions 107 are arranged in the two regions of the N + polysilicon 105 and the P-type base region 106, and then N-type impurities are injected between the P + isolation layer 103 and the N + polysilicon 105 and at the sides of the P + source regions 107 in the regions of the N + polysilicon 105 and the P-type base region 106 to form an N + source region 108; an insulating medium layer 109 is deposited on the N-type epitaxial layer 102, and a front metal layer 110 is etched on the insulating medium layer 109.

An insulating dielectric layer 109 is located between the N-type epitaxial layer 102 and the front side metal layer 110.

The P + substrate layer 101 and the N type epitaxial layer 102 form D1, the P + source region 107 and the N + source region 108 form D2, and D1 and D2 form a diode string.

The P + substrate layer 101, the N type epitaxial layer 102, the P type base region 106, the N + source region 108 between the P + isolation layer 103 and the N + polysilicon 105 form a PNPN type thyristor.

Furthermore, four front metals M1-M4 can be seen as four front metals in the A-A' direction. M4 is a GND electrode. The back is a back metal electrode CH, and the current runs in the longitudinal direction. The M1~ M3 front metal area is located the territory marginal region, carries out area matching according to the current demand, and the electric potential floats sky, and the at utmost makes rational use of chip area.

The N + polysilicon 105 and the N type epitaxial layer 102 are separated by the thermal oxide layer 104, the P + source region 107 and the N + source region 108 in the polysilicon form a diode string, and when the pulse voltage exceeds 1.5V, and the polysilicon diode string is turned on, current flows into the P type base region 106 of the trigger region of the SCR through the metal layer, so that the SCR is triggered to be conducted. Since the trigger current can be adjusted by adjusting the resistance R1 of the P-type base region 106, it is usually controlled within 50 mA. And the integrated polysilicon resistor can be adjusted by adjusting the concentration and the spacing of polysilicon, so that the diode path is prevented from passing large current after the residual voltage rises under the condition of large current after the SCR is conducted.

Furthermore, effective electrical isolation is formed after the N + polysilicon is located on the thermal oxide layer grown after pit etching, and CMP planarization treatment is performed after the deposition of the N + polysilicon 105 is completed. The formation of structures in the polysilicon is compatible with subsequent conventional processes.

As shown in fig. 6 to 12, the method for manufacturing an ultra low voltage trigger device includes the following steps:

firstly, preparing a P + substrate layer 101 material, and depositing an N type epitaxial layer 102 material.

Secondly, boron ions are etched and implanted into the surface of the N-type epitaxial layer 102, and the boron ions are diffused with the P + substrate layer 101 to form a P + isolation layer 103 through high-temperature propulsion.

Depositing a mask layer on the surface of the silicon wafer, forming a deep groove by photoetching and etching the groove, and removing the etching mask layer; the depth of the groove is 1-5 mu m; after the groove etching is finished, growing a thermal oxide layer of 3000-8000A by wet oxygen, wherein the thermal oxidation temperature is 950-1150 ℃; then depositing 3-5 mu m in-situ doped N + polysilicon 105; CMP planarization is then performed until the un-etched areas expose the N-type epitaxial layer 102.

And fourthly, after the CMP is finished, pre-oxidation growth is carried out, and photoetching ions are implanted with P-type impurities to form a P-type base region 106 through knot pushing.

Fifthly, in the regions of the N + polysilicon 105 and the P-type base region 106, high-concentration P-type impurities are implanted through photoetching to form a P + source region 107, and then N-type impurities are implanted through photoetching to form an N + source region 108.

And sixthly, depositing an insulating medium layer 109, and photoetching and etching the contact hole region after densification. And depositing a metal layer, and photoetching, etching and alloying to complete the front metal layer 110.

And seventhly, thinning the P + substrate layer 101, and depositing a back metal electrode 111.

And further, the high temperature of the second step is 1250 ℃, the junction pushing time is 300min, and the punch-through well is adopted for isolation so as to ensure that the chip can withstand voltage in two directions and improve the reliability of the device.

In the third step, the groove etching and the thermal oxidation need smaller wafer stress, so that the wafer is prevented from warping due to overlarge stress. Thereby ensuring that the consistency of the effective thickness of the polysilicon in the wafer is high after CMP planarization.

And in the fifth step, high-concentration ion implantation is adopted in the P + source region 107 and the N + source region 108, and the energy is 30-90 kev. The combination of lower implantation energy and rapid thermal annealing process is adopted to realize shallower junction depth so as to reduce the cell size and improve the current density of the chip per unit area.

And after the etching of the lead hole in the sixth step is finished, depositing a layer of TI/TIN and then growing a metal layer of AlSiCu alloy. The contact resistance is reduced, and meanwhile, the failure rate of metal overheating can be effectively reduced.

And in the seventh step, the back metal is a back electrode, and the direction of the current is vertical, so that the packaging resistance is reduced.

N + polysilicon 105 is separated from N-type epitaxial layer 102 by thermal oxide layer 104, wherein D1 formed by P + substrate layer 101 and N-type epitaxial layer 102 forms a diode string with D2 of P + source region 107 and N + source region 108 in the polysilicon.

The P + substrate layer 101, the N-type epitaxial layer 102, the P-type base region 106 and the N + source region 108 form a PNPN type thyristor with an interlayer resistor R1. Wherein the resistance of the base sandwich resistor R1 determines the turn-on current of the SCR. The trigger current is provided by a forward biased diode string.

The thermal oxide layer 104, the P + substrate layer 101 and the N + polysilicon 105 are not present elsewhere on the material surface, and are removed in the CMP planarization step.

An insulating dielectric layer 109 is located between the N-type epitaxial layer 102 and the front side metal layer 110.

The layout of the P + source region 107 and the N + source region 108 in the polysilicon is adjusted, so that the pitch is increased, and the resistance of the polysilicon in series connection is introduced. The current limiting device is beneficial to limiting the current of the small current path, and avoids overcurrent failure of the small current path caused by overlarge current.

The thermal oxide layer 104 and the N + polysilicon 105 can be replaced by the P-type base region 106, so that the process is simplified.

Phosphorus, arsenic and antimony particles can also be used as the N-type doped ions.

The manufacturing process of the utility model is as follows:

firstly, a P-type substrate sheet doped with phosphorus and having a substrate resistivity of 0.001-0.005 Ω & cm, preferably 0.002 Ω & cm, and a crystal orientation of <111 >. And growing a phosphorus-doped N-type epitaxy with the resistivity of 10-50 omega cm on the surface, wherein the thickness of the N-type epitaxy is 10-30 mu m. Preferably, the resistivity is 20. omega. cm and the thickness is 20 μm.

And (4) forming a deep groove in the epitaxial deposition mask layer and the photoetching groove, and removing the etching mask layer. The depth of the groove is 1 to 5 μm, preferably 3 μm. Too deep a groove results in excessive stress on the wafer and increased cost. After the groove etching is completed, growing a thermal oxidation layer of 3000-8000A by wet oxygen, wherein the thickness is preferably 5000A, and the thermal oxidation temperature is 950-1150 ℃.

Then 3-5 μm in-situ doped N + polysilicon 105 is deposited. The thickness is preferably 3 μm. CMP planarization is then performed until the un-etched regions expose the N-type material.

After the CMP is finished, pre-oxidation growth is carried out, P-type boron impurities are implanted through photoetching ions, and the implantation dosage is 1E 13-1E 14cm-2, preferably 5E14 cm-2. The high temperature push-knot is formed to a knot depth of 3-5 μm.

And photoetching and injecting high-concentration P-type impurities into the N + polysilicon, the N-type base region and the P-type base region to form a P + source region, and photoetching and injecting high-concentration N-type impurities to form an N + source region. The dosage of the junction depth of the P + source region and the N + source region is 2E 15-1E 16cm-2, preferably 5E15cm-2, and the junction depth is about 0.5 mu m.

And then depositing an isolation dielectric layer, depositing the dielectric layer of 7000A by adopting a low-pressure tetraethoxysilane growth process (LPTEOS), and performing contact hole etching after refluxing. And depositing a layer of TI/TIN and growing a metal layer of AlSiCu alloy. The contact resistance is reduced, and meanwhile, the failure rate of metal overheating can be effectively reduced.

The substrate 101 is then thinned to a thickness of 100 to 300 μm, preferably 140 μm, and a back metal electrode 111 is deposited.

Utilize above-mentioned the utility model discloses a manufacturing approach of low pressure ESD protection device only needs the series connection number of the positive bias diode of adjustment diode region, both can adjust SCR's flyback voltage to be applied to the ESD protection of low pressure systems such as 1.2V, 1.8V, 2V, 2.5V, 2.8V, 3.3V, the flyback current of SCR can be adjusted to the base region resistance R1 of adjustment P type base region. Meanwhile, the low-voltage ESD protection of ultralow residual voltage can be realized by adjusting the junction depth and the distance between the high-resistance regions.

Fig. 5 is a cross-sectional view of an improved a-a' structure of the present invention. The etched groove is oxidized and filled with polysilicon, and PN junction isolation is changed, so that the same performance can be realized.

The TLP test result of the ultra-low voltage trigger device of the present invention is shown in fig. 13.

Claims (5)

1. The ultra-low voltage trigger device is characterized in that: the silicon-based epitaxial wafer comprises a back metal electrode (111), wherein a P + substrate layer (101) is arranged on the back metal electrode (111), an N-type epitaxial layer (102) is deposited on the P + substrate layer (101), the end face of the N-type epitaxial layer (102) is sequentially pushed from one side to the other side to form a P + isolation layer (103), N + polycrystalline silicon (105) is deposited and a P-type base region (106) is formed by pushing; the P + isolation layer (103) penetrates to the P + substrate layer (101); p + source regions (107) are arranged in the two regions of the N + polysilicon (105) and the P-type base region (106), and then N-type impurities are injected between the P + isolation layer (103) and the N + polysilicon (105) and on the sides of the P + source regions (107) in the regions of the N + polysilicon (105) and the P-type base region (106) to form an N + source region (108); and depositing an insulating medium layer (109) on the N-type epitaxial layer (102), and etching a front metal layer (110) on the insulating medium layer (109).

2. The ultra low voltage trigger device of claim 1, wherein: a thermal oxide layer (104) is arranged between the N + polysilicon (105) and the N-type epitaxial layer (102).

3. The ultra low voltage trigger device of claim 1, wherein: the insulating medium layer (109) is located between the N-type epitaxial layer (102) and the front metal layer (110).

4. The ultra low voltage trigger device of claim 1, wherein: the P + substrate layer (101) and the N-type epitaxial layer (102) form D1, the P + source region (107) and the N + source region (108) form D2, and D1 and D2 form a diode string.

5. The ultra low voltage trigger device of claim 1, wherein: and the P + substrate layer (101), the N type epitaxial layer (102), the P type base region (106), the N + source region (108) between the P + isolation layer (103) and the N + polysilicon (105) form a PNPN type thyristor.

Images