CN215815878U

CN215815878U - Integrated chip with isolation structure

Info

Publication number: CN215815878U
Application number: CN202120980267.7U
Authority: CN
Inventors: 赵起越; 石瑜
Original assignee: Innoscience Zhuhai Technology Co Ltd
Current assignee: Innoscience Zhuhai Technology Co Ltd
Priority date: 2021-05-08
Filing date: 2021-05-08
Publication date: 2022-02-11
Anticipated expiration: 2031-05-08

Abstract

The utility model provides an integrated chip with an isolation structure, which comprises a substrate and an epitaxial structure arranged along a longitudinal direction. The epitaxial structure includes an interlayer dielectric (ild) layer, an isolation region dividing the integrated chip into a first semiconductor device region and a second semiconductor device region arranged in a lateral direction. The substrate comprises an N-type region and a P-type region, two PN junctions are formed between the N-type region and the P-type region, and the two PN junctions are respectively located in the first semiconductor device region and the second semiconductor device region. Three glass through holes extending longitudinally are formed in the epitaxial structure. An isolation medium is arranged in the first glass through hole, and the first glass through hole penetrates through the I LD layer in the longitudinal direction and extends downwards to the bottom layer of the substrate. The first source is electrically connected to the epitaxial layer of the substrate through a first electrical interconnect, and the second drain is shorted to the first source. The second source is electrically connected to the epitaxial layer of the substrate through a second electrical interconnect. The integrated chip can realize effective isolation of two semiconductor device area substrates.

Description

Integrated chip with isolation structure

Technical Field

The utility model relates to the technical field of semiconductor devices, in particular to an integrated chip with an isolation structure.

Background

Due to the characteristics of High switching speed, low conduction loss, low switching loss and the like, a wide bandgap gallium nitride High Electron Mobility Transistor (GaN HEMT) device becomes a power device which is currently concerned in the fields of High frequency application and High power density application. GaN HEMTs are beginning to find wider application in the conventional DC-DC field (such as buck, boost, and fly back). The half-bridge circuit has wide application in PWM motor control, DC-AC inversion, electronic ballast and other occasions. Compared with a depletion type GaN HEMT device, the enhancement type GaN HEMT device is more simple in driving circuit, beneficial to reducing the area and complexity of a system and more suitable for being applied to a half-bridge circuit. However, most GaN HEMT devices in the current market are discrete devices, and need to be connected with other devices through an external circuit to realize specific functions, so that the circuit is large in size and strong in parasitic phenomenon, and cannot meet the requirements of a system on higher frequency, smaller size and the like.

If an upper tube and a lower tube in a half-bridge circuit can be integrated on the same chip, the parasitic effect caused by interconnection between devices can be reduced, the switching speed of the switching tube is increased, and the switching power consumption of the switching tube is reduced. However, in an integrated half-bridge circuit designed by using an enhanced GaN HEMT device, if the upper tube and the lower tube are not effectively isolated, the substrates of the upper tube and the lower tube are in a grounded state. When the upper tube is conducted, the source electrode and the drain electrode are both positive voltages close to Vdd, and the substrate is at 0 potential, so that the threshold voltage and the on-resistance of the device can be increased due to the back gate effect, the power consumption of the upper tube is increased, and the power consumption of the whole system is further increased.

In addition, in the case of a lack of effective isolation of substrate potentials of various parts of an integrated circuit, the substrate potentials may interfere with each other due to differences in voltage levels between the power transistor part and the analog part of the integrated circuit. When the potential of the power tube is unstable, the analog part may be affected, and the analog part may malfunction or even burn out.

Disclosure of Invention

The utility model aims to provide an integrated chip with an isolation structure, which can realize effective isolation of substrates of two semiconductor device areas.

To achieve the above object, the present invention provides an integrated chip having an isolation structure, the integrated chip including a substrate and an epitaxial structure arranged in a longitudinal direction. The epitaxial structure includes an interlayer dielectric (ILD) layer, and the integrated chip is provided with an isolation region dividing the integrated chip into a first semiconductor device region and a second semiconductor device region arranged in a lateral direction. The substrate comprises a bottom layer and an epitaxial layer formed by extending upwards from the bottom layer, one of the bottom layer and the epitaxial layer is an N-type region, the other one of the bottom layer and the epitaxial layer is a P-type region, two PN junctions are formed between the N-type region and the P-type region, and the two PN junctions are respectively located in the first semiconductor device region and the second semiconductor device region. The upper side of the epitaxial structure is provided with a first drain electrode, a first grid electrode, a first source electrode, a second drain electrode, a second grid electrode and a second source electrode, the first drain electrode, the first grid electrode and the first source electrode are all located in the first semiconductor device area, and the second drain electrode, the second grid electrode and the second source electrode are all located in the second semiconductor device area. Glass through-hole is worn to the first glass through-hole, second that set up longitudinal extension in the epitaxial structure and the glass through-hole is worn to the third, and the second is worn the glass through-hole and is located first semiconductor device district, and the glass through-hole is worn to the third and is located second semiconductor device district. An isolation medium is arranged in the first through glass via hole, the first through glass via hole penetrates through the ILD layer in the longitudinal direction and extends downwards to the bottom layer of the substrate, and the isolation medium forms an isolation region. A first electrical interconnection is arranged in the second through glass through hole, the first source electrode is electrically connected with the epitaxial layer of the substrate through the first electrical interconnection, and the second drain electrode is in short circuit with the first source electrode. A second electrical interconnection is arranged in the third through glass via, and the second source electrode is electrically connected with the epitaxial layer of the substrate through the second electrical interconnection.

According to the scheme, the isolation region, the first through glass via hole, the second through glass via hole and the third through glass via hole are arranged, and two equivalent diodes are formed in the part, located in the first semiconductor device region, of the substrate and the part, located in the second semiconductor device region, of the substrate. When the circuit works, the first drain electrode is connected with a high voltage Vdd, the second source electrode is grounded (0V), and the first source electrode and the second drain electrode are in short circuit and then serve as output.

Therefore, substrate isolation of the first semiconductor device region and the second semiconductor device region is achieved, namely the first semiconductor device region and the second semiconductor device region can have independent substrate potentials according to different device working states, when the first semiconductor device region is conducted, the influence of a back gate effect caused by the fact that the substrates of the first semiconductor device region and the second semiconductor device region are both 0 potential is avoided, and the increase of system power consumption caused by the increase of the conduction resistance of the first semiconductor device region due to the back gate effect is reduced.

The integrated chip integrates the first semiconductor device area and the second semiconductor device area on the same substrate and effectively isolates the substrate potential through the isolation area, thereby reducing the parasitic effect introduced by interconnection between the devices, increasing the switching speed of the switching tube and reducing the switching power consumption of the switching tube.

Preferably, the bottom layer is a P-type silicon substrate, the epitaxial layer is an N-type silicon epitaxial layer, the P-type silicon substrate serves as a P-type region, and the N-type silicon epitaxial layer serves as an N-type region.

Further, the first through glass via extends downward into the P-type silicon substrate, and the first electrical interconnection and the second electrical interconnection extend downward into the N-type silicon epitaxial layer.

Preferably, the bottom layer is an N-type silicon substrate, the epitaxial layer is a P-type silicon epitaxial layer, the P-type silicon epitaxial layer serves as a P-type region, and the N-type silicon epitaxial layer serves as an N-type region.

Further, the first through glass via extends downward into the N-type silicon substrate, and the first electrical interconnection and the second electrical interconnection extend downward into the P-type silicon epitaxial layer.

Preferably, the material of the isolation dielectric is silicon dioxide or silicon nitride.

In a preferred embodiment, the epitaxial structure comprises a channel layer, a barrier layer, an EPI passivation protection layer, an interlayer dielectric (ILD) layer, a first metal layer, an inter-metal dielectric (IMD) layer, a second metal layer and a passivation protection layer, which are stacked in sequence from bottom to top; an ohmic metal layer is arranged on the EPI passivation protection layer, the upper end of the ohmic metal layer is positioned in the ILD layer, and the lower end of the ohmic metal layer is connected with the barrier layer; a P-type gate dielectric layer and a gate metal layer which are longitudinally overlapped are also arranged in the EPI passivation protective layer, and the P-type gate dielectric layer is connected above the barrier layer; a first contact hole and a second contact hole are formed in the ILD layer, and the ohmic metal layer and the first metal layer are electrically connected through metal filled in the first contact hole.

In a further aspect, the ohmic metal layer includes a first drain ohmic metal contact, a first source ohmic metal contact, a second drain ohmic metal contact, and a second source ohmic metal contact, the first drain is electrically connected to the first drain ohmic metal contact, the first source is electrically connected to the first source ohmic metal contact, the second drain is electrically connected to the second drain ohmic metal contact, and the second source is electrically connected to the second source ohmic metal contact. The second contact hole penetrates through the ILD layer and the EPI passivation protective layer in the longitudinal direction, and metal filled in the second contact hole electrically connects the gate metal layer with the first metal layer; a through hole is formed in the IMD layer, and the second metal layer is electrically connected with the first metal layer through metal filled in the through hole; the passivation protection layer is provided with a plurality of openings in a penetrating manner in the longitudinal direction, and the first drain electrode, the first grid electrode, the first source electrode, the second drain electrode, the second grid electrode and the second source electrode are all located on the second metal layer and respectively leak out from the corresponding openings.

Further, the upper end of the isolation dielectric extends to the upper surface of the ILD layer.

In a further aspect, the upper end of the isolation dielectric extends to the upper surface of the IMD layer.

It can be seen that the isolation region fabrication step can be after the ILD process, and can also be after the IMD process.

Further, the upper ends of the first electrical interconnection and the second electrical interconnection are connected to the second metal layer.

In a preferred embodiment, the isolation region surrounds the first semiconductor device region, and the second semiconductor device region is located outside the isolation region.

It can be seen that the first semiconductor device region is fabricated in a region surrounded by the isolation region.

Preferably, the isolation region surrounds the second semiconductor device region, and the first semiconductor device region is located outside the isolation region.

Thus, the second semiconductor device region is formed in the region surrounded by the isolation region.

Drawings

Fig. 1 is a schematic cross-sectional view of a first embodiment of an integrated chip according to the present invention.

Fig. 2 is a schematic top view of a first embodiment of an integrated chip according to the present invention.

Fig. 3 is a schematic diagram of forming an N-type silicon epitaxial layer on a P-type silicon substrate in a first embodiment of an integrated chip of the utility model.

Fig. 4 is a schematic diagram after forming a channel layer, a barrier layer and a dielectric layer on a P-type silicon epitaxial layer in the first embodiment of the integrated chip of the utility model.

Fig. 5 is a schematic diagram of a first embodiment of an integrated chip according to the present invention, in which a metal layer is formed on a dielectric layer.

Fig. 6 is a schematic diagram of forming a P-type gate dielectric layer and a gate metal layer in a first embodiment of an integrated chip according to the present invention.

Fig. 7 is a schematic diagram of forming an EPI passivation layer in a first embodiment of an integrated chip according to the present invention.

Fig. 8 is a schematic diagram of the integrated chip according to the first embodiment of the present invention after forming an ohmic contact hole on the EPI passivation layer.

Fig. 9 is a schematic diagram of the integrated chip according to the first embodiment of the present invention after forming the ohmic metal layer.

Fig. 10 is a schematic diagram of the integrated chip after an ILD layer is formed in the first embodiment of the present invention.

Fig. 11 is a schematic diagram of the integrated chip according to the first embodiment of the present invention after the first through glass via is formed.

Fig. 12 is a schematic diagram of the integrated chip according to the first embodiment of the present invention after an isolation medium is deposited in the first through-glass via.

Fig. 13 is a schematic diagram of a first embodiment of an integrated chip according to the present invention after removing the excess isolation dielectric on the surface of the ILD layer.

Fig. 14 is a schematic diagram of the integrated chip according to the first embodiment of the present invention after forming the contact holes.

Fig. 15 is a schematic diagram of the contact hole and the first through glass via hole filled with the tungsten plug in the first embodiment of the integrated chip according to the present invention.

Fig. 16 is a schematic diagram of the integrated chip according to the first embodiment of the present invention after the first metal layer is formed.

Fig. 17 is a schematic diagram of the integrated chip according to the first embodiment of the present invention after forming an IMD layer.

Fig. 18 is a schematic diagram of the integrated chip according to the first embodiment of the present invention after forming a via hole in the IMD layer.

Fig. 19 is a schematic diagram of the first embodiment of the integrated chip according to the present invention after filling the tungsten plug in the via hole.

Fig. 20 is a schematic view of the integrated chip of the first embodiment of the present invention after forming the second through glass via and the third through glass via.

Fig. 21 is a diagram illustrating the first embodiment of the integrated chip of the present invention after forming the second metal layer.

Fig. 22 is a schematic diagram of the integrated chip according to the first embodiment of the present invention after forming the passivation layer.

Fig. 23 is a schematic top view of a fourth embodiment of an integrated chip according to the present invention.

Fig. 24 is a schematic top view of a fifth embodiment of an integrated chip according to the present invention.

The utility model is further explained with reference to the drawings and the embodiments.

Detailed Description

First embodiment of integrated chip with isolation structure:

referring to fig. 1 and 2, the integrated chip with an isolation structure of the present embodiment includes a substrate 20 and an epitaxial structure 30 arranged in a longitudinal direction.

The substrate 20 has a two-layer structure, and the substrate 20 includes a P-type silicon substrate 21 and an N-type silicon epitaxial layer 22 epitaxially formed upward from the P-type silicon substrate 21. An isolation region 24 is provided in the integrated chip, the isolation region 24 divides the integrated chip into a first semiconductor device region and a second semiconductor device region which are arranged along the transverse direction, the first semiconductor device region is an E-mode GaN HEMT Q1 device region in the figure 1 and is hereinafter referred to as an upper tube Q1, and the second semiconductor device region is an E-mode GaN HEMT Q2 device region in the figure 1 and is hereinafter referred to as a lower tube Q2. In this embodiment, the isolation region 24 is rectangular around the upper tube Q1, and the lower tube Q2 is located outside the isolation region 24.

The upper side of the epitaxial structure 30 is provided with a first drain 11, a first gate 12, a first source 13, a second drain 14, a second gate 15 and a second source 16, which are arranged in sequence along the lateral direction, the first drain 11, the first gate 12 and the first source 13 are all located in the upper tube Q1 portion, and the second drain 14, the second gate 15 and the second source 16 are all located in the lower tube Q2 portion.

The epitaxial structure 30 includes a channel layer 3, a barrier layer 4, an EPI passivation layer 5, an interlayer dielectric (ILD) layer 6, a first metal layer 7, an inter-metal dielectric (IMD) layer 8, a second metal layer 9, and a passivation protection layer 10, which are sequentially stacked from bottom to top, and the channel layer 3 is connected to the N-type silicon epitaxial layer 22. An ohmic metal layer 51 is disposed on the EPI passivation layer 5, an upper end of the ohmic metal layer 51 is positioned in the ILD layer 6, and a lower end of the ohmic metal layer 51 is connected to the barrier layer 4. The EPI passivation layer 5 is also provided with a P-type gate dielectric layer 52 and a gate metal layer 53 which are vertically overlapped, and the P-type gate dielectric layer 52 is connected above the barrier layer 4. The channel layer 3 is made of GaN, the barrier layer 4 is made of AlGaN, the P-type gate dielectric layer 52 is made of GaN, and the EPI passivation layer 5 is made of Si3N 4.

A first contact hole 61(contact) and a second contact hole 62 are formed in the ILD layer 6, the metal filled in the first contact hole 61 electrically connects the ohmic metal layer 51 with the first metal layer 7, the ohmic metal layer 51 includes a first drain ohmic metal contact 511, a first source ohmic metal contact 512, a second drain ohmic metal contact 513 and a second source ohmic metal contact 514, the first drain 11 is electrically connected with the first drain ohmic metal contact 511, the first source 13 is electrically connected with the first source ohmic metal contact 512, the second drain 14 is electrically connected with the second drain ohmic metal contact 513, and the second source 16 is electrically connected with the second source ohmic metal contact 514. The second contact hole 62 penetrates the ILD layer 6 and the EPI passivation layer 5 in the longitudinal direction, and the metal filled in the second contact hole 62 electrically connects the gate metal layer 53 with the first metal layer 7. A through hole 81(via) is formed in the IMD layer 8, and the metal filled in the through hole 81 electrically connects the second metal layer 9 and the first metal layer 7. The passivation layer 10 is longitudinally and penetratingly provided with a plurality of openings 101, and the first drain 11, the first gate 12, the first source 13, the second drain 14, the second gate 15 and the second source 16 are all located on the second metal layer 9 and respectively leak out of the corresponding openings 101.

A first through glass via 31 (TGV), a second through glass via 32 and a third through glass via 33 are longitudinally extended in the epitaxial structure 30, the second through glass via 32 is located on the upper tube Q1, and the third through glass via 33 is located on the lower tube Q2. The first through glass via 31 extends from the upper surface of the ILD layer 6 to the P-type silicon substrate 21 along the longitudinal direction, and an isolation medium is arranged in the first through glass via 31 and forms an isolation region 24. The isolation medium is made of silicon dioxide, silicon nitride or the like.

The first through glass via 32 is internally provided with a first electrical interconnection 321, the first source electrode 13 is electrically connected with the part of the N-type silicon epitaxial layer 22 on the upper tube Q1 through the first electrical interconnection 321, and the second drain electrode 14 is shorted with the first source electrode 13 through the second metal layer 9. The upper end of the first electrical interconnect 321 is connected to the first source 13 of the second metal layer 9, and the lower end of the first electrical interconnect 321 extends into the portion of the N-type silicon epitaxial layer 22 located on the upper tube Q1.

A second electrical interconnect 331 is disposed within third through glass via 33, and second source 16 is electrically connected to the portion of N-type silicon epitaxial layer 22 located at lower tube Q2 through second electrical interconnect 331. The upper end of the second electrical interconnect 331 is connected to the second source 16 of the second metal layer 9, and the lower end of the second electrical interconnect 331 extends into the portion of the N-type silicon epitaxial layer 22 located in the lower tube Q2.

The manufacturing method of the integrated chip comprises the following steps.

First, a P-type silicon substrate 21 is provided.

Next, as shown in fig. 3, an N-type silicon epitaxial layer 22 is epitaxially formed on the P-type silicon substrate 21.

Next, as shown in fig. 4, a channel layer 3, a barrier layer 4, and a dielectric layer 520 are epitaxially grown in this order on the N-type silicon epitaxial layer 22 of the substrate 20.

Next, as shown in fig. 5, a metal layer 530 is formed by metal deposition on the dielectric layer 520.

Next, the dielectric layer 520 and the metal layer 530 are patterned by using a semiconductor photolithography technique and an etching technique to form the P-type gate dielectric layer 52 and the gate metal layer 53 as shown in fig. 6.

Next, as shown in fig. 7, an EPI passivation layer 5 is formed by deposition, where the EPI passivation layer 5 is made of silicon nitride.

Next, as shown in fig. 8, an ohmic contact hole 510 is formed on the EPI passivation layer 5 using a photolithography technique and an etching technique.

Next, as shown in fig. 9, after ohmic metal deposition is performed on the EPI passivation layer 5, an ohmic metal layer 51 is formed using a photolithography technique and an etching technique.

Next, as shown in FIG. 10, an ILD layer 6 is formed using deposition and planarization processes.

Next, as shown in fig. 11, a first through glass via 31 extending longitudinally into the P-type silicon substrate 21 is formed using a photolithography technique and an etching technique.

Next, as shown in fig. 12, an isolation medium is deposited within the first through glass via 31.

Next, as shown in fig. 13, the excess isolation dielectric on the surface of the ILD layer 6 is removed, and the isolation dielectric in the first through glass via 31 forms an isolation region 24.

Next, as shown in fig. 14, a first contact hole 61 penetrating the ILD layer 6 in the longitudinal direction is formed above the ohmic metal layer 51 using a photolithography technique and an etching technique, and a second contact hole 62 penetrating the ILD layer 6 and the EPI passivation layer 5 in the longitudinal direction is formed above the gate metal layer 53.

Next, as shown in fig. 15, tungsten plugs are filled in the first contact hole 61 and the second contact hole 62, and excess tungsten on the surface of the ILD layer 6 is removed.

Next, as shown in fig. 16, a first metal layer 7 is formed on the ILD layer 6 by metal deposition, and the first metal layer 7 is patterned by using photolithography and etching techniques.

Next, an IMD layer 8 as shown in fig. 17 is formed using deposition and planarization processes.

Next, as shown in fig. 18, a through hole 81(via) penetrating the IMD layer 8 in the longitudinal direction is formed using a photolithography technique and an etching technique.

Next, as shown in fig. 19, a tungsten plug is filled in the through hole 81, and excess tungsten on the surface of the IMD layer 8 is removed.

Next, a second through glass via 32 and a third through glass via 33 extending into the N-type silicon epitaxial layer 22 in the longitudinal direction as shown in fig. 20 are formed using a photolithography technique and an etching technique.

Next, as shown in fig. 21, metal is deposited on the IMD layer 8, and the second metal layer 9 is patterned using photolithography and etching techniques.

Finally, as shown in fig. 22, a passivation protection layer 10 is deposited on the second metal layer 9, and the passivation protection layer 10 is patterned by using a photolithography technique and an etching technique, so that the first drain electrode 11, the first gate electrode 12, the first source electrode 13, the second drain electrode 14, the second gate electrode 15, and the second source electrode 16 are exposed.

The utility model changes the traditional P-type silicon substrate into a P-N two-layer substrate structure, and forms an isolation region which extends to the P-type silicon substrate 21 in the longitudinal direction in the integrated chip, wherein the isolation region 24 surrounds the region where the upper tube Q1 is positioned. In addition, the N-type silicon epitaxial layer 22 on the upper layer in the substrate in the area surrounded by the inner side of the isolation region 24 is connected to the first source 13 of the upper tube Q1 through a second through-glass via 32, and the N-type silicon epitaxial layer 22 on the upper layer in the substrate in the area outside the isolation region 24 is connected to the second source 16 of the lower tube Q2 through a third through-glass via 33, so that the N-type silicon epitaxial layer 22 on the upper layer in the substrate in the area surrounded by the upper tube Q1 is divided into two parts by the isolation region 24 in the area of the upper tube Q1 and the lower tube Q2, and the second through-glass via 32 in the upper tube Q1 and the third through-glass via 33 in the lower tube Q2 are connected to the substrates of the upper tube Q1 and the lower tube Q2, respectively. Due to the existence of the isolation region 24, PN junctions are formed between the P-type silicon substrate 21 and the N-type silicon epitaxial layer 22 in the substrate region of the upper tube Q1 and the substrate region of the lower tube Q2, and complete isolation of the device portion and the substrate portion between the upper tube Q1 and the lower tube Q2 is achieved.

When the upper tube Q1 is turned on and the lower tube Q2 is turned off, the output end outputs a high potential, at this time, the first source 13 of the upper tube Q1 is at a high potential close to Vdd (Vdd minus the turn-on voltage of the upper tube Q1), the second source 16 of the lower tube Q2 is at a 0 potential, at this time, the PN junction equivalent diode a1 at the substrate of the upper tube Q1 is in a reverse bias state, the PN junction equivalent diode a2 at the substrate of the lower tube Q2 is in a zero bias state, and a1 forms a depletion region to bear Vdd voltage, so that the N-type silicon epitaxial layer 22 at the upper layer in the substrate of the upper tube Q1 is at a high potential, the N-type silicon epitaxial layer 22 at the upper layer in the substrate of the lower tube Q2 is at a zero potential, and V is provided for both the upper tube Q1 and the lower tube Q2_BSWhen the upper transistor Q1 is turned on, the back gate effect due to the substrate and source potential difference and the increase in circuit power consumption caused by the back gate effect are eliminated.

When the upper tube Q1 is turned off and the lower tube Q2 is turned on, the output terminal outputs a low potential, at this time, the first source 13 of the upper tube Q1 is at a low potential close to 0 potential (lower tube Q2 on voltage), the second source 16 of the lower tube Q2 is at 0 potential, a1 is in a weak reverse bias state, a2 is in a zero bias state, the upper N-type silicon epitaxial layer 22 in the substrate of the upper tube Q1 and the lower tube Q2 is both close to 0 potential, and V is provided for both the upper tube Q1 and the lower tube Q2_BS0, no back gate effect.

In this case, substrate isolation of the upper tube Q1 and the lower tube Q2 is achieved, that is, the upper tube Q1 and the lower tube Q2 can have independent substrate potentials according to different device operating states, the influence of a back gate effect caused by the fact that the substrates of the upper tube Q1 and the lower tube Q2 are both 0 potential is avoided when the upper tube Q1 is turned on, and the increase of system power consumption caused by the increase of on resistance of the upper tube Q1 due to the back gate effect is reduced.

Second embodiment of integrated chip with isolation structure:

as a description of the second embodiment of the integrated chip of the present invention, only the differences from the first embodiment of the integrated chip described above will be described below.

In this embodiment, the substrate has an NP two-layer structure, and includes an N-type silicon substrate and a P-type silicon epitaxial layer epitaxially formed upward from the N-type silicon substrate. The first through glass via extends longitudinally downward into the N-type silicon substrate from the upper surface of the ILD layer, and the first electrical interconnection and the second electrical interconnection extend downward into the P-type silicon epitaxial layer.

Third embodiment of integrated chip with isolation structure:

as a description of the third embodiment of the integrated chip of the present invention, only the differences from the first embodiment of the integrated chip described above will be described below.

In this embodiment, the isolation region manufacturing step may also be located after the IMD process step, that is, after the IMD layer is formed, a first through glass via is formed, the first through glass via penetrates the IMD layer and the ILD layer in the longitudinal direction and extends downward to the P-type silicon substrate located in the lower layer in the substrate, then an isolation medium is deposited in the first through glass via, then the excess isolation medium on the surface of the IMD layer is removed, and the isolation medium located in the first through glass via forms the isolation region.

In this embodiment, the upper end of the isolation dielectric extends to the upper surface of the IMD layer.

Fourth embodiment of integrated chip with isolation structure:

as a description of the fourth embodiment of the integrated chip of the present invention, only the differences from the first embodiment of the integrated chip described above will be described below.

Referring to fig. 23, in the present embodiment, the isolation region 424 surrounds the lower tube Q2, and the upper tube Q1 is located outside the isolation region 424.

Fifth embodiment of integrated chip with isolation structure:

as a description of the fifth embodiment of the integrated chip of the present invention, only the differences from the first embodiment of the integrated chip described above will be described below.

Referring to fig. 24, in the present embodiment, the isolation region 524 extends linearly in a top view, and the isolation region 524 is located between the upper tube Q1 and the lower tube Q2 and penetrates the integrated chip in a direction perpendicular to both the lateral direction and the longitudinal direction.

In addition, the upper ends of the first and second electrical interconnects may also both be connected to the first metal layer. The upper ends of the first and second electrical interconnects may also both be connected to the second metal layer. The process flow of device fabrication, the number of metal layers on the upper layer, and the interconnection mode can be modified according to design. The substrate can also be a P-N-P three-layer structure, namely after an N-type epitaxial layer is formed on the P-type substrate in an epitaxial mode, the P-type silicon epitaxial layer on the upper layer is formed in an epitaxial mode continuously. The substrate can also be an N-P-N three-layer structure, and when the substrate is of the three-layer structure, the first glass through hole extends downwards to the bottommost layer of the substrate. The above-described modifications also achieve the object of the present invention.

Finally, it should be emphasized that the above-described preferred embodiments of the present invention are merely examples of implementations, not limitations, and various changes and modifications may be made by those skilled in the art, without departing from the spirit and scope of the utility model, and any changes, equivalents, improvements, etc. made within the spirit and scope of the present invention are intended to be embraced therein.

Claims

1. The integrated chip with the isolation structure is characterized by comprising a substrate and an epitaxial structure which are arranged along a longitudinal direction, wherein the epitaxial structure comprises an ILD layer;

the integrated chip is provided with an isolation region which divides the integrated chip into a first semiconductor device region and a second semiconductor device region which are arranged along the transverse direction;

the substrate comprises a bottom layer and an epitaxial layer formed by extending upwards from the bottom layer, one of the bottom layer and the epitaxial layer is an N-type region, the other one of the bottom layer and the epitaxial layer is a P-type region, two PN junctions are formed between the N-type region and the P-type region, and the two PN junctions are respectively located in the first semiconductor device region and the second semiconductor device region;

a first drain electrode, a first grid electrode, a first source electrode, a second drain electrode, a second grid electrode and a second source electrode are arranged on the upper side of the epitaxial structure, the first drain electrode, the first grid electrode and the first source electrode are all located in the first semiconductor device region, and the second drain electrode, the second grid electrode and the second source electrode are all located in the second semiconductor device region;

a first glass through hole, a second glass through hole and a third glass through hole which extend longitudinally are formed in the epitaxial structure, the second glass through hole is located in the first semiconductor device area, and the third glass through hole is located in the second semiconductor device area;

an isolation medium is arranged in the first through glass via, the first through glass via penetrates through the ILD layer in the longitudinal direction and extends downwards to the bottom layer of the substrate, and the isolation medium forms the isolation region;

a first electrical interconnection is arranged in the second through glass via, the first source electrode is electrically connected with the epitaxial layer of the substrate through the first electrical interconnection, and the second drain electrode is in short circuit with the first source electrode;

and a second electrical interconnection is arranged in the third through glass via, and the second source electrode is electrically connected with the epitaxial layer of the substrate through the second electrical interconnection.

2. The integrated chip of claim 1, wherein:

the bottom layer is a P-type silicon substrate, the epitaxial layer is an N-type silicon epitaxial layer, the P-type silicon substrate serves as the P-type region, and the N-type silicon epitaxial layer serves as the N-type region.

3. The integrated chip of claim 2, wherein:

the first through glass via extends down into the P-type silicon substrate, and the first electrical interconnect and the second electrical interconnect both extend down into the N-type silicon epitaxial layer.

4. The integrated chip of claim 1, wherein:

the bottom layer is an N-type silicon substrate, the epitaxial layer is a P-type silicon epitaxial layer, the P-type silicon epitaxial layer serves as the P-type region, and the N-type silicon epitaxial layer serves as the N-type region.

5. The integrated chip of claim 4, wherein:

the first through glass via extends down into the N-type silicon substrate, and the first electrical interconnect and the second electrical interconnect both extend down into the P-type silicon epitaxial layer.

6. The integrated chip according to any one of claims 1 to 5, wherein:

the isolation medium is made of silicon dioxide or silicon nitride.

7. The integrated chip according to any one of claims 1 to 5, wherein:

the epitaxial structure comprises a channel layer, a barrier layer, an EPI passivation protective layer, the ILD layer, a first metal layer, an IMD layer, a second metal layer and a passivation protective layer which are sequentially stacked from bottom to top;

an ohmic metal layer is arranged on the EPI passivation protection layer, the upper end of the ohmic metal layer is positioned in the ILD layer, and the lower end of the ohmic metal layer is connected with the barrier layer;

a P-type gate dielectric layer and a gate metal layer which are longitudinally overlapped are also arranged in the EPI passivation protective layer, and the P-type gate dielectric layer is connected above the barrier layer;

and a first contact hole and a second contact hole are formed in the ILD layer, and the ohmic metal layer and the first metal layer are electrically connected by metal filled in the first contact hole.

8. The integrated chip of claim 7, wherein:

the ohmic metal layer comprises a first drain ohmic metal contact, a first source ohmic metal contact, a second drain ohmic metal contact and a second source ohmic metal contact, the first drain is electrically connected with the first drain ohmic metal contact, the first source is electrically connected with the first source ohmic metal contact, the second drain is electrically connected with the second drain ohmic metal contact, and the second source is electrically connected with the second source ohmic metal contact;

the second contact hole penetrates through the ILD layer and the EPI passivation protective layer in the longitudinal direction, and metal filled in the second contact hole electrically connects the gate metal layer with the first metal layer;

a through hole is formed in the IMD layer, and the second metal layer is electrically connected with the first metal layer through metal filled in the through hole;

the passivation protection layer is provided with a plurality of openings in a penetrating manner in the longitudinal direction, and the first drain electrode, the first gate electrode, the first source electrode, the second drain electrode, the second gate electrode and the second source electrode are all located on the second metal layer and respectively leak out from the corresponding openings.

9. The integrated chip of claim 7, wherein:

an upper end of the isolation dielectric extends to an upper surface of the ILD layer.

10. The integrated chip of claim 7, wherein:

the upper end of the isolation medium extends to the upper surface of the IMD layer.

11. The integrated chip of claim 7, wherein:

the upper ends of the first and second electrical interconnects are both connected to the second metal layer.

12. The integrated chip according to any one of claims 1 to 5, wherein:

the isolation region surrounds the first semiconductor device region, and the second semiconductor device region is located outside the isolation region.

13. The integrated chip according to any one of claims 1 to 5, wherein:

the isolation region surrounds the second semiconductor device region, and the first semiconductor device region is located outside the isolation region.