CN102130119B - Diode and preparation method thereof - Google Patents
Diode and preparation method thereof Download PDFInfo
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- CN102130119B CN102130119B CN 201010027291 CN201010027291A CN102130119B CN 102130119 B CN102130119 B CN 102130119B CN 201010027291 CN201010027291 CN 201010027291 CN 201010027291 A CN201010027291 A CN 201010027291A CN 102130119 B CN102130119 B CN 102130119B
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Abstract
The invention discloses a diode which is designed on the basis of a triode. A buried layer is arranged below the triode and used for separating the triode and a substrate; the outer side of the base region of the triode is provided with an ion implanted region for preventing the series connection between the collector and a spacer ring; and the emitter of the triode is used as the anode of the diode, and the base, collector and heavily-doped trap of the triode are short-circuited and used as the cathode of the diode. The invention also discloses a preparation method of the diode. The diode disclosed by the invention has the characteristics of almost no leakage of electricity, and high breakdown voltage, can bear high voltage, and can be used in a high-voltage environment. Meanwhile, the preparation method is simple and convenient.
Description
Technical field
The present invention relates to a kind of semiconductor device and manufacture method thereof.
Background technology
See also Fig. 1, this is a kind of existing diode device structure schematic diagram.Having on 12, two buried regions of N-shaped buried regions 11 and p-type buried regions in p-type substrate 10 is N-type epitaxial loayer 13.High pressure p trap 14, heavy doping n trap 15 and shading ring 16 are arranged in p-type epitaxial loayer 13.Wherein shading ring 16 comprises high pressure p trap 161, low pressure p trap 162 and heavy doping p trap 163.And the bottom of high pressure p trap 161 contacts with p-type buried regions 11, and low pressure p trap 162 is among high pressure p trap 161, and heavy doping p trap 163 is among low pressure p trap 162.If from depression angle, shading ring 16 surrounds around the whole device, and device and the external world are isolated.
In the diode component shown in Figure 1, high pressure p trap 14 is as the anode of diode, and heavy doping n trap 15 is as the negative electrode of diode, but shading ring 16 also external electrode as the substrate exit.Hole in the original high pressure p trap 14 should flow to heavy doping n trap 15.Test is found, has formed a positive-negative-positive parasitic triode that is comprised of high pressure p trap 14, N-shaped epitaxial loayer 13 and p-type shading ring 16 in the diode structure shown in Figure 1.Because the doping content of N-shaped epitaxial loayer 13 is very low, a part of hole in the high pressure p trap 14 has little time to move to heavy doping n trap 15, is just taken away by p-type shading ring 16 by meeting, thereby form larger substrate current in N-shaped epitaxial loayer 13.This parasitic triode is so that diode component shown in Figure 1 produces serious leaky, thereby also can't use in hyperbaric environment.
Summary of the invention
Technical problem to be solved by this invention provides a kind of diode, can avoid producing electric leakage, can bear high pressure again.
For solving the problems of the technologies described above, diode of the present invention is: have the first buried regions 21 and the second buried regions 22 in the substrate 20; It is epitaxial loayer 23 on the substrate 20; In epitaxial loayer 23, have the first low pressure trap 261, the first high pressure trap 251, the second high pressure trap 252, ion implanted region 28 and third high and press trap 253, and have isolation structure 24 and isolate; Wherein the bottom of ion implanted region 28 contacts with the first buried regions 21; Third high presses the bottom of trap 253 to contact with the second buried regions 22;
The second low pressure trap 262 is arranged in the first high pressure trap 251; The 3rd low pressure trap 263 is arranged in the second high pressure trap 252; The 4th low pressure trap 264 is arranged in the ion implanted region 28; Third high is pressed in the trap 253 the 5th low pressure trap 265;
The first heavy doping trap 271 is arranged in the first low pressure trap 261; The second heavy doping trap 272 is arranged in the second low pressure trap 262; In the 3rd low pressure trap 263 triple dopant wells 273 are arranged; In the 4th low pressure trap 264 quadruple dopant well 274 is arranged; The 5th heavy doping trap 275 is arranged in the 5th low pressure trap 265;
Described the first heavy doping trap 271 is the anode of diode;
Described the second heavy doping trap 272, triple dopant wells 273, quadruple dopant well 274 are connected and are the negative electrode of diode.
The manufacture method of described diode comprises the steps:
In the 1st step, in substrate 20, form the first buried regions 21 and the second buried regions 22 by ion implantation technology;
In the 2nd step, by epitaxy technique growth one deck monocrystalline silicon, be called epitaxial loayer 23 at silicon chip surface;
The 3rd step formed the first high pressure trap 251, the second high pressure trap 252 and third high by ion implantation technology and presses trap 253 in epitaxial loayer 23, wherein third high presses the bottom of trap 253 to contact with the second buried regions 22;
The 4th step, in epitaxial loayer 23, form the first low pressure trap 261 and the 4th low pressure trap 264 by ion implantation technology, in the first high pressure trap 251, form the second low pressure trap 262 with ion implantation technology, in the second high pressure trap 252, form the 3rd low pressure trap 263 with ion implantation technology, press in the trap 253 in third high to form the 5th low pressure trap 265 with ion implantation technology;
The 5th step, in the first low pressure trap 261, form the first heavy doping trap 271 by ion implantation technology, in the second low pressure trap 262, form the second heavy doping trap 272 with ion implantation technology, in the 3rd low pressure trap 263, form triple dopant wells 273 with ion implantation technology, in the 4th low pressure trap 264, form quadruple dopant well 274 with ion implantation technology, in the 5th low pressure trap 265, form the 5th heavy doping trap 275 with ion implantation technology;
The 6th step formed ion implanted region 28 with ion implantation technology in epitaxial loayer 23, described ion implanted region 28 surrounds the 4th low pressure trap 264 fully, and the bottom of described ion implanted region 28 contacts with the first buried regions 21;
Described the first heavy doping trap 271 is as the anode of diode;
Described the second heavy doping trap 272, triple dopant wells 273, quadruple dopant well 274 are connected and are the negative electrode of diode.
Diode of the present invention can have been stopped the generation of electric leakage, and has the large characteristics of puncture voltage.
Description of drawings
Fig. 1 is the cross-sectional view of existing diode;
Fig. 2 is the cross-sectional view of diode of the present invention.
Description of reference numerals among the figure:
10 is the p-type substrate; 11 is the N-shaped buried regions; 12 is the p-type buried regions; 13 is the N-shaped epitaxial loayer; 14 is high pressure p trap; The 15 Doped n traps of attaching most importance to; 16 is shading ring; 161 is high pressure p trap; 162 is low pressure p trap; 163 are heavy doping p trap; 20 is the p-type substrate; 21 is the p-type buried regions; 22 is the N-shaped buried regions; 23 is the N-shaped epitaxial loayer; 24 is isolation structure; 251,253 is high pressure p trap; 252 is high pressure n trap; 261,262,265 is low pressure p trap; 263,264 is low pressure n trap; 271,272,275 are heavy doping p trap; 273, the 274 Doped n traps of attaching most importance to; 28 is the N-shaped ion implanted region.
Embodiment
See also Fig. 2, diode of the present invention is: have N-shaped buried regions 21 and p-type buried regions 22 in the p-type substrate 20; It is N-shaped epitaxial loayer 23 on the p-type substrate 20; In N-shaped epitaxial loayer 23, have low pressure p trap 261, high pressure p trap 251, high pressure n trap 252, N-shaped ion implanted region 28 and high pressure p trap 253, and have isolation structure 24 and isolate; Wherein the bottom of N-shaped ion implanted region 28 contacts with N-shaped buried regions 21; The bottom of high pressure p trap 253 contacts with p-type buried regions 22;
Low pressure p trap 262 is arranged in the high pressure p trap 251; Low pressure n trap 263 is arranged in the high pressure n trap 252; Low pressure n trap 264 is arranged in the N-shaped ion implanted region 28; Low pressure p trap 265 is arranged in the high pressure p trap 253;
Heavy doping p trap 271 is arranged in the low pressure p trap 261; Heavy doping p trap 272 is arranged in the low pressure p trap 262; Heavy doping n trap 273 is arranged in the low pressure n trap 263; Heavy doping n trap 274 is arranged in the low pressure n trap 264; Heavy doping p trap 275 is arranged in the low pressure p trap 265;
Described heavy doping p trap 271 is the anode of diode;
Described heavy doping p trap 272, heavy doping n trap 273, heavy doping n trap 274 are connected and are the negative electrode of diode.
On the ordinary meaning, the high pressure trap refers to that the trap that forms through high temperature furnace annealing technique behind the Implantation, low pressure trap refer to behind the Implantation trap that forms without crossing high temperature furnace annealing technique, and the heavy doping trap refers to that larger dose (for example＞1 * 10
15Every square centimeter in atom or ion) the formed trap of Implantation.
Fig. 2 schematically shows as symmetrical structure, and practical devices need not necessarily to adopt this symmetrical structure.
Diode shown in Figure 2 is actually with a positive-negative-positive triode (bipolar transistor) as design basis.The emitter of described positive-negative-positive triode is heavy doping p trap 271, and base terminal is heavy doping n trap 273, and collector electrode is heavy doping p trap 272.The present invention is the emitter 271 of the described positive-negative-positive triode anode as diode, with base terminal 273, collector electrode 272 and heavy doping n trap 274 short circuits of the described positive-negative-positive triode negative electrode as diode.
In the diode of the present invention, has N-shaped buried regions 21 as the below of the positive-negative-positive triode of design basis, as the isolation between described positive-negative-positive triode and the p-type substrate 20.Newly-increased N-shaped ion implanted region 28 is in base stage 273 and the outside, base, and link to each other with N-shaped buried regions 21, prevent break-through between p-type collector electrode 272 and the p-type shading ring (being formed by high pressure p trap 253, low pressure p trap 265, heavy doping p trap 275), realize the complete and extraneous isolation the hole of highly doped N-shaped enclosure wall, effectively prevent electric leakage.
Because base stage 273 and the collector electrode 272 of described positive-negative-positive triode do not have voltage difference, so that the electronic energy of emitter 271 is run in current collection level 272 as much as possible, thereby so that the inflow current of the anode of diode of the present invention equals the outflow electric current of negative electrode, stopped the generation of electric leakage.
The p-type shading ring of described diode also can external electrode, as the substrate exit, and the common ground connection of this substrate exit.
The each several part doping type of diode shown in Figure 2 is become on the contrary, based on the design basis of NPN type triode as diode of the present invention, also is feasible namely.
The manufacture method of described diode comprises the steps:
In the 1st step, in p-type substrate 20, form N-shaped buried regions 21 and p-type buried regions 22 by ion implantation technology;
In the 2nd step, by epitaxy technique growth one deck N-shaped monocrystalline silicon, be called N-shaped epitaxial loayer 23 at silicon chip surface;
The 3rd step formed high pressure p trap 251, high pressure n trap 252 and high pressure p trap 253 by ion implantation technology in N-shaped epitaxial loayer 23, the bottom of its mesohigh p trap 253 contacts with p-type buried regions 22;
The 4th step, in N-shaped epitaxial loayer 23, form low pressure p trap 261 and low pressure n trap 264 by ion implantation technology, in high pressure p trap 251, form low pressure p trap 262 with ion implantation technology, in high pressure n trap 252, form low pressure n trap 263 with ion implantation technology, in high pressure p trap 253, form low pressure p trap 265 with ion implantation technology;
The 5th step, in low pressure p trap 261, form heavy doping p trap 271 by ion implantation technology, in low pressure p trap 262, form heavy doping p trap 272 with ion implantation technology, in low pressure n trap 263, form heavy doping n trap 273 with ion implantation technology, in low pressure n trap 264, form heavy doping n trap 274 with ion implantation technology, in low pressure p trap 265, form heavy doping p trap 275 with ion implantation technology;
The 6th step formed N-shaped ion implanted region 28 with ion implantation technology in N-shaped epitaxial loayer 23, described N-shaped ion implanted region 28 surrounds low pressure n trap 264 fully, and the bottom of described N-shaped ion implanted region 28 contacts with N-shaped buried regions 21;
Making at last isolation structure 24 in N-shaped epitaxial loayer 23, for example is oxygen isolation (LOCOS) technique or shallow-trench isolation (STI) technique.
Described heavy doping p trap 271 is as the anode of diode;
Described heavy doping p trap 272, heavy doping n trap 273, heavy doping n trap 274 are connected and are the negative electrode of diode.
In described the 1st step of method, the 3rd～6 step, all have annealing process after ion implantation technology, described annealing process is high temperature furnace annealing.
Described method is in the 6th step, and ion implantation dosage is greater than 1 * 10
15Atom per square centimeter (or ion every square centimeter), energy is greater than 100keV.
The manufacture method of described diode becomes the implanted dopant type on the contrary during with each step ion implantation technology, the doping type of each several part structure become on the contrary, and also be feasible.
In sum, diode of the present invention has hardly electric leakage, characteristics that puncture voltage is large, can bear high pressure, can be applied to hyperbaric environment.Simultaneously its manufacture method also have simply, characteristics easily.
Structure in above-described embodiment, shape, position, step, parameter etc. are signal, and under overall thought disclosed in this invention, one of ordinary skill in the art can be made any equivalents, and these all should belong within protection scope of the present invention.
Claims (6)
1. a diode is characterized in that, has the first buried regions (21) and the second buried regions (22) in the substrate (20); Be epitaxial loayer (23) on the substrate (20); In epitaxial loayer (23), have the first low pressure trap (261), the first high pressure trap (251), the second high pressure trap (252), ion implanted region (28) and third high and press trap (253), and have isolation structure (24) and isolate; Wherein the bottom of ion implanted region (28) contacts with the first buried regions (21); Third high presses the bottom of trap (253) to contact with the second buried regions (22);
The second low pressure trap (262) is arranged in the first high pressure trap (251); The 3rd low pressure trap (263) is arranged in the second high pressure trap (252); The 4th low pressure trap (264) is arranged in the ion implanted region (28); Third high is pressed in the trap (253) the 5th low pressure trap (265);
The first heavy doping trap (271) is arranged in the first low pressure trap (261); The second heavy doping trap (272) is arranged in the second low pressure trap (262); In the 3rd low pressure trap (263) triple dopant wells (273) are arranged; In the 4th low pressure trap (264) quadruple dopant well (274) is arranged; The 5th heavy doping trap (275) is arranged in the 5th low pressure trap (265);
Described the first heavy doping trap (271) is the anode of diode;
Described the second heavy doping trap (272), triple dopant wells (273), quadruple dopant well (274) are connected and are the negative electrode of diode.
2. diode according to claim 1, it is characterized in that it is p-type that described substrate (20), the second buried regions (22), the first high pressure trap (251), third high are pressed trap (253), the first low pressure trap (261), the second low pressure trap (262), the 5th low pressure trap (265), the first heavy doping trap (271), the second heavy doping trap (272), the 5th heavy doping trap (275); Described the first buried regions (21), epitaxial loayer (23), the second high pressure trap (252), the 3rd low pressure trap (263), the 4th low pressure trap (264), triple dopant wells (273), quadruple dopant well (274), ion implanted region (28) are N-shaped.
3. diode according to claim 1 is characterized in that, the anode of described diode and negative electrode exchange; It is N-shaped that described substrate (20), the second buried regions (22), the first high pressure trap (251), third high are pressed trap (253), the first low pressure trap (261), the second low pressure trap (262), the 5th low pressure trap (265), the first heavy doping trap (271), the second heavy doping trap (272), the 5th heavy doping trap (275); Described the first buried regions (21), epitaxial loayer (23), the second high pressure trap (252), the 3rd low pressure trap (263), the 4th low pressure trap (264), triple dopant wells (273), quadruple dopant well (274), ion implanted region (28) are p-type.
4. the manufacture method of diode as claimed in claim 1 is characterized in that, comprises the steps:
In the 1st step, in substrate (20), form the first buried regions (21) and the second buried regions (22) by ion implantation technology;
In the 2nd step, by epitaxy technique growth one deck monocrystalline silicon, be called epitaxial loayer (23) at silicon chip surface;
The 3rd step, form the first high pressure trap (251), the second high pressure trap (252) and third high by ion implantation technology and press trap (253) in epitaxial loayer (23), wherein third high presses the bottom of trap (253) to contact with the second buried regions (22);
The 4th step, in epitaxial loayer (23), form the first low pressure trap (261) and the 4th low pressure trap (264) by ion implantation technology, in the first high pressure trap (251), form the second low pressure trap (262) with ion implantation technology, in the second high pressure trap (252), form the 3rd low pressure trap (263) with ion implantation technology, press in the trap (253) in third high to form the 5th low pressure trap (265) with ion implantation technology;
The 5th step, in the first low pressure trap (261), form the first heavy doping trap (271) by ion implantation technology, in the second low pressure trap (262), form the second heavy doping trap (272) with ion implantation technology, in the 3rd low pressure trap (263), form triple dopant wells (273) with ion implantation technology, in the 4th low pressure trap (264), form quadruple dopant well (274) with ion implantation technology, in the 5th low pressure trap (265), form the 5th heavy doping trap (275) with ion implantation technology;
The 6th step, in epitaxial loayer (23), form ion implanted region (28) with ion implantation technology, described ion implanted region (28) surrounds the 4th low pressure trap (264) fully, and the bottom of described ion implanted region (28) contacts with the first buried regions (21);
Described the first heavy doping trap (271) is as the anode of diode;
Described the second heavy doping trap (272), triple dopant wells (273), quadruple dopant well (274) are connected and are the negative electrode of diode.
5. the manufacture method of diode according to claim 4 is characterized in that, in described the 1st step of method, the 3rd～6 step, all has annealing process after ion implantation technology, and described annealing process is high temperature furnace annealing.
6. the manufacture method of diode according to claim 4 is characterized in that, described method is in the 6th step, and ion implantation dosage is greater than 1 * 10
15Atom per square centimeter, energy is greater than 100keV.
Priority Applications (1)
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|---|---|---|---|
| CN 201010027291 CN102130119B (en) | 2010-01-18 | 2010-01-18 | Diode and preparation method thereof |
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|---|---|---|---|
| CN 201010027291 CN102130119B (en) | 2010-01-18 | 2010-01-18 | Diode and preparation method thereof |
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| CN102130119A CN102130119A (en) | 2011-07-20 |
| CN102130119B true CN102130119B (en) | 2013-03-13 |
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| CN110828549B (en) * | 2019-11-14 | 2022-08-16 | 西安微电子技术研究所 | Guard ring doped anti-radiation transistor structure and preparation method thereof |
| CN114709254B (en) * | 2022-04-01 | 2023-03-21 | 无锡友达电子有限公司 | High-voltage parallel diode structure with composite buried layer and preparation method thereof |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6919603B2 (en) * | 2003-04-30 | 2005-07-19 | Texas Instruments Incorporated | Efficient protection structure for reverse pin-to-pin electrostatic discharge |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6919603B2 (en) * | 2003-04-30 | 2005-07-19 | Texas Instruments Incorporated | Efficient protection structure for reverse pin-to-pin electrostatic discharge |
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Owner name: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING Free format text: FORMER OWNER: HUAHONG NEC ELECTRONICS CO LTD, SHANGHAI Effective date: 20131216 |
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Effective date of registration: 20131216 Address after: 201203 Shanghai city Zuchongzhi road Pudong New Area Zhangjiang hi tech Park No. 1399 Patentee after: Shanghai Huahong Grace Semiconductor Manufacturing Corporation Address before: 201206, Shanghai, Pudong New Area, Sichuan Road, No. 1188 Bridge Patentee before: Shanghai Huahong NEC Electronics Co., Ltd. |