CN114664861A

CN114664861A - Three-dimensional memory, preparation method thereof and storage system

Info

Publication number: CN114664861A
Application number: CN202210266451.4A
Authority: CN
Inventors: 张坤; 周文犀; 夏志良; 霍宗亮
Original assignee: Yangtze Memory Technologies Co Ltd
Current assignee: Yangtze Memory Technologies Co Ltd
Priority date: 2022-03-17
Filing date: 2022-03-17
Publication date: 2022-06-24

Abstract

The invention provides a three-dimensional memory, a preparation method thereof and a storage system, relates to the field of semiconductor chips, and aims to reduce misalignment errors between an array device and a peripheral device and reduce process difficulty. The preparation method of the three-dimensional memory comprises the following steps: forming a stacked structure on a first side of a substrate; forming isolation grooves penetrating through the laminated structure and extending into the substrate, and filling sacrificial materials in the isolation grooves; forming a plurality of conductive structures on one side of the laminated structure far away from the substrate; providing a peripheral circuit, bonding the peripheral circuit to at least one of the plurality of conductive structures; removing at least a portion of the substrate to expose the sacrificial material; and removing the sacrificial material, and replacing the sacrificial layer with the first conductive layer through the isolation groove. According to the manufacturing method, the peripheral circuit is bonded with the conductive structure, then the sacrificial material is removed, and the first conductive layer is manufactured, so that the misalignment error between the peripheral circuit and the array device comprising the conductive structure is reduced.

Description

Three-dimensional memory, preparation method thereof and storage system

Technical Field

The disclosure relates to the technical field of semiconductor chips, in particular to a three-dimensional memory, a preparation method thereof and a storage system.

Background

As the feature size of memory cells approaches the lower process limit, planar processes and fabrication techniques become challenging and costly, which causes the storage density of 2D or planar NAND flash memories to approach the upper limit.

To overcome the limitations imposed by 2D or planar NAND flash memories, memories having a three-dimensional structure (3D NAND) have been developed to increase the storage density by arranging memory cells three-dimensionally over a substrate.

In forming 3D NAND, it is necessary to bond array devices on one substrate with peripheral devices on another substrate. However, misalignment errors are liable to occur between the bonded array device and the peripheral device.

Disclosure of Invention

The embodiment of the disclosure provides a three-dimensional memory, a preparation method thereof and a storage system.

The embodiment of the disclosure adopts the following technical scheme:

in one aspect, a method for manufacturing a three-dimensional memory is provided, where the method includes: forming a laminated structure on a first side of a substrate, wherein the laminated structure comprises dielectric layers and sacrificial layers which are alternately arranged; forming an isolation groove which penetrates through the laminated structure and extends into the substrate, and filling a sacrificial material in the isolation groove; forming a plurality of conductive structures on a side of the laminated structure away from the substrate, wherein at least part of the conductive structures in the plurality of conductive structures extend into the laminated structure; providing a peripheral circuit, bonding the peripheral circuit to at least one of the plurality of conductive structures; removing at least part of the substrate to expose the sacrificial material in the isolation groove; removing the sacrificial material in the isolation grooves, and replacing the sacrificial layer with a first conductive layer through the isolation grooves so that at least part of the conductive structures in the plurality of conductive structures are electrically connected to the first conductive layer.

In some embodiments, the substrate comprises a first substrate layer and a second substrate layer sequentially adjacent to the stacked structure; the second substrate layer and the first substrate layer have different etching selection ratios, and the separation groove extends into the first substrate layer; the step of removing at least a portion of the substrate to expose the sacrificial material within the gate spacer comprises: and etching the first substrate layer to the second substrate layer to expose the sacrificial material in the grid isolation groove.

In some embodiments, after the step of replacing the sacrificial layer with the first conductive layer, the method further comprises: sequentially forming a first protective layer in the separation groove along the direction far away from the inner wall of the separation groove, forming a first conductive part on one side of the first insulating layer far away from the first protective layer, and forming a second protective layer covering one end of the first conductive part far away from the peripheral circuit; removing the second substrate layer to expose the second protective layer; and forming a source electrode layer covering the second protective layer.

In some embodiments, after the step of replacing the sacrificial layer with the first conductive layer, the method further comprises: sequentially forming a first protective layer and a first insulating layer in the separation groove along the direction far away from the inner wall of the separation groove, forming a first conductive part on one side of the first insulating layer far away from the first protective layer, and forming a second protective layer covering one end, far away from the peripheral circuit, of the first conductive part; removing the second substrate layer, the second protective layer, a part of the first insulating layer and a part of the first protective layer to expose one end of the first conductive part far away from the peripheral circuit; forming a source layer overlying an end of the first conductive portion remote from the peripheral circuitry.

In some embodiments, the substrate further comprises: a third substrate layer; the third substrate layer is positioned on one side, far away from the first substrate layer, of the second substrate layer; the third substrate layer and the second substrate layer have different etching selection ratios. After removing the second substrate layer, the method further comprises: removing at least a portion of the third substrate layer.

In some embodiments, the stacked structure comprises a plateau region and a storage region; before the step of forming the isolation trenches extending through the stacked structure and into the substrate, further comprising: forming a channel hole penetrating through the laminated structure and extending into the third substrate layer in the storage region, and sequentially forming a storage function layer and a channel layer in the channel hole along a direction far away from the inner wall of the channel hole to form a channel structure; forming a virtual channel hole penetrating through the laminated structure and extending into the first substrate layer in the step area, and filling a dielectric material in the virtual channel hole to form a virtual channel structure; wherein a portion of the plurality of conductive structures are electrically connected to the channel layer.

In some embodiments, before the step of forming the stacked structure, the method further comprises: sequentially forming a first etching stop layer and a second etching stop layer on one side, close to the laminated structure, of the third substrate layer and along the direction far away from the third substrate layer, wherein the first etching stop layer and the second etching stop layer have different etching selection ratios; the step of removing the second substrate layer and at least a portion of the third substrate layer comprises: etching the second substrate layer and at least part of the third substrate layer to the first etching stop layer to expose a part of the storage function layer extending into the third substrate layer; etching the exposed parts of the first etching stop layer and the memory function layer to the second etching stop layer so as to expose one end of the channel layer far away from the peripheral circuit; after the source layer is formed, the source layer is electrically connected with one end of the channel layer far away from the peripheral circuit.

In some embodiments, before the step of forming the source layer, the method further comprises: ion doping at least the exposed portion of the channel layer, the ion doping being of the same type as the doping type of the source layer.

In some embodiments, before the step of filling the sacrificial material in the isolation trench, the method further includes: forming a third protective layer on at least a part of the inner wall of the isolation groove; wherein the third protective layer covers at least a surface of the third substrate layer exposed in the cell, a surface of the first substrate layer exposed in the cell, and a surface of the second etch stop layer exposed in the cell.

In some embodiments, after etching the second substrate layer and before etching at least a portion of the third substrate layer, further comprising: and setting a mask plate covering the virtual channel structure, so that after part of the third substrate layer is etched, the part of the third substrate layer covering the virtual channel structure is reserved.

In some embodiments, after the step of forming the source layer, the method further comprises: forming a dielectric layer on a side of the source layer away from the stacked structure; forming a second conductive portion in the dielectric layer, the second conductive portion electrically connected to the source layer; and forming a second conductive layer on one side of the dielectric layer far away from the laminated structure, wherein the second conductive layer is electrically connected with the second conductive part.

In some embodiments, the plurality of conductive structures further comprises a first conductive structure and a second conductive structure; the first conductive structure is electrically connected with the source electrode layer, and the second conductive structure is electrically connected with the peripheral circuit; after the first substrate layer, the second substrate layer, the third substrate layer and the second etching barrier layer are etched, the tail ends of the first conductive structure and the second conductive structure are exposed; the dielectric layer separates the source layer from the first and second conductive structures.

In some embodiments, during the forming of the second conductive portion, a third conductive portion and a fourth conductive portion are also formed in the dielectric layer, the third conductive portion being electrically connected to the first conductive structure, the fourth conductive portion being electrically connected to the peripheral circuitry; the second conductive layer is also electrically connected to the third conductive portion.

In some embodiments, in the forming of the second conductive layer, a fifth conductive portion is further formed on a side of the dielectric layer away from the stacked structure, and the fifth conductive portion is electrically connected to the fourth conductive portion.

In another aspect, a three-dimensional memory is provided, the three-dimensional memory including a semiconductor layer, a stacked structure, a plurality of conductive structures, a peripheral circuit, and a separation structure.

In some embodiments, the stacked structure is located on one side of the semiconductor layer; the stacked structure comprises dielectric layers and conductive layers which are alternately arranged. The plurality of conductive structures are located on a side of the stacked structure far away from the semiconductor layer, and at least part of the plurality of conductive structures extend into the stacked structure. The peripheral circuit is bonded to at least one of the plurality of conductive structures. The separation structure penetrates through the stacked structure and extends into the semiconductor layer; the width of one end, close to the semiconductor layer, of the separation structure is smaller than the width of one end, far away from the semiconductor layer, of the separation structure.

In some embodiments, the separation structure has an air gap therein.

In some embodiments, the air gap extends in a direction perpendicular to the semiconductor layer; the width of the region of the air gap close to the semiconductor layer is smaller than the width of the region of the air gap far from the semiconductor layer.

In yet another aspect, a storage system is provided that includes a controller and the three-dimensional memory described above, the controller coupled to the three-dimensional memory to control the three-dimensional memory.

According to the method for manufacturing the three-dimensional memory provided by the embodiment of the disclosure, the peripheral circuit is bonded with the plurality of conductive structures on the substrate before the step of removing the sacrificial material in the separation groove and replacing the sacrificial layer in the laminated structure with the first conductive layer, so that the plurality of conductive structures on the substrate can be well supported before bonding, and therefore, the plurality of conductive structures are not easy to be dislocated when being bonded with the peripheral circuit, namely, the misalignment error when the peripheral circuit is bonded with the plurality of conductive structures is improved. It will be appreciated that the plurality of conductive structures are part of the array device on the substrate, and therefore misalignment errors between the peripheral circuitry and the array device to be further formed later are also improved.

On the basis, the step of replacing the sacrificial layer in the laminated structure with the first conductive layer by removing the sacrificial material in the separation groove later is beneficial to reducing the stress generated before bonding, so that the stability and the reliability of the formed three-dimensional memory are improved.

In addition, when the separation grooves are formed, the sacrificial materials in the separation grooves can be exposed in a mode of removing at least part of the substrate only by ensuring that the lower ends of the separation grooves extend into part of the substrate, so that the separation grooves are conveniently used for replacing the sacrificial layers in the laminated structure with the first conductive layers. It can be understood that, here, the depths of the plurality of isolation grooves extending into the substrate may be the same or different, and it is necessary to open the isolation grooves from the back side and remove the sacrificial material in the isolation grooves subsequently, therefore, the method for manufacturing a three-dimensional memory provided by the embodiment of the disclosure has low requirements on the etching precision of the isolation grooves, thereby further contributing to reducing the process difficulty and saving the process cost.

The beneficial effects achieved by the three-dimensional memory and the storage system provided by the embodiments of the disclosure can refer to the beneficial effects of the above preparation method of the three-dimensional memory, and are not repeated herein.

Drawings

In order to more clearly illustrate the technical solutions in the present disclosure, the drawings needed to be used in some embodiments of the present disclosure will be briefly described below, and it is apparent that the drawings in the following description are only drawings of some embodiments of the present disclosure, and other drawings can be obtained by those skilled in the art according to the drawings. Furthermore, the drawings in the following description may be regarded as schematic diagrams, and do not limit the actual size of products, the actual flow of methods, the actual timing of signals, and the like, involved in the embodiments of the present disclosure.

FIGS. 1A-1G are flow diagrams of methods of fabricating three-dimensional memories according to some embodiments;

fig. 2A to 2Q are longitudinal-sectional structural views corresponding to respective steps in a method of manufacturing a three-dimensional memory according to some embodiments;

FIG. 3A is a top view block diagram of a three-dimensional memory according to some embodiments;

FIG. 3B is a top view block diagram of another three-dimensional memory according to some embodiments;

FIGS. 4A-4D are longitudinal cross-sectional block diagrams of three-dimensional memories according to some embodiments;

FIG. 5 is a block diagram of a storage system according to some embodiments;

FIG. 6 is a block diagram of another memory system according to some embodiments.

Detailed Description

Technical solutions in some embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings, and it is obvious that the described embodiments are only a part of the embodiments of the present disclosure, and not all of the embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments provided by the present disclosure belong to the protection scope of the present disclosure.

In the description of the present disclosure, it is to be understood that the terms "center", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like indicate orientations or positional relationships based on those shown in the drawings, and are only for convenience in describing and simplifying the disclosure, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed in a specific orientation, and be operated, and thus, should not be construed as limiting the disclosure.

Throughout the specification and claims, the term "comprising" is to be interpreted in an open, inclusive sense, i.e., as "including, but not limited to," unless the context requires otherwise. In the description herein, the terms "one embodiment," "some embodiments," "an example embodiment," "exemplary" or "some examples" or the like are intended to mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the disclosure. The schematic representations of the above terms are not necessarily referring to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be included in any suitable manner in any one or more embodiments or examples.

In the following, the terms "first", "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the embodiments of the present disclosure, "a plurality" means two or more unless otherwise specified.

Example embodiments are described herein with reference to cross-sectional and/or plan views as idealized example figures. In the drawings, the thickness of layers and regions are exaggerated for clarity. Variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, the exemplary embodiments should not be construed as limited to the shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the exemplary embodiments.

As used herein, the term "substrate" refers to a material onto which subsequent layers of material may be added. The substrate itself may be patterned. The material added on the substrate may be patterned or may remain unpatterned. In addition, the substrate may include a variety of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, and the like. Alternatively, the substrate may be made of a non-conductive material such as glass, plastic, or sapphire wafer.

The term "three-dimensional memory" refers to a semiconductor device formed of memory cell transistor strings (referred to herein as "memory cell strings", e.g., NAND memory cell strings) arranged in an array on a major surface of a substrate and extending in a direction perpendicular to the substrate. As used herein, the term "perpendicular" means nominally perpendicular to a major surface (i.e., a lateral surface) of a substrate.

Fig. 1A to 1G are flow charts of methods for manufacturing a three-dimensional memory according to some embodiments of the present disclosure; fig. 2A to 2Q are longitudinal-sectional structural views corresponding to respective steps in a method of manufacturing a three-dimensional memory according to some embodiments. It should be understood that the steps shown in fig. 1A-1G are not exclusive, and that other steps may be performed before, after, or between any of the steps shown. Further, some of the steps may be performed simultaneously, or may be performed in an order different from that shown in fig. 1. The following describes a method for manufacturing a three-dimensional memory in some embodiments with reference to fig. 1A to 1G and fig. 2A to 2Q.

Referring to fig. 1A, fig. 1A is a flowchart illustrating a method for fabricating a three-dimensional memory, where the method includes steps S1 to S6.

S1, forming a stacked structure 2 on the first side of the substrate 11, wherein the stacked structure 2 comprises dielectric layers 21 and sacrificial layers 22 which are alternately arranged.

In step S1, referring to fig. 2A, fig. 2A is a diagram illustrating a vertical sectional structure of the three-dimensional memory after forming the stacked structure 2 on the first side of the substrate 11, and a method for forming the stacked structure 2 includes a thin film Deposition process such as Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), or Atomic Layer Deposition (ALD).

In some examples, the thicknesses of the plurality of dielectric layers 21 in the stacked structure 2 may be the same or different; the thicknesses of the plurality of sacrificial layers 22 may be the same or different; the method can be specifically set according to the process requirements. In addition, in the manufacturing process of the stacked structure 2, different stacking layers correspond to different stacking heights, for example, the number of stacked layers of the stacked structure 2 may be 8, 32, 64, 128, and the like, and the greater the number of stacked layers of the stacked structure 2, the higher the integration level, i.e., the greater the number of memory cells to be formed subsequently. Specifically, the number of stacked layers and the stacking height of the stacked structure 2 may be designed according to actual storage requirements, which is not specifically limited by the present disclosure.

In some examples, the dielectric layer 21 and the sacrificial layer 22 have different etching selectivity, the sacrificial layer 22 may be removed in a subsequent process to form a sacrificial gap, and a conductive material may be filled in the sacrificial gap (i.e., a space where the sacrificial layer 22 is located) to form a first conductive layer, i.e., a word line. Illustratively, the material of the dielectric layer 21 includes silicon oxide, and the material of the sacrificial layer 22 includes silicon nitride. The step of forming the first conductive layer will be described in detail in some embodiments later.

It is to be understood that, although some embodiments of the present disclosure employ an embodiment in which the sacrificial layer 22 is subsequently replaced with a conductive material to form the first conductive layer 23, the embodiment in which the first conductive layer 23 is formed in the present disclosure is not limited thereto, and may also be implemented, for example, by directly forming the dielectric layer 21 and the first conductive layer 23 which are overlapped and overlapped.

In some embodiments, referring to fig. 2A, substrate 11 comprises a first substrate layer 11, a second substrate layer 12, and a third substrate layer 13, in sequence adjacent to stack 2. I.e. the third substrate layer 13 is close to the stack 2, the second substrate layer 12 is located at the side of the third substrate layer 13 remote from the stack 2, and the first substrate layer 11 is located at the side of the second substrate layer remote from the third substrate layer 13. The second substrate layer 12 has a different etch selectivity than the first substrate layer 11 and the second substrate layer 12 has a different etch selectivity than the third substrate layer 13.

Illustratively, the material of the second substrate layer 12 is silicon oxide, and the materials of the first substrate layer 11 and the third substrate layer 13 are polysilicon.

It should be noted that, the second substrate layer 12 is made of a different material than the first substrate layer 11 and the third substrate layer 13, so that the second substrate layer 12, the first substrate layer 11, and the third substrate layer 13 respectively have different etching selection ratios, thereby facilitating control of process uniformity in the process of removing the first substrate layer 11.

In some examples, the second substrate layer 12 and the third substrate layer 13 may be formed on the first substrate layer 11 on a side of the first substrate layer 11 close to the stacked structure 2 using a thin film deposition process such as CVD, PVD, or ALD, and sequentially formed on the first substrate layer 11 in a direction in which the first substrate layer 11 is close to the stacked structure 2.

In some embodiments, referring to fig. 1B, fig. 1B is a flow chart of a method for forming a channel structure 3 and a dummy channel structure 3' in a stacked structure 2. The stacked structure 2 further includes a storage region a and a step region B, and the above manufacturing method further includes steps S01 to S02.

S01, forming a channel hole 31 penetrating through the stacked structure 2 and extending into the third substrate layer 13 in the storage region a, and sequentially forming the storage function layer 32 and the channel layer 33 in the channel hole 31 in a direction away from an inner wall of the channel hole 31 to form the channel structure 3.

Referring to fig. 2B, fig. 2B is a longitudinal sectional structural view of the three-dimensional memory after forming the channel hole 31 in the stacked structure 2, in step S01, the channel hole 31 may be formed in the stacked structure 2 by using, for example, a dry/wet etching process, and the channel hole 31 may be perpendicular to the substrate 1 and extend in a direction close to the substrate 1 so as to extend into the third substrate layer 13.

Referring to fig. 2C, fig. 2C is a longitudinal sectional structure view of the three-dimensional memory after forming the channel structure 3 in the stacked structure 2. The charge blocking layer 321, the charge trapping layer 322, the tunneling layer 323, and the channel layer 33 may be sequentially deposited on the inner wall (including the bottom wall and the side wall) of the channel hole 31 in a direction away from the inner wall of the channel hole 31 using a thin film deposition process such as CVD, PVD, or ALD. The charge blocking layer 321, the charge trapping layer 322, and the tunneling layer 323 constitute the storage function layer 32. Illustratively, the material of the charge blocking layer 321 is silicon oxide, the material of the charge trapping layer 322 is silicon nitride, and the material of the tunneling layer 323 is silicon oxide, so as to form an "ONO" structure.

In some examples, the material of the channel layer 33 is polysilicon.

In the above steps, a thin film deposition process such as CVD, PVD, or ALD may also be employed to fill a dielectric material, for example, silicon oxide, in the channel hole 31 where the memory function layer 32 and the channel layer 33 are formed, to form the channel structure 3 having the channel layer 33, the memory function layer 32, and the filled dielectric material. Illustratively, one or more air gaps may be formed during the filling process to relieve structural stress by controlling the trench fill process.

When the charge blocking layer 321, the charge trapping layer 322, the tunneling layer 323, and the channel layer 33 are made of silicon oxide, silicon nitride, silicon oxide, and polysilicon in sequence, and the filled dielectric material is silicon oxide, the formed channel structure 33 may be referred to as an "ONOPO" structure.

In some examples, with continued reference to fig. 2B and 2C, prior to forming the memory function layer 32, an oxide layer 34 and a high-k dielectric layer 35 may be sequentially formed on the inner wall of the channel hole 31 in a direction away from the inner wall of the channel hole 31. By adopting the scheme that the high-dielectric-constant dielectric layer 35 is formed in the channel hole 31, compared with the scheme that the high-dielectric-constant dielectric layer 35 is arranged in the sacrificial gap formed after the sacrificial layer 22 is removed, the thickness of the total laminated structure 2 can be reduced, and the reduction of the load of etching the channel hole 31, etching the gate line gap and etching the contact hole is facilitated. The use of a high-k dielectric layer 35 formed in the trench opening 31 also allows for an increased process window for etching the trench opening 31 and for removing the backside memory stack (e.g., ONO), with the oxide layer 34 serving as adhesion enhancement and isolation protection.

In some examples, the oxide layer 34 and the high-k dielectric layer 35 are formed using a thin film deposition process such as CVD, PVD, or ALD. The dielectric constant of the high-k dielectric layer 35 is higher than that of silicon oxide, for example, the value k >4.2, and the material of the high-k dielectric layer 35 includes, but is not limited to, aluminum oxide. The material of oxide layer 34 includes, but is not limited to, silicon oxide.

In this example, fig. 2B and 2C illustrate two channel structures 3 as an example, and in actual manufacturing, the number of channel structures 3 may be greater than two, that is, a plurality of channel structures 3 may be formed to penetrate through the stacked structure 2 and extend into the third substrate layer 13. The number and arrangement of the channel structures 3 may be made according to the actual memory requirements of the memory. After the above-mentioned processes, a region corresponding to the channel structure 3 formed on the substrate 1 through the stacked structure 2 may be referred to as a storage region a of the array device (e.g., the storage region a shown in fig. 2D), and the storage region a may be used to implement a storage function of the three-dimensional memory.

Referring to fig. 2D, fig. 2D is a longitudinal sectional structure diagram of the three-dimensional memory after forming a step structure, a barrier layer BB covering the step structure, and an insulating layer 4 covering the barrier layer BB on the stacked structure 2. In some embodiments, a step-like structure is formed at the edge of the stacked structure 2, and the step-like structure may be formed by performing a plurality of "trim-etch" cycles to the plurality of dielectric layers 21 and the plurality of sacrificial layers 22 of the stacked structure 2.

On this basis, the barrier layer BB and the insulating layer 4 distant from the substrate 1 may be formed in order on the stepped structure. The insulating cover layer 4 may be formed by forming a dielectric material over and covering the stepped structure. Illustratively, the insulating layer 4 may extend toward an edge direction of the stacked structure 2 (e.g., a direction near the peripheral region C).

The method of forming the insulating layer 4 may be a thin film deposition process such as CVD, PVD, or ALD. The material of the insulating layer 4 may be selected from the same materials as the dielectric layer 21, such as silicon oxide. Illustratively, the surface of the insulating layer 4 remote from the substrate 1 may be planarized using, for example, a Chemical Mechanical Polishing (CMP) process.

After the above-mentioned process, the region corresponding to the step-like structure formed by the stacked structure 2 on the substrate 1 may be referred to as a step region B of the array device, and the step region B may be an electrical connection region of the word line (the first conductive layer 23). The region of the substrate 1 corresponding entirely to the insulating layer 4 may be referred to as a peripheral region C, which may be used to form a peripheral contact structure (for example, hereinafter, the fourth conductive portion A3) and a source contact (for example, hereinafter, the second conductive portion a1 and/or the third conductive portion a2) structure electrically connected to the peripheral circuit layer in a subsequent process. The steps of forming the fourth conductive portion A3 and the second conductive portion a1 and/or the third conductive portion a2 will be described in detail in some embodiments later.

S02, forming a dummy trench hole penetrating the stacked structure 2 and extending into the first substrate layer 11 at the step region B, and filling a dielectric material in the dummy trench hole to form a dummy trench structure 3'.

In this step, with reference to fig. 2D being continued, fig. 2D shows a vertical sectional structure of the three-dimensional memory after forming the dummy channel structure 3' in the stacked-layer structure 2. It should be noted that the number of the dummy channel structures 3 'may be plural, and the number of the dummy channel structures 3' is not particularly limited in the present disclosure. The plurality of dummy channel structures 3' may extend into the first substrate layer 11 to the same or different depths. With continuing reference to fig. 2D, fig. 2D illustrates an example in which the dummy trench structures 3' extend into the substrate 1 to the same depth.

In the step of forming the dummy channel structures 3 ', a thin film deposition process such as CVD, PVD, or ALD may be used to fill dielectric material, such as silicon oxide, into the dummy channel holes to form the dummy channel structures 3'. Illustratively, by controlling the filling process, one or more air gaps may be formed during the filling process to relieve structural stresses. In embodiments of the present disclosure, the dummy channel structure 3' may be used to provide a mechanical support effect without forming a memory function layer and a channel layer having a memory function.

It should be noted that, the dummy channel structure 3 ' and the channel structure 3 are only illustrated as being formed separately (the channel structure 3 is formed before the step of forming the step-like structure at the edge of the stacked structure 2, and the dummy channel structure 3 ' is formed after the step of forming the step-like structure at the edge of the stacked structure 2), but in other embodiments, the dummy channel structure 3 ' and the channel structure 3 may be formed under the same process.

S2, forming isolation trenches 51 extending through the stacked structure 2 and into the substrate 1, and filling the isolation trenches 51 with the sacrificial material 50.

In step S2, with continued reference to fig. 2D, fig. 2D shows a vertical cross-sectional structure of the three-dimensional memory after filling the spacer grooves 51 with the sacrificial material 50. The spacer grooves 51 may be formed in the stacked structure 2 using, for example, a dry/wet etching process, and the spacer grooves 51 may be perpendicular to the substrate 1 and extend in a direction close to the substrate 1 to extend into the first substrate layer 11.

In some examples, defining: the end of the separation groove 51 far away from the substrate 1 is a first end, and the end of the separation groove 51 extending into the substrate 1 is a second end. With continued reference to FIG. 2D, the width H1 of the first end opening of the compartment 51 is greater than the width H2 of the second end opening of the compartment 51. For example, the width of the partition groove 51 may gradually decrease from the first end to the second end. In this example, since the first end of the isolation trench 51 is opened more, the sacrificial material 50 is easier to fill in the isolation trench 51, so that the three-dimensional memory filled with the sacrificial material 50 can have better support stability.

Here, it is understood that fig. 2D to 2Q are only schematic views, and therefore do not illustrate a change in the width of the partition groove 51.

In some examples, the sacrificial material 50 includes, but is not limited to, polysilicon. Also, the sacrificial material 50 may be filled in the isolation grooves 51 using a thin film deposition process such as CVD, PVD, or ALD.

In some examples, with continued reference to fig. 2D, a capping layer T is formed on the side of the stacked-layer structure 2 remote from the substrate 1 using a thin film deposition process such as CVD, PVD, or ALD. The capping layer T may cover an end surface of the partition groove 51 at an end away from the substrate 1 and an end surface of the virtual channel structure 3 ' at an end away from the substrate 1, so as to seal and protect the virtual channel structure 3 ', and prevent the structure of the virtual channel structure 3 ' from being damaged by subsequent etching and other processes. For example, the capping layer T may be made of the same material (e.g., silicon oxide) as the insulating layer 4 and the dielectric layer 21.

S3, forming a plurality of conductive structures 6 on one side of the laminated structure 2 away from the substrate 1; at least some of the plurality of conductive structures 6 extend into the stacked structure 2.

In step S3, referring to fig. 2E, fig. 2E is a longitudinal sectional structure view of the three-dimensional memory after a plurality of conductive structures 6 are formed. The electrical connection of the channel layer 33, the word lines and the peripheral region C to the peripheral circuitry 7 may be achieved by the conductive structure 6.

In some embodiments, the plurality of conductive structures 6 includes a first conductive structure 61 and a second conductive structure 62. Illustratively, the first conductive structure 61 is a source conductive structure, the second conductive structure 62 is a peripheral conductive structure, the first conductive structure 61 is used for electrically connecting with a source layer 8 to be formed later, and the second conductive structure 62 is used for electrically connecting with a peripheral circuit 7. The first and second

conductive structures

61 and 62 may penetrate the insulating layer 4 and extend into the substrate 1 at the peripheral region C, and illustratively, the first and second

conductive structures

61 and 62 may penetrate the insulating layer 4 vertically and extend into the substrate 1 at the peripheral region C. The first conductive structure 61 may extend into the substrate 1 to the same or different depth as the channel structure 3 extends into the substrate 1, and likewise, the second conductive structure 62 may extend into the substrate 1 to the same or different depth as the channel structure 3 extends into the substrate 1. The number and arrangement of the first conductive structures 61 and the second conductive structures 62 may be prepared according to actual requirements of the three-dimensional memory, for example, the number and arrangement may be designed according to signal transmission requirements of the three-dimensional memory, which is not limited in this embodiment of the disclosure.

While the first conductive structure 61 and the second conductive structure 62 are fabricated, illustratively, as shown in fig. 2E, a word line conductive structure 63 and a channel conductive structure 64 may also be fabricated at the same time. The word line conductive structure 63 is electrically connected to the first conductive layer 23 formed later, and the channel conductive structure 64 is electrically connected to the channel structure 3. A plurality of word line conductive structures 63 extend into the stacked structure 2 to be electrically connected to the first conductive layer 23 described below, respectively.

It is understood that, in the case where the capping layer T is provided, as shown in fig. 2E, the first conductive structure 61, the second conductive structure 62, the word line conductive structure 63, and the channel conductive structure 64 may also penetrate through the capping layer T.

S4, providing a peripheral circuit 7, and bonding the peripheral circuit 7 with at least one conductive structure 6 of the plurality of conductive structures 6.

In step S4, as shown in fig. 2F, fig. 2F is a vertical sectional structure diagram of the three-dimensional memory after the peripheral circuit 7 is bonded to at least one conductive structure 6 of the plurality of conductive structures 6. In some examples, a side of the peripheral circuitry 7 remote from the conductive structure 6 is also provided with a substrate 71 for carrying the peripheral circuitry 7.

In some examples, the bonding manner may be a hybrid bonding. For example, the two are joined by a relatively flat surface to make an electrical connection.

The peripheral circuit 7 may be electrically connected to the first conductive structure 61, the second conductive structure 62, the word line conductive structure 63, and the channel conductive structure 64.

It should be noted that the plurality of conductive structures are a part of an array device on the substrate 1, and the substrate 1 and the array device constitute another semiconductor structure that can be bonded to the peripheral circuit 7. In some examples, the array device may include: a stacked structure, and the channel structure 3, the dummy channel structure 3', the plurality of conductive structures 6, and the separation structure 5 formed after the isolation trenches 51 are filled (as shown in fig. 2I). For example, the stacked structure may be formed by replacing the sacrificial layer 22 in the stacked structure 2 with the first conductive layer 23.

Wherein the peripheral circuitry 7 is configured to control and sense the array device. The peripheral circuitry 7 may include, for example, page buffers, decoders (e.g., row and column decoders), sense amplifiers, drivers (e.g., word line drivers), or any active (or passive) components of circuitry (e.g., transistors, diodes, resistors, capacitors, etc.).

The peripheral circuit 7 may include a plurality of transistors, all or a portion of which are formed in the substrate 71 (e.g., under a surface of the substrate 71 on a side away from the peripheral circuit 7) and/or directly on the substrate 71. Likewise, shallow trench isolation and doped regions (e.g., source and drain regions of a transistor) may also be formed in the substrate 71.

It should be noted that the peripheral circuit 7 may also include any other circuit compatible with high-level logic processes. Illustratively, the peripheral circuits 7 include logic circuits (e.g., processors and Programmable Logic Devices (PLDs)), and/or memory circuits (e.g., Static Random Access Memories (SRAMs)).

S5, at least a portion of the substrate 1 is removed to expose the sacrificial material 50 in the trenches 51.

In some examples, referring to fig. 2G, fig. 2G is a longitudinal sectional structure diagram of the three-dimensional memory after removing the first substrate layer 11. Step S5 includes: the first substrate layer 11 is etched to the second substrate layer 12 to expose the sacrificial material 50 in the spacer trenches 51. The first substrate layer 11 is removed by a dry/wet etching process, and after removing a part of the substrate 1, the sacrificial material 50 in the isolation groove 51 and one end of the dummy channel structure 3' away from the peripheral circuit 7 are exposed.

S6, removing the sacrificial material 50 in the trenches 51, and replacing the sacrificial layer 22 with the first conductive layer 23 through the trenches 51, so that at least some of the plurality of conductive structures 6 (e.g., the word line conductive structures 63 described above) are electrically connected to the first conductive layer 23.

In this step, referring to fig. 2H, fig. 2H is a cross-sectional structure diagram of the three-dimensional memory after removing the sacrificial material 50 in the isolation trenches 51. The sacrificial material 50 in the spacer 51 is removed by a dry/wet etching process, and the sacrificial layer is removed through the spacer 51 as a channel of the etchant to form a sacrificial gap, for example, all the sacrificial layer 22 in the stacked structure is removed by a wet etching process to form a plurality of sacrificial gaps.

In the step of forming the first conductive layer 23 within the sacrificial gap, a thin film deposition process such as CVD, PVD, or ALD may be employed to form the first conductive layer 23 within the sacrificial gap. The material of the first conductive layer 23 may be any one or a combination of conductive materials of tungsten, cobalt, copper, aluminum, doped crystalline silicon, or silicide.

In some examples, a gate barrier layer may be formed on the gate gap and the inner walls of the plurality of sacrificial gaps using a thin film deposition process such as CVD, PVD, or ALD prior to the step of forming the first conductive layer 23 within the sacrificial gaps. On this basis, illustratively, an adhesion layer is formed on the surface of the gate barrier layer within the sacrificial gap using a thin film deposition process such as CVD, PVD, or ALD.

The material of the gate blocking layer may be a high dielectric constant material, such as aluminum oxide. The material of the adhesion layer may be tantalum nitride, titanium nitride, or the like, for example. The adhesion layer helps to increase the adhesion between the gate barrier layer and the first conductive layer 23 formed during subsequent processes.

Illustratively, after the step of forming the gate barrier layer and the adhesion layer, the gate barrier layer, and a portion of the first conductive layer 23 adjacent to the spacer 51 may be removed using, for example, a wet etching process to form a groove in the slot, but implementations of the present disclosure are not limited thereto. In other embodiments, the filled first conductive layer 23 may be aligned with the inner wall of the isolation groove 51 without forming a groove. At this point, a gate barrier layer and an adhesive layer are sequentially deposited on the inner wall of the sacrificial gap, and filled with the first conductive layer 23.

In summary, according to the method for manufacturing a three-dimensional memory provided in some embodiments of the present disclosure, before the step of removing the sacrificial material 50 in the isolation trench 51 and replacing the sacrificial layer 22 in the stacked structure 2 with the first conductive layer 23, the peripheral circuit 7 is bonded to the plurality of conductive structures 6 on the substrate 1, so that the plurality of conductive structures 6 on the substrate 1 can be well supported before bonding, and therefore, misalignment between the plurality of conductive structures 6 and the peripheral circuit 7 is not likely to occur, that is, misalignment errors when the peripheral circuit 7 is bonded to the plurality of conductive structures 6 are improved. It will be appreciated that the plurality of conductive structures 6 are part of the array device on the substrate 1, and therefore misalignment errors between the peripheral circuitry 7 and the array device to be further formed subsequently are also ameliorated.

On the basis of the above, the step of replacing the sacrificial layer 22 in the stacked structure 2 with the first conductive layer 23 by removing the sacrificial material 50 in the isolation groove 51 later is also beneficial to reducing the stress generated before bonding, thereby improving the stability and reliability of the formed three-dimensional memory.

In addition, when the isolation grooves 51 are formed, only by ensuring that the lower ends of the isolation grooves 51 extend into a part of the substrate 1, the sacrificial material 50 in the isolation grooves 51 can be exposed by removing at least a part of the substrate 1, so that the sacrificial layer 22 in the stacked structure 2 can be replaced with the first conductive layer 23 by using the isolation grooves 51. It can be understood that, here, the depth of the plurality of isolation grooves 51 extending into the substrate 1 may be uniform or may not be uniform, and it is further necessary to open the isolation grooves 51 from the back side and remove the sacrificial material 50 in the isolation grooves 51, so that the embodiment of the disclosure provides a method for manufacturing a three-dimensional memory, and the requirement on the etching precision of the isolation grooves 51 is not high, which is further helpful to reduce the process difficulty and save the process cost.

In some embodiments, referring to fig. 1C, fig. 1C is a flow chart of a method of forming the separation structure 5 and the source layer 8. Steps S7 to S9 are also included after the step of replacing the sacrificial layer 22 with the first conductive layer 23.

S7, sequentially forming a first protective layer 52 and a first insulating layer 53 in the trench 51 along a direction away from the inner wall of the trench 51, forming a first conductive portion 54 on a side of the first insulating layer 53 away from the first protective layer 52, and forming a second protective layer 55 covering an end of the first conductive portion 54 away from the peripheral circuit 7.

Referring to fig. 2I, fig. 2I is a longitudinal sectional structure diagram of the three-dimensional memory after forming the first protection layer 52, the first insulating layer 53, the first conductive portion 54, and the second protection layer 55 in the isolation trench 51. A thin film deposition process such as CVD, PVD or ALD may be used to sequentially deposit a first protective layer 52 and a first insulating layer 53 on the inner walls (sidewalls and bottom wall) of the isolation trenches 51, and form a first conductive portion 54 in the inner cavity formed by the first insulating layer 53, and form a second protective layer 55 at an end of the first conductive portion 54 away from the peripheral device 7 to form the separation structure 5. The first protective layer 52 can prevent the first conductive layer 23 from directly contacting the first conductive portion 54; first insulating layer 53 can further electrically isolate first conductive layer 23 from first conductive portion 54; the second protection layer 55 can electrically isolate the source layer 8 to be formed subsequently from the first conductive portion 54, so as to satisfy the functional requirements of the three-dimensional memory.

In some examples, the material of the first protection layer 52 is silicon oxide, the material of the first insulation layer 53 is silicon nitride, the material of the first conductive portion 54 is polysilicon, silicon nitride, silicon oxide, or the like, and the material of the second protection layer 55 is silicon oxide.

S8, removing the second substrate layer 12 and at least a portion of the third substrate layer 13 to expose the second protective layer 55.

Referring to fig. 2J and 2K, fig. 2J is a longitudinal sectional structural view of the three-dimensional memory after the second substrate layer 12 and the third substrate layer 13 are removed, and fig. 2K is a longitudinal sectional structural view of the three-dimensional memory after the second substrate layer 12 and a part of the third substrate layer 13 are removed. The second substrate layer 12 and at least part of the third substrate layer 13 may be removed using, for example, a dry/wet etching process. Removing "at least a portion of third substrate layer 13" as described above refers to removing all of third substrate layer 13 or removing a portion of third substrate layer 13.

Illustratively, referring to FIG. 2J, third substrate layer 13 is removed entirely. At this time, the portions of the dummy conductive structures 3' located in the third substrate 13 may also be substantially entirely removed.

In other examples, after etching the second substrate layer 12 and between etching the third substrate layers 13, further comprising: a mask covering the virtual channel structure 3 'is arranged to leave a portion of the third substrate layer 13 covering the virtual channel structure 3' after etching the third substrate layer 13.

Referring to fig. 2K, a portion of the third substrate layer 13 remains, thereby enhancing the supporting effect on the dummy channel structure 3'.

S9, the source layer 8 is formed to cover the second protective layer 55.

In this step, referring to fig. 2L and 2M, fig. 2L is a longitudinal sectional structural view of a three-dimensional memory in which the third substrate layer 13 is entirely removed; fig. 2M is a longitudinal sectional structural view of another three-dimensional memory, in which a third substrate layer 13 covering a dummy channel structure 3 'is retained, thereby enhancing a supporting function of the dummy channel structure 3'. The source layer 8 is formed to cover the exposed portion Q1 of the channel layer 33 so that electrical contact can be made between the source layer 8 and the end of the channel layer 33 remote from the peripheral circuitry 7. Since the portion of the first conductive portion 54 located in the source layer 8 is covered with the second protective layer 55 and other protective layers, the first conductive portion 54 is electrically isolated from the source layer 8.

In this step, with continued reference to fig. 2L and 2M, a polysilicon layer may be deposited using a thin film deposition process to form the source layer 8. The source layer 8 may be in electrical contact with exposed portions of the channel layer 33, thereby enabling electrical connection of the channel structure 3 to the source layer 8. Illustratively, as shown in fig. 2L and fig. 2M, the source layer 8 surrounds the channel layer 33 at the end of the channel structure 3, which enables the source layer 8 and the channel layer 33 at the end of the channel structure 3 to have a larger contact area, thereby facilitating to increase the reliability of the contact connection and improving the performance of the completed three-dimensional memory.

In some embodiments of the present disclosure, the bottom of the channel structure 3 is exposed by directly removing the material of the substrate 1 at the bottom of the channel, so that the channel layer 33 can be exposed by performing an etching process from the bottom of the channel structure 3, and the electrical connection between the channel layer 33 and the source can be realized by forming the source layer 8. Thus, the situation that holes are formed in the bottom of the channel is avoided, the storage function layer 32 on the side wall of the channel structure 3 is opened by etching for multiple times through the slit, and the process implementation difficulty is greatly reduced.

In some embodiments, with continued reference to fig. 2L, the source layer 8 further covers the exposed end portion of the dummy channel structure 3' and the first protection layer 52 located on the outer sidewall of the first conductive portion 54, the second protection layer 55 located on the end of the first conductive portion 54 away from the peripheral circuit 7, and the third protection layer 56 located in the source layer 8 and located on the outer wall of the first protection layer 52.

In other embodiments, referring to fig. 1D, fig. 1D is a flow chart of another manufacturing method for forming the separation structure 5 and the source layer 8 in the isolation trench 51. Steps S8 and S9 described above are not included after step S7, but steps S80 to S90 are included.

S80, removing the second substrate layer 12, at least part of the third substrate layer 13, the second protective layer 55, part of the first insulating layer 53 and part of the first protective layer 52 to expose an end of the first conductive part 54 away from the peripheral circuit 7.

In this step, referring to fig. 2N and fig. 2O, fig. 2N is a longitudinal sectional structural view of the three-dimensional memory after removing the second passivation layer 55, in which the third substrate layer 13 originally covering the end of the dummy channel structure 3' far from the peripheral circuit 7 is completely removed. Fig. 2O is a longitudinal sectional structural view of another three-dimensional memory after the second protective layer 55 is removed, in which a portion of the third substrate layer 13 covering an end of the dummy channel structure 3' remote from the peripheral circuit 7 remains.

In some examples, second substrate layer 12, at least a portion of third substrate layer 13, second protective layer 55, a portion of first insulating layer 53, and a portion of first protective layer 52 may be removed using, for example, a dry/wet etch process. Referring to fig. 2P, fig. 2P is a schematic diagram of a vertical cross-section of a three-dimensional memory after forming the source layer 8, in which the third substrate layer 13 is completely removed. After removing the third substrate layer 13, an end of the first conductive portion 54 away from the peripheral circuit 7 is exposed, so that the first conductive portion 54 can be electrically connected to the source layer 8.

In some examples, referring to fig. 2N, third substrate layer 13 is completely removed by dry/wet etching.

In some examples, referring to fig. 2O, after etching second substrate layer 12 and before etching third substrate layer 13, further comprising: and setting a mask plate covering the virtual channel structure 3 ' so as to reserve the third substrate layer 13 to cover the part of the virtual channel structure 3 ' far away from one end of the peripheral circuit 7 after etching the third substrate layer 13, thereby strengthening the supporting effect on the virtual channel structure 3 '.

S90, forming a source layer 8 covering the end of the first conductive portion 54 away from the peripheral circuit 7.

In this step, referring to fig. 2P and 2Q, the source layer 8 is formed to cover the exposed portion of the channel layer 33 and the end of the first conductive portion 54 away from the peripheral circuit 7, so that electrical contact can be made between the source layer 8 and the end of the channel layer 33 away from the peripheral circuit 7 and the end of the first conductive portion 54 away from the peripheral circuit 7. Fig. 2Q is a schematic diagram of a longitudinal cross-sectional view of another three-dimensional memory after forming the source layer 8, in which a portion of the third substrate layer 13 covering the dummy channel structure 3' is retained and an end of the first conductive portion 54 away from the peripheral circuit 7 is exposed, thereby facilitating electrical connection of the first conductive portion 54 with the formed source layer 8.

In this step, the source layer 8 is formed in a manner similar to that described above, and will not be described herein.

In some embodiments, prior to the above step S9 (or step S90), the preparation method further comprises: at least the exposed portion of the channel layer 33 is ion-doped, which is of the same type as the source layer 8.

In this step, with continued reference to fig. 2K and 2L, when the source layer 8 is doped with N-type ion dopants, at least the portion of Q1 exposed to the channel layer 33 is doped with N-type ion dopants; when the source layer 8 is doped with P-type ion dopants, at least the portion of Q1 exposed to the channel layer 33 is doped with P-type ion dopants. Since the ion doping types of the two layers are the same, the conductivity between the source layer 8 and the channel layer 33 is improved.

In some embodiments, the same type of ion doping may also be performed on a portion Q2 of the channel layer 33 near the exposed portion Q1 to improve the conductive stability.

In some embodiments, referring to fig. 1E, fig. 1E is a flowchart of a method for manufacturing a three-dimensional memory including the steps of forming a first etch stop layer 91, a second etch stop layer 92, and exposing an end of the channel structure 3 away from the peripheral circuit 7. Step S001 is also included before step S1.

S001, forming a first etching stop layer 91 and a second etching stop layer 92 along the direction far away from the third substrate layer 13 on the side, close to the laminated structure 2, of the third substrate layer 13, wherein the first etching stop layer 91 and the second etching stop layer 92 have different etching selection ratios.

In this step, as shown in fig. 2C, first etch stop layer 91 is formed on the surface of third substrate layer 13, and second etch stop layer 92 is formed on the surface of first etch stop layer 91 remote from third substrate layer 13. By adding the first etching stop layer 91 and the second etching stop layer 92, the etching can be stopped at the first etching stop layer 91 or the second etching stop layer 92, which is beneficial to controlling the process uniformity in the process of removing the third substrate layer 13 and the first etching stop layer 91, thereby ensuring the uniformity of the channel layer 33 after removing part of the memory function layer 32 of the channel structure 3.

Illustratively, the first etch stop layer 91 and the second etch stop layer 92 may be formed using at least one of thin film deposition processes such as CVD, PVD, ALD, and the like. The first etch stop layer 91 may be made of silicon oxide. The second etch stop layer 92 may be optionally made of polysilicon. It should be noted that the first etch stop layer 91 and the second etch stop layer 92 should be made of materials with a predetermined etch selectivity ratio to the material to be etched later, and the first etch stop layer 91 and the second etch stop layer 92 should have different etch selectivity ratios.

Based on this, in some embodiments, and with continued reference to FIG. 1E, the steps of removing the second substrate layer 12 and at least a portion of the third substrate layer 13, in the steps S8 and S80 described above, include steps S81-S82.

S81, etching the second substrate layer 12 and at least part of the third substrate layer 13 to the first etch stop layer 91 to expose the portion of the memory function layer 32 extending into the third substrate layer 13.

Referring to fig. 2J, 2K, 2N and 2O, in this step, the second substrate layer 12 and at least part of the third substrate layer 13 may be removed, for example, by a wet etching process, and the etching may be stopped at the first etch stop layer 91 by selecting a predetermined etchant.

The etching selection ratio of the first etching stopper layer 91 to the memory function layer 32 is the same as or similar to that. For example, the material of the first etching stopper layer 91 is the same as the material of the charge blocking layer 321 of the storage function layer 32, that is, the etching selection ratio of the first etching stopper layer 91 to the storage function layer 32 is the same.

When the material of the first etch stop layer 91 is the same as the material of the charge blocking layer 321 of the memory function layer 32, for example both made of silicon oxide, and the third substrate layer 13 is removed by, for example, a wet etching process, the etching may also be stopped at the charge blocking layer 321, thereby exposing the portion of the memory function layer 32 of the channel structure 3 that extends into the third substrate layer 13. By adding the first etch stop layer 91, it is facilitated to control the process uniformity during the removal of the second substrate layer 12 and at least part of the third substrate layer 13.

S82, the exposed portions of the first etch stop layer 91 and the memory function layer 32 are etched to the second etch stop layer 92 to expose an end of the channel layer 33 remote from the peripheral circuit 7.

With continuing reference to fig. 2J, 2K, 2N, and 2O, in this step, the first etch stop layer 91 may be removed, for example, using a wet etch process, and the etch may be stopped at the second etch stop layer 92 by selecting a predetermined etchant.

The etching selection ratio of the second etching stop layer 92 to the channel layer 33 is the same or similar. For example, the material of the second etch stop layer 92 is the same as the material of the channel layer 33, i.e., the etch selectivity of the second etch stop layer 92 to the channel layer 33 is the same.

When the material of the second etch stop layer 92 is the same as the material of the channel layer 33 of the channel structure 3, e.g., both made of polysilicon, and the first etch stop layer 91 and the memory function layer 32 are removed using, e.g., a wet etching process, the etching may also be stopped at the channel layer 33, thereby exposing portions of the channel layer 33 of the channel structure 3 that extend into the second substrate layer 12 and the third substrate layer 13. By adding the second etch stop layer 92, it is helpful to control the process uniformity during the removal of the first etch stop layer 91 and the memory functional layer 32.

On this basis, for example, the portion of the memory function layer 32 of the channel structure 3 extending into the second etch stop layer 92 may be further removed by controlling the etching time, so as to make the channel layer 33 of the channel structure 3 have a larger exposed area.

In some embodiments, after etching the third substrate layer 13, the portion of the dummy channel structure 3' extending into the third substrate layer 13 is also exposed; during the etching of the exposed portions of the first etch stop layer 91 and the memory function layer 32, at least a portion of the dummy channel structure 3' exposed is removed. For example, fig. 2K, 2M, 2O and 2Q illustrate an example in which the exposed portion of the dummy channel structure 3 'is partially removed, and it is understood that in other examples, the exposed portion of the dummy channel structure 3' may be completely removed.

In some embodiments, with continued reference to fig. 2J, 2K, 2N, and 2O, after etching the third substrate layer 13 and the first etch stop layer 91, the portion of the first conductive structure 61 extending into both the third substrate layer 13 and the first etch stop layer 91 and the portion of the second conductive structure 62 extending into both the third substrate layer 13 and the first etch stop layer 91 are also exposed.

In some embodiments, with continued reference to fig. 2J, 2K, 2N, and 2O, after etching the third substrate layer 13 and the first etch stop layer 91, the portion of the first conductive portion 54 extending into both the third substrate layer 13 and the first etch stop layer 91 is also exposed.

Illustratively, the third substrate layer 13 and the first etching stop layer 91 may be removed by, for example, a wet etching process, and the etching is stopped by selecting a predetermined etchant or controlling the etching time such that the dummy channel structure 3 'extends to the outer surface of the third substrate layer 13 and the first etching stop layer, the first conductive structure 61 extends to the outer surface of the third substrate layer 13 and the first etching stop layer 91, the second conductive structure 62 extends to the outer surface of the third substrate layer 13 and the first etching stop layer 91, and the first conductive part 54 extends to the outer surface of the third substrate layer 13 and the first etching stop layer 91, so as to expose the end of the dummy channel structure 3' extending to the third substrate layer 13 and the first etching stop layer 91, the end of the first conductive structure 61 extending to the third substrate layer 13 and the first etching stop layer 91, and the second conductive part 54 extends to the outer surface of the third substrate layer 13 and the first etching stop layer 91, The second conductive structure 62 extends to the end of both the third substrate layer 13 and the first etch stop layer 91, and the first conductive portion 54 extends to the end of both the third substrate layer 13 and the first etch stop layer 91.

The cross-sectional structure of the three-dimensional memory processed by the process of step S82 is shown in fig. 2J, fig. 2K, fig. 2N, and fig. 2O. The three-dimensional memory formed in fig. 2J and 2N does not have the third substrate layer 13 and the first etch stop layer 91 described above, but still leaves the second etch stop layer 92. The second etch stop layer 92 may also serve as a spacer layer for the stacked structure 2 and the source layer 8 formed in subsequent processes. And by controlling the thickness of the second etch stop layer 92, the distance between the first conductive layer 23 (word line) and the source layer 8 in the stacked-layer structure 2 can be effectively controlled.

In some embodiments, referring to fig. 1F, fig. 1F is a flow chart of a method for fabricating a three-dimensional memory including forming a third passivation layer 56. Step S0001 is further included before the step of filling the sacrificial material 50 in the isolation trench 51 in step S2.

And S0001, forming a third protective layer 56 on at least part of the inner wall of the isolation groove 51.

Wherein the third protective layer 56 covers at least the surface of the third substrate layer 13 exposed in the trenches 51, the surface of the first substrate layer 11 exposed in the trenches 51, and the surface of the second etch stop layer 92 exposed in the trenches 51.

In this step, referring to fig. 2D to 2F, when the materials of the third substrate layer 13, the first substrate layer 11, and the second etching stop layer 92 are the same as the material of the sacrificial material 50, and the sacrificial material 50 in the separation groove 51 is removed by etching, the third protective layer 56 can well stop etching at the third protective layer 56, so as to prevent the third substrate layer 13, the first substrate layer 11, and the second etching stop layer 92 from being etched.

It will be appreciated that the material of the third protective layer 56 is different here from the third substrate layer 13, the first substrate layer 11, the second etch stop layer 92 and the sacrificial material 50. Illustratively, the third substrate layer 13, the first substrate layer 11, the second etch stop layer 92, and the sacrificial material 50 are all made of polysilicon, and the third protective layer 56 is made of silicon oxide.

After the isolation grooves 51 are formed, the third substrate layer 13, the first substrate layer 11 and the second etching stop layer 92 are etched back through the isolation grooves 51, grooves are formed on the third substrate layer 13, the first substrate layer 11 and the second etching stop layer 92 by the side walls of the isolation grooves 51, then the third protective layer 56 is formed by at least one of thin film deposition processes such as CVD, PVD and ALD, and the inner walls of the third protective layer 56 and the inner walls of the isolation grooves 51 are in the same plane, so that the sacrificial material 50 can be well deposited on the side walls of the isolation grooves 51 in the following process.

In some embodiments, referring to fig. 1G, fig. 1G is a flowchart illustrating a method for manufacturing a three-dimensional memory device with a dielectric layer 101, a second conductive portion a1, and a second conductive layer 102. The preparation method of the three-dimensional memory further comprises the following steps: S10-S12

S10, a dielectric layer 101 is formed on the side of the source layer 8 away from the stacked structure 2.

In this step, referring to fig. 2L, 2M, 2P and 2Q, a dielectric material, such as silicon oxide, may be filled on the side of the source layer 8 away from the stacked structure 2 by, for example, a high density plasma chemical vapor deposition process to form the dielectric layer 101. On this basis, the surface of dielectric layer 101 remote from stack 2 may be planarized, for example, using a CMP process.

In some embodiments, referring to fig. 2L, 2M, 2P and 2Q, a dry or wet etching process may be used to remove the portion of the source layer 8 corresponding to the first conductive structure 61 and to remove the portion of the source layer 8 corresponding to the second conductive structure 62 before forming the dielectric layer 101. On this basis, for example, by controlling the etching time, the portion of the second etch stop layer 92 corresponding to the first conductive structure 61 may be removed, and the portion of the second etch stop layer 92 corresponding to the second conductive structure 62 may be removed.

S11, a second conductive portion a1 is formed in the dielectric layer 101, and the second conductive portion a1 is electrically connected to the source layer 8.

In this step, referring to fig. 2L, 2M, 2P and 2Q, a dry or wet etching process may be used to remove a portion of dielectric layer 101 corresponding to source layer 8 (e.g., a portion of dielectric layer 101 corresponding to channel structure 3 in fig. 2L, 2M, 2P and 2Q) to form an open area, and then a conductive material may be deposited in the open area to form a second conductive portion a1 electrically connected to source layer 8.

On this basis, for example, a dry or wet etching process may be used to remove the portion of dielectric layer 101 corresponding to first conductive structure 61 and to remove the portion of dielectric layer 101 corresponding to second conductive structure 62. Thus, an end portion of the first conductive structure 61 and an end portion of the second conductive structure 62 may be exposed, and then a third conductive portion a2 electrically connected to the end portion of the first conductive structure 61 and a fourth conductive portion A3 electrically connected to the end portion of the second conductive structure 62 are formed in the dielectric layer 101, the fourth conductive portion A3 being electrically connected to the peripheral circuit 7 through the second conductive structure 62.

The second conductive portion a1, the third conductive portion a2, and the fourth conductive portion A3 may be formed by a thin film deposition process such as CVD, PVD, ALD, or the like.

In some embodiments, as shown in fig. 2L, 2M, 2P, and 2Q, the dielectric layer 101 separates the source layer 8 from the first and second

conductive structures

61 and 62, preventing direct electrical contact between the source layer 8 and any two of the first and second

conductive structures

61 and 62. Thus, crosstalk between the source layer 8 and the first and second

conductive structures

61 and 62 can be prevented when receiving and transmitting signals.

S12, a second conductive layer 102 is formed on the side of the dielectric layer 101 away from the stacked structure 2, and the second conductive layer 102 is electrically connected to the second conductive portion a 1.

In this step, a thin film deposition process such as CVD, PVD, ALD, etc. may be used to form a metal thin film, and then the metal thin film is subjected to a patterning process (e.g., exposure, development, etc.) to form the second conductive layer 102. Referring to fig. 2L, fig. 2M, fig. 2P and fig. 2Q, the second conductive layer 102 may be electrically connected to the second conductive portion a1 and the third conductive portion a2 at the same time, so as to implement transmission of the source signal.

In some embodiments, referring to fig. 2L, 2M, 2P and 2Q, during the formation of the second conductive layer 102, a fifth conductive portion 102 'is also formed on a side of the dielectric layer 101 away from the stacked-layer structure 2, the fifth conductive portion 102' being electrically connected to the fourth conductive portion a 3. The fifth conductive portion 102' is used for connection to an external circuit.

In some embodiments, the method for manufacturing a three-dimensional memory further comprises: referring to fig. 2L, fig. 2M, fig. 2P and fig. 2Q, the step of forming the blocking layer 103 blocks the fifth conductive part 102 'and the second conductive layer 102, so that signal interference does not easily occur between the fifth conductive part 102' and the second conductive layer 102.

In some embodiments, the present disclosure provides a three-dimensional memory, and the three-dimensional memory 10 provided by some embodiments of the present disclosure is manufactured by the manufacturing method of any one of the embodiments described above. The beneficial effects of the preparation method according to any of the above embodiments can be seen from the above description, and are not described herein again.

Fig. 3A and 3B are top view structural diagrams of a three-dimensional memory according to some embodiments, and fig. 4A to 4D are longitudinal section structural diagrams of a three-dimensional memory according to some embodiments.

In the three-dimensional memory 10 shown in fig. 3A, four three-dimensional memories are included on a wafer, a step area B of one three-dimensional memory is located between two storage areas a, that is, the three-dimensional memory is in an intermediate driving form, and a cutting lane V is further provided between adjacent three-dimensional memories, and the cutting lane V is used for subsequently cutting and separating the plurality of three-dimensional memories; in the three-dimensional memory shown in fig. 3B, the step areas B of one three-dimensional memory are located on both sides of the storage area a, i.e., the three-dimensional memory is in a two-side driving form, and a cutting track V is also arranged between adjacent three-dimensional memories.

Fig. 4A to 4D are longitudinal sectional structural views of four three-dimensional memories prepared by the foregoing preparation method. Referring to fig. 4A to 4D, the three-dimensional memory 10 includes a semiconductor layer 200, a stacked structure 201, a plurality of conductive structures 6, a peripheral circuit 7, and a separation structure 5.

The stacked structure 201 is located at one side of the semiconductor layer 200; the stacked structure 201 includes dielectric layers 201a and conductive layers 201b alternately arranged. The plurality of conductive structures 6 are located on a side of the stacked structure 201 away from the semiconductor layer 200, and at least a portion of the plurality of conductive structures 6 extends into the stacked structure 201. The peripheral circuit 7 is bonded to at least one conductive structure 6 of the plurality of conductive structures 6. The separation structure 5 penetrates the stacked structure 201 and extends into the semiconductor layer 200. The width of the end of the separation structure 5 close to the semiconductor layer 200 is smaller than the width of the end of the separation structure 5 remote from the semiconductor layer 200.

The three-dimensional memory device 10 adopts the manufacturing method described in any of the above embodiments, and in the manufacturing process, since the peripheral circuit 7 is bonded to the plurality of conductive structures 6 on the substrate 1 before the step of removing the sacrificial material 50 in the isolation groove 51 and replacing the sacrificial layer 22 in the stacked structure 2 with the first conductive layer 23, the plurality of conductive structures 6 on the substrate can be well supported before bonding, so that the plurality of conductive structures 6 are not easily dislocated when bonded to the peripheral circuit 7, that is, misalignment errors when the peripheral circuit 7 is bonded to the plurality of conductive structures 6 are improved. It will be appreciated that the plurality of conductive structures 6 are part of the array devices on the substrate 1, and therefore, misalignment errors between the peripheral circuitry 7 and the array devices to be further formed later are also improved. On the basis, the step of replacing the sacrificial layer 22 in the laminated structure 2 with the first conductive layer 23 by removing the sacrificial material 50 in the isolation groove 51 later is also beneficial to reducing the stress generated before bonding, so that the structural deformation when the peripheral circuit 7 is bonded with the conductive structure 6 is reduced, the yield of a three-dimensional memory device product and the stability of the structure and the performance of the three-dimensional memory device product are improved, and the service life of the three-dimensional memory device product is prolonged.

On the other hand, since the width D1 of the partition structure 5 near the end of the semiconductor layer 200 is smaller than the width D2 of the partition structure 5 far from the end of the semiconductor layer 200, the supporting force of the partition structure 5 at the end with the larger width is increased.

In some embodiments, the width of the separation grooves 51 in the separation structure 5 gradually increases in a direction away from the semiconductor layer 200.

The width of the partition groove 51 in the partition structure 5 gradually increases along one direction, so that the size change of the partition groove 51 is gentle, sudden change is avoided, and stress concentration at a certain position of the partition groove 51 is avoided.

It should be noted that fig. 4A to 4D are schematic diagrams, and the width difference of the separation structure 5 along the direction away from the semiconductor layer 200 is not obviously shown. It is understood that the width difference of the separation structures 5 is derived from the width difference of the formed isolation grooves 51, that is, the isolation grooves 51 also have the width difference, and similarly, fig. 2D to 2Q are only schematic diagrams, and the width difference of each of the isolation grooves 51 and the separation structures 5 in the direction away from the semiconductor layer 200 is not clearly shown.

In some embodiments, an air gap 202 is provided in the separation structure 5.

Referring to fig. 4A to 4D, the air gap 202 is disposed in the separation structure 5, and the stress in the separation structure 5 can be released through the air gap 202.

In some embodiments, the air gap 202 extends in a direction perpendicular to the semiconductor layer 200, and a width of a region of the air gap 202 near the semiconductor layer 200 is smaller than a width of a region of the air gap 202 far from the semiconductor layer 200.

With continued reference to fig. 4A-4D, the width of the air gap 202 is configured such that the size of the air gap 202 matches the overall size of the partition structure 5, thereby facilitating better stress relief of the air gap 202 at different locations.

Note that, when forming the first conductive portion 54 in the partition structure 5, a deposition process such as CVD, PVD, ALD, or the like may be employed, and at this time, the first conductive portion 54 starts to grow from the sidewall of the isolation groove 51, so the sidewall of the air gap 202 formed in the middle may have a concave-convex structure corresponding to the inner wall of the isolation groove 51, and fig. 4A to 4D are only schematic diagrams, and do not clearly show the concave-convex structure on the sidewall of the air gap 202.

In some examples, with continued reference to fig. 4A-4D, the width of the air gap 202 generally increases gradually in a direction away from the semiconductor layer 200 (i.e., without considering the concave-convex structure on the sidewall of the air gap 202), i.e., the cross-section of the air gap in fig. 4A-4D is generally isosceles triangle.

With this arrangement, the size of the air gap 202 in the direction away from the semiconductor layer 200 can be gradually changed without generating a sudden change, and the structural stress can be more uniformly released.

FIG. 5 is a block diagram of a storage system 100 according to some embodiments. FIG. 6 is a block diagram of another memory system 100 according to some embodiments. Referring to fig. 5 and 6, some embodiments of the present disclosure also provide a storage system 100. The storage system 100 includes a controller 20 and the three-dimensional memory 10 of some embodiments as above, the controller 20 being coupled to the three-dimensional memory 10 to control the three-dimensional memory 10 to store data. The beneficial effects of the storage system 100 are the same as those of the three-dimensional memory 10 and the method for manufacturing the three-dimensional memory described in any of the above embodiments, and are not described herein again.

Among other things, the Storage system 100 may be integrated into various types of Storage devices, for example, included in the same package (e.g., a Universal Flash Storage (UFS) package or an Embedded multimedia Card (eMMC) package). That is, the storage system 100 may be applied to and packaged into different types of electronic products, such as mobile phones, desktop computers, laptop computers, tablet computers, vehicle computers, game consoles, printers, positioning devices, wearable electronic devices, smart sensors, Virtual Reality (VR) devices, Augmented Reality (AR) devices, or any other suitable electronic device having storage therein.

In some embodiments, referring to fig. 5, the memory system 100 includes a controller 20 and a three-dimensional memory 10, and the memory system 100 may be integrated into a memory card.

The Memory Card includes any one of a PC Card (PCMCIA), a Compact Flash (CF) Card, a Smart Media (SM) Card, a Memory stick, a Multimedia Card (MMC), a Secure Digital Memory Card (SD), and a UFS.

In other embodiments, referring to fig. 6, the storage system 100 includes a controller 20 and a plurality of three-dimensional memories 10 (fig. 4 illustrates four three-dimensional memories as an example), and the storage system 100 is integrated into a Solid State Drive (SSD).

In storage system 100, in some embodiments, controller 20 is configured for operation in a low duty cycle environment, such as an SD card, CF card, Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, mobile phones, and the like.

In other embodiments, the controller 20 is configured for operation in a high duty cycle environment SSD or eMMC for data storage and enterprise storage arrays of mobile devices such as smart phones, tablets, laptops, and the like.

In some embodiments, the controller 20 may be configured to manage data stored in the three-dimensional memory 10 and communicate with an external device (e.g., a host). In some embodiments, the controller 20 may also be configured to control operations of the three-dimensional memory 10, such as read, erase, and program operations. In some embodiments, the controller 20 may also be configured to manage various functions with respect to data stored or to be stored in the three-dimensional memory 10, including at least one of bad block management, garbage collection, logical to physical address translation, wear leveling. In some embodiments, the controller 20 is further configured to process error correction codes with respect to data read from the three-dimensional memory 10 or written to the three-dimensional memory 10.

Of course, the controller 20 may also perform any other suitable function, such as formatting the three-dimensional memory 10. For example, the controller 20 may communicate with an external device (e.g., a host) through at least one of various interface protocols.

It should be noted that the interface protocol includes at least one of a USB protocol, an MMC protocol, a Peripheral Component Interconnect (PCI) protocol, a PCI express (PCI-E) protocol, an Advanced Technology Attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a Small Computer System Interface (SCSI) protocol, an Enhanced Small Disk Interface (ESDI) protocol, an Integrated Drive Electronics (IDE) protocol, and a Firewire protocol.

The controller may be, for example, a Central Processing Unit (CPU), a general purpose Processor, a Digital Signal Processor (DSP), an Application-Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other Programmable logic device, a transistor logic device, a hardware component, or any combination thereof.

The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are also within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.

Claims

1. A method for preparing a three-dimensional memory is characterized by comprising the following steps:

forming a laminated structure on a first side of a substrate, wherein the laminated structure comprises dielectric layers and sacrificial layers which are alternately arranged;

forming an isolation groove which penetrates through the laminated structure and extends into the substrate, and filling a sacrificial material in the isolation groove;

forming a plurality of conductive structures on one side of the laminated structure far away from the substrate; at least some of the plurality of conductive structures extend into the laminate structure;

providing a peripheral circuit, bonding the peripheral circuit to at least one of the plurality of conductive structures;

removing at least part of the substrate to expose the sacrificial material in the isolation grooves;

removing the sacrificial material in the isolation grooves, and replacing the sacrificial layer with a first conductive layer through the isolation grooves so that at least part of the conductive structures in the plurality of conductive structures are electrically connected to the first conductive layer.

2. The production method according to claim 1, wherein the substrate includes a first substrate layer and a second substrate layer which are adjacent to the laminated structure in this order; the second substrate layer and the first substrate layer have different etching selection ratios, and the separation groove extends into the first substrate layer;

the step of removing at least a portion of the substrate to expose the sacrificial material in the spacer trench includes:

and etching the first substrate layer to the second substrate layer to expose the sacrificial material in the isolation groove.

3. The method for manufacturing according to claim 2, further comprising, after the step of replacing the sacrificial layer with the first conductive layer:

sequentially forming a first protective layer and a first insulating layer in the separation groove along the direction far away from the inner wall of the separation groove;

forming a first conductive part on one side of the first insulating layer, which is far away from the first protective layer, and forming a second protective layer which covers one end, which is far away from the peripheral circuit, of the first conductive part;

removing the second substrate layer to expose the second protective layer;

and forming a source electrode layer covering the second protective layer.

4. The method according to claim 2, further comprising, after the step of replacing the sacrificial layer with the first conductive layer:

removing the second substrate layer, the second protective layer, a part of the first insulating layer and a part of the first protective layer to expose one end of the first conductive part far away from the peripheral circuit;

and forming a source electrode layer covering one end of the first conductive part far away from the peripheral circuit.

5. The production method according to claim 3 or 4, wherein the substrate further comprises: a third substrate layer; the third substrate layer is positioned on one side, far away from the first substrate layer, of the second substrate layer; the third substrate layer and the second substrate layer have different etching selection ratios;

after removing the second substrate layer, the method further comprises: removing at least a portion of the third substrate layer.

6. The production method according to claim 5, wherein the laminated structure includes a step region and a storage region;

before the step of forming the isolation trenches extending through the stacked structure and into the substrate, further comprising:

forming a channel hole penetrating through the laminated structure and extending into the third substrate layer in the storage region, and sequentially forming a storage function layer and a channel layer in the channel hole along a direction far away from the inner wall of the channel hole to form a channel structure;

forming a virtual channel hole penetrating through the laminated structure and extending into the first substrate layer in the step area, and filling a dielectric material in the virtual channel hole to form a virtual channel structure;

wherein a portion of the plurality of conductive structures are electrically connected to the channel layer.

7. The method of manufacturing according to claim 6, further comprising, before the step of forming the laminated structure:

sequentially forming a first etching stop layer and a second etching stop layer on one side, close to the laminated structure, of the third substrate layer and along the direction far away from the third substrate layer, wherein the first etching stop layer and the second etching stop layer have different etching selection ratios;

the step of removing the second substrate layer and at least a portion of the third substrate layer comprises:

etching the second substrate layer and at least part of the third substrate layer to the first etching stop layer to expose a part of the storage function layer extending into the third substrate layer;

etching the exposed parts of the first etching stop layer and the memory function layer to the second etching stop layer so as to expose one end of the channel layer far away from the peripheral circuit;

after the source layer is formed, the source layer is electrically connected with one end of the channel layer far away from the peripheral circuit.

8. The method of claim 7, further comprising, prior to the step of forming the source layer:

ion doping at least the exposed portion of the channel layer, the ion doping being of the same type as the doping type of the source layer.

9. The method according to claim 7, wherein before the step of filling the sacrificial material in the isolation trenches, the method further comprises:

forming a third protective layer on at least a part of the inner wall of the isolation groove;

wherein the third protective layer covers at least a surface of the third substrate layer exposed in the cell, a surface of the first substrate layer exposed in the cell, and a surface of the second etch stop layer exposed in the cell.

10. The method of claim 6, further comprising, after etching the second substrate layer and before etching at least a portion of the third substrate layer:

and setting a mask plate covering the virtual channel structure, so that after part of the third substrate layer is etched, the part of the third substrate layer covering the virtual channel structure is reserved.

11. The method of manufacturing according to claim 3 or 4, further comprising, after the step of forming the source layer:

forming a dielectric layer on a side of the source layer away from the stacked structure;

forming a second conductive portion in the dielectric layer, the second conductive portion electrically connected to the source layer;

and forming a second conductive layer on one side of the dielectric layer far away from the laminated structure, wherein the second conductive layer is electrically connected with the second conductive part.

12. The method of manufacturing according to claim 11, wherein the plurality of conductive structures include a first conductive structure and a second conductive structure;

the first conductive structure is electrically connected with the source electrode layer, and the second conductive structure is electrically connected with the peripheral circuit;

after the first substrate layer, the second substrate layer, the third substrate layer and the second etching barrier layer are etched, one ends of the first conductive structure and the second conductive structure far away from the peripheral circuit are exposed;

the dielectric layer separates the source layer from the first and second conductive structures.

13. The production method according to claim 12,

in the process of forming the second conductive part, a third conductive part and a fourth conductive part are further formed in the dielectric layer, the third conductive part is electrically connected with the first conductive structure, and the fourth conductive part is electrically connected with the peripheral circuit; the second conductive layer is also electrically connected to the third conductive portion.

14. The method of claim 13,

in the process of forming the second conductive layer, a fifth conductive part is further formed on one side of the dielectric layer far away from the laminated structure, and the fifth conductive part is electrically connected with the fourth conductive part.

15. A three-dimensional memory, comprising:

a semiconductor layer;

a stacked structure on one side of the semiconductor layer; the stacked structure comprises dielectric layers and conductive layers which are alternately arranged;

a plurality of conductive structures located on a side of the stacked structure away from the semiconductor layer, wherein at least a portion of the plurality of conductive structures extends into the stacked structure;

a peripheral circuit bonded to at least one of the plurality of conductive structures; and the number of the first and second groups,

a separation structure extending through the stacked structure and into the semiconductor layer; the width of one end, close to the semiconductor layer, of the separation structure is smaller than the width of one end, far away from the semiconductor layer, of the separation structure.

16. The three-dimensional memory according to claim 15, wherein the partition structure has an air gap therein.

17. The three-dimensional memory according to claim 16, wherein the air gap extends in a direction perpendicular to the semiconductor layer; the width of a region of the air gap close to the semiconductor layer is smaller than the width of a region of the air gap far from the semiconductor layer.

18. A storage system comprising a three-dimensional memory according to any one of claims 15 to 17 and a controller coupled to the three-dimensional memory to control the three-dimensional memory.