CN114664851A

CN114664851A - Semiconductor structure, manufacturing method thereof, memory, storage system and electronic device

Info

Publication number: CN114664851A
Application number: CN202210220730.7A
Authority: CN
Inventors: 顾妍; 王迪; 张庆福; 周文犀
Original assignee: Yangtze Memory Technologies Co Ltd
Current assignee: Yangtze Memory Technologies Co Ltd
Priority date: 2022-03-08
Filing date: 2022-03-08
Publication date: 2022-06-24

Abstract

The disclosure provides a semiconductor structure, a preparation method thereof, a memory, a storage system and electronic equipment, relates to the technical field of semiconductor chips, and aims to solve the technical problem that the production cost of a three-dimensional memory is high in the prior art. The semiconductor structure includes a stacked structure, a conductive structure, and a conductive plug. The stacked structure includes a core region and a non-core region. The stacked structure includes a plurality of gate layers stacked in a first direction. The multi-layer gate layers are distributed at intervals. The conductive structure is located in the non-core region. The conductive structure includes a first portion and a second portion. The first portion is disposed in a same layer as and in electrical contact with a gate layer. The second portion is in electrical contact with the first portion. The second portion extends upward through the stack structure and encloses the plug opening. An electrically conductive plug is positioned within the plug opening and in electrical contact with the second portion. The semiconductor structure is applied to a three-dimensional memory to realize reading and writing operations of data.

Description

Semiconductor structure, manufacturing method thereof, memory, storage system and electronic device

Technical Field

The present disclosure relates to the field of semiconductor chip technologies, and in particular, to a semiconductor structure, a method for manufacturing the semiconductor structure, a three-dimensional memory, a storage system, and an electronic device.

Background

As the feature size of memory cells approaches the lower process limit, planar processes and fabrication techniques become challenging and costly, which causes the storage density of 2D or planar NAND flash memories to approach the upper limit.

To overcome the limitations imposed by 2D or planar NAND flash memories, memories having a three-dimensional structure (3D NAND) have been developed to increase the storage density by arranging memory cells three-dimensionally over a substrate.

In the prior art, the difficulty and the complexity in electrically connecting the gate layer (i.e., the word line) and the word line contact are high, so that the production cost of the three-dimensional memory is increased.

Disclosure of Invention

Embodiments of the present disclosure provide a semiconductor structure, a method for manufacturing the semiconductor structure, a three-dimensional memory, a storage system, and an electronic device, and aim to solve the problem in the prior art that the production cost of the three-dimensional memory is high.

In order to achieve the above purpose, the embodiments of the present disclosure adopt the following technical solutions:

in one aspect, a semiconductor structure is provided. The semiconductor structure comprises a stacked structure, a conductive structure and a conductive plug. The stacked structure includes a core region and a non-core region. The stacked structure includes a plurality of gate layers stacked in a first direction. The multiple gate layers are distributed at intervals. The conductive structure is located in the non-core region. The conductive structure includes a first portion and a second portion. The first portion is disposed in a same layer as and in electrical contact with a gate layer. The second portion is in electrical contact with the first portion. The second portion extends through the stack structure and encloses the plug opening. An electrically conductive plug is positioned within the plug opening and in electrical contact with the second portion.

In some embodiments of the present disclosure, a semiconductor structure is provided in which a first portion of a conductive structure is disposed in a same layer as and in electrical contact with a gate layer, a second portion is in electrical contact with the first portion, and the second portion extends upwardly through the stacked structure, such that the conductive structure can be embedded within the stacked structure and in electrical contact with the gate layer.

Therefore, the grid layer can be electrically connected with other parts (such as subsequently formed word line contacts) through the conductive structure, a step structure is not needed, the problem that the word line Contact holes are difficult to align with the step structure is solved, the conductive structure is electrically connected with the grid layer through an SCT (Chinese name: Self-aligned Contact, and English name: SCT for short), the manufacturing process is simplified, and the production cost of the semiconductor structure is reduced.

In addition, the second part encloses a plug opening, a conductive plug is arranged in the plug opening and is electrically contacted with the second part, so that the subsequently formed word line contact can be electrically connected with the gate layer through at least one of the conductive plug and the conductive structure. That is, the word line contact may be disposed in electrical contact with an end surface of the second portion of the conductive structure remote from the first portion, the word line contact may be disposed in electrical contact with a surface of the conductive plug remote from the stacked structure, the word line contact may be disposed in electrical contact with both an end surface of the second portion of the conductive structure remote from the first portion, and a surface of the conductive plug remote from the stacked structure.

According to the arrangement, on one hand, the contact area of the subsequently formed word line contact and the grid layer in the electric connection process is increased, namely, the landing window of the word line contact and the grid layer in the electric connection process is increased, the convenience of the electric connection between the word line contact and the grid layer is improved, the manufacturing process is simplified, the production cost of the semiconductor structure is reduced, and therefore the production cost of the three-dimensional memory is reduced.

On the other hand, the contact area between the word line contact and the conductive structure during electric connection is increased, the resistance between the word line contact and the grid layer can be reduced, and the reliability of electric signal transmission is improved.

In another aspect, the word line contact is electrically connected with the gate layer through the conductive plug and the conductive structure, and no other conductive structure is required to be arranged between the word line contact and the conductive plug, so that the structure of the semiconductor structure is simplified, and the cost of the semiconductor structure is further reduced.

In another aspect, the conductive plug is disposed in the plug opening, so that the conductive plug can be embedded in the conductive structure, and no additional interlayer structure is required to be disposed to accommodate the conductive plug, so that the SCT architecture can be combined with the conductive plug, thereby further simplifying the structure of the semiconductor structure and reducing the cost of the semiconductor structure.

In some embodiments, the semiconductor structure further comprises a first dielectric layer. The first dielectric layer is located on the stacking structure. The first dielectric layer is provided with a first opening, the end part of the second part far away from the first part and the conductive plug are positioned in the first opening.

In some embodiments, the first dielectric layer further has a second opening. The semiconductor structure also includes a channel structure and a channel contact. The channel structure is located in the core region and penetrates through the stacked structure. A channel contact is located within the second opening and is in electrical contact with an end of the channel structure proximate the first dielectric layer.

In some embodiments, the conductive plug and the channel contact are of the same material at the same layer.

In some embodiments, the second portion includes an extension. The first end of the extension is in electrical contact with the first portion and the second end of the extension encloses the plug opening.

In some embodiments, the second portion further comprises a contact. The contact portion is located in an opening surrounded by the first end of the extension portion, and the contact portion is in electrical contact with the first portion and the extension portion.

In some embodiments, the area of the opening of the plug is larger than the area of the opening surrounded by the first end of the extension portion, and the area of the orthographic projection of the first portion on the reference surface is larger than the area of the opening surrounded by the first end of the extension portion. Wherein the reference plane is parallel to the multilayer gate layer.

In some embodiments, the semiconductor structure further comprises an electrical isolation layer. An electrically isolating layer is located between the second portion and the stacked structure.

In some embodiments, the conductive structure and the conductive plug are enclosed to form a receiving cavity. The semiconductor structure also includes an insulating material. The insulating material is filled in the accommodating cavity.

In some embodiments, the receiving cavity has an air gap therein.

In some embodiments, the stacked structure comprises a memory stack structure. The multi-layer gate layer is located in the memory stack structure. The storage stack structure further comprises a plurality of gate insulating layers, and the gate insulating layers and the gate electrode layers are alternately stacked. The channel structure includes a memory channel structure. The memory channel structure extends through the memory stack structure. The memory channel structure includes at least a memory functional layer and a channel layer sequentially distant from the multi-layer gate layer.

In some embodiments, the stacked structure further comprises a selective stack structure. The selection stack is located above the memory stack. The selective laminated structure comprises an insulating medium layer, a first conducting layer and a second medium layer which are sequentially arranged. The insulating dielectric layer extends from the core region to the non-core region, and the first conductive layer and the second dielectric layer are located in the core region. The channel structure further includes a select channel structure. The selection channel structure penetrates through the selection stack structure and is in electrical contact with an end portion of the memory channel structure in the first direction. The selection channel structure includes at least an insulating layer and a second conductive layer sequentially distant from the first conductive layer.

In some embodiments, the semiconductor structure further comprises a semiconductor structure layer. The semiconductor structure layer is positioned on one side of the stacking structure far away from the first dielectric layer.

In some embodiments, the semiconductor structure further comprises a plurality of dummy channel structures. The plurality of virtual channel structures are positioned in the non-core region and penetrate through the stacked structure.

In another aspect, a method of fabricating a semiconductor structure is provided. A method of fabricating a semiconductor structure includes forming an initial stack structure on one side of a substrate. The initial stacked structure has a core region and a non-core region. The initial stacked structure includes a plurality of gate sacrificial layers stacked in a first direction. The multilayer grid sacrificial layers are distributed at intervals. Wherein the first direction is perpendicular to the substrate. Forming a conductive structure. The conductive structure is located in the non-core region. The conductive structure includes a first portion and a second portion. The first portion is disposed on and in contact with a gate sacrificial layer. The second portion is in electrical contact with the first portion. The second portion extends upwardly through the initial stack structure and encloses a plug opening. And forming a conductive plug. An electrically conductive plug is positioned within the plug opening and in electrical contact with the second portion.

In some embodiments, before the step of forming the conductive structure, forming a first dielectric film is further included. A first dielectric film is over the initial stack. The step of forming the conductive structure includes forming a first contact hole in the non-core region, the first contact hole penetrating through the first dielectric film and exposing the target gate sacrificial layer. The target gate sacrificial layer is one of the plurality of gate sacrificial layers. And removing part of the target gate sacrificial layer through the first contact hole to form an epitaxial contact hole. A first portion is formed within the epitaxial contact hole. A second portion is formed within the first contact hole, the second portion being in electrical contact with the first portion.

In some embodiments, the initial stacked structure further includes a plurality of gate insulating layers, the gate insulating layers and the gate sacrificial layers being alternately stacked. The step of forming the first contact hole in the non-core region includes forming an initial contact hole in the non-core region. The initial contact hole penetrates through the first dielectric film and exposes the target gate insulating layer. The target gate insulating layer is one of the plurality of gate insulating layers. And forming an electrical isolation film in the initial contact hole. The bottom wall of the electrical isolation film and a part of the target gate insulating layer are removed to form an electrical isolation layer, and a first contact hole exposing the target gate sacrificial layer is formed inside the electrical isolation layer.

In some embodiments, after the step of forming the second portion in the first contact hole, filling the second portion with an insulating material is further included.

In some embodiments, the forming of the second portion in the first contact hole and the filling of the insulating material in the second portion include forming a first conductive film. The first conductive film includes a first sub-film covering the first dielectric film and a second sub-film covering the sidewall and the first portion of the first contact hole. An insulating material is deposited. An insulating material fills the cavity defined by the second sub-film, and the insulating material covers the first sub-film. And etching the insulating material to the first sub-film to remove part of the insulating material in the cavity defined by the second sub-film and the insulating material covering the first sub-film. And removing the first sub-film and the end part of the second sub-film beyond the surface of the first dielectric film far away from the substrate to form a second part.

In some embodiments, after the step of forming the first dielectric film and before the step of forming the first contact hole in the non-core region, forming a stop layer is further included. The stop layer covers the first dielectric film. And forming a first contact hole in the non-core region, wherein the first contact hole penetrates through the stop layer and the first dielectric film and exposes the target grid sacrificial layer. The forming of the second portion in the first contact hole and the filling of the insulating material in the second portion include forming a second conductive film including a third sub-film and a fourth sub-film. The third sub-film covers the stop layer, and the fourth sub-film covers the sidewalls and the first portion of the first contact hole. And removing the third sub-film to expose the stop layer. And depositing an insulating material, wherein the insulating material fills the cavity defined by the fourth sub-film, and the insulating material covers the stop layer. And etching the insulating material to at least part of the stop layer to remove part of the insulating material in the cavity defined by the fourth sub-film and the insulating material covering the stop layer. And removing the rest part of the stop layer to expose the first dielectric film. And removing the end part of the fourth sub-film beyond the surface of the first dielectric film on the side far away from the substrate to form a second part.

In some embodiments, the step of forming the stop layer includes forming a first stop layer on a side of the first dielectric film away from the initial stack structure. And forming a first protective layer, wherein the first protective layer is positioned on one side of the first stop layer, which is far away from the first dielectric film. The step of etching the insulating material to at least a portion of the stop layer includes etching the insulating material and the first protective layer to the first stop layer. The step of removing the remaining portion of the stop layer includes removing the first stop layer.

In some embodiments, the semiconductor structure further comprises a channel structure. The channel structure is located in the core region and penetrates through the initial stacked structure. The preparation method of the semiconductor structure further comprises the step of forming a second opening on the first dielectric film to prepare a first dielectric layer. The second opening exposes an end of the channel structure away from the substrate. The step of forming the conductive plug further includes forming a channel contact in electrical contact with an end of the channel structure proximate the first dielectric layer.

In some embodiments, the step of forming the second opening in the first dielectric film includes forming a mask on a side of the first dielectric film away from the initial stacked structure, the mask having an etching opening. And forming a second opening on the first dielectric film by utilizing the etching opening of the mask.

In some embodiments, the step of forming a mask on a side of the first dielectric film remote from the initial stack structure includes forming a hard mask, the hard mask overlying the first dielectric film. And forming a photoresist film, wherein the photoresist film covers the hard mask. An etch opening is formed through the photoresist film and the hard mask.

In some embodiments, after the step of forming the conductive plug, forming a gate line slit through the initial stacked structure is further included. A gate line gap separates the core region of an initial stacked structure into two initial memory blocks. And replacing the grid sacrificial layer with a grid layer through the grid line gap to form a stacked structure and a storage block. Wherein the gate layer is in electrical contact with the first portion.

In some embodiments, prior to the step of forming the conductive structure, forming a gate line slit through the initial stacked structure is further included. A gate line gap separates the core region of an initial stacked structure into two initial memory blocks. And replacing the grid sacrificial layer in the core region with the first grid layer through the grid line gap. After the step of forming the conductive plug, the method further comprises replacing a part of the gate sacrificial layer which is arranged on the same layer as and in contact with the first part with a second gate layer through the gate line gap to form a stacked structure and a memory block. Wherein the second gate layer is in electrical contact with the first gate layer and the first portion.

In yet another aspect, a three-dimensional memory is provided. The three-dimensional memory includes the semiconductor structure of some embodiments as above, and a peripheral device electrically connected to the semiconductor structure.

In yet another aspect, a storage system is provided, which includes the three-dimensional memory as above, and a controller coupled to the three-dimensional memory to control the three-dimensional memory to store data.

In yet another aspect, an electronic device is provided, which includes the storage system as above.

It can be understood that, in the manufacturing method of the semiconductor structure, the three-dimensional memory, the storage system and the electronic device provided in the embodiments of the disclosure, reference may be made to the above beneficial effects of the semiconductor structure, and details are not described herein again.

Drawings

In order to more clearly illustrate the technical solutions of the present disclosure, the drawings required to be used in some embodiments of the present disclosure will be briefly described below, and it is apparent that the drawings in the following description are only drawings of some embodiments of the present disclosure, and other drawings can be obtained by those skilled in the art according to these drawings. Furthermore, the drawings in the following description may be considered as schematic diagrams, and do not limit the actual size of products, the actual flow of methods, the actual timing of signals, and the like, involved in the embodiments of the present disclosure.

FIG. 1 is a perspective block diagram of a three-dimensional memory according to some embodiments;

FIG. 2 is a cross-sectional view of a three-dimensional memory according to some embodiments;

FIG. 3 is a cross-sectional view of a memory cell string of the three-dimensional memory of FIG. 1 along section line AA';

FIG. 4 is an equivalent circuit diagram of a memory cell string;

FIG. 5 is a block diagram of a semiconductor structure according to some embodiments;

FIG. 6 is a block diagram of a semiconductor structure according to further embodiments;

FIG. 7 is a sectional view taken along A-A of FIG. 5;

FIG. 8 is a sectional view taken along the line B-B in FIG. 5;

FIG. 9 is a block diagram of a conductive structure according to some embodiments;

FIG. 10 is a block diagram of a conductive structure and a conductive plug according to some embodiments;

FIG. 11 is a block diagram of a stacked structure according to some embodiments;

FIG. 12 is a block diagram of a channel structure according to some embodiments;

FIG. 13 is a block diagram of a stacked configuration according to further embodiments;

FIG. 14 is a flow chart of method steps for fabricating a semiconductor structure according to some embodiments;

FIG. 15 is a block diagram of an initial stack structure according to some embodiments;

FIG. 16 is a block diagram of a semiconductor structure according to yet further embodiments;

fig. 17 is a structural diagram of a first dielectric film according to some embodiments;

FIG. 18 is a flow chart of method steps for fabricating a semiconductor structure according to further embodiments;

FIG. 19 is a block diagram of a first contact hole according to some embodiments;

FIG. 20 is a block diagram of a first contact hole according to other embodiments;

FIG. 21 is a block diagram of a first contact hole according to yet other embodiments;

FIG. 22 is a block diagram of a first portion according to some embodiments;

FIG. 23 is a block diagram of a conductive structure according to further embodiments;

FIG. 24 is a flow chart of method steps for fabricating a semiconductor structure according to yet further embodiments;

FIG. 25 is a block diagram of an initial contact hole according to some embodiments;

FIG. 26 is a block diagram of an electrical isolation diaphragm according to some embodiments;

FIG. 27 is a fill pattern of an insulating material according to some embodiments;

FIG. 28 is a flow chart of method steps for fabricating a semiconductor structure according to still further embodiments;

fig. 29 is a structural diagram of a first conductive film according to some embodiments;

FIG. 30 is a fill pattern of an insulating material according to further embodiments;

FIG. 31 is a fill pattern of an insulating material according to still further embodiments;

FIG. 32 is a block diagram of a stop layer according to some embodiments;

FIG. 33 is a block diagram of initial contact holes according to further embodiments;

FIG. 34 is a block diagram of a first contact hole according to yet other embodiments;

FIG. 35 is a flow chart of method steps for fabricating a semiconductor structure according to yet further embodiments;

fig. 36 is a structural view of a second conductive film according to some embodiments;

FIG. 37 is a block diagram of a fourth sub-film according to some embodiments;

FIG. 38 is a fill pattern of an insulating material according to still further embodiments;

FIG. 39 is a fill pattern of an insulating material according to still other embodiments;

FIG. 40 is a fill pattern of an insulating material according to still other embodiments;

FIG. 41 is a fill pattern of an insulating material according to still other embodiments;

FIG. 42 is a block diagram of a channel structure according to further embodiments;

FIG. 43 is a block diagram of an initial stack structure according to further embodiments;

FIG. 44 is a block diagram of a first dielectric layer according to some embodiments;

FIG. 45 is a block diagram of a semiconductor structure according to still further embodiments;

FIG. 46 is a flow chart of method steps for fabricating a semiconductor structure according to yet further embodiments;

FIG. 47 is a block diagram of a reticle according to some embodiments;

FIG. 48 is a flow chart of method steps for fabricating a semiconductor structure according to still further embodiments;

FIG. 49 is a block diagram of a reticle according to further embodiments;

FIG. 50 is a block diagram of a reticle according to further embodiments;

FIG. 51 is a block diagram of a reticle according to further embodiments;

FIG. 52 is a block diagram of a fourth sub-film according to other embodiments;

FIG. 53 is a flow chart of method steps for fabricating a semiconductor structure according to yet further embodiments;

fig. 54 is a block diagram of a first gate layer according to some embodiments;

fig. 55 is a block diagram of a first gate layer and a second gate layer according to some embodiments;

FIG. 56 is a block diagram of a storage system according to some embodiments;

FIG. 57 is a block diagram of memory systems according to further embodiments.

Detailed Description

Technical solutions in some embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings, and it is obvious that the described embodiments are only a part of the embodiments of the present disclosure, and not all of the embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments provided by the present disclosure belong to the protection scope of the present disclosure.

In the description of the present disclosure, it is to be understood that the terms "center", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like indicate orientations or positional relationships based on those shown in the drawings, merely for convenience in describing the present disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed in a particular orientation, and be operated, and therefore, should not be construed as limiting the present disclosure.

Throughout the specification and claims, the term "comprising" is to be interpreted in an open, inclusive sense, i.e., as "including, but not limited to," unless the context requires otherwise. In the description herein, the terms "one embodiment," "some embodiments," "an example embodiment," "exemplary" or "some examples" or the like are intended to mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the disclosure. The schematic representations of the above terms are not necessarily referring to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be included in any suitable manner in any one or more embodiments or examples.

In the following, the terms "first", "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the embodiments of the present disclosure, "a plurality" means two or more unless otherwise specified.

In describing some embodiments, expressions of "coupled" and "connected," along with their derivatives, may be used. For example, the term "connected" may be used in describing some embodiments to indicate that two or more elements are in direct physical or electrical contact with each other. As another example, some embodiments may be described using the term "coupled" to indicate that two or more elements are in direct physical or electrical contact. The term "coupled," however, may also mean that two or more elements are not in direct contact with each other, but yet still co-operate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents herein.

"at least one of A, B and C" has the same meaning as "A, B or at least one of C", both including the following combination of A, B and C: a alone, B alone, C alone, a combination of a and B, a combination of a and C, a combination of B and C, and a combination of A, B and C.

"A and/or B" includes the following three combinations: a alone, B alone, and a combination of A and B.

The use of "adapted to" or "configured to" herein is meant to be an open and inclusive language that does not exclude devices adapted to or configured to perform additional tasks or steps.

Additionally, the use of "based on" means open and inclusive, as a process, step, calculation, or other action that is "based on" one or more stated conditions or values may in practice be based on additional conditions or values beyond those stated.

As used herein, "approximate" includes the stated value as well as an average value that is within an acceptable deviation range for the particular value, as determined by one of ordinary skill in the art in view of the measurement in question and the error associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

In the context of this disclosure, the meaning of "on … …," above, "and" over "should be interpreted in the broadest manner such that" on.

Example embodiments are described herein with reference to cross-sectional and/or plan views as idealized example figures. In the drawings, the thickness of layers and regions are exaggerated for clarity. Variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, the exemplary embodiments should not be construed as limited to the shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the exemplary embodiments.

As used herein, the term "substrate" refers to a material onto which subsequent layers of material may be added. The substrate itself may be patterned. The material added on the substrate may be patterned or may remain unpatterned. In addition, the substrate may include a variety of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, and the like. Alternatively, the substrate may be made of a non-conductive material such as glass, plastic, or sapphire wafer.

The term "three-dimensional memory" refers to a semiconductor device formed of strings of memory cell transistors (referred to herein as "strings of memory cells," e.g., NAND memory cells) arranged in an array on a major surface of a substrate or a source layer and extending in a direction perpendicular to the substrate or source layer. As used herein, the term "vertically" means nominally perpendicular to a major surface (i.e., a lateral surface) of the substrate or source layer.

Fig. 1 is a perspective view of a three-dimensional memory according to some embodiments of the present disclosure, fig. 2 is a cross-sectional view of the three-dimensional memory, fig. 3 is a cross-sectional view of a memory cell string of the three-dimensional memory shown in fig. 1 along a section line AA', and fig. 4 is an equivalent circuit diagram of the memory cell string.

In fig. 1 and 2, the three-dimensional memory 10 extends in an X-Y plane, and the first direction X and the second direction Y are, for example, two orthogonal directions in a plane in which the semiconductor structure 200 is located (for example, a plane in which a Source Layer SL is located, Source Layer, SL): the first direction X is, for example, an extending direction of a Word Line (WL), and the second direction Y is, for example, an extending direction of a Bit Line (BL). The third direction Z is perpendicular to the plane of the semiconductor structure 200, i.e., perpendicular to the X-Y plane.

As used in this disclosure, whether a component (e.g., a layer, structure, or device) is "on," "above," or "below" another component (e.g., a layer, structure, or device) of a semiconductor device (e.g., a three-dimensional memory) is determined in a third direction Z relative to a substrate or a source layer of the semiconductor device when the substrate or the source layer is located in a lowest plane of the semiconductor device in the third direction Z. Throughout this disclosure, the same concepts are applied to describe spatial relationships.

In order to show the structure of the device more clearly, in fig. 2, a view of the array area CA and a view of the step area SS are shown, the view of the array area CA is based on a left-side coordinate system, the view of the step area SS is based on the left-side coordinate system, that is, the view of the array area CA shows a cross-sectional structure along the Y direction, and the view of the step area SS shows a cross-sectional structure along the X direction.

Referring to fig. 1 and 2, some embodiments of the present disclosure provide a three-dimensional memory 10. The three-dimensional memory 10 may include a semiconductor structure 200 and a peripheral device 100 coupled to the semiconductor structure 200. Where the semiconductor structure 200 includes a source layer SL, the peripheral device 100 may be disposed on a side away from the source layer SL.

The source layer SL may include a semiconductor material such as single crystal silicon, single crystal germanium, a III-V compound semiconductor material, a II-VI compound semiconductor material, and other suitable semiconductor materials. The source layer SL may be partially or fully doped. Illustratively, the source layer SL may include a doped region doped with a p-type dopant. The source layer SL may further include an undoped region.

The semiconductor structure 200 may include memory cell transistor strings (referred to herein as "memory cell strings," e.g., NAND memory cell strings) 400 arranged in an array. The source layer SL may be coupled to sources of the plurality of memory cell strings 400.

Specifically, referring to fig. 3 and 4, the memory cell string 400 may include a plurality of transistors T, and one transistor T (e.g., T1 to T6 in fig. 4) may be provided as one memory cell, and the transistors T are connected together to form the memory cell string. One transistor T (e.g., each transistor T) may be formed of a semiconductor channel 241 and one gate line G surrounding the semiconductor channel 241. Wherein the gate line G is configured to control a turn-on state of the transistor.

It should be noted that the numbers of the transistors in fig. 1 to fig. 4 are only schematic, and the memory cell string of the three-dimensional memory provided by the embodiment of the present disclosure may further include other numbers of transistors, for example, 4, 16, 32, and 64.

Further, along the third direction Z, a lowermost gate line of the gate lines G (e.g., a gate line closest to the source layer SL of the gate lines G) is configured as a source select gate SGS, and the source select gate SGS is configured to control the on-state of the transistor T6, and thus the on-state of the source channel in the memory cell string 400. The uppermost gate line among the plurality of gate lines G (e.g., the gate line farthest from the source layer SL among the plurality of gate lines G) is configured as a drain select gate SGD configured to control the on-state of the transistor T1, thereby controlling the on-state of the drain channel in the memory cell string 400. The gate line in the middle of the plurality of gate lines G may be configured as a plurality of word lines WL, including, for example, word line WL0, word line WL1, word line WL2, and word line WL 3. Writing, reading, and erasing of data to individual memory cells (e.g., transistors T) in the memory cell string 400 may be accomplished by writing different voltages on the word lines WL.

With continued reference to fig. 1 and 2, in some embodiments, the semiconductor structure 200 may further include an array interconnect layer 290. Array interconnect layer 290 may be coupled with memory cell string 400. The array interconnect layer 290 may include a drain terminal (i.e., a bit line BL) of the memory cell string 400, which may be coupled to a semiconductor channel of each transistor T in at least one memory cell string 400.

The array interconnect layer 290 may include one or more first interlayer insulating layers 292, and may further include a plurality of contacts insulated from each other by the first interlayer insulating layers 292, the contacts including, for example, bit line contacts BL-CNT coupled to the bit lines BL; a drain select gate contact SGD-CNT coupled to drain select gate SGD. The array interconnect layer 290 may also include one or more first interconnect conductor layers 291. The first interconnect conductor layer 291 may include a plurality of connection lines, such as bit lines BL, and word line connection lines WL-CL coupled to word lines WL. The material of the first interconnect conductor layer 291 and the contacts may be a conductive material such as a combination of one or more of tungsten, cobalt, copper, aluminum, and metal silicide, and may be other suitable materials. The material of the first interlayer insulating layer 292 is an insulating material, such as silicon oxide, silicon nitride, and a combination of one or more of high-k insulating materials, and may be other suitable materials.

The peripheral device 100 may include peripheral circuitry. The peripheral circuitry is configured to control and sense the array device. The peripheral circuitry may be any suitable digital, analog, and/or mixed signal control and sensing circuitry for supporting array device operation (or working), including but not limited to page buffers, decoders (e.g., row and column decoders), sense amplifiers, drivers (e.g., word line drivers), charge pumps, current or voltage references, or any active or passive component of circuitry (e.g., transistors, diodes, resistors, or capacitors). The peripheral circuits may also include any other circuits compatible with advanced Logic processes, including Logic circuits (e.g., processors and Programmable Logic Devices (PLDs) or Memory circuits (e.g., Static Random-Access memories (SRAMs)).

Specifically, in some embodiments, the peripheral device 100 may include a substrate 110, a transistor 120 disposed on the substrate 110, and a peripheral interconnect layer 130 disposed on the substrate 110. The peripheral circuitry may include a transistor 120.

The material of the substrate 110 may be monocrystalline silicon, or may be other suitable materials, such as silicon germanium, or a silicon-on-insulator thin film.

Peripheral interconnect layer 130 is coupled to transistor 120 to enable the transmission of electrical signals between transistor 120 and peripheral interconnect layer 130. The peripheral interconnection layer 130 may include one or more second interlayer insulating layers 131 and may further include one or more second interconnection conductor layers 132. Different second interconnect conductor layers 132 may be coupled to each other by contacts. The material of the second interconnect conductor layer 132 and the contacts may be a conductive material, such as a combination of one or more of tungsten, cobalt, copper, aluminum, and metal silicide, and may be other suitable materials. The material of the second interlayer insulating layer 131 is an insulating material, such as one or a combination of silicon oxide, silicon nitride, and a high-k insulating material, and may be other suitable materials.

The peripheral interconnect layer 130 may be coupled with the array interconnect layer 290 such that the semiconductor structure 200 and the peripheral device 100 may be coupled. Specifically, since the peripheral interconnect layer 130 is coupled to the array interconnect layer 290, peripheral circuits in the peripheral device 100 may be coupled to the memory cell strings in the semiconductor structure 200 to enable transmission of electrical signals between the peripheral circuits and the memory cell strings. In some possible implementations, a bonding interface 500 may be disposed between the peripheral interconnection layer 130 and the array interconnection layer 290, and the peripheral interconnection layer 130 and the array interconnection layer 290 may be bonded and coupled to each other through the bonding interface 500.

Referring again to fig. 1 and 2, in some implementations, a word line contact hole is typically opened in the step region SS, and a conductive structure is disposed in the word line contact hole and electrically contacts the gate layer (i.e., the word line WL). The word line contact is in electrical contact with the conductive structure and the word line connection line WL-CL is in electrical contact with the word line contact such that an electrical signal can be transmitted between the word line connection line WL-CL and the gate layer.

However, it is not easy to realize that the word line contact hole just falls on the step structure during the manufacturing process. The non-complete etching (hereinafter referred to as "under Through") or the Punch-Through etching (hereinafter referred to as "Punch Through") is a commonly occurring defect, which increases the difficulty of electrical contact between the conductive structure and the gate layer, thereby increasing the process complexity of the semiconductor structure 200 and resulting in an increase in the production cost of the three-dimensional memory 10.

In other implementations, electrical Contact between the gate layer and the wordline contacts is achieved through a self-aligned Contact (SCT) architecture. The SCT architecture does not form a ladder structure, but embeds a conductive structure in a non-core region (i.e., a ladder region SS), and leads out a gate layer (i.e., a word line WL) through the conductive structure to electrically connect the gate layer and a word line contact. The word line connection lines WL-CL are in electrical contact with the word line contacts so that electrical signals can be transmitted between the word line connection lines WL-CL and the gate layer.

In some examples, the conductive structures in the SCT architecture are formed from a thicker conductive material (e.g., metallic tungsten). However, the inventors of the present disclosure have found that forming a thick conductive structure with a single conductive material can cause large stress variation, which can seriously deteriorate the stress state of the wafer (i.e., the substrate), and even cause defects such as wafer cracks.

In other examples, the conductive structures in the SCT architecture include a conductive layer and an insulating layer to reduce the stress effect of a single conductive material when forming thicker conductive structures. Illustratively, the insulating layer is located at a central portion of the conductive layer, and the conductive layer may be formed in a ring shape to surround the insulating layer. However, the inventors of the present disclosure have found that, since the insulating layer is not conductive, when the conductive structure is electrically connected to the word line contact, the word line contact can only land on the annular conductive layer, and the presence of the insulating layer occupies the landing window, which increases the difficulty of electrical connection between the word line contact and the gate layer. In addition, in the case where the conductive layer is deposited less, the thickness of the conductive layer may be thinner, and a portion of the word line contact may land on the insulating layer, resulting in an increase in contact resistance between the word line contact and the gate layer.

As can be seen from the above, the difficulty of electrical contact between the conductive structure and the word line contact is high, that is, the difficulty of electrical connection between the gate layer and the word line contact is high, so that the process complexity of the semiconductor structure 200 is increased, and the production cost of the three-dimensional memory 10 is increased.

In order to solve the above problem, some embodiments of the present disclosure provide a semiconductor structure 200, and the semiconductor structure 200 provided by some embodiments of the present disclosure is illustrated below with reference to fig. 5 to 13.

Fig. 5 is a block diagram of a semiconductor structure according to some embodiments. FIG. 6 is a block diagram of a semiconductor structure according to further embodiments. Fig. 7 is a sectional view along a-a of fig. 5. Fig. 8 is a sectional view along B-B of fig. 5.

In some embodiments, as shown in fig. 5, the semiconductor structure 200 includes a stacked structure 210. As shown in fig. 6, the stacked structure 210 has a core region and a non-core region.

In some examples, as shown in fig. 7, the semiconductor structure 200 further includes a substrate 201, and the stacked structure 210 is located on one side of the substrate 201. It is understood that the substrate 201 includes a source layer SL. On this basis, the base 201 may further include a substrate 260, and the substrate 260 is located on a side of the source layer SL far from the stacked structure 210.

In some embodiments, substrate 260 may include at least one of single crystal silicon, polycrystalline silicon, single crystal germanium, a group III-V compound semiconductor material, a group II-VI compound semiconductor material, or other semiconductor materials known in the art.

In some embodiments, the substrate 260 may be a single layer structure, and in other embodiments, the substrate 260 may also be a multi-layer composite structure. For example, when the substrate 260 has a multi-layer composite structure, the substrate 260 may include silicon oxide layers and polysilicon layers alternately stacked.

Illustratively, as shown in fig. 7, the stacked structure 210 includes at least two materials alternately stacked in the first direction. In some embodiments, the stacked number of layers of the stacked structure 210 may be 4, 16, 32, 64, or 128 layers. The number of layers of the stacked structure 210 is not further limited by the embodiments of the present disclosure.

In some embodiments, as shown in fig. 7, the stacked structure 210 includes a plurality of gate layers 2211 stacked in a first direction. The gate layers 2211 are spaced apart, and it is understood that each gate layer 2211 extends from the core region to the non-core region.

Illustratively, as shown in fig. 7, the first direction is a direction perpendicular or approximately perpendicular to the substrate 201.

As shown in fig. 7, the core region is disposed adjacent to the non-core region. The core region is used to store data and the non-core region is used to electrically connect gate layer 2211 (i.e., word line WL) to word line contact V0.

In some embodiments, the number of core and non-core regions may be plural. The core area may be disposed between two non-core areas, and the plurality of core areas may be disposed at intervals from the plurality of non-core areas.

It is understood that the plurality of gate layers 2211 are stacked and spaced along the first direction, and each gate layer 2211 extends from the core region to the non-core region, so that an electrical connection between the core region and the non-core region can be realized through each gate layer 2211. Thus, by electrically connecting the word line contact V0 to the gate layer 2211 located in the non-core region, data writing, reading, erasing, and the like can be realized.

In some embodiments, the material of gate layer 2211 includes at least one of tungsten, cobalt, copper, aluminum, doped polysilicon, and metal silicide. The material and thickness of each gate layer 2211 may be the same or different.

To electrically connect gate layer 2211 located in the non-core region with word line contact V0, in some embodiments, semiconductor structure 200 further includes conductive structure 230 and conductive plug 240, as shown in fig. 7. The conductive structure 230 is located in the non-core region, and the conductive plug 240 is located in a plug opening 242 formed in the conductive structure 230.

In some embodiments, as shown in fig. 7, the conductive structure 230 includes a first portion 231 and a second portion 232. As shown in fig. 8, the first portion 231 is disposed on the same layer as and in electrical contact with the gate layer 2211, that is, the first portion 231 of the conductive structure 230 can be in electrical contact with the gate layer 2211 located in the non-core region, so that an electrical signal can be transmitted between the gate layer 2211 and the first portion 231.

In some embodiments, the thickness of the first portion 231 is the same or approximately the same as the thickness of one of the gate layers 2211.

Illustratively, the material of the conductive structure 230 includes at least one of tungsten, cobalt, copper, aluminum, doped polysilicon, and metal silicide. The conductive structure 230 and the gate layer 2211 may be made of the same material or different materials.

In some embodiments, the first portion 231 and the second portion 232 of the conductive structure 230 may be an integrally molded structure, which improves the reliability of the electrical contact between the first portion 231 and the second portion 232.

Fig. 9 is a block diagram of a conductive structure according to some embodiments. Fig. 10 is a block diagram of a conductive structure and a conductive plug according to some embodiments.

As shown in fig. 9, the second portion 232 of the conductive structure 230 is in electrical contact with the first portion 231, and as shown in fig. 8, the second portion 232 extends upward through the stacked structure 210. As shown in fig. 9, second portion 232 encloses a plug opening 242.

It is to be understood that the second portion 232 extends "upward" through the stacked structure 210, i.e. the second portion 232 extends through the stacked structure 210 in a direction away from the substrate 201. For example, as shown in fig. 8, one end of the second portion 232 is in contact with the first portion 231, and the other end thereof penetrates through the stacked structure 210 in a direction away from the substrate 201 and encloses the plug opening 242.

In some embodiments, the plug opening 242 may be a closed shape, such as a square, circle, or irregular polygon, among others. In other embodiments, the plug opening 242 may also have a non-closed shape, such as a C-shape, U-shape, or other non-closed irregular shape.

As shown in fig. 10, conductive plug 240 is positioned within plug opening 242 and is in electrical contact with second portion 232. As can be appreciated, since the first portion 231 of the conductive structure 230 is in electrical contact with a gate layer 2211, the second portion 232 of the conductive structure 230 is in electrical contact with the first portion 231, such that the conductive plug 240 can be electrically connected with the gate layer 2211 through the first portion 231 and the second portion 232 of the conductive structure 230.

Thus, electrically contacting word line contact V0 with one or more of conductive plug 240 and second portion 232 allows for electrical connection between word line contact V0 and gate layer 2211, increases the landing window for electrical connection between word line contact V0 and gate layer 2211, and reduces the difficulty of electrical connection between word line contact V0 and gate layer 2211.

Illustratively, the material of the conductive plug 240 includes at least one of tungsten, cobalt, copper, aluminum, doped polysilicon, and metal silicide. The conductive plug 240 and the conductive structure 230 may be made of the same material or different materials.

It is to be understood that the conductive plug 240 can close the plug opening 242, as shown in fig. 10. In some embodiments, conductive plug 240 can form an enclosed structure with conductive structure 230 (including first portion 231 and second portion 232). In other embodiments, the conductive plug 240 may form a closed structure with only the second portion 232 of the conductive structure 230.

In some embodiments, as shown in fig. 7, a side of the conductive plug 240 remote from the substrate 201 is flush or approximately flush with a side of the second portion 232 remote from the first portion 231, thereby improving structural regularity of the semiconductor structure 200 and facilitating electrical contact between the word line contact V0 and the conductive plug 240 and the conductive structure 230.

As described above, the number of the gate layers 2211 is plural. In some embodiments, the number of conductive structures 230 is the same as the number of gate layers 2211. The first portion 231 of one conductive structure 230 is in electrical contact with one of the gate layers 2211. The number of conductive plugs 240 is the same as the number of conductive structures 230, with one conductive plug 240 in electrical contact with the second portion 232 of one conductive structure 230.

With this arrangement, the plurality of gate layers 2211 can be electrically connected to the plurality of conductive plugs 240, respectively, and an electrical signal can be transmitted between the word line contact V0 and the gate layer 2211 through the different conductive plugs 240, thereby improving the reliability of the semiconductor structure 200.

In some embodiments, as shown in fig. 7, the semiconductor structure 200 further includes a third dielectric layer 258, wherein the third dielectric layer 258 is located on one side of the stacked structure 210 along the first direction, that is, the third dielectric layer 258 is located on one side of the stacked structure 210 away from the substrate 201. Word line contact V0 is embedded within third dielectric layer 258 and is in electrical contact with conductive plug 240. It will be appreciated that the third dielectric layer 258 can protect the word line contact V0.

As can be seen from the above, in some embodiments of the present disclosure, as shown in fig. 8, the first portion 231 of the conductive structure 230 is disposed on and electrically contacted with a gate layer 2211, the second portion 232 is electrically contacted with the first portion 231, and the second portion 232 extends upward through the stacked structure 210, so that the conductive structure 230 can be embedded in the stacked structure 210 and electrically contacted with a gate layer 2211. Thus, the gate layer 2211 can be electrically connected to other components (e.g., the subsequently formed word line contact V0) through the conductive structure 230, so that a step structure is not required, the problem that the word line contact hole is difficult to align with the step structure is solved, the conductive structure 230 is electrically connected to the gate layer 2211 through the SCT architecture, the fabrication process is simplified, and the production cost of the semiconductor structure 200 is reduced.

In addition, the second portion 232 encloses the plug opening 242, and the conductive plug 240 is disposed in the plug opening 242 and in electrical contact with the second portion 232, such that the subsequently formed word line contact V0 can be electrically connected to the gate layer 2211 through at least one of the conductive plug 240 and the conductive structure 230. That is, word line contact V0 may be disposed in electrical contact with the end of second portion 232 of conductive structure 230 distal from first portion 231, word line contact V0 may be disposed in electrical contact with the surface of conductive plug 240 distal from stacked structure 210, word line contact V0 may be disposed in electrical contact with both the end of second portion 232 of conductive structure 230 distal from first portion 231 and the surface of conductive plug 240 distal from stacked structure 210.

With such an arrangement, on one hand, a contact area of the subsequently formed word line contact V0 when electrically connected with the gate layer 2211 is increased, that is, a landing window of the word line contact V0 when electrically connected with the gate layer 2211 is increased, convenience of electrical connection between the word line contact V0 and the gate layer 2211 is improved, a manufacturing process is simplified, and production cost of the semiconductor structure 200 is reduced, so that production cost of the three-dimensional memory 10 is reduced.

On the other hand, by increasing the contact area when the word line contact V0 and the conductive structure 230 are electrically connected, the resistance between the word line contact V0 and the gate layer 2211 can be reduced, and the reliability of electrical signal transmission can be improved.

In another aspect, word line contact V0 is electrically connected to gate layer 2211 through conductive plug 240 and conductive structure 230, and no other conductive structure is required to be disposed between word line contact V0 and conductive plug 240, which simplifies the structure of semiconductor structure 200 and further reduces the cost of semiconductor structure 200.

In another aspect, the conductive plug 240 is disposed in the plug opening 242, so that the conductive plug 240 can be embedded in the conductive structure 230, and no additional interlayer structure is required to be disposed to accommodate the conductive plug 240, so that the SCT architecture can be combined with the conductive plug 240, thereby further simplifying the structure of the semiconductor structure 200 and reducing the cost of the semiconductor structure 200.

In some embodiments, as shown in fig. 5, the semiconductor structure 200 is formed with a gate line slit 206, and the gate line slit 206 penetrates through the stacked structure 210 along a direction perpendicular to the substrate 201. Also, the gate line slit 206 extends from the core region to the non-core region.

It is to be appreciated that one gate line slit 206 can separate the core area of one stacked structure 210 into two memory blocks 220.

In some embodiments, an insulating material may be disposed on an inner wall of the gate line slit 206, and a conductive material may be filled in the accommodating cavity formed by the insulating material, so as to electrically isolate the conductive material by the insulating material on the inner wall. For example, the conductive material in the gate line slit 206 may be in electrical contact with the source layer SL, so that an electrical signal on the source layer SL can be transmitted through the conductive material filled in the gate line slit 206.

For example, the insulating material on the inner wall of the gate line slit 206 may include at least one of silicon nitride, silicon oxynitride, doped silicon oxide, organosilicate glass, dielectric metal oxide (e.g., aluminum oxide, hafnium oxide, etc.) and silicate thereof, and organic insulating material. The conductive material filled in the gate line slit 206 may include at least one of tungsten, cobalt, copper, aluminum, doped polysilicon, and metal silicide.

Fig. 11 is a block diagram of a stacked structure according to some embodiments.

In some embodiments, as shown in fig. 11, the semiconductor structure 200 further comprises a first dielectric layer 250. A first dielectric layer 250 is located over the stacked structure 210. Illustratively, as shown in fig. 11, the first dielectric layer 250 is located on one side of the stacked structure 210 along the first direction, that is, the first dielectric layer 250 is located on one side of the stacked structure 210 away from the substrate 201.

It is understood that the first dielectric layer 250 can cover a side of the stacked structure 210 away from the substrate 201, and serves to protect the stacked structure 210. In some embodiments, the side of the first dielectric layer 250 away from the substrate 201 is a smooth planar structure.

Illustratively, the material of the first dielectric layer 250 includes at least one of silicon oxide, silicon nitride, silicon oxynitride, doped silicon oxide, organosilicate glass, dielectric metal oxide (e.g., aluminum oxide, hafnium oxide, etc.) and silicates thereof, and organic insulating materials.

As shown in fig. 11, the first dielectric layer 250 has a first opening 251, and it is understood that the first opening 251 penetrates through the first dielectric layer 250 in a direction perpendicular to the substrate 201.

As shown in fig. 7, the end of the second portion 232 away from the first portion 231 and the conductive plug 240 are located in the first opening 251. It is understood that the end of the second portion 232 away from the first portion 231 can not only extend through the stacked structure 210, but also extend through the first dielectric layer 250, such that the end of the second portion 232 away from the first portion 231 can be located within the first opening 251. The conductive plug 240 is located in a plug opening 242 formed in an end of the second portion 232 remote from the first portion 231, thereby enabling the conductive plug 240 to also be located in the first opening 251 of the first dielectric layer 250.

In some embodiments, as shown in fig. 7, the side of the conductive plug 240 away from the substrate 201, the side of the second portion 232 away from the substrate 201, and the side of the first dielectric layer 250 away from the substrate 201 are flush or nearly flush, which improves the structural regularity of the semiconductor structure 200.

By disposing the first dielectric layer 250 and disposing the end of the second portion 232 far from the first portion 231 and the conductive plug 240 in the first opening 251, the first dielectric layer 250 can protect the end of the second portion 232 far from the first portion 231 and the conductive plug 240. Furthermore, the first dielectric layer 250 can also electrically isolate the second portion 232 and the conductive plug 240 from other structures (e.g., the channel contact 226), which improves the reliability of the semiconductor structure 200.

In some examples, as shown in fig. 7, the third dielectric layer 258 is located on a side of the first dielectric layer 250 away from the stack structure 210 such that the word line contact V0 embedded in the third dielectric layer 258 can make electrical contact with at least one of the conductive plug 240 and the conductive structure 230.

In some embodiments, as shown in fig. 11, the semiconductor structure 200 further comprises a channel structure 223. The channel structure 223 is located in the core region and penetrates through the stacked structure 210. It is understood that the channel structure 223 penetrates the stacked structure 210 in a direction perpendicular to the substrate 201.

In some embodiments, at least a portion of channel structure 223 is used to store data to enable the core region to perform a memory function.

It is understood that the number of the channel structures 223 may be plural to increase the storage capacity of the stacked structure 210. The shape of the channel structure 223 may be a cylinder, a truncated cone, a prism, or the like, and the shape of the channel structure 223 is not further limited by the embodiments of the present disclosure.

As shown in fig. 11, the first dielectric layer 250 also has a second opening 252. It is understood that the position of the second opening 252 corresponds to the position of the channel structure 223, and the second opening 252 penetrates through the first dielectric layer 250 in a direction perpendicular to the substrate 201, so that the end of the channel structure 223 away from the substrate 201 can be exposed.

As shown in fig. 7, the semiconductor structure 200 further includes a channel contact 226. The channel contact 226 is located within the second opening 252 and is in electrical contact with an end of the channel structure 223 proximate to the first dielectric layer 250, i.e., the channel contact 226 is in electrical contact with an end of the channel structure 223 distal from the substrate 201. The channel structure 223 is electrically connected to the outside through the channel contact 226, so that the semiconductor structure 200 can write, store, erase, and the like of data.

As shown in fig. 7, the channel contact 226 is disposed in the second opening 252, so that the first dielectric layer 250 can protect the channel contact 226, and in addition, the channel contact 226 and the conductive plug 240 can be disposed on the same layer, which improves the structural regularity of the semiconductor structure 200, facilitates the fabrication of the semiconductor structure 200, further simplifies the fabrication steps of the semiconductor structure 200, and reduces the production cost of the semiconductor structure 200.

In some embodiments, the side of the channel contact 226 remote from the substrate 201 is flush or approximately flush with the side of the first dielectric layer 250 remote from the substrate 201.

In some embodiments, as shown in fig. 7, the conductive plug 240 and the channel contact 226 are the same material at the same layer.

It is to be understood that "the same layer" refers to a layer structure formed by forming a film layer for forming a specific pattern using the same film forming process and then forming the layer structure by a single patterning process using the same mask plate. Depending on the specific pattern, the single patterning process may include multiple exposure, development or etching processes, and the specific pattern in the formed layer structure may be continuous or discontinuous, and the specific patterns may be at different heights or have different thicknesses.

The conductive plug 240 and the channel contact 226 are made of the same material at the same layer, which improves the structural regularity of the semiconductor structure 200 and facilitates electrical contact between the conductive plug 240 and the channel contact 226 and other components. On the other hand, the manufacturing of the semiconductor structure 200 is facilitated, the manufacturing steps of the semiconductor structure 200 are simplified, the production efficiency of the semiconductor structure 200 is improved, and the production cost of the semiconductor structure 200 is reduced.

As can be seen from the above, the second portion 232 is in electrical contact with the first portion 231. In some embodiments, as shown in fig. 9, second portion 232 includes an extension 2321. A first end of extension 2321 is in electrical contact with first portion 231 and a second end of extension 2321 encloses plug opening 242.

In some embodiments, the extension 2321 may be a closed shape, such as a circular ring, a rectangular ring, or other irregularly shaped ring. In other embodiments, the extension 231 may also have a non-closed shape, such as a C-shape, U-shape, or other non-closed shape.

As shown in fig. 8, a first end of the extension 2321 is electrically contacted with the first portion 231, and a second end of the extension 2321 penetrates the stacked structure 210 and the first dielectric layer 250 upward. Also, as shown in fig. 9, a second end of extension 2321 can be encircled to form plug opening 242.

As shown in fig. 10, the conductive plug 240 can be embedded in the plug opening 242 formed around the extension 2321 and electrically contact the extension 2321.

The second portion 232 is disposed to include the extension 2321, a first end of the extension 2321 is electrically contacted with the first portion 231, a second end of the extension 2321 upwardly penetrates through the stacked structure 210 and the first dielectric layer 250, and the plug opening 242 is defined, so that an area of electrical contact between the second portion 232 and the first portion 231 and the conductive plug 240 is increased, resistance between the second portion 232 and the first portion 231 and the conductive plug 240 is reduced, and reliability of electrical connection between the second portion 232 and the first portion 231 and the conductive plug 240 is improved.

In some embodiments, as shown in fig. 9, the first end of the extension 2321 can be enclosed to form an opening P. As shown in fig. 10, the second portion 232 also includes a contact 2322. The contact 2322 is located in the opening P surrounded by the first end of the extension 2321, and the contact 2322 is in electrical contact with the first portion 231 and the extension 2321.

In some embodiments, the contact 2322 can close an opening P formed around the first end of the extension 2321.

It is understood that by providing the contact 2322 and electrically contacting the contact 2322 with the first portion 231 and the extension 2321, the area of electrical contact between the second portion 232 and the first portion 231 is further increased, the electrical resistance between the second portion 232 and the first portion 231 is reduced, and the reliability of the electrical contact between the first portion 231 and the second portion 232 is improved.

In some embodiments, the contact 2322 and the extension 2321 may be an integrally formed structure, which improves the reliability of the electrical contact between the contact 2322 and the extension 2321.

In some embodiments, as shown in fig. 9, the area of plug opening 242 is greater than the area of opening P surrounded by the first end of extension 2321.

As shown in fig. 10, the contact 2322 is located in the opening P defined by the first end of the extension 2321, and the conductive plug 240 is located in the plug opening 242 defined by the second end of the extension 2321. Therefore, the area of plug opening 242 is larger than the area of opening P surrounded by the first end of extension 2321, and the area of conductive plug 240 can be further increased.

In some examples, when the extension 2321 is a circular ring, the area of the plug opening 242 is larger than the area of the opening P surrounded by the first end of the extension 2321, so that the extension 2321 can be surrounded with the contact 2322 and the conductive plug 240 to form a closed circular truncated cone structure. The conductive plug 240 is a lower bottom surface of the circular truncated cone structure, and the contact 2322 is an upper bottom surface of the circular truncated cone structure. It can be understood that the upper bottom surface and the lower bottom surface of the circular truncated cone structure are parallel, and the area of the upper bottom surface is smaller than that of the lower bottom surface.

In other examples, when the extension 2321 is a rectangular ring, the area of the plug opening 242 is larger than the area of the opening P surrounded by the first end of the extension 2321, so that the extension 2321 can surround the contact 2322 and the conductive plug 240 to form a closed frustum structure. Conductive plug 240 is a lower bottom surface of the pyramid structure and contact 2322 is an upper bottom surface of the pyramid structure. It will be appreciated that the upper and lower base surfaces of the pyramid formation are parallel and that the area of the upper base surface is less than the area of the lower base surface.

The area of the plug opening 242 is larger than the area of the opening P surrounded by the first end of the extension 2321, which can further increase the area of the conductive plug 240, thereby increasing the landing window when the word line contact V0 is electrically connected to the gate layer 2211, improving the convenience of electrical contact between the word line contact V0 and the conductive plug 240, that is, improving the convenience of electrical connection between the word line contact V0 and the gate layer 2211, simplifying the manufacturing process of the semiconductor structure 200, and reducing the cost of the semiconductor structure 200.

In some embodiments, as shown in fig. 10, an area of an orthographic projection of the first portion 231 on the reference plane is larger than an area of the opening P surrounded by the first end of the extension 2321. Where the reference plane is parallel to the multi-layer gate layer 2211.

It is understood that the reference plane is a virtual plane parallel to the multilayer gate layer 2211. The area of the orthographic projection of the first portion 231 on the reference surface is set to be larger than the area of the opening P surrounded by the first end of the extension portion 2321, so that the area of the electrical contact between the first portion 231 and the gate layer 2211 is increased, the resistance between the first portion 231 and the gate layer 2211 is reduced, and the use reliability of the conductive structure 230 is improved.

In some examples, the area of the surface of the first portion 231, which is in electrical contact with the extension 2321, is larger than the area of the opening P surrounded by the first end of the extension 2321, so as to further increase the area of electrical contact between the first portion 231 and the one gate layer 2211, and reduce the resistance between the first portion 231 and the one gate layer 2211.

In some embodiments, as shown in fig. 10, the semiconductor structure 200 further comprises an electrical isolation layer 202. As shown in fig. 8, an electrically isolating layer 202 is located between the second portion 232 and the stacked structure 210.

It is understood that the electrically isolating layer 202 comprises an insulating material, which serves as electrical isolation. As shown in fig. 8, a first portion 231 of the conductive structure 230 is in electrical contact with a gate layer 2211, and a portion of the second portion 232 is embedded within the stacked structure 210 and is in electrical contact with the first portion 231. Therefore, by disposing the electrical isolation layer 202 between the second portion 232 and the stacked structure 210, electrical contact between the gate layer 2211 and the second portion 232 can be avoided, so that the gate layer 2211 can only electrically contact the first portion 231, but cannot directly electrically contact the second portion 232 (including the extension 2321 and the contact 2322), thereby improving the reliability of the conductive structure 230.

Illustratively, the material of the electrical isolation layer 202 includes at least one of silicon oxide, silicon nitride, silicon oxynitride, doped silicon oxide, organosilicate glass, dielectric metal oxides (e.g., aluminum oxide, hafnium oxide, etc.) and silicates thereof, and organic insulating materials.

In some embodiments, as shown in fig. 10, the electrical isolation layer 202 is located at the outer periphery side of the extension 2321, so that the electrical isolation layer 202 can perform an electrical isolation function between the extension 2321 and the gate layer 2211, further improving the reliability of the semiconductor structure 200.

In some embodiments, as shown in fig. 10, the conductive structure 230 and the conductive plug 240 are enclosed to form a receiving cavity Q. As shown in fig. 7, the semiconductor structure 200 further includes an insulating material 203. The insulating material 203 is filled in the accommodation cavity Q.

In some embodiments, the receiving cavity Q enclosed by the conductive structure 230 and the conductive plug 240 is a closed receiving cavity. The insulating material 203 is filled in the receiving cavity Q, so that the conductive structure 230 and the conductive plug 240 can be mechanically supported, the mechanical strength of the electrical contact between the conductive structure 230 and the conductive plug 240 is improved, and the reliability of the semiconductor structure 200 is improved.

Illustratively, the insulating material 203 may include at least one of silicon oxide, silicon nitride, silicon oxynitride, doped silicon oxide, organosilicate glass, dielectric metal oxides (e.g., aluminum oxide, hafnium oxide, etc.) and silicates thereof, and organic insulating materials.

In some embodiments, as shown in fig. 7, the receiving cavity Q also has an air gap 204 therein.

It is understood that the number of air gaps 204 may be one or more. In some embodiments, the air gap 204 may be formed while filling the insulating material 203 to relieve structural stress and improve reliability of the semiconductor structure 200.

As can be seen from the above description, as shown in fig. 11, the semiconductor structure 200 includes a channel structure 223, and the channel structure 223 is located in the core region and penetrates through the stacked structure 210. At least a portion of the channel structure 223 is used to store data.

Figure 12 is a block diagram of a channel structure according to some embodiments. FIG. 13 is a block diagram of a stacked configuration according to further embodiments. Referring now to fig. 12 and 13, a stack structure 210 and a channel structure 223 are illustrated.

In some embodiments, as shown in fig. 12, stacked structure 220 comprises a storage stack structure 221. A plurality of gate layers 2211 are located in the memory stack structure 221. The memory stack structure 221 further includes a plurality of gate insulating layers 2212, and the gate insulating layers 2212 and the gate electrode layers 2211 are alternately stacked.

As shown in fig. 11, each gate insulating layer 2212 extends from the core region to the non-core region. It can be understood that the gate insulating layer 2212 can perform an insulating function, and the gate insulating layers 2212 and the gate electrode layers 2211 are alternately stacked, so that a short circuit between two adjacent gate electrode layers 2211 is avoided, and the reliability of the semiconductor structure 200 is improved.

It is to be understood that the thicknesses of the gate insulating layer 2212 and the gate layer 2211 may be the same or different. For example, the material of the gate insulating layer 2212 may include at least one of silicon oxide, silicon nitride, silicon oxynitride, doped silicon oxide, organosilicate glass, dielectric metal oxide (e.g., aluminum oxide, hafnium oxide, etc.) and silicate thereof, and organic insulating material.

In some embodiments, as shown in fig. 12, the channel structure 223 includes a memory channel structure 224, and the memory channel structure 224 penetrates through the memory stack structure 221. It will be appreciated that the memory channel structure 224 is used to store data.

In some embodiments, the memory channel structure 224 may include a plurality of memory cells to implement a memory function. In some embodiments, the semiconductor structure 200 may include a plurality of memory channel structures 224 to increase the memory capacity of the semiconductor structure 200.

In some embodiments, as shown in fig. 12, the memory channel structure 224 includes at least a memory function layer 2241 and a channel layer 2242 sequentially distant from the plurality of gate layers 2211. It is to be understood that the storage function layer 2241 is used to store data.

In some embodiments, the storage function layer 2241 may include a blocking layer, a charge trapping layer, and a tunneling layer. The charge trap layer is used to store charges, and the blocking layer is used to block charges stored in the charge trap layer and provide electrical insulation between the charge trap layer and the gate layer 2211. The tunneling layer is used to generate charges (electrons or holes).

For example, the material of the blocking layer includes, but is not limited to, silicon oxide, the material of the charge trapping layer includes, but is not limited to, silicon nitride, and the material of the tunneling layer includes, but is not limited to, silicon oxide. In some embodiments, the memory function layer 2241 can form an "ONO" structure when the material of the blocking layer is silicon oxide, the material of the charge trapping layer is silicon nitride, and the material of the tunneling layer is silicon oxide.

The channel layer 2242 is used to transport desired charges, and the material of the channel layer 2242 includes, but is not limited to, doped polysilicon, for example.

In some embodiments, as shown in fig. 12, the storage channel structure 224 may further include a storage channel filling medium 2247, and the storage channel filling medium 2247 fills a receiving space formed in the channel layer 2242, and functions to support the storage channel structure 224.

By way of example, the material of the storage trench filling medium 2247 may include at least one of silicon oxide, silicon nitride, silicon oxynitride, doped silicon oxide, organosilicate glass, dielectric metal oxide (e.g., aluminum oxide, hafnium oxide, etc.) and silicates thereof, and organic insulating materials.

In some embodiments, the storage channel fill media 2247 filled in the storage channel structure 224 may include an air gap to relieve structural stress.

In some embodiments, as shown in fig. 12, the memory channel structure 224 may further include a memory channel plug 2246. The memory channel plug 2246 is disposed at an end of the memory channel structure 224 away from the substrate 201, and is embedded in the memory channel structure 224, in electrical contact with the channel layer 2242. The electrical signals are transmitted through the storage channel plugs 2246. For example, the material of the storage channel plug 2246 may be single crystal silicon or polycrystalline silicon, etc.

In some embodiments, as shown in fig. 12, the substrate 201 includes a source layer SL. Channel layer 2242 and storage channel fill medium 2247 of storage channel structure 224 near the end of substrate 201 are embedded in source layer SL, enabling electrical contact with source layer SL at the end of storage channel structure 224 near substrate 201, thereby enabling a common source for multiple memory cells on storage channel structure 224.

In some embodiments, as shown in fig. 12, the storage stack structure 221 includes a first storage stack structure 2213 and a second storage stack structure 2214. The first storage stack layer 2213 is disposed on one side of the substrate 201, and the second storage stack layer 2214 is disposed on one side of the first storage stack layer 2213 away from the substrate 201.

It is understood that the number of stacked layers of the first storage stacked layer structure 2213 and the number of stacked layers of the second storage stacked layer structure 2214 may be the same or different.

As shown in fig. 12, the memory channel structure 224 includes a first memory channel structure 2244 and a second memory channel structure 2245. The first memory channel structure 2244 extends through the first memory stack structure 2213, and the second memory channel structure 2245 extends through the second memory stack structure 2214. It will be appreciated that the second memory channel structure 2245 is in electrical contact with an end of the first memory channel structure 2244 remote from the substrate 201. The source layer SL is in electrical contact with an end of the first memory channel structure 2244 remote from the second memory channel structure 2245. The storage channel plug 2246 is disposed at an end of the second storage channel structure 2245 far from the first storage channel structure 2244, and embedded in the second storage channel structure 2245.

By arranging the memory stack structure 221 and the memory channel structure 224, the semiconductor structure 200 can realize functions of writing, reading, erasing and the like of data, and the use performance of the semiconductor structure 200 is improved.

In some embodiments, as shown in fig. 12, the stacked structure 210 further includes a select stack structure 222. The selection stack structure 222 is located above the storage stack structure 221, and for example, as shown in fig. 12, the selection stack structure 222 is located on a side of the storage stack structure 221 along the first direction, that is, the selection stack structure 222 is located on a side of the storage stack structure 221 away from the substrate 201.

It is to be understood that when the storage stack structure 221 includes the first storage stack structure 2213 and the second storage stack structure 2214, the selection stack structure 222 is located on a side of the second storage stack structure 2214 away from the substrate 201.

As shown in fig. 12, the selective laminated structure 222 includes an insulating dielectric layer 2221, a first conductive layer 2222, and a second dielectric layer 2223, which are sequentially disposed. As shown in fig. 13, the insulating dielectric layer 2221 extends from the core region to the non-core region, and the first conductive layer 2222 and the second dielectric layer 2223 are located in the core region.

Illustratively, the insulating dielectric layer 2221 includes silicon oxide, the first conductive layer 2222 includes polysilicon, and the second dielectric layer 2223 includes silicon nitride.

As shown in fig. 13, since the first conductive layer 2222 and the second dielectric layer 2223 are located in the core region, the insulating dielectric layer 2221 extends to the non-core region. Thus, a height difference exists between a surface of the core region away from the substrate 201 (i.e., a surface of the second dielectric layer 2223 away from the substrate 201) and a surface of the non-core region away from the substrate 201 (i.e., a surface of the insulating dielectric layer 2221 away from the substrate 201).

In some embodiments, as shown in fig. 13, the stacked structure 210 further includes a filling layer 208, and the filling layer 208 is located on a side of the insulating dielectric layer 2221 away from the memory stack structure 221 and located in the non-core region.

By arranging the filling layer 208, the side of the filling layer 208 away from the insulating dielectric layer 2221 and the side of the second dielectric layer 2223 away from the insulating dielectric layer 2221 can be flush or approximately flush, that is, the surface of the core region away from the substrate 201 and the surface of the non-core region away from the substrate 201 can be flush or approximately flush, so that the structural regularity of the semiconductor structure 200 is improved.

Illustratively, the material of the filling layer 208 includes at least one of silicon oxide, silicon nitride, silicon oxynitride, doped silicon oxide, organosilicate glass, dielectric metal oxide (e.g., aluminum oxide, hafnium oxide, etc.) and silicate thereof, and organic insulating material.

In other embodiments, the filling layer 208 may not be provided, and the first dielectric layer 250 may be used to fill the side of the insulating dielectric layer 2221 away from the substrate 201, so that the side of the first dielectric layer 250 away from the substrate 201 has a smooth planar structure.

As shown in fig. 12, channel structure 223 further includes a select channel structure 225. The selection channel structure 225 penetrates the selection stack structure 222 and is in electrical contact with an end of the memory channel structure 224 in the first direction, that is, the selection channel structure 225 is in electrical contact with an end of the memory channel structure 224 away from the substrate 201. It will be appreciated that the select channel structure 225 is used to control the memory channel structure 224 for writing, reading or erasing data.

In some embodiments, when the memory channel structure 224 includes the first memory channel structure 2244 and the second memory channel structure 2245, the selection channel structure 225 is in electrical contact with an end portion of the second memory channel structure 2245 distant from the first memory channel structure 2244. Illustratively, when the memory channel plug 2246 is located at an end of the second memory channel structure 2245, the selection channel structure 225 is in electrical contact with the memory channel plug 2246.

As shown in fig. 12, the selection channel structure 225 includes at least an insulating layer 2251 and a second conductive layer 2252 sequentially distant from the first conductive layer 2222. It is to be understood that the second conductive layer 2252 serves to transfer charges, and the insulating layer 2251 serves to block charges on the second conductive layer 2252 from being transferred to a structure other than the storage channel structure 224. As an example, the insulating layer 2251 may be made of silicon oxide, and the second conductive layer 2252 may be made of polysilicon.

In some embodiments, select channel structure 225 may further include a select channel fill dielectric 2254, as shown in fig. 12. The selection channel filling medium 2254 fills the receiving space formed by the second conductive layer 2252, and serves to support the selection channel structure 225.

Illustratively, the material of the trench fill dielectric 2254 may be at least one of silicon oxide, silicon nitride, silicon oxynitride, doped silicon oxide, organosilicate glass, dielectric metal oxide (e.g., aluminum oxide, hafnium oxide, etc.) and silicates thereof, and organic insulating material. In some embodiments, the select channel fill dielectric 2254 filling the select channel structure 225 may include air gaps to relieve structural stress.

In some embodiments, as shown in fig. 12, the selection channel structure 225 may further include a selection channel plug 2253, the selection channel plug 2253 is disposed at an end of the selection channel structure 225 away from the memory channel structure 224 and embedded in the selection channel structure 225 to be in electrical contact with the second conductive layer 2252, and an electrical signal is transmitted through the selection channel plug 2253. For example, the material of the selection channel plug 2253 may be single crystal silicon or polycrystalline silicon.

By providing the selection stack structure 222 and the selection channel structure 225, the memory channel structure 224 can be controlled to perform operations such as writing, reading, or erasing of data, thereby further improving the performance of the semiconductor structure 200.

In some embodiments, the selection channel structure 225 may be configured as a simple Metal-Oxide-Semiconductor (MOS) transistor, which simplifies the process and reduces the manufacturing cost.

In some embodiments, when channel structure 223 includes a select channel structure 225, as shown in fig. 12, channel contact 226 is in electrical contact with the select channel structure 225 near the end of first dielectric layer 250.

In some embodiments, as shown in fig. 5, the semiconductor structure 200 further includes a select stack cut 207, the select stack cut 207 extending through the select stack structure 222 in a direction perpendicular to the substrate 201 to separate the plurality of select channel structures 225 from one another.

With such an arrangement, it is convenient to control each selection channel structure 225, so as to effectively reduce the time required for data writing, reading and erasing, and improve the performance of the semiconductor structure 200.

In some embodiments, the selective stack cut 207 may be filled with silicon oxide or silicon nitride, etc., to improve the mechanical strength of the semiconductor structure 200 and to serve as an insulator.

In some embodiments, as shown in fig. 7, the semiconductor structure 200 further includes a semiconductor structure layer 205. The semiconductor structure layer 205 is located on a side of the stacked structure 210 away from the first dielectric layer 250. For example, as shown in fig. 7, the semiconductor structure layer 205 is located between the substrate 201 and the stacked structure 210.

It is understood that the material of the semiconductor structure layer 205 may be polysilicon, and the semiconductor structure layer 205 extends from the core region to the non-core region and is located between the substrate 201 and the stacked structure 210, so as to increase the mechanical strength of the semiconductor structure 200 and improve the reliability of the semiconductor structure 200.

In some embodiments, as shown in fig. 5, the semiconductor structure 200 further includes a plurality of dummy channel structures 209. As shown in fig. 8, the plurality of dummy channel structures 209 are located in the non-core region and extend through the stacked structure 210.

It is understood that the plurality of dummy channels 209 penetrate the stacked structure 210 in a direction perpendicular to the substrate 201. The dummy trench structures 209 are spaced apart from each other in the non-core region and are recessed from the conductive structure 230, which serves to provide mechanical support for the semiconductor structure 200.

For example, the dummy trench structure 209 may be filled with at least one of silicon oxide, silicon nitride, silicon oxynitride, doped silicon oxide, organosilicate glass, dielectric metal oxide (e.g., aluminum oxide, hafnium oxide, etc.) and silicate thereof, and organic insulating material.

On the other hand, some embodiments of the present disclosure also provide a method for manufacturing a semiconductor structure, which is illustrated below with reference to fig. 14 to 55.

Figure 14 is a flow chart of method steps for fabricating a semiconductor structure according to some embodiments. Fig. 15 is a block diagram of an initial stack structure according to some embodiments. Fig. 16 is a block diagram of a semiconductor structure according to still further embodiments.

In some embodiments, as shown in fig. 14, a method of fabricating a semiconductor structure includes:

step S101, an initial stacked structure is formed on one side of a substrate. The initial stacked structure has a core region and a non-core region. The initial stacked structure includes a plurality of gate sacrificial layers stacked in a first direction. The multilayer grid sacrificial layers are distributed at intervals. Wherein the first direction is perpendicular to the substrate.

In some embodiments, substrate 260 may be a single layer substrate. In other embodiments, as shown in FIG. 15, the substrate 260 may also be a composite substrate. For example, when the substrate 260 includes a composite substrate, the composite substrate may include polysilicon layers and silicon oxide layers alternately stacked. In some embodiments, the composite substrate may be formed by ion implantation.

As shown in fig. 15, the initial stacked structure 210' includes at least two materials, the at least two materials being alternately stacked in a first direction, i.e., the at least two materials being alternately stacked in a direction perpendicular or approximately perpendicular to the substrate 260.

For example, the initial stacked structure 210' may be formed on one side of the substrate 260 by using any one of Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), and Atomic Layer Deposition (ALD).

Illustratively, as shown in fig. 15, the initial stacked structure 210' has a core region and a non-core region. The initial stacked structure 210' includes a plurality of gate sacrificial layers 2215 stacked in a first direction. The plurality of gate sacrificial layers 2215 are spaced apart, and it is understood that each gate sacrificial layer 2215 extends from the core region to the non-core region.

It is understood that the gate sacrificial layer 2215 in the core region can be replaced with the gate layer 2211 in subsequent fabrication steps, and at least a portion of the gate layer 2215 in the non-core region can be replaced with the gate layer 2211 in subsequent fabrication steps.

For example, the material of the gate sacrificial layer 2215 may be one of silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, amorphous silicon, amorphous carbon, and polysilicon.

Step S102, forming a conductive structure, wherein the conductive structure is located in a non-core area. The conductive structure includes a first portion and a second portion. The first portion is disposed on and in contact with a gate sacrificial layer. The second portion is in electrical contact with the first portion. The second portion extends upwardly through the initial stack structure and encloses a plug opening.

As shown in fig. 10, the conductive structure 230 includes a first portion 231 and a second portion 232. As shown in fig. 16, the first portion 231 is disposed in layer and in contact with a gate sacrificial layer 2215. For example, when performing a gate replacement (i.e., replacing the gate sacrificial layer 2215 with the gate layer 2212), a portion of the gate sacrificial layer 2215, which is in the non-core region and in contact with the first portion 231, may be replaced with the gate layer 2211, so that the first portion 231 can be in electrical contact with one of the gate layers 2211. The gate sacrificial layer 2215 in the non-core region and not in contact with the first portion 231 is remained to serve as an electrical isolation.

As shown in fig. 16, an end of the second portion 232 is in electrical contact with the first portion 231, and the second portion 232 extends upwardly through the initial stacked structure 210 ', and as an example, an end of the second portion 232 remote from the first portion 231 can extend through the initial stacked structure 210' in a direction away from the substrate 260, and as shown in fig. 9, an end of the second portion 232 remote from the first portion 231 forms a plug opening 242.

In some embodiments, the conductive structure 230 may be formed using any one of a CVD, PVD, and ALD thin film deposition process.

Step S103, forming a conductive plug, wherein the conductive plug is located in the plug opening and electrically contacts with the second portion.

As shown in fig. 16, after forming the plug opening 242, the conductive plug 240 is formed such that the conductive plug 240 can close the plug opening 242 and make electrical contact with the second portion 232.

In some embodiments, the conductive plug 240 may be formed using any one of a CVD, PVD, and ALD thin film deposition process.

It is to be understood that the structures, materials, and the like of the conductive structures 230 and the conductive plugs 240 have been illustrated in the above embodiments of the disclosure, and are not described herein again.

The method of electrical contact between the word line contact V0 and the conductive plug 240 is illustrated below.

In some embodiments, as shown in fig. 16, a third dielectric layer 258 may be formed on the side of the first dielectric layer 250 away from the initial stacked structure 210'. A first mask is formed on the side of the third dielectric layer 258 away from the first dielectric layer 250. And patterning the first mask plate to form a first etching opening. The third dielectric layer 258 is etched through the first etching opening to form a receiving hole, and the receiving hole penetrates through the third dielectric layer 258 along a direction from the third dielectric layer 258 to the conductive plug 240 and exposes the conductive plug 240. A word line contact V0 is formed within the receiving hole so that the word line contact V0 can be embedded within the third dielectric layer 258.

It will be appreciated that word line contact V0 is in electrical contact with at least one of conductive plug 240 and conductive structure 230, i.e., such that an electrical signal is transmitted between word line contact V0 and gate layer 2211. That is, by providing the conductive plug 240, the landing window when the word line contact V0 is electrically connected to the gate layer 2211 is increased, and the process difficulty of electrical connection between the word line contact V0 and the gate layer 2211 is reduced, so that the accuracy requirement on the pattern on the first mask is reduced, repeated correction on the pattern on the first mask is not required, the manufacturing process of the semiconductor structure 200 is simplified, and the cost of the semiconductor structure 200 is reduced.

As can be seen from the above, in some embodiments of the present disclosure, by disposing the first portion 231 of the conductive structure 230 in layer with and in contact with a layer of the gate sacrificial layer 2215, the first portion 231 is enabled to be disposed in layer with and in electrical contact with a layer of the gate layer 2211 after the gate sacrificial layer 2215 is replaced with the gate layer 2211.

The second portion 232 is electrically contacted to the first portion 231, and the second portion 232 extends upward through the initial stacked structure 210 ', and encloses the plug opening 242, that is, an end of the second portion 232 away from the first portion 231 can extend upward through the initial stacked structure 210 ' (stacked structure 210), so that the conductive structure 230 can be embedded in the initial stacked structure 210 ' (stacked structure 210) and electrically contacted to a gate layer 2211.

Thus, the gate layer 2211 can be electrically connected to other components (e.g., the subsequently formed word line contact V0) through the conductive structure 230, so that a step structure is not required, the problem that the word line contact hole is difficult to align with the step structure is solved, the conductive structure 230 is electrically connected to the gate layer 2211 through the SCT architecture, the fabrication process is simplified, and the production cost of the semiconductor structure 200 is reduced.

Fig. 17 is a structural diagram of a first dielectric film according to some embodiments. FIG. 18 is a flow chart of method steps for fabricating a semiconductor structure according to other embodiments. FIG. 19 is a block diagram of a first contact hole according to some embodiments. FIG. 20 is a block diagram of a first contact hole according to further embodiments. FIG. 21 is a block diagram of a first contact hole according to still further embodiments. FIG. 22 is a block diagram of a first portion according to some embodiments. FIG. 23 is a block diagram of a conductive structure according to further embodiments.

In some embodiments, before the step of forming the conductive structure, that is, before the step S102, the method for manufacturing a semiconductor structure further includes:

and forming a first dielectric film, wherein the first dielectric film is positioned on the initial stacking structure.

As shown in fig. 17, after forming the initial stacked structure 210 'on one side of the substrate 260 and before forming the conductive structure 230, the method of fabricating the semiconductor structure 200 includes forming a first dielectric film 250', the first dielectric film 250 'being over the initial stacked structure 210'. For example, as shown in fig. 17, a first dielectric film 250 ' may be formed on a side of the initial stacked structure 210 ' along the first direction, that is, on a side of the initial stacked structure 210 ' far from the substrate 260.

Illustratively, the material of the first dielectric film 250' includes at least one of silicon oxide, silicon nitride, silicon oxynitride, doped silicon oxide, organosilicate glass, dielectric metal oxide (e.g., aluminum oxide, hafnium oxide, etc.) and silicates thereof, and organic insulating materials.

For example, the first dielectric film 250 'may be formed on the side of the starting stacked structure 210' remote from the substrate 260 by any one of CVD, PVD and ALD thin film deposition processes.

In some embodiments, as shown in fig. 18, the step of forming the conductive structure (i.e., step S102) includes:

step S1021, a first contact hole is formed in the non-core region, where the first contact hole penetrates through the first dielectric film and exposes the target gate sacrificial layer, and the target gate sacrificial layer is one of the gate sacrificial layers.

It is understood that the first contact hole 261 penetrates the first dielectric film 250 'so that the first opening 251 can be formed on the first dielectric film 250'.

As shown in fig. 16, the initial stacked structure 210' further includes a plurality of gate insulating layers 2212, and the gate insulating layers 2212 are alternately stacked with the gate sacrificial layers 2215. When the gate sacrificial layer 2215 is replaced with the gate layer 2211, the gate insulating layer 2212 can insulate between the two gate layers 2211. The material and thickness of the gate insulating layer 2212 are exemplified in the above embodiments of the disclosure, and are not described herein again.

In some embodiments, as shown in fig. 19, the first contact hole 261 may be opened directly to the target gate sacrificial layer 2215a, so that the target gate sacrificial layer 2215a can be exposed.

In other embodiments, as shown in fig. 20, the first contact hole 261 may be opened to the gate insulating layer 2212 on the target gate sacrificial layer 2215a, and then a portion of the gate insulating layer 2212 on the target gate sacrificial layer 2215a may be removed to expose the target gate sacrificial layer 2215 a.

Illustratively, the first contact hole 261 may be formed by dry etching or wet etching to expose the target gate sacrificial layer 2215 a.

It is understood that the Critical Dimension (CD) of the first contact hole 261 is not further limited by the embodiments of the present disclosure.

In step S1022, a portion of the target gate sacrificial layer is removed through the first contact hole to form an epitaxial contact hole.

As shown in fig. 21, after the first contact hole 261 is formed, a portion of the target gate sacrificial layer 2215a may be removed through the first contact hole 261 to form the epitaxial contact hole 262. Illustratively, the area of the orthographic projection of the epitaxial contact hole 262 on the reference plane is larger than the area of the bottom opening of the first contact hole 261. That is, the area of the orthographic projection of the epitaxial contact hole 262 on the substrate 260 is larger than the area of the bottom opening of the first contact hole 261.

Illustratively, a dry etching or a wet etching may be used to remove a portion of the target gate sacrificial layer 2215a to form the epitaxial contact hole 262.

In step S1023, a first portion is formed in the epitaxial contact hole.

As shown in fig. 22, the first portion 231 is formed within the epitaxial contact hole 262 so that the first portion 231 can be disposed in the same layer as and in contact with the target gate sacrificial layer 2215 a. As can be seen from the above, the gate sacrificial layer 2215 in contact with the first portion 231 can be replaced with a gate layer 2211, so that the first portion 231 can be disposed on the same layer as and in electrical contact with the gate layer 2211.

Step S1024, forming a second portion in the first contact hole, wherein the second portion is in electrical contact with the first portion.

As shown in fig. 23, the second portion 232 is formed on a sidewall of the first contact hole 261 and covers a side of the first portion 231 remote from the substrate 260, such that one end of the second portion 232 can be electrically contacted with the first portion 231 and the other end can penetrate the stack structure 210 'and the first dielectric film 250' upward.

It is understood that, since the area of the orthographic projection of the epitaxial contact hole 262 on the substrate 260 is larger than the area of the bottom opening of the first contact hole 261, the area of the orthographic projection of the first portion 231 formed in the epitaxial contact hole 262 on the substrate 260 (i.e. the area of the orthographic projection of the first portion 231 on the reference plane) can be larger than the area of the opening P formed by enclosing the first end of the second portion 232.

For example, the first and

second portions

231 and 232 may be formed using any one of a thin film deposition process of CVD, PVD, and ALD. The above embodiments of the disclosure have illustrated the structures, materials, and the like of the first portion 231 and the second portion 232, and are not described herein again.

As can be seen from the above description, in some embodiments of the present disclosure, after the initial stacked structure 210 ' is formed, the first dielectric film 250 ' covering the initial stacked structure 210 ' is formed, and then the first contact hole 261 is opened, so that the first contact hole 261 can penetrate through the first dielectric film 250 ', and the first opening 251 is formed in the first dielectric film 250 '.

The epitaxial contact hole 262 is formed through the first contact hole 261, and the first portion 231 and the second portion 232 of the conductive structure 230 are formed, so that the first portion 231 can be disposed in the same layer as and in contact with a layer of the gate sacrificial layer 2215, and the second portion 232 can penetrate the initial stacked structure 210 'and the first dielectric film 250' upward. The conductive structure 230 is formed through the above steps, so that a portion of the conductive structure 230 (including the first portion 231 and a portion of the second portion 232) can be embedded in the initial stacked structure 210' and is in contact with the gate sacrificial layer 2215, the process is simple, and the production cost of the semiconductor structure 200 is reduced.

Figure 24 is a flow chart of method steps for fabricating a semiconductor structure according to still further embodiments. FIG. 25 is a block diagram of an initial contact hole according to some embodiments. Fig. 26 is a block diagram of an electrical isolation diaphragm according to some embodiments.

As can be seen from the above description, as shown in fig. 23, the initial stacked structure 210' further includes a plurality of gate insulating layers 2212, and the gate insulating layers 2212 and the gate sacrificial layers 2215 are alternately stacked.

In some embodiments, as shown in fig. 24, the step of forming the first contact hole in the non-core region (step S1021) includes:

step S10211, forming an initial contact hole in the non-core region, where the initial contact hole penetrates through the first dielectric film and exposes the target gate insulating layer, where the target gate insulating layer is one of the gate insulating layers.

As shown in fig. 25, the initial contact hole 263 penetrates the first dielectric film 250 'and extends to the initial stacked structure 210', so that the target gate insulating layer 2212a can be exposed. For example, the initial contact hole 263 may be formed by dry etching or wet etching.

Step S10212, forming an electrical isolation film in the initial contact hole.

As shown in fig. 26, an electrical isolation film 202' is formed on the inner wall (including the sidewall and the bottom wall) of the preliminary contact hole 263. Illustratively, the electrical isolation film 202' may be formed using any one of a thin film deposition process of CVD, PVD, and ALD.

Illustratively, the material of the electrical isolation film 202' includes at least one of silicon oxide, silicon nitride, silicon oxynitride, doped silicon oxide, organosilicate glass, dielectric metal oxide (e.g., aluminum oxide, hafnium oxide, etc.) and silicates thereof, and organic insulating materials, which serve as electrical isolation.

Step S10213, removing the bottom wall of the electrical isolation film and a portion of the target gate insulating layer to form an electrical isolation layer, and forming a first contact hole exposing the target gate sacrificial layer inside the electrical isolation layer.

The electrical isolation film 202' at the bottom wall of the initial contact hole 263 is removed to form an electrical isolation layer 202, and the target gate insulating layer 2212a can be exposed. A portion of the target gate insulating layer 2212a (i.e., the target gate insulating layer 2212a forming a bottom wall portion of the initial contact hole 263) is removed so that the target gate sacrificial layer 2215a can be exposed. Thus, as shown in fig. 19, the first contact hole 261 exposing the target gate sacrificial layer 2215a is formed inside the electrical isolation layer 202.

In other embodiments, the initial contact hole 263 may also be opened directly to the target gate sacrificial layer 2215a, so that the electrical isolation film 202' can cover the target gate sacrificial layer 2215 a. The electrical isolation layer 202 and the first contact hole 261 exposing the target gate sacrificial layer 2215a are formed by removing the electrical isolation film 202' from the bottom wall of the initial contact hole 263.

It can be understood that, the electrical isolation layer 202 is formed on the inner wall of the initial contact hole 263, and the first contact hole 261 is located inside the electrical isolation layer 202, so that the electrical isolation layer 202 can electrically isolate the second portion 232, and the second portion 232 is prevented from contacting the gate sacrificial layer 2215, that is, the second portion 232 is prevented from being in direct electrical contact with the gate layer 2211, so that the electrical signal on the gate layer 2211 can be transmitted to the second portion 232 only through the first portion 231, and the reliability of the conductive structure 230 is improved. Moreover, by the preparation method, the electrical isolation layer 202 can be positioned between the second portion 232 and the gate sacrificial layer 2215, the process is simple, and the production cost of the semiconductor structure 200 is reduced.

Fig. 27 is a fill pattern of an insulating material according to some embodiments.

In some embodiments, after the step of forming the second portion in the first contact hole (i.e., after step S1024), the method for manufacturing the semiconductor structure 200 further includes:

and filling the second part with an insulating material.

It is understood that the second portion 232 is formed on the sidewall of the first contact hole 261, so that the second portion 232 can be surrounded to form a cavity structure. As shown in fig. 27, after the second portion 232 is formed, the insulating material 203 is filled in the second portion 232, and the insulating material 203 supports the second portion 232, thereby improving the mechanical strength of the second portion 232.

In addition, since the conductive plug 240 is formed in the plug opening 242 surrounded by the second portion 232, the cavity formed by the second portion 232 is filled with the insulating material 203, and the mechanical strength of the electrical contact between the conductive plug 240 and the second portion 232 can be improved, thereby improving the reliability of the semiconductor structure 200.

The above embodiments of the present disclosure have exemplified the material of the insulating material 203, and are not described in detail herein. Illustratively, a High Aspect Ratio (HARP) process may be used to fill the cavity formed by the second portion 232 with the insulating material 203.

In some embodiments, as shown in fig. 27, during the process of filling the insulating material 203 in the second portion 232, the air gap 204 may be formed by controlling the filling process to reduce the structural stress.

It will be appreciated that as shown in fig. 27, there is a predetermined distance between the surface of the insulating material 203 remote from the substrate 260 and the surface of the second portion 232 remote from the first portion 231, such that the conductive plug 240 can be disposed within the plug opening 242 and in electrical contact with the second portion 232.

Figure 28 is a flow chart of method steps for fabricating a semiconductor structure according to still further embodiments. Fig. 29 is a structural diagram of a first conductive film according to some embodiments. FIG. 30 is a fill pattern of an insulating material according to further embodiments. Fig. 31 is a fill pattern of an insulating material according to still further embodiments.

In some embodiments, as shown in fig. 28, the step of forming a second portion in the first contact hole and filling the second portion with an insulating material includes:

step S10241, a first conductive film is formed, the first conductive film including a first sub-film covering the first dielectric film and a second sub-film covering the sidewall and the first portion of the first contact hole.

As shown in fig. 29, the first conductive film 271 includes a first sub-film 2711 and a second sub-film 2712. The first sub-film 2711 covers the first dielectric film 250'. As shown in fig. 21, the non-core region has a first contact hole 261 and an epitaxial contact hole 262, and as shown in fig. 22, the first portion 231 is formed in the epitaxial contact hole 262. As shown in fig. 29, the second sub-film 2712 covers the sidewalls of the first contact hole 261 and the first portion 231 formed in the epitaxial contact hole 262.

As can be appreciated, the second subpanel 2712 covers the side of the first portion 231 remote from the substrate 260. The second sub-film 2712 can form the second portion 232 of the conductive structure 230.

For example, the first conductive film 271 may be formed using any one of CVD, PVD, and ALD thin film deposition processes. Illustratively, the material of the first conductive film 271 includes at least one of tungsten, cobalt, copper, aluminum, doped polysilicon, and metal silicide.

Step S10242, an insulating material is deposited, the insulating material fills the cavity defined by the second sub-film, and the insulating material covers the first sub-film.

As shown in fig. 29, the second sub-film 2712 covers the sidewalls of the first contact hole 261 and the first portion 231 formed in the epitaxial contact hole 262, so that the second sub-film 2712 can define a concave cavity 2713.

As shown in fig. 30, an insulating material 203 is deposited, the insulating material 203 can fill a cavity 2713 defined by the second subpanel 2712, and the insulating material 203 can cover the first subpanel 2711. Illustratively, the insulating material 203 may be deposited using a HARP process.

Step S10243, etching the insulating material to the first sub-film to remove part of the insulating material in the cavity defined by the second sub-film and the insulating material covering the first sub-film.

As shown in fig. 31, when the insulating material 203 is etched, the insulating material 203 covering the first sub-film 2711 is removed with the first sub-film 2711 as an etching stopper. As can be appreciated, since the first sub-film 2711 and the second sub-film 2712 are formed in the same step (step S10241), an additional step is not required to form an etching stop layer, which simplifies the manufacturing process of the semiconductor structure 200, reduces the manufacturing cost of the semiconductor structure 200, and improves the production efficiency. Illustratively, the insulating material 203 may be etched by dry etching or wet etching.

As can be seen from the above, the second sub-film 2712 can form the second portion 232 of the conductive structure 230. Therefore, in order to form the plug opening 242 at the end of the second sub-film 2712 far from the first portion 231, as shown in fig. 31, after the insulating material 203 covering the first sub-film 2711 is removed, the insulating material 203 in the cavity 2713 defined by the second sub-film 2712 may be etched continuously, so that the surface of the insulating material 203 in the cavity 2713 defined by the second sub-film 2712 far from the substrate 260 can be lower than the surface of the first dielectric film 250' far from the substrate 260.

It can be understood that, since the conductive plug 240 can close the plug opening 242, that is, the insulating material 203 can be located in the closed accommodating cavity, the requirement for the smoothness of the surface of the insulating material 203 on the side away from the substrate 260, that is, the requirement for the etching process of the insulating material 203, is reduced, the manufacturing process of the semiconductor structure 200 is simplified, and the production cost of the semiconductor structure 200 is reduced.

In addition, the conductive plug 240 is disposed to close the plug opening 242, so as to reduce the requirement of the height difference (H in fig. 31) between the surface of the insulating material 203 on the side away from the substrate 260 and the surface of the first dielectric film 250' on the side away from the substrate 260, thereby further simplifying the manufacturing process of the semiconductor structure 200 and reducing the production cost of the semiconductor structure 200.

As can be appreciated, since the first sub-film 2711 covers the first dielectric film 250 ', when the insulating material 203 in the cavity 2713 defined by the second sub-film 2712 is etched, the first sub-film 2711 can protect the first dielectric film 250 ', so as to prevent the first dielectric film 250 ' from being damaged during the etching process, thereby improving the reliability of the manufacturing method of the semiconductor structure 200.

Step S10244, removing the first sub-film and the end part of the second sub-film beyond the substrate-far side surface of the first dielectric film to form a second part.

As shown in fig. 27, after the first sub-film 2711 is removed, the first dielectric film 250' is exposed. Also, while removing the first sub-film 2711, the end of the second sub-film 2712 remote from the substrate 260 and beyond the first dielectric film 250 'can be removed so that the side of the second sub-film 2712 remote from the substrate 260 can be flush or nearly flush with the side of the first dielectric film 250' remote from the substrate 260 to form the second portion 232.

It is understood that in the embodiments of the present disclosure, "simultaneously" refers to the same step, and is not limited to the same time.

For example, a Chemical Mechanical Polishing (CMP) process may be used to remove the first sub-film 2711 and the end portion of the second sub-film 2712 of the first dielectric film 250 'away from the substrate 260, so as to planarize the first dielectric film 250' during removal.

FIG. 32 is a block diagram of a stop layer according to some embodiments. FIG. 33 is a block diagram of initial contact holes according to further embodiments. FIG. 34 is a block diagram of a first contact hole according to still further embodiments.

As can be seen from the above, in some embodiments of the present disclosure, the first sub-film 2711 of the first conductive film 271 may be used as an etching stop layer of the insulating material 203. In other embodiments of the present disclosure, after the step of forming the first dielectric film and before the step of forming the first contact hole in the non-core region, the method further includes:

and forming a stop layer, wherein the stop layer covers the first dielectric film.

As shown in fig. 32, after the first dielectric film 250 ' is formed and before the first contact hole 261 is opened, a stop layer 273 may be formed on a side of the first dielectric film 250 ' away from the substrate 260, and the stop layer 273 may cover the first dielectric film 250 '.

Illustratively, as shown in fig. 32, the stop layer 273 includes a first stop layer 2731 and a first protective layer 2732.

In some examples, the step of forming the stop layer 273 includes:

and forming a first stop layer, wherein the first stop layer is positioned on one side of the first dielectric film, which is far away from the initial stack structure.

And forming a first protective layer, wherein the first protective layer is positioned on one side of the first stop layer, which is far away from the first dielectric film.

As can be appreciated, in forming the stop layer 273, the first stop layer 2731 is formed first on a side of the initial stacked structure 210 'away from the substrate 260, and then the first protection layer 2732 is formed on a side of the first stop layer 2731 away from the initial stacked structure 210'.

For example, the first stop layer 2731 and the first protective layer 2732 may be formed using any one of a thin film deposition process of CVD, PVD, and ALD.

In some embodiments, the material of the first stop layer 2731 includes silicon nitride and the material of the first protection layer 2732 includes silicon oxide. When the material of the first dielectric film 250 'is silicon oxide, the first dielectric film 250', the first stop layer 2731 and the first protection layer 2732 can form an "ONO" structure.

It is to be understood that the first stop layer 2731 functions as an etch stop and the first protection layer 2732 functions to protect the first stop layer 2731. In some embodiments, after forming the stop layer 273 and before filling the insulating material 203, the method for manufacturing the semiconductor structure 200 may further include other steps, such as etching other contact holes. Therefore, the first protective layer 2732 is arranged to cover the first stop layer 2731, so that the first protective layer 2732 can protect the first stop layer 2731, the first stop layer 2731 is prevented from being damaged before the insulating material 203 is etched, and the reliability of the preparation method of the semiconductor structure 200 is improved.

In other embodiments, after the stop layer 273 is formed and before the insulating material 203 is filled, when the method for manufacturing the semiconductor structure 200 does not include a step of etching another contact hole, that is, when there is no step that may damage the first stop layer 2731, the first protection layer 2731 may not be provided, thereby further simplifying the manufacturing process of the semiconductor structure 200.

It is understood that the stop layer 273 can be removed in a subsequent fabrication process to expose the first dielectric film 250'. Illustratively, the first dielectric film 250' may be prepared as the first dielectric layer 250 after the stop layer 273 is removed, and the third dielectric layer 258 and the word line contact V0 may be formed on the side of the first dielectric layer 250 remote from the substrate 260.

Forming a first contact hole in the non-core region, comprising:

a first contact hole penetrating through the stop layer and the first dielectric film and exposing the target gate sacrificial layer is formed in the non-core region.

It is understood that since the stop layer 273 covers the first dielectric film 250 ', as shown in fig. 33, when the initial contact hole 263 is formed, the initial contact hole 263 can penetrate not only the first dielectric film 250' but also the stop layer 273.

Thus, when the initial contact hole 263 is prepared as the first contact hole 261, as shown in fig. 34, the first contact hole 261 is also allowed to penetrate the stop layer 273 and the first dielectric film 250', and the target gate sacrificial layer 2215a is exposed.

It can be understood that, by using a non-metal material as the stop layer 273, the structural stress generated by the stop layer 273 is reduced, the risk of the wafer bending under the stress is reduced, and the reliability of the manufacturing method of the semiconductor structure 200 is further improved.

Figure 35 is a flow chart of method steps for fabricating a semiconductor structure according to yet further embodiments. Fig. 36 is a structural diagram of a second conductive film according to some embodiments. FIG. 37 is a block diagram of a fourth sub-film according to some embodiments. Fig. 38 is a fill pattern of an insulating material according to still further embodiments. Fig. 39 is a fill pattern of an insulating material according to still further embodiments. Fig. 40 is a fill pattern of an insulating material according to still further embodiments. Fig. 41 is a fill pattern of an insulating material according to still other embodiments.

As shown in fig. 35, in other embodiments, after forming the stop layer 273, the step of forming the second portion in the first contact hole and filling the insulating material in the second portion includes:

step S10241' forms a second conductive film including a third sub-film and a fourth sub-film. The third sub-film covers the stop layer, and the fourth sub-film covers the sidewalls and the first portion of the first contact hole.

As shown in fig. 36, the second conductive film 272 includes a third sub-film 2722 and a fourth sub-film 2723. The third sub-film 2722 covers the stop layer 273, and it is understood that the third sub-film 2722 is located on a side of the initial stacked structure 210' away from the substrate 260.

As shown in fig. 21, the non-core region has a first contact hole 261 and an epitaxial contact hole 262, and as shown in fig. 22, the first portion 231 is formed in the epitaxial contact hole 262. As shown in fig. 36, the fourth sub-film 2723 covers sidewalls of the first contact hole 261 and the first portion 231 formed within the epitaxial contact hole 262. It is appreciated that fourth sub-film 2723 can form second portion 232 of conductive structure 230.

For example, the third and fourth sub-films 2722 and 2723 may be formed using any one of CVD, PVD, and ALD thin film deposition processes.

Illustratively, the material of the third and fourth sub-films 2722 and 2723 includes at least one of tungsten, cobalt, copper, aluminum, doped polysilicon, and metal silicide.

Step S10242' removes the third sub-film to expose the stop layer.

After the third sub-film 2722 is removed, the stop layer 273 may be exposed, as shown in FIG. 37. Illustratively, the third sub-film 2722 covering the stop layer 273 may be removed using a CMP process to expose the stop layer 273.

Step S10243', an insulating material is deposited, the insulating material fills the cavity defined by the fourth sub-film, and the insulating material covers the stop layer.

It is to be appreciated that, as shown in fig. 37, since the fourth sub-film 2723 covers the sidewalls of the first contact hole 261 and the first portion 231 formed within the epitaxial contact hole 262, the fourth sub-film 2723 can define the cavity 2721.

As shown in fig. 38, after removing the third sub-film 2722, the insulating material 203 is deposited so that the insulating material 203 can fill the cavity 2721 defined by the fourth sub-film 2723 and can cover the stop layer 273. Illustratively, the insulating material 203 may be deposited using a HARP process.

Step S10244', etching the insulating material to at least a portion of the stop layer to remove a portion of the insulating material and the insulating material covering the stop layer in the cavity defined by the fourth sub-film.

As shown in fig. 39, the insulating material 203 is etched at least partially into the stop layer 273 to remove the insulating material 203 covering the stop layer 273 and a portion of the insulating material 203 within the cavity 2721 defined by the fourth sub-film 2723.

As can be seen from the above, fourth sub-film 2723 can form second portion 232 of conductive structure 230. Therefore, in order to enable the end of the fourth sub-film 2723 away from the first portion 231 to form the plug opening 242, as shown in fig. 39, after removing the insulating material 203 covering the stop layer 273, the insulating material 203 in the cavity 2721 defined by the fourth sub-film 2723 may be etched continuously, so that the surface of the insulating material 203 in the cavity 2721 defined by the fourth sub-film 2723 away from the substrate 260 side can be lower than the surface of the first dielectric film 250' away from the substrate 260 side.

It can be understood that, since the conductive plug 240 can close the plug opening 242, that is, the insulating material 203 can be located in the closed accommodating cavity, the requirement for the smoothness of the surface of the insulating material 203 on the side away from the substrate 260, that is, the requirement for the etching process of the insulating material 203 is reduced, the manufacturing process of the semiconductor structure 200 is simplified, and the production cost of the semiconductor structure 200 is reduced.

In addition, the conductive plug 240 is provided to close the plug opening 242, so that the requirement of reducing the height difference (L in fig. 39) between the surface of the insulating material 203 on the side away from the substrate 260 and the surface of the first dielectric film 250' on the side away from the substrate 260 can be reduced, thereby further simplifying the manufacturing process of the semiconductor structure 200 and reducing the production cost of the semiconductor structure 200.

Illustratively, the insulating material 203 and at least a portion of the stop layer may be removed by dry etching or wet etching.

It is understood that when the insulating material 203 in the cavity 2721 defined by the fourth sub-film 2723 is etched, at least a portion of the stop layer 273 can cover the first dielectric film 250 ', so as to protect the first dielectric film 250 ', prevent the first dielectric film 250 ' from being damaged during the etching process, and improve the reliability of the manufacturing method of the semiconductor structure 200.

Step S10245', the remaining portion of the stop layer is removed to expose the first dielectric film.

As shown in fig. 40, the remaining portion of the stop layer 273 is removed so that the first dielectric film 250' can be exposed. Illustratively, the remaining portion of the stop layer 273 may be removed using a CMP process or an etching process.

Step S10246', removing the end part of the fourth sub-film beyond the surface of the first dielectric film on the side far away from the substrate to form a second part.

As shown in fig. 41, the end of the fourth sub-film 2723 beyond the side of the first dielectric film 250 'away from the substrate 260 is removed so that the end of the fourth sub-film 2723 away from the substrate 260 can be flush or nearly flush with the side of the first dielectric film 250' away from the substrate 260 to form the second portion 232.

Illustratively, a CMP process may be used to remove the end of the fourth sub-film 2723 beyond the side of the first dielectric film 250' away from the substrate 260.

As can be seen from the above, the stop layer 273 includes a first stop layer 2731 and a first protective layer 2732. In some embodiments, the step of etching the insulating material to at least partially stop the layer (i.e., step S10244') includes:

and etching the insulating material and the first protection layer to the first stop layer.

As shown in fig. 39, when the insulating material 203 covering the stop layer 273 is etched, the first stop layer 2731 is used as an etching stop layer, and the first protection layer 2732 and the insulating material 203 covering the first protection layer 2732 are etched and removed together, so that an additional step is not required to remove the first protection layer 2732, the manufacturing process of the semiconductor structure 200 is further simplified, and the manufacturing cost of the semiconductor structure 200 is reduced.

It is to be understood that when the insulating material 203 in the cavity 2721 defined by the fourth sub-film 2723 is etched, the first etch stop layer 2731 can cover the first dielectric film 250 ', thereby protecting the first dielectric film 250 ' and preventing the first dielectric film 250 ' from being damaged.

In some embodiments, the step of removing the remaining portion of the stop layer (i.e., step S10245') includes:

the first stop layer is removed.

For example, as shown in fig. 40, an etching process or a CMP process may be used to remove the first stop layer 2731 so that the first dielectric film 250' can be exposed.

FIG. 42 is a block diagram of a channel structure according to further embodiments.

In some embodiments, as shown in fig. 42, the semiconductor structure 200 further includes a channel structure 223, the channel structure 223 being located in the core region and extending through the initial stacked structure 210'.

The above embodiments of the present disclosure have illustrated the structure and function of the channel structure 223, and are not described herein again. A method of forming the channel structure 223 is illustrated below.

FIG. 43 is a block diagram of an initial stacked configuration according to further embodiments.

In some embodiments, as shown in fig. 43, the initial stack structure 210 'includes an initial storage stack structure 221'. The initial memory stack structure 221' includes a plurality of gate sacrificial layers 2215 and gate insulating layers 2212, and the gate insulating layers 2212 and the gate sacrificial layers 2215 are alternately stacked.

Illustratively, the initial memory stack structure 221' may be formed using any one of a thin film deposition process of CVD, PVD, and ALD. The above embodiments of the disclosure have exemplified the materials, thicknesses, etc. of the gate insulating layer 2212 and the gate sacrificial layer 2215, and are not described herein again.

As shown in fig. 12, the channel structure 223 includes a storage channel structure 224, and the storage channel structure 224 penetrates through the initial storage stack structure 221'. A method of forming the memory channel structure 224 is illustrated below.

In some embodiments, a storage channel hole may be opened in a direction perpendicular to the substrate 260, the storage channel hole penetrating the initial storage stack structure 221'. A memory function layer 2241 and a channel layer 2242 are sequentially formed in the memory channel hole, and a storage channel filling medium 2247 is filled in a receiving space surrounded by the channel layer 2242 to form a storage channel structure 224.

Illustratively, the storage channel hole may be formed using a dry etching process or a wet etching process, and the storage function layer 2241 and the channel layer 2242 may be formed using any one of a thin film deposition process of CVD, PVD and ALD.

As shown in fig. 12, in some embodiments, the memory channel structure 224 includes a first memory channel structure 2244 and a second memory channel structure 2245, and the first memory channel structure 2244 and the second memory channel structure 2245 may be formed as follows.

For example, as shown in fig. 43, a first initial memory stack structure 2213 'may be formed on one side of the substrate 260, a first memory channel hole may be opened on the first initial memory stack structure 2213', and a channel sacrificial medium may be filled in the first memory channel hole to support the first memory channel hole. In some embodiments, the channel sacrificial dielectric may be silicon oxide or silicon nitride.

A second initial memory stack structure 2214 ' is formed on a side of the first initial memory stack structure 2213 ' away from the substrate 260, and a second memory channel hole is opened in the second initial memory stack structure 2214 ', and the second memory channel hole is communicated with the first memory channel hole. The channel sacrificial medium in the first storage channel hole is removed and the storage function layer 2241, the channel layer 2242 and the storage channel filling medium 2247 are sequentially formed in the first storage channel hole and the second storage channel hole to form the first storage channel structure 2244 and the second storage channel structure 2245.

In some embodiments, the memory channel plug 2246 may be formed as follows.

The second memory channel structure 2245 is etched away from the memory channel fill medium 2247 at the end of the first memory channel structure 2244 to form a memory channel window. Forming a memory channel plug 2246 within the memory channel window so that the memory channel plug 2246 can be in electrical contact with the channel layer 2242

In some embodiments, as shown in fig. 43, the initial stacked structure 210' further includes a selective stack structure 222. The select stack 222 is located on a side of the initial memory stack 221' remote from the substrate 260. The above embodiments of the present disclosure have been illustrated for selecting the structure and materials of the stacked structure 222, and will not be described herein. The following describes a method for selecting the formation method of the stacked structure 222.

In some embodiments, an insulating dielectric layer 2221, a first conductive layer 2222, and a second dielectric layer 2223 may be sequentially formed on a side of the initial memory stack structure 221' away from the substrate 260. As shown in fig. 42, the insulating dielectric layer 2221, the first conductive layer 2222, and the second dielectric layer 2223 extend from the core region to the non-core region.

The insulating dielectric layer 2221 is used as an etching stop layer, and the first conductive layer 2222 and the second dielectric layer 2223 in the non-core region are removed. For example, the first conductive layer 2222 and the second dielectric layer 2223 in the non-core region may be removed by dry etching or wet etching.

It is understood that after the first conductive layer 2222 and the second dielectric layer 2223 in the non-core region are removed, a height difference exists between the surface of the core region on the side away from the substrate 260 (i.e., the surface of the second dielectric layer 2223 on the side away from the substrate 260) and the surface of the non-core region on the side away from the substrate 260 (i.e., the surface of the insulating dielectric layer 2221 on the side away from the substrate 260).

In some embodiments, as shown in fig. 42, a filling layer 208 may be formed on a side of the insulating dielectric layer 2221 away from the initial memory stack structure 221'. The side of the filling layer 208 away from the insulating dielectric layer 2221 is flush or approximately flush with the side of the second dielectric layer 2223 away from the insulating dielectric layer 2221, that is, the surface of the core region away from the substrate 260 and the surface of the non-core region away from the substrate 260 can be flush or approximately flush, so as to improve the structural regularity of the semiconductor structure 200.

Illustratively, the fill layer 208 is formed using any one of a thin film deposition process of CVD, PVD, and ALD.

In other embodiments, the first dielectric layer 250 may be used to fill the insulating dielectric layer 2221 on the side away from the substrate 260 instead of the filling layer 208, so that the side of the first dielectric layer 250 away from the substrate 260 has a smooth planar structure.

The method of fabricating the select channel structure 225 is illustrated below.

Illustratively, a selection channel hole may be opened on the selection stacked structure 222, the selection channel hole penetrating through the selection stacked structure 222 in a direction perpendicular to the substrate 260 so that the memory channel plug 2246 can be exposed. An insulating layer 2251, a second conductive layer 2252, and a selection trench filling dielectric 2254 are sequentially formed within the selection trench hole to form a selection trench structure 225.

In some embodiments, the selective channel hole may be formed using a dry etch process or a wet etch process. Insulating layer 2251 and second conductive layer 2252 can be formed using any of CVD, PVD, and ALD thin film deposition processes.

In some embodiments, a portion of the selection channel fill dielectric 2254 of the selection channel structure 225 away from the end of the memory channel structure 224 may be removed by etching to form a selection channel window. A selection channel plug 2253 is formed within the selection channel window so that the selection channel plug 2253 can be electrically contacted to the second conductive layer 2252.

A method of forming the substrate 201 is illustrated below.

As can be seen from the above, the substrate 260 may be a composite substrate. In some embodiments, as shown in fig. 43, the semiconductor structure 200 further comprises a first etch stop layer 265 and a second etch stop layer 205'. A first etch stop layer 265 and a second etch stop layer 205 'are located between the substrate 260 and the initial memory stack structure 221'. The first etching barrier layer 265 is disposed on one side of the composite substrate, and the second etching barrier layer 205' is disposed on one side of the first etching barrier layer 265 away from the composite substrate.

For example, the first etch stopper 265 and the second etch stopper 205' may be formed using any one of a thin film deposition process of CVD, PVD, and ALD. For example, the material of the first etch stopper 265 may be silicon oxide, and the material of the second etch stopper 205' may be polysilicon.

In some embodiments, the composite substrate may be removed with the first etch stop layer 265 as an etch stop layer, so that the first etch stop layer 265 is exposed. With the second etch stop layer 205' as an etch stop layer, the first etch stop layer 265 is removed, and the memory function layer 2241 of the memory channel structure 224 away from the end of the selection channel structure 225, so that the channel layer 2242 of the memory channel structure 224 away from the end of the selection channel structure 225 can be exposed.

The source layer SL is formed such that the memory channel structure 224 is away from the channel layer 2242 at the end of the selection channel structure 225, and the memory channel filling medium 2247 filled in the channel layer 2242 can be embedded in the source layer SL, which is in electrical contact with the end of the memory channel structure 224 away from the selection channel structure 225, such that the substrate 260 can form the base 201, and such that the second etch stopper layer 205' can form the semiconductor structure layer 205.

Illustratively, the composite substrate and the first etch stop layer 265 may be removed using a dry etch process or a wet etch process.

Fig. 44 is a block diagram of a first dielectric layer according to some embodiments. FIG. 45 is a block diagram of a semiconductor structure according to yet further embodiments.

As can be seen from the above, the semiconductor structure 200 further includes a channel structure 223. The channel structure 223 is located in the core region and extends through the initial stacked structure 210'.

In some embodiments, the method for manufacturing the semiconductor structure 200 further comprises:

and forming a second opening on the first dielectric film to prepare a first dielectric layer. The second opening exposes an end of the channel structure away from the substrate.

As shown in fig. 44, a second opening 252 is formed in the first dielectric film 250' to prepare the first dielectric layer 250. Also, the second opening 252 exposes an end of the channel structure 223 remote from the substrate 260. It is understood that when the channel structure 223 includes the storage channel structure 224 and the selection channel structure 225, the second opening 252 can expose an end of the selection channel structure 225 away from the storage channel structure 224.

In some embodiments, the second opening 252 may be formed by dry etching or wet etching. It is understood that when the second opening 252 is formed by dry etching or wet etching, a portion of impurities may be formed in the second opening 252. Therefore, in some embodiments, after forming the second opening 252, the second opening 252 may be cleaned by wet etching or acid cleaning, etc. to remove impurities in the second opening 252.

In the embodiment of the disclosure, the first opening 251 and the second opening 252 are formed in the first dielectric film 250 ' to prepare the first dielectric layer 250, that is, the first dielectric layer 250 does not include other film layer structures except the first dielectric film 250 ', so that the first dielectric film 250 ' does not need to be repeatedly deposited or planarized, the preparation process of the semiconductor structure 200 is simplified, and the production cost of the semiconductor structure 200 is reduced.

In addition, since no other film layer structure needs to be formed on the first dielectric film 250 ', the thickness of the first dielectric film 250 ' is reduced, which facilitates the formation of the second opening 252 on the first dielectric film 250 ', i.e., facilitates the preparation of the first dielectric film 250, and further improves the convenience of the preparation method of the semiconductor structure 200.

Simultaneously with the step of forming the conductive plug, the method further comprises:

a channel contact is formed in electrical contact with an end of the channel structure proximate the first dielectric layer.

As shown in fig. 45, at the same time as forming the conductive plug 240, a channel contact 226 is formed in the second opening 252, so that the channel contact 226 can be electrically contacted with the end of the channel structure 223 close to the first dielectric layer 250, that is, the channel contact 226 can be electrically contacted with the end of the channel structure 223 far from the substrate 260.

It is to be understood that when channel structure 223 includes a storage channel structure 224 and a select channel structure 225, channel contact 226 can be in electrical contact with an end of select channel structure 225 distal to storage channel structure 224.

It should be noted that, in the embodiment of the present disclosure, the conductive plug 240 and the channel contact 226 are formed at the same time, which is understood to mean that the conductive plug 240 and the channel contact 226 are formed in the same step, but not limited to that both need to be formed at the same "time".

In the embodiment of the present disclosure, the channel contact 226 is formed at the same time as the conductive plug 240 is formed, so that the manufacturing process of the semiconductor structure 200 is further simplified, and the production cost of the semiconductor structure 200 is reduced. In addition, since the conductive plug 240 and the channel contact 226 are embedded in the first dielectric layer 250, the gate layer 2211 and the channel structure 223 can be electrically connected to the outside without depositing other film structures on the side of the first dielectric layer 250 away from the substrate 260, so that the structure of the semiconductor structure 200 is further simplified, the production flow of the semiconductor structure 200 is simplified, and the production cost of the semiconductor structure 200 is reduced.

In some embodiments, after the conductive plug 240 and the channel contact 226 are formed, a CMP process may be used to planarize a side of the conductive plug 240 away from the substrate 260, a side of the channel contact 226 away from the substrate 260, and a side of the first dielectric layer 250 away from the substrate 260, so that the side of the conductive plug 240 away from the substrate 260, the side of the channel contact 226 away from the substrate 260, and the side of the first dielectric layer 250 away from the substrate 260 can be leveled or nearly leveled, so as to improve structural regularity of the semiconductor structure 200.

In some embodiments, the conductive plug 240 and the channel contact 226 are the same material at the same layer.

FIG. 46 is a flow chart of method steps for fabricating a semiconductor structure according to still further embodiments. FIG. 47 is a block diagram of a reticle according to some embodiments.

In some embodiments, as shown in fig. 46, the step of forming the second opening on the first dielectric film comprises:

step S301, forming a mask plate on one side of the first dielectric film, which is far away from the initial stacking structure, wherein the mask plate is provided with an etching opening.

As shown in fig. 47, before forming the second opening 252, a mask 274 may be formed on a side of the first dielectric film 250 ' away from the initial stacked structure 210 ' so that the mask 274 can cover the first dielectric film 250 ', the second portion 232, and the insulating material 203 filled in the second portion 232.

Step S302, forming a second opening on the first dielectric film by utilizing the etching opening of the mask.

As shown in fig. 47, the mask 274 has an etching opening 2743, and the first dielectric film 250 'is etched through the etching opening 2743, so as to form a second opening 252 in the first dielectric film 250' and prepare the first dielectric layer 250. Illustratively, the second opening 252 may be formed by dry etching or wet etching.

It can be understood that by providing the mask 274, the portion of the first dielectric film 250 '(that is, the portion excluding the second opening 252) that does not need to be etched, the second portion 232, and the insulating material 203 filled in the second portion 232 can be protected, so that the insulating material 203 filled in the first dielectric film 250', the second portion 232, and the second portion 232 is prevented from being damaged by the etching process, and the reliability of the manufacturing method of the semiconductor structure 200 is improved.

In some embodiments, after forming the second opening 252, the reticle 274 may be removed to avoid the reticle 274 from interfering with the formation of the channel contact 226. Illustratively, the reticle 274 may be removed using a CMP process.

FIG. 48 is a flow chart of method steps for fabricating a semiconductor structure according to still further embodiments. FIG. 49 is a block diagram of a reticle according to further embodiments.

In some embodiments, as shown in fig. 48, the step of forming a mask on a side of the first dielectric film away from the initial stacked structure (i.e., step S301) includes:

in step S3011, a hard mask is formed and covers the first dielectric film.

It is to be understood that, as shown in fig. 49, a Hard Mask 2741 (hereinafter, referred to as Hard Mask) is formed on a side of the first dielectric film 250 ' away from the initial stacked structure 210 ' such that the Hard Mask 2741 covers the first dielectric film 250 '.

As can be appreciated, hard mask 2741 has a greater hardness. Illustratively, the material of the hard mask 2741 may be polysilicon, aluminum oxide, or other metals. In some embodiments, the hard mask 2741 can be formed using any one of a CVD, PVD, and ALD thin film deposition process.

In step S3012, a photoresist film is formed and the photoresist film covers the hard mask.

As shown in fig. 49, a photoresist film 2742 (Photo Resist, PR) is formed on a side of the hard mask 2741 away from the initial stack structure 210', so that the photoresist film 2742 can cover the hard mask 2741. For example, the photoresist film 2742 may be formed using any one of a thin film deposition process of CVD, PVD, and ALD.

It is to be appreciated that the hard mask 2741 can act as a support for the photoresist film 2742 due to the greater hardness of the hard mask 2741.

Step S3013, an etching opening penetrating the photoresist film and the hard mask is formed.

In some embodiments, the photoresist film 2742 may be exposed, the exposed photoresist film 2742 may be developed, and the unexposed photoresist film 2742 may be removed to pattern the photoresist film 2742, i.e., form an opening through the photoresist film 2742.

With the patterned photoresist film 2742 as a mask, the hard mask 2741 is etched to form a patterned hard mask 2741, as shown in FIG. 47, forming an etch opening 2743 through the hard mask 2741 and the photoresist film 2742.

It is understood that the first opening 251 is formed already when the first contact hole 263 is formed, since the first contact hole 263 penetrates the first dielectric film 250'. Thus, only the etching openings 2743 need to be formed on the mask 274 in the core region, and the etching openings 2743 do not need to be formed on the mask 274 in the non-core region, which reduces the number of the etching openings 2743 on the mask 274, facilitates the patterning of the photoresist film 2742 and the hard mask 2741, further simplifies the manufacturing process of the semiconductor structure 200, and reduces the production cost of the semiconductor structure 200.

As can be seen from the above, in some embodiments, after removing the first sub-film 2711 overlying the first dielectric film 250 'when the first sub-film 2711 is used as an etch stop layer for the insulating material 203, a CMP process may be used to remove the second sub-film 2712 away from the substrate 260 and beyond the end of the first dielectric film 250'. When the stop layer 273 is used as an etch stop layer for the insulating material 203, after the first stop layer 2731 covering the first dielectric film 250 'is removed, a CMP process may also be used to remove the end portion of the fourth sub-film 2723 away from the substrate 260 and beyond the first dielectric film 250'.

As can be seen, in some embodiments of the present disclosure, a CMP process may be used to perform a planarization process after removing the etch stop layer (e.g., the first sub-film 2711 or the first stop layer 2731) of the insulating material 203, so that the end of the second portion 232 away from the substrate 260 can be flush or nearly flush with the side of the first dielectric film 250' away from the substrate 260.

In other embodiments of the present disclosure, the planarization process may not be performed after the etching stop layer (e.g., the first sub-film 2711 or the first stop layer 2731) of the insulating material 203 is removed, so that, as shown in fig. 39 (taking the first stop layer 2731 as an example of an etching stop layer), an end of the fourth sub-film 2723 on a side away from the substrate 260 protrudes from a surface of the first dielectric film 250' on a side away from the substrate 260.

FIG. 50 is a block diagram of a reticle according to further embodiments. FIG. 51 is a block diagram of a reticle according to still further embodiments. FIG. 52 is a block diagram of a fourth sub-film according to further embodiments.

As shown in fig. 50, in other embodiments of the present disclosure, after removing the first stop layer 2731, no planarization process is performed, so that when the mask 274 is formed on the side of the first dielectric film 250 'away from the initial stacked structure 210', the end of the fourth sub-film 2723 away from the substrate 260 can protrude into the mask 274.

As shown in fig. 51, an etch opening 2743 is formed through the hard mask 2741 and the photoresist film 2742, and a second opening 252 is formed by etching the opening 2743 to prepare the first dielectric layer 250.

As shown in fig. 52, in some embodiments, after removing the hard mask 2741 and the photoresist film 2742, a CMP process may be used to planarize an end of the fourth sub-film 2723 on a side away from the substrate 260 to form the second portion 232.

In other embodiments, after forming the channel contact 226, the end of the fourth sub-film 2723 away from the substrate 260 may be planarized to form the second portion 232.

FIG. 53 is a flowchart of method steps for fabricating a semiconductor structure according to still further embodiments.

In some embodiments, as shown in fig. 53, after the step of forming the conductive plug, the method further includes:

step S401, a gate line gap penetrating the initial stacked structure is formed, and one gate line gap divides a core region of the initial stacked structure into two initial memory blocks.

It is to be understood that, as shown in fig. 5, the gate line slit 206 penetrates the initial stacked structures 210 ' in a direction perpendicular to the substrate 260, and separates two initial memory blocks 220 ' by a core region of one initial stacked structure 210 '. Illustratively, the gridline gap 206 extends from the core region to the non-core region.

In step S402, the gate sacrificial layer is replaced with a gate layer through the gate line gap to form a stacked structure and a memory block. Wherein the gate layer is in electrical contact with the first portion.

In some embodiments, the gate sacrificial layer 2215 may be removed through the gate line slit 206 by dry etching or wet etching to form the spaced cavities. Thereafter, the gate layer 2211 is formed in the cavity again through the gate line slit 206 to form the stacked structure 210 and the memory block 220.

It will be appreciated that first portion 231 of conductive structure 230 is disposed on and in contact with a layer of gate sacrificial layer 2215, thereby enabling gate layer 2211 to be in electrical contact with first portion 231 after gate sacrificial layer 2215 is replaced with gate layer 2211.

Fig. 54 is a block diagram of a first gate layer according to some embodiments. Fig. 55 is a block diagram of a first gate layer and a second gate layer according to some embodiments.

As can be seen from the above, in some embodiments, the gate line slit 206 may be formed after the conductive plug 240 is formed. In other embodiments, before the step of forming the conductive structure, the method further comprises:

a gate line gap is formed through the initial stacked structure, and a core area of the initial stacked structure is divided into two initial memory blocks by one gate line gap.

And replacing the grid sacrificial layer in the core area with a first grid layer through the grid line gap.

It is understood that, before the conductive structure 230 is formed, the gate line slit 206 is formed through the initial stacked structure 210 ', and as shown in fig. 54, the gate sacrificial layer 2215 in the core region of the initial stacked structure 210' is replaced by the first gate layer 2211c through the gate line slit 206, and the gate sacrificial layer 2215 in the non-core region is remained.

After the step of forming the conductive plug, further comprising:

and replacing a part of the grid sacrificial layer which is arranged at the same layer as and contacted with the first part with a second grid layer through the grid line gap so as to form a stacked structure and a storage block. Wherein the second gate layer is in electrical contact with the first gate layer and the first portion.

After the conductive plug 240 is formed, a portion of the gate sacrificial layer 2215 in the non-core region, which is in contact with the first portion 231, is replaced by the second gate layer 2211d, as shown in fig. 55, and the portion of the gate sacrificial layer 2215 which is not in contact with the first portion 231 remains.

It is understood that after replacing a portion of the gate sacrificial layer 2215, which is in the non-core region and in contact with the first portion 231, with the first gate layer 2211d, as shown in fig. 5, the stacked structure 210 and the memory block 220 can be formed.

It is to be understood that the second gate layer 2211d is in electrical contact with the first gate layer 2211c and the first portion 231, so that electrical signals can be transmitted between the second gate layer 2211d, the first gate layer 2211c and the first portion 231.

It should be noted that, in the embodiment of the disclosure, the first gate layer 2211c and the second gate layer 2211d are only used for distinguishing the gate layer 2211 located in the core region from the gate layer 2211 located in the non-core region, and the structure, material, and the like of the gate layer 2211 are not further limited.

It is to be understood that after the conductive plug 240 is formed, only a portion of the gate sacrificial layer 2215 in the non-core region and in contact with the first portion 231 is replaced with the gate layer 2211, and the portion of the gate sacrificial layer 2215 not in contact with the first portion is remained, so that the gate sacrificial layer 2215 can function as an electrical isolation, and the rest of the conductive structure 230 (except for the first portion 231) is prevented from being in electrical contact with the gate layer 2211, so that the gate layer 2211 can be electrically connected with the conductive plug 240 only through the first portion 231, thereby improving the reliability of the semiconductor structure 200.

FIG. 56 is a block diagram of a storage system according to some embodiments. FIG. 57 is a block diagram of memory systems according to further embodiments.

Referring to fig. 56, some embodiments of the present disclosure also provide a storage system 1000. The memory system 1000 includes a controller 20, and the three-dimensional memory 10 of some embodiments as above, the controller 20 being coupled to the three-dimensional memory 10 to control the three-dimensional memory 10 to store data.

The Storage system 1000 may be integrated into various types of Storage devices, for example, included in the same package (e.g., Universal Flash Storage (UFS) package or Embedded multimedia Card (eMMC) package). That is, the storage system 1000 may be applied to and packaged into different types of electronic products, such as a mobile phone (e.g., a cell phone), a desktop computer, a tablet computer, a laptop computer, a server, an in-vehicle device, a game console, a printer, a positioning device, a wearable device, a smart sensor, a mobile power supply, a Virtual Reality (VR) device, an Augmented Reality (AR) device, or any other suitable electronic device having storage therein.

In some embodiments, referring to fig. 56, the memory system 1000 includes the controller 20 and a three-dimensional memory 10, and the memory system 1000 may be integrated into a memory card.

The Memory Card includes any one of a PC Card (PCMCIA), a Compact Flash (CF) Card, a Smart Media (SM) Card, a Memory stick, a Multimedia Card (MMC), a Secure Digital Memory Card (SD), and a UFS.

In other embodiments, referring to fig. 57, the storage system 1000 includes a controller 20 and a plurality of three-dimensional memories 10, and the storage system 1000 is integrated into a Solid State Drive (SSD).

In storage system 1000, in some embodiments, controller 20 is configured for operation in a low duty cycle environment, such as an SD card, CF card, Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, mobile phones, and the like.

In other embodiments, the controller 20 is configured for operation in a high duty cycle environment SSD or eMMC for data storage and enterprise storage arrays for mobile devices such as smart phones, tablets, laptops, and the like.

In some embodiments, the controller 20 may be configured to manage data stored in the three-dimensional memory 10 and communicate with an external device (e.g., a host). In some embodiments, the controller 20 may also be configured to control operations of the three-dimensional memory 10, such as read, erase, and program operations. In some embodiments, the controller 20 may also be configured to manage various functions with respect to data stored or to be stored in the three-dimensional memory 10, including at least one of bad block management, garbage collection, logical to physical address translation, wear leveling. In some embodiments, the controller 20 is further configured to process error correction codes for data read from the three-dimensional memory 10 or written to the three-dimensional memory 10.

Of course, the controller 20 may also perform any other suitable functions, such as formatting the three-dimensional memory 10; for example, the controller 20 may communicate with an external device (e.g., a host) via at least one of various interface protocols.

It should be noted that the interface protocol includes at least one of a USB protocol, an MMC protocol, a Peripheral Component Interconnect (PCI) protocol, a PCI express (PCI-E) protocol, an Advanced Technology Attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a Small Computer System Interface (SCSI) protocol, an Enhanced Small Disk Interface (ESDI) protocol, an Integrated Drive Electronics (IDE) protocol, and a Firewire protocol.

Some embodiments of the present disclosure also provide an electronic device. The electronic device may be any one of a mobile phone, a desktop computer, a tablet computer, a notebook computer, a server, an in-vehicle device, a wearable device (e.g., a smart watch, a smart bracelet, smart glasses, etc.), a mobile power source, a game console, a digital multimedia player, and the like.

The electronic device may include the storage system 1000 described above, and may further include at least one of a Central Processing Unit (CPU), a cache (cache), and the like.

The above description is only for the specific embodiments of the present disclosure, but the scope of the present disclosure is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present disclosure should be covered within the scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims

1. A semiconductor structure, comprising:

a stacked structure comprising a core region and a non-core region; the stacked structure comprises a plurality of gate layers which are arranged in a stacking mode along a first direction, and the plurality of gate layers are distributed at intervals;

a conductive structure in the non-core region; the conductive structure includes a first portion and a second portion; the first portion is disposed in a same layer as and in electrical contact with a gate layer; the second part is electrically contacted with the first part, penetrates through the stacked structure upwards and encloses a plug opening; and the number of the first and second groups,

an electrically conductive plug located within the plug opening and in electrical contact with the second portion.

2. The semiconductor structure of claim 1, further comprising:

a first dielectric layer located over the stacked structure; the first dielectric layer is provided with a first opening, the end part of the second part far away from the first part and the conductive plug are positioned in the first opening.

3. The semiconductor structure of claim 2, wherein the first dielectric layer further has a second opening; the semiconductor structure further includes:

the channel structure is positioned in the core region and penetrates through the stacked structure;

and the channel contact is positioned in the second opening and is electrically contacted with the end part of the channel structure close to the first dielectric layer.

4. The semiconductor structure of claim 3, wherein the conductive plug is of the same material as the channel contact.

5. The semiconductor structure of claim 1, wherein the second portion comprises:

an extension, a first end of the extension in electrical contact with the first portion, a second end of the extension enclosing the plug opening.

6. The semiconductor structure of claim 1, further comprising:

an electrically isolating layer between the second portion and the stacked structure.

7. The semiconductor structure of claim 1, wherein the conductive structure and the conductive plug are enclosed to form a receiving cavity; the semiconductor structure further includes:

and the insulating material is filled in the accommodating cavity.

8. The semiconductor structure of claim 7, wherein the receiving cavity has an air gap therein.

9. The semiconductor structure of any one of claims 1 to 8, further comprising:

and the virtual channel structures are positioned in the non-core region and penetrate through the stacked structure.

10. A method for fabricating a semiconductor structure, comprising:

forming an initial stacked structure on one side of a substrate; the initial stacked structure comprises a core region and a non-core region; the initial stacking structure comprises a plurality of layers of grid sacrificial layers which are arranged in a stacking mode along a first direction, and the plurality of layers of grid sacrificial layers are distributed at intervals; wherein the first direction is perpendicular to the substrate;

forming a conductive structure in the non-core region; the conductive structure includes a first portion and a second portion; the first part and the grid sacrificial layer are arranged on the same layer and are in contact with each other, the second part is in electrical contact with the first part, and the second part penetrates through the initial stacking structure upwards and surrounds a plug opening;

forming a conductive plug within the plug opening and in electrical contact with the second portion.

11. The method of claim 10, further comprising, prior to the step of forming a conductive structure:

forming a first dielectric film, wherein the first dielectric film is positioned on the initial stacking structure;

the step of forming the conductive structure includes:

forming a first contact hole in the non-core area, wherein the first contact hole penetrates through the first dielectric film and exposes the target grid sacrificial layer; the target grid sacrificial layer is one of a plurality of grid sacrificial layers;

removing a portion of the target gate sacrificial layer through the first contact hole to form an epitaxial contact hole;

forming the first portion within the epitaxial contact hole;

forming the second portion within the first contact hole, the second portion in electrical contact with the first portion.

12. The method for fabricating a semiconductor structure according to claim 11, wherein the initial stacked structure further comprises a plurality of gate insulating layers, the gate insulating layers and the gate sacrificial layers being alternately stacked;

the step of forming a first contact hole in the non-core region comprises:

forming an initial contact hole in the non-core area, wherein the initial contact hole penetrates through the first dielectric film and exposes the target grid electrode insulating layer; the target gate insulating layer is one of a plurality of gate insulating layers;

forming an electrical isolation film in the initial contact hole;

and removing the bottom wall of the electric isolation film and part of the target gate insulating layer to form an electric isolation layer, and forming the first contact hole exposing the target gate sacrificial layer on the inner side of the electric isolation layer.

13. The method of claim 11, further comprising, after the step of forming the second portion in the first contact hole:

and filling an insulating material in the second part.

14. The method for manufacturing a semiconductor structure according to claim 13, wherein the steps of forming the second portion in the first contact hole and filling the second portion with an insulating material comprise:

forming a first conductive film including a first sub-film covering the first dielectric film and a second sub-film covering a sidewall of the first contact hole and the first portion;

depositing an insulating material, wherein the insulating material fills the cavity defined by the second sub-film, and the insulating material covers the first sub-film;

etching the insulating material to the first sub-film to remove a part of the insulating material in a cavity defined by the second sub-film and the insulating material covering the first sub-film;

and removing the first sub-film and the end part of the second sub-film beyond the surface of one side of the first dielectric film, which is far away from the substrate, so as to form the second part.

15. The method as claimed in claim 13, further comprising, after the step of forming the first dielectric film and before the step of forming the first contact hole in the non-core region:

forming a stop layer, wherein the stop layer covers the first dielectric film;

the step of forming a first contact hole in the non-core region includes:

forming the first contact hole which penetrates through the stop layer and the first dielectric film and exposes the target grid sacrificial layer in the non-core area;

the step of forming the second portion in the first contact hole and filling the second portion with an insulating material includes:

forming a second conductive film including a third sub-film and a fourth sub-film; the third sub-film covers the stop layer, and the fourth sub-film covers a sidewall of the first contact hole and the first portion;

removing the third sub-film to expose the stop layer;

depositing an insulating material, wherein the insulating material fills the cavity defined by the fourth sub-film, and covers the stop layer;

etching the insulating material to at least part of the stop layer so as to remove part of the insulating material in a cavity defined by the fourth sub-film and the insulating material covering the stop layer;

removing the rest part of the stop layer to expose the first dielectric film;

and removing the end part of the fourth sub-film beyond the surface of one side of the first dielectric film, which is far away from the substrate, so as to form the second part.

16. The method for fabricating a semiconductor structure according to any one of claims 11 to 15, wherein the semiconductor structure further comprises a channel structure located in the core region and extending through the initial stacked structure;

the preparation method further comprises the following steps:

forming a second opening on the first dielectric film to prepare a first dielectric layer; the second opening exposes the end part of the channel structure far away from the substrate;

simultaneously with the step of forming the conductive plug, the method further includes:

and forming a channel contact which is electrically contacted with the end part of the channel structure close to the first dielectric layer.

17. The method for fabricating a semiconductor structure according to claim 10, further comprising, after the step of forming a conductive plug:

forming gate line gaps penetrating the initial stacked structures, one gate line gap dividing the core region of one initial stacked structure into two initial memory blocks;

replacing the gate sacrificial layer with a gate layer through the gate line slit to form a stacked structure and a memory block, wherein the gate layer is in electrical contact with the first portion.

18. The method of claim 10, further comprising, prior to the step of forming a conductive structure:

replacing the grid sacrificial layer in the core area with a first grid layer through the grid line gap;

after the step of forming the conductive plug, further comprising:

and replacing a part of the grid sacrificial layer which is arranged on the same layer as and contacted with the first part by a second grid layer through the grid line gap so as to form a stacked structure and a storage block, wherein the second grid layer is electrically contacted with the first grid layer and the first part.

19. A three-dimensional memory, comprising:

a semiconductor structure as claimed in any one of claims 1 to 9;

a peripheral device electrically connected to the semiconductor structure.

20. A storage system, comprising:

the three-dimensional memory of claim 19;

a controller coupled to the three-dimensional memory to control the three-dimensional memory to store data.

21. An electronic device comprising the storage system of claim 20.