CN114420698A

CN114420698A - Semiconductor structure, manufacturing method thereof, memory, storage system and electronic device

Info

Publication number: CN114420698A
Application number: CN202111584084.4A
Authority: CN
Inventors: 贾信磊; 韩佳茵; 徐盼; 杨琨; 靳磊
Original assignee: Yangtze Memory Technologies Co Ltd
Current assignee: Yangtze Memory Technologies Co Ltd
Priority date: 2021-12-22
Filing date: 2021-12-22
Publication date: 2022-04-29

Abstract

The disclosure provides a semiconductor structure and a preparation method thereof, a memory, a storage system and electronic equipment, and relates to the technical field of semiconductor chips, so that mutual interference among storage units is reduced, and device performance is improved. The semiconductor structure includes a stacked layer, and a first isolation structure, a second isolation structure, and a channel structure that penetrate the stacked layer. The stack layer includes a plurality of first dielectric layers and a plurality of gate line layers alternately stacked. The first isolation structure extends along a first direction to divide the gate line layer into a plurality of gate lines. The second isolation structure extends along the first direction to divide the grid line into at least two sub-grid lines; the dielectric constant of the second isolation structure is smaller than that of the first dielectric layer. At least part of the channel structure is positioned on a straight line where the second isolation structure is positioned, and the sub-gate lines on two sides of the second isolation structure are respectively contacted with the channel structure. The semiconductor structure is applied to a memory to realize reading and writing operations of data.

Description

Semiconductor structure, manufacturing method thereof, memory, storage system and electronic device

Technical Field

The present disclosure relates to the field of semiconductor chip technologies, and in particular, to a semiconductor structure, a manufacturing method thereof, a memory, a storage system, and an electronic device.

Background

As the feature size of memory cells approaches the lower process limit, planar processes and manufacturing techniques become challenging and costly, which causes the storage density of 2D or planar NAND flash memories to approach the upper limit.

To overcome the limitations imposed by 2D or planar NAND flash memories, memories having a three-dimensional structure (3D NAND) have been developed to increase the storage density by arranging memory cells three-dimensionally over a substrate.

However, in order to increase the storage density, the size of the memory is smaller and smaller, and mutual interference between memory cells is difficult to ignore when programming operation is performed, which affects the performance of the device.

Disclosure of Invention

Embodiments of the present disclosure provide a semiconductor structure, a manufacturing method thereof, a memory, a storage system, and an electronic device, so as to reduce mutual interference between storage units and improve device performance.

In order to achieve the purpose, the embodiment of the disclosure adopts the following technical scheme:

in one aspect, a semiconductor structure is provided. The semiconductor structure includes a stack layer, and a first isolation structure, a second isolation structure, and a channel structure that penetrate the stack layer. The stack layer includes a plurality of first dielectric layers and a plurality of gate line layers that are alternately stacked. The first isolation structure extends along a first direction to divide the gate line layer into a plurality of gate lines. The second isolation structure extends along the first direction to divide the grid line into at least two sub-grid lines; the dielectric constant of the second isolation structure is smaller than that of the first dielectric layer. The channel structure is arranged between two adjacent first isolation structures; at least part of the channel structure is located on the straight line where the second isolation structure is located, and the sub-gate lines on the two sides of the second isolation structure are respectively in contact with the channel structure located on the straight line where the second isolation structure is located.

In the semiconductor structure provided by the above embodiment of the present disclosure, the second isolation structure divides the gate line into a plurality of sub-gate lines, the channel structure is located on a straight line where the second isolation structure is located, and the sub-gate lines located on two sides of the second isolation structure where the channel structure is located are respectively in contact with the channel structure. That is, in the plane of the gate line layer, one channel structure is in contact with each of the two sub-gate lines to form two transistors disposed opposite to each other. In this case, one memory cell string may include more memory cells, which may increase the memory density of the semiconductor structure without increasing the total number of stacked layers.

In addition, the dielectric constant of the second isolation structure is smaller than that of the first dielectric layer. That is to say, the second isolation structure can be made of a material with a low dielectric constant, so that the effect of reducing electric field coupling between two transistors oppositely arranged on the plane where the grid line layer is located in the same memory cell string and the effect of reducing interference between two adjacent grid line layers in the direction perpendicular to the plane where the grid line layer is located are achieved, and therefore device performance is improved.

In some embodiments, the second isolation structure penetrates through a corresponding row of channel structures along the first direction to divide the channel structures into a first sub-channel structure and a second sub-channel structure, the first sub-channel structure being in line contact with the first sub-gate, and the second sub-channel structure being in line contact with the second sub-gate.

In some embodiments, the second isolation structure is in contact with an outer surface of a corresponding row of channel structures along the first direction.

In some embodiments, the semiconductor structure further comprises a third isolation structure extending through the stacked layers, the third isolation structure being located between two adjacent second isolation structures.

In some embodiments, the second isolation structure has a dielectric constant less than or equal to 3.

In some embodiments, the material of the second isolation structure comprises any one of carbon-doped silicon oxide, carbon-doped silicon hydroxide, and fluorine-doped silicon oxide.

In some embodiments, the dimension of the second isolation structure along a second direction is smaller than the diameter of the channel structure, the second direction is perpendicular to the first direction and parallel to the plane of the stacked layers.

In some embodiments, the first dielectric layer is recessed near the boundary of the channel structure compared to the sub-gate line. The semiconductor structure further comprises a plurality of second dielectric layers, and the second dielectric layers are positioned between the first dielectric layers and the channel structures along the direction parallel to the plane of the stacked layers; and the second dielectric layer is positioned between two adjacent gate layers along the direction vertical to the plane of the stacked layers, and the dielectric constant of the second dielectric layer is smaller than that of the first dielectric layer.

In some embodiments, one side of the second dielectric layer is in contact with the first dielectric layer and the other side is in contact with the channel structure.

In another aspect, a method for fabricating a semiconductor structure is provided, including: preparing an intermediate semiconductor structure; the intermediate semiconductor structure comprises a stacked layer, a first isolation structure and a channel structure, wherein the first isolation structure and the channel structure penetrate through the stacked layer; the stacked layer comprises a plurality of first dielectric layers and a plurality of grid line layers which are alternately stacked, the first isolation structures extend along a first direction to divide the grid line layers into a plurality of grid lines, and the channel structures are located between two adjacent first isolation structures. Forming a second isolation structure penetrating through the stack layer, wherein the second isolation structure extends along the first direction to divide the grid line into at least two sub-grid lines; the dielectric constant of the second isolation structure is smaller than that of the first dielectric layer; at least part of the channel structures are in contact with one second isolation structure and are in contact with the two sub-grid lines in the plane direction of the grid line layer.

In some embodiments, the forming a second isolation structure through the stacked layers comprises: etching the stacked layer to form a second gap; the second slit extends in the first direction to divide the gate line into sub-gate lines and the channel structure into a first sub-channel structure and a second sub-channel structure. Filling a target material in the second gap to form a second isolation structure; the dielectric constant of the target material is less than the dielectric constant of the material of the first dielectric layer.

In some embodiments, the preparing the intermediate semiconductor structure comprises: forming an initial stack layer; the initial stack layer comprises a plurality of sacrificial layers and a plurality of first dielectric layers which are alternately arranged. Forming a trench hole through the initial stack of layers. And forming a channel structure in the channel hole. A first aperture is formed through the initial stack of layers. Replacing the sacrificial layer with a gate line layer via the first slit. And forming a first isolation structure in the first gap.

In some embodiments, between forming the channel hole and forming the channel structure, the method of making further comprises: and removing the edge part of the first dielectric layer close to the channel hole through the channel hole, so that the boundary of the first dielectric layer close to the channel hole is retracted compared with the boundary of the sacrificial layer close to the channel hole, and a groove is formed. Forming a second dielectric layer in the groove; the dielectric constant of the second dielectric layer is smaller than that of the first dielectric layer.

In some embodiments, the forming a second dielectric layer in the groove includes: depositing a target material to form a second dielectric film; the dielectric constant of the target material is less than the dielectric constant of the material of the first dielectric layer. And removing the part of the second dielectric film covering the initial stacking layer and the part of the second dielectric film covering the inner wall of the channel hole to form the second dielectric layer.

In another aspect, a method for fabricating a semiconductor structure is provided, including: forming an initial stack layer; the initial stack layer comprises a plurality of sacrificial layers and a plurality of first dielectric layers which are alternately arranged. Forming a second isolation structure through the initial stack of layers; the second isolation structure extends along a first direction to divide the sacrificial layer into a plurality of sub-sacrificial layers; the dielectric constant of the second isolation structure is smaller than that of the first dielectric layer. Forming a channel hole penetrating through the initial stacking layer, and forming a channel structure in the channel hole; at least part of the channel structure is in contact with one second isolation structure and is in contact with the two sub-sacrificial layers in the plane direction of the sacrificial layer.

In some embodiments, the forming a second isolation structure through the initial stack of layers comprises: forming a second aperture through the initial stack of layers; the second slit extends in the first direction to divide the sacrificial layer into a plurality of sub-sacrificial layers. Filling a target material in the second gap; the dielectric constant of the target material is less than the dielectric constant of the material of the first dielectric layer.

In some embodiments, after forming the channel structure, the method of making further comprises: forming a first gap and a third gap through the initial stack of layers; the first gap and the third gap extend along a first direction, the first gap is located on two sides of the channel structures arranged in an array mode, and the third gap is located between two adjacent rows of the channel structures. Replacing the sacrificial layer with a gate line layer via the first slit and the third slit. And respectively forming a first isolation structure and a third isolation structure in the first gap and the third gap.

In yet another aspect, a memory is provided. The memory includes a semiconductor structure as described in some embodiments above, and a peripheral device electrically connected to the semiconductor structure.

In yet another aspect, a storage system is provided, including: a memory as described above, and a controller coupled to the memory to control the memory to store data.

In yet another aspect, an electronic device is provided, which includes the storage system as described above.

It can be understood that, in the manufacturing method of the semiconductor structure, the memory, the storage system and the electronic device provided in the embodiments of the disclosure, reference may be made to the above beneficial effects of the semiconductor structure, and details are not described herein again.

Drawings

In order to more clearly illustrate the technical solutions in the present disclosure, the drawings needed to be used in some embodiments of the present disclosure will be briefly described below, and it is apparent that the drawings in the following description are only drawings of some embodiments of the present disclosure, and other drawings can be obtained by those skilled in the art according to the drawings. Furthermore, the drawings in the following description may be regarded as schematic diagrams, and do not limit the actual size of products, the actual flow of methods, the actual timing of signals, and the like, involved in the embodiments of the present disclosure.

FIG. 1 is a cross-sectional view of a memory according to some embodiments;

FIG. 2 is a cross-sectional view of a memory cell string in the memory of FIG. 1;

FIG. 3 is an equivalent circuit diagram of the memory cell string of FIG. 2;

FIG. 4 is a top view of a semiconductor structure according to some embodiments;

FIG. 5 is a top view of semiconductor structures according to other embodiments;

FIG. 6 is a cross-sectional view taken along section line A-A' of FIG. 4;

FIGS. 7-18 are diagrams of fabrication steps of methods of fabricating semiconductor structures according to some embodiments;

FIGS. 19-23 are diagrams of fabrication steps of methods of fabricating semiconductor structures according to further embodiments;

FIGS. 24-30 are flow diagrams of methods of fabricating semiconductor structures according to some embodiments;

FIGS. 31-37 are flow diagrams of methods of fabricating semiconductor structures according to further embodiments;

FIG. 38 is a block diagram of a storage system according to some embodiments;

FIG. 39 is a block diagram of memory systems according to further embodiments.

Detailed Description

Technical solutions in some embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings, and it is obvious that the described embodiments are only a part of the embodiments of the present disclosure, and not all of the embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments provided by the present disclosure belong to the protection scope of the present disclosure.

In the description of the present disclosure, it is to be understood that the terms "center", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like indicate orientations or positional relationships based on those shown in the drawings, and are only for convenience in describing and simplifying the disclosure, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed in a specific orientation, and be operated, and thus, should not be construed as limiting the disclosure.

Throughout the specification and claims, the term "comprising" is to be interpreted in an open, inclusive sense, i.e., as "including, but not limited to," unless the context requires otherwise. In the description herein, the terms "one embodiment," "some embodiments," "an example embodiment," "exemplary" or "some examples" or the like are intended to mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the disclosure. The schematic representations of the above terms are not necessarily referring to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be included in any suitable manner in any one or more embodiments or examples.

In the following, the terms "first", "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the embodiments of the present disclosure, "a plurality" means two or more unless otherwise specified.

In describing some embodiments, expressions of "coupled" and "connected," along with their derivatives, may be used. For example, the term "connected" may be used in describing some embodiments to indicate that two or more elements are in direct physical or electrical contact with each other. As another example, some embodiments may be described using the term "coupled" to indicate that two or more elements are in direct physical or electrical contact. The term "coupled," however, may also mean that two or more elements are not in direct contact with each other, but yet still co-operate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents herein.

"at least one of A, B and C" has the same meaning as "A, B or at least one of C," each including the following combination of A, B and C: a alone, B alone, C alone, a and B in combination, a and C in combination, B and C in combination, and A, B and C in combination.

"A and/or B" includes the following three combinations: a alone, B alone, and a combination of A and B.

The use of "adapted to" or "configured to" herein is meant to be an open and inclusive language that does not exclude devices adapted to or configured to perform additional tasks or steps.

Additionally, the use of "based on" means open and inclusive, as a process, step, calculation, or other action that is "based on" one or more stated conditions or values may in practice be based on additional conditions or values beyond those stated.

As used herein, "about," "approximately," or "approximately" includes the stated values as well as average values that are within an acceptable range of deviation for the particular value, as determined by one of ordinary skill in the art in view of the measurement in question and the error associated with measurement of the particular quantity (i.e., the limitations of the measurement system).

In the context of this disclosure, the meaning of "on … …," above, "and" over "should be interpreted in the broadest manner such that" on.

Example embodiments are described herein with reference to cross-sectional and/or plan views as idealized example figures. In the drawings, the thickness of layers and regions are exaggerated for clarity. Variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, the exemplary embodiments should not be construed as limited to the shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the exemplary embodiments.

As used herein, the term "substrate" refers to a material onto which subsequent layers of material may be added. The substrate itself may be patterned. The material added on the substrate may be patterned or may remain unpatterned. In addition, the substrate may include a variety of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, and the like. Alternatively, the substrate may be made of a non-conductive material such as glass, plastic, or sapphire wafer.

The term "three-dimensional memory" refers to a semiconductor device formed of strings of memory cell transistors (referred to herein as "strings of memory cells," e.g., NAND memory cells) arranged in an array on a major surface of a substrate or a source layer and extending in a direction perpendicular to the substrate or source layer. As used herein, the term "vertically" means nominally perpendicular to a major surface (i.e., a lateral surface) of the substrate or source layer.

Fig. 1 is a cross-sectional view of a memory according to some embodiments of the present disclosure, fig. 2 is a cross-sectional view of a memory cell string in the memory shown in fig. 1, and fig. 3 is an equivalent circuit diagram of the memory cell string in fig. 2.

Referring to fig. 1, some embodiments of the present disclosure provide a memory 10. Memory 10 may include a semiconductor structure 200. The memory 10 may further include a source layer SL coupled to the semiconductor structure 200, and a peripheral device 100 coupled to the semiconductor structure 200. The peripheral device 100 may be disposed on a side of the semiconductor structure 200 away from the source layer SL.

The material of the source layer SL may include a semiconductor material such as monocrystalline silicon, polycrystalline silicon, monocrystalline germanium, a III-V compound semiconductor material, a II-VI compound semiconductor material, and other suitable semiconductor materials. The source layer SL may be partially or fully doped. Illustratively, the source layer SL may include a doped region doped with a p-type dopant. The source layer SL may further include an undoped region.

Referring to fig. 1 and 2, a semiconductor structure 200 may include memory cell transistor strings 400 (referred to herein as "memory cell strings," e.g., NAND memory cell strings) arranged in an array. The source layer SL may be coupled to sources of the plurality of memory cell strings 400.

Specifically, referring to fig. 2 and 3, the memory cell string 400 may include a plurality of transistors T, and one transistor T (e.g., T1 to T12 in fig. 3) may be provided as one memory cell, and the transistors T are connected together to form the memory cell string 400. One transistor T (e.g., each transistor T) may be formed of a semiconductor channel 241 and one gate line G surrounding the semiconductor channel 241. Wherein the gate line G is configured to control a turn-on state of the transistor T.

It should be noted that the numbers of transistors in fig. 1 to fig. 3 are merely schematic, and the memory cell string of the memory provided by the embodiment of the present disclosure may further include other numbers of transistors, for example, 4, 16, 32, and 64.

Further, along the third direction Z, the gate line positioned lowermost among the plurality of gate lines G (e.g., the gate line closest to the source layer SL among the plurality of gate lines G) is configured as a source side select gate SGS1 and an SGS2, and the source side select gate SGS1 is configured to control the on-state of the transistor T6, and thus the on-state of one source side channel in the memory cell string 400; the source select gate SGS2 is configured to control the conduction state of transistor T12, which in turn controls the conduction state of another source channel in the string of memory cells 400. The uppermost gate line among the gate lines G (e.g., the gate line farthest from the source layer SL among the gate lines G) is configured as drain select gates SGD1 and SGD2, and the drain select gate SGD1 is configured to control the on-state of the transistor T1, and thus, the on-state of one drain channel in the memory cell string 400; the drain select gate SGD2 is configured to control the conduction state of transistor T7, which in turn controls the conduction state of another drain channel in the string of memory cells 400. The gate line located in the middle of the plurality of gate lines G may be configured as a plurality of word lines WL including, for example, word line WL0, word line WL1, word line WL2, word lines WL3, WL4, WL5, WL6, and WL 7. Writing, reading, and erasing of data of individual memory cells (e.g., transistors T) in the memory cell string 400 may be accomplished by writing different voltages on the word lines WL.

The memory 10 extends in an X-Y plane, and the first direction X and the second direction Y are, for example, two orthogonal directions in a plane (e.g., a plane in which the source layer SL is located) in which the semiconductor structure 200 is located: the first direction X is, for example, an extending direction of the word lines WL, and the second direction Y is, for example, an extending direction of the bit lines. The third direction Z is perpendicular to the plane of the semiconductor structure 200, i.e., perpendicular to the X-Y plane.

As used in this disclosure, whether a component (e.g., a layer, structure, or device) is "on," "above," or "below" another component (e.g., a layer, structure, or device) of a semiconductor device (e.g., a memory) is determined in a third direction Z relative to a substrate or a source layer of the semiconductor device when the substrate or the source layer is located in a lowest plane of the semiconductor device in the third direction Z. Throughout this disclosure, the same concepts are applied to describe spatial relationships.

With continued reference to fig. 1, in some embodiments, the semiconductor structure 200 may further include an array interconnect layer 290. Array interconnect layer 290 may be coupled with memory cell string 400. The array interconnect layer 290 may include drain terminals (i.e., bit lines) of the memory cell strings 400, which may be coupled to semiconductor channels of the respective transistors T in at least one of the memory cell strings 400.

The array interconnect layer 290 may include one or more first interlayer insulating layers 292, and may further include a plurality of contacts insulated from each other by the first interlayer insulating layers 292, the contacts including, for example, bitline contacts BL-CNT coupled to bitlines; a drain select gate contact coupled to drain select gate SGD. The array interconnect layer 290 may also include one or more first interconnect conductor layers 291. The first interconnect conductor layer 291 may include a plurality of connection lines, such as bit lines, and word line connection lines coupled to the word lines WL. The material of the first interconnect conductor layer 291 and the contact may be a conductive material such as a combination of one or more of tungsten, cobalt, copper, aluminum, and metal silicide, and may be other suitable materials. The material of the first interlayer insulating layer 292 is an insulating material, such as silicon oxide, silicon nitride, and a combination of one or more of high-k insulating materials, and may be other suitable materials.

The peripheral device 100 may include peripheral circuitry. The peripheral circuitry is configured to control and sense the array device. The peripheral circuitry may be any suitable digital, analog, and/or mixed signal control and sensing circuitry for supporting array device operation (or working), including but not limited to page buffers, decoders (e.g., row and column decoders), sense amplifiers, drivers (e.g., word line drivers), charge pumps, current or voltage references, or any active or passive component of circuitry (e.g., transistors, diodes, resistors, or capacitors). The peripheral circuits may also include any other circuits compatible with advanced Logic processes, including Logic circuits (e.g., processors and Programmable Logic Devices (PLDs) or Memory circuits (e.g., Static Random-Access memories (SRAMs)).

Specifically, in some embodiments, the peripheral device 100 may include a substrate 110, a transistor 120 disposed on the substrate 110, and a peripheral interconnect layer 130 disposed on the substrate 110. The peripheral circuitry may include a transistor 120.

The material of the substrate 110 may be monocrystalline silicon, or may be other suitable materials, such as silicon germanium, or a silicon-on-insulator thin film.

Peripheral interconnect layer 130 is coupled to transistor 120 to enable the transmission of electrical signals between transistor 120 and peripheral interconnect layer 130. The peripheral interconnection layer 130 may include one or more second interlayer insulating layers 131 and may further include one or more second interconnection conductor layers 132. Different second interconnect conductor layers 132 may be coupled to each other by contacts. The material of the second interconnect conductor layer 132 and the contacts may be a conductive material, such as a combination of one or more of tungsten, cobalt, copper, aluminum, and metal silicide, and may be other suitable materials. The material of the second interlayer insulating layer 131 is an insulating material, such as one or a combination of silicon oxide, silicon nitride, and a high-k insulating material, and may be other suitable materials.

The peripheral interconnect layer 130 may be coupled with the array interconnect layer 290 such that the semiconductor structure 200 and the peripheral device 100 may be coupled. Specifically, since the peripheral interconnect layer 130 is coupled to the array interconnect layer 290, peripheral circuits in the peripheral device 100 may be coupled to the memory cell strings in the semiconductor structure 100 to enable transmission of electrical signals between the peripheral circuits and the memory cell strings. In some possible implementations, a bonding interface 500 may be disposed between the peripheral interconnection layer 130 and the array interconnection layer 290, and the peripheral interconnection layer 130 and the array interconnection layer 290 may be bonded and coupled to each other through the bonding interface 500.

To increase memory density, the size of memory 10 is smaller and smaller, as are the distances between the individual transistors T in the memory cell string 400. In this case, when the transistor T is programmed, threshold voltages of other transistors T adjacent to the transistor T being programmed in the same memory cell string 400 may increase due to electric field coupling, thereby affecting device performance.

Based on this, in some embodiments, as shown in fig. 4 and 6, the semiconductor structure 200 described above includes a stacked layer 210, and a first isolation structure 220, a second isolation structure 230, and a channel structure 240 penetrating the stacked layer 210.

With reference to fig. 4 and fig. 6, the stack layer 210 may be disposed on the source layer SL, that is, the stack layer 210 is located on one side of the thickness direction of the source layer SL (i.e., the third direction Z in fig. 6). The stack layer 210 includes a plurality of first dielectric layers 211 and a plurality of gate line layers 212, and the first dielectric layers 211 and the gate line layers 212 are alternately stacked in the third direction Z.

It should be noted that the material of the first dielectric layer 211 may include an insulating material, and the insulating material includes at least one of silicon oxide, silicon nitride, silicon oxynitride, doped silicon oxide, organosilicate glass, dielectric metal oxide (e.g., aluminum oxide, hafnium oxide, etc.) and silicate thereof, and an organic insulating material.

The gate line layer 212 may include a conductor layer 2121, and a material of the conductor layer 2121 may include a conductive material, such as at least one of tungsten, cobalt, copper, aluminum, doped silicon, and silicide.

In some embodiments, as shown in fig. 6, the gate line layer 212 may further include a metal compound layer 2122, the metal compound layer 2122 being located between the conductor layer 2121, the channel structure 240 and the first dielectric layer 211, the metal compound layer 2122 being configured as an adhesive layer to improve adhesion between the conductor layer 2121 and the first dielectric layer 211. Wherein the material of the metal compound layer 2122 includes at least one of titanium nitride, tantalum nitride, and tungsten carbide.

In some embodiments, as shown in fig. 6, the gate line layer 212 may further include a high dielectric constant layer 2123, the high dielectric constant layer 2123 being located between the metal compound layer 2122, the channel structure 240 and the first dielectric layer 211 to reduce the risk of charges in the channel structure 240 flowing to the conductor layer. Wherein the high-k layer 2123 has a dielectric constant value greater than or equal to 7. Illustratively, the material of high dielectric constant layer 2123 includes at least one of aluminum oxide, hafnium oxide, and tantalum oxide.

In some embodiments, the stack layer 210 is in contact with the source layer SL. In other embodiments, other functional layers are disposed between the stack layer 210 and the source layer SL. For example, a semiconductor layer 281 and a third dielectric layer 282 are further disposed between the stack layer 210 and the source layer SL, the semiconductor layer 281 is in contact with the stack layer 210, and the third dielectric layer 282 is in contact with the source layer SL. The layer of the stack 210 closest to the source layer SL may be the first dielectric layer 211.

Note that the material of the semiconductor layer 281 includes a semiconductor material such as single crystal silicon, polycrystalline silicon, single crystal germanium, a group III-V compound semiconductor material, a group II-VI compound semiconductor material, and other suitable semiconductor materials. The material of the third dielectric layer 282 includes an insulating material, which may include at least one of silicon oxide, silicon nitride, silicon oxynitride, doped silicon oxide, organosilicate glass, dielectric metal oxides (e.g., aluminum oxide, hafnium oxide, etc.) and silicates thereof, and organic insulating materials.

The number of layers of the stacked layer 210 is not limited by the embodiments of the present disclosure, for example, the number of layers of the stacked layer 210 may be 8, 64, 128, and the like. It is understood that the greater the number of layers of the stacked layers 210, the higher the integration, the greater the number of transistors T in the memory cell string 400 formed therefrom.

As shown in fig. 4 and 6, the first isolation structure 220 extends in the first direction X and penetrates the stack layer 210 to divide the gate line layer 212 into a plurality of gate lines G. The first isolation structure 220 includes an insulating isolation portion 221, and the insulating isolation portion 221 contacts with the first dielectric layer 211 and the side surface of the gate line layer 212. It should be noted that the material of the gate line filling layer 222 may be an insulating material, and the insulating material may include at least one of silicon oxide, silicon nitride, and a high-k insulating material, which is not limited in this disclosure.

In some embodiments, as shown in fig. 6, the first isolation structure 220 may further include a gate line filling layer 222. The insulating isolation portion 221 contacts with the first dielectric layer 211 and the side surface of the gate line layer 212, a cavity is left inside the insulating isolation portion 221, and the gate line filling layer 222 fills the cavity to provide a mechanical support effect. It should be noted that the material of the gate line filling layer 222 may be a conductive material or an insulating material, and the disclosure is not limited in this respect.

As shown in fig. 4 and 6, the second isolation structure 230 extends along the first direction X and penetrates the stack layer 210 to separate the gate line G into at least two sub-gate lines G1. The dielectric constant of the second isolation structure 230 is less than the dielectric constant of the first dielectric layer 211.

As shown in fig. 4 and 6, the channel structure 240 penetrates the stack layer 210 and is arranged between two adjacent first isolation structures 220. In addition, at least a portion of the channel structure 240 is located on a straight line where the second isolation structure 230 is located, and the sub-gate lines G1 on two sides of the second isolation structure 230 are respectively in contact with the channel structure 240 located on the straight line where the second isolation structure 230 is located.

It should be noted that, in the case that the stack layer 210 may be disposed on the source layer SL, and a semiconductor layer and a third dielectric layer are further disposed between the stack layer 210 and the source layer SL, the channel structure 240 further penetrates through the semiconductor layer and the third dielectric layer, so that the channel structure 240 may be coupled with the source layer SL.

In some embodiments, referring to fig. 6, the channel structure 240 includes a memory function layer 241 and a semiconductor channel layer 242, one side of the memory function layer 241 is in contact with the first dielectric layer 211 and the side of the gate layer 212, and the other side is in contact with the semiconductor channel layer 242; that is, the memory function layer 241 is located between the semiconductor channel layer 242 and the first dielectric layer 211 and the gate line layer 212.

Note that the material of the semiconductor channel layer 242 includes a semiconductor material such as single crystal silicon, polycrystalline silicon, single crystal germanium, a group III-V compound semiconductor material, a group II-VI compound semiconductor material, and other suitable semiconductor materials.

The memory function layer 241 includes a blocking layer 2411, a charge trapping layer 2412 and a tunneling layer 2413, and the materials of the blocking layer 2411, the charge trapping layer 2412, the tunneling layer 2413 and the semiconductor channel layer 242 may be silicon oxide, silicon nitride, silicon oxide and polysilicon, respectively, so as to form a "SONO" structure.

In some embodiments, as shown in fig. 6, the channel structure 240 further includes a channel filling layer 243, and the channel filling layer 243 is disposed on a side of the semiconductor channel layer 242 away from the storage function layer 241 to provide a mechanical supporting function. The material of the trench filling layer 243 includes an insulating material, and the insulating material may include at least one of silicon oxide, silicon nitride, silicon oxynitride, doped silicon oxide, organosilicate glass, dielectric metal oxide (e.g., aluminum oxide, hafnium oxide, etc.) and silicate thereof, and an organic insulating material.

As can be seen from the above, the second isolation structure 230 divides the gate line G into a plurality of sub-gate lines G1, the channel structure 240 is located on the straight line where the second isolation structure 230 is located, and the sub-gate lines G1 located at two sides of the second isolation structure 230 where the channel structure 240 is located are in contact with the channel structure 240 respectively. That is, in the plane (X-Y plane) in which the gate line layer 212 is located, one channel structure 240 is in contact with two sub-gate lines G1, respectively, to form two transistors T disposed oppositely. In this case, one memory cell string 400 may include more memory cells, which may increase the memory density of the semiconductor structure 200 without increasing the total number of layers of the stacked layers 210.

In addition, the dielectric constant of the second isolation structure 230 is smaller than that of the first dielectric layer 211. That is, the second isolation structure 230 may be made of a material with a low dielectric constant, so as to reduce the electric field coupling between two transistors T oppositely disposed on the X-Y plane in the same memory cell string 400, and reduce the interference between two adjacent gate line layers 212 in the direction perpendicular to the plane where the gate line layers 212 are located (the Z direction in fig. 1), thereby improving the device performance.

Illustratively, the dielectric constant of the second isolation structure 230 is less than or equal to 3. For example, the material of the second isolation structure 230 may include any one of carbon-doped silicon hydroxide and fluorine-doped silicon oxide.

In some embodiments, as shown in fig. 4 and 6, the second isolation structure 230 penetrates through a corresponding row of channel structures 240 along the first direction X to divide the channel structure 240 into a first sub-channel structure 244 and a second sub-channel structure 245, the first sub-channel structure 241 being in contact with the first sub-gate line, and the second sub-channel structure 245 being in contact with the second sub-gate line. In this case, the channel structures 240 corresponding to the two transistors T (see fig. 3) oppositely disposed on the X-Y plane are separated, and the risk of leakage current can be reduced.

The dimension of the second isolation structure 230 is smaller than the diameter of the channel structure 240 along a second direction Y, which is perpendicular to the first direction X and parallel to the plane (X-Y plane) of the stacked layer 210.

In other embodiments, as shown in fig. 5, along the first direction X, the second isolation structures 230 contact the outer surface of the corresponding row of channel structures 240, which may also improve the storage density of the semiconductor structure 200.

As shown in fig. 5, in the case that the second isolation structures 230 are in contact with the outer surface of a corresponding row of channel structures 240, the semiconductor structure 200 further includes a third isolation structure 250 penetrating through the stack layer 210 (see fig. 23), and the third isolation structure 250 is located between two adjacent second isolation structures 230, so as to ensure that the sub-gate line G1 between two adjacent second isolation structures 230 can be formed through a replacement process.

Referring to fig. 5 and 23, a material of the third isolation structure 250 may be the same as that of the first isolation structure 220, or may be different from that of the first isolation structure 220, and the disclosure is not limited in this respect.

It should be noted that the third isolation structure 250 and the first isolation structure 220 may be performed in the same process, for example, the first isolation structure 220 and the third isolation structure 250 are formed by a single etching and a single filling process, which may be referred to below specifically, and the disclosure is not repeated herein.

In some embodiments, referring to fig. 6, the first dielectric layer 211 is recessed near the edge of the channel structure 240 along a direction parallel to the plane of the stack 210 (i.e., the plane defined by X-Y in fig. 4) compared to the gate line layer 212 (which may also be the sub-gate line G1 in fig. 4 or fig. 5) near the edge of the channel structure 240.

On this basis, as shown in fig. 6, the semiconductor structure 200 further includes a second dielectric layer 260, the second dielectric layer 260 is located between the first dielectric layer 211 and the channel structure 240, and the dielectric constant of the second dielectric layer 260 is smaller than that of the first dielectric layer 211. Here, the material of the second dielectric layer 260 may be the same as the material of the second isolation structure 230, and of course, the material of the second dielectric layer 260 may be different from the material of the second isolation structure 230.

Based on this, the first dielectric layer 211 and the second dielectric layer 260 may be made of different materials, respectively. That is, the first dielectric layer 211 and the second dielectric layer 260 can be made of suitable materials according to respective design requirements, and the cost is low.

For example, the first dielectric layer 211 may be made of a material with a large elastic modulus to support the stacked layer 210. The first dielectric layer 211 does not need to consider whether the dielectric constant of the material is too high; in this way, the first dielectric layer 211 can be made of a wide variety of materials at a low cost. The second dielectric layer 260 may be made of a material with a low dielectric constant, so as to reduce the electric field coupling between the transistors T adjacent to each other in the third direction Z in the same memory cell string 400, thereby improving the device performance. The second dielectric layer 260 does not need to consider whether the elastic modulus of the material is too low; in this way, the second dielectric layer 260 can be made of a wider variety of materials at a lower cost.

For example, the dielectric constant of the second dielectric layer 260 is less than or equal to 3. Specifically, the material of the second dielectric layer 260 may include any one of carbon-doped silicon hydroxide and fluorine-doped silicon oxide. At this time, the second dielectric layer 260 has a smaller elastic modulus than the first dielectric layer 211.

For example, the elastic modulus of the first dielectric layer 211 is greater than the elastic modulus of the second dielectric layer 260, so as to improve the structural stability of the stacked layer 210 and reduce the risk of the stacked layer 210 falling. The elastic modulus of the first dielectric layer 211 may be 70GPa to 100 GPa. Specifically, the material of the first dielectric layer 211 may be silicon dioxide. At this time, the dielectric constant of the first dielectric layer 211 was 3.9.

In some embodiments, as shown in fig. 6, one side of the second dielectric layer 260 is in contact with the first dielectric layer 211 and the other side is in contact with the channel structure 240. That is, the second dielectric layer 260 fills the gap between the first dielectric layer 211 and the trench structure 22, so as to avoid the problem of short circuit between the gate line layers 212 of different layers during the process of manufacturing the semiconductor structure 200, particularly during the process of replacing the gate line layers 212.

In some embodiments, as shown in fig. 6, the second dielectric layer 260 is far from the boundary of the first dielectric layer 211 and is flush with the boundary of the gate line layer 212 close to the channel structure 240, so that the second dielectric layers 260 with lower dielectric constants are disposed between the edge portions of different gate line layers 212 close to the channel structure 240, the effect of electric field coupling between the transistors T in the same memory cell string 400 is reduced as much as possible, and the device performance is improved.

The distance between the second dielectric layer 260 and the boundary of the second dielectric layer 260 far from the first dielectric layer 211 is 0.5 nm-5 nm, so that the problem that the stacked layer 210 is toppled due to overlarge size of the second dielectric layer 260 can be avoided; and, it is avoided that the size of the second dielectric layer 260 is too small, which may result in that the electric field coupling between the transistors T in the same memory cell string 400 may not be reduced to a predetermined requirement. Illustratively, the second dielectric layer 260 is close to the boundary of the first dielectric layer 211 at any one of a distance of 0.5nm, 1nm, 2nm, 3nm, 4nm, and 5nm from the boundary of the second dielectric layer 260 away from the first dielectric layer 211.

In some embodiments, as shown in fig. 6, the semiconductor structure 200 may further include a dummy channel structure 270.

Wherein the dummy channel structure 270 extends through the stack layer 210, and the dummy channel structure 270 is configured to provide mechanical support to the semiconductor structure 200. It should be noted that the dummy channel structure 270 may be penetrated and divided by the second isolation structure 230, and may also avoid the second isolation structure 230, that is, the dummy channel structure 270 and the second isolation structure 230 are disposed in a staggered manner, which is not limited in this disclosure. In addition, the dummy channel structure 270 may include an insulating material, such as a combination of one or more of silicon oxide, silicon nitride, and a high-k insulating material, as well as other suitable materials. In addition, the dummy channel structure 270 may also include one or more air gaps to reduce structural stress.

In some embodiments, referring to fig. 6, the semiconductor structure 200 may further include a capping layer 280. The capping layer 280 may cover the stack layer 210 to function as a protection of the semiconductor structure 200. Wherein the material of the capping layer 280 may include an insulating material, and the insulating material may include at least one of silicon oxide, silicon nitride, and a high dielectric constant insulating material, to which the present disclosure is not limited.

It should be noted that the surface of the covering layer 280 away from the stack layer 210 needs to be processed by a chemical mechanical polishing process to planarize the surface of the covering layer 280 away from the stack layer 210 globally.

Embodiments of the present disclosure also provide a method for manufacturing the semiconductor structure 200, as shown in fig. 24, the method includes steps S100 to S200.

S100: referring to fig. 16, an intermediate semiconductor structure 200' is prepared.

In the above steps, the intermediate semiconductor structure 200' includes the stacked layer 210, and the first isolation structure 220 and the channel structure 240 penetrating through the stacked layer 210. The stack layer 210 includes a plurality of first dielectric layers 211 and a plurality of gate line layers 212 alternately stacked, and in conjunction with fig. 4, the first isolation structures 220 extend along a first direction X to divide the gate line layer 212 into a plurality of gate lines G, and the channel structure 240 is located between two adjacent first isolation structures 220.

It should be noted that, for a specific process for preparing the intermediate semiconductor structure 200', reference may be made to S110 to S160, which are not described herein again in this disclosure.

S200: referring to fig. 18, a second isolation structure 230 is formed through the stack of layers 210.

In the above steps, as shown in fig. 4 and 18, the second isolation structure 230 extends along the first direction X to separate the gate line G into at least two sub-gate lines G1. The dielectric constant of the second isolation structure 230 is smaller than that of the first dielectric layer 211. At least a portion of the channel structure 240 contacts one of the second isolation structures 230 and contacts two of the sub-gate lines G1 in a planar direction in which the gate line layer 212 is located.

In some embodiments, referring to FIG. 25, S200 includes S210-S220.

S210: referring to fig. 17, the stack layer 210 is etched to form a second gap GLS 2.

In the above steps, referring to fig. 4 and 17, the second slit GLS2 extends in the first direction X to divide the gate line G into the sub-gate lines G1 and the channel structure 240 into the first and second

sub-channel structures

244 and 245.

In the above step, the second slit GLS2 may be formed through the stack layer 210 by a dry/wet etching process. Illustratively, a photoresist layer is formed on the upper surface of the stack layer 210, and an anisotropic etching (any one of dry etching such as ion milling, plasma etching, reactive ion etching, and laser ablation) process is used to form the second gap GLS2 using the photoresist layer as a mask.

S220: referring to fig. 17 and 18, the second gap GLS2 is filled with a target material to form a second isolation structure 230.

In the above step, the dielectric constant of the target material is smaller than the dielectric constant of the material of the first dielectric layer 211. Specifically, the target material may be deposited by any of thin film deposition processes of CVD, PVD, and ALD. The target material is a material of the second isolation structure 230, which may be referred to above specifically and is not described herein again.

Note that, in the case where a photoresist layer is formed on the upper surface of the stack layer 210, the photoresist layer needs to be removed after the second isolation structure 230 is formed.

In some embodiments, as shown in FIG. 26, S100 includes S110-S160.

S110: as shown in FIG. 7, an initial stack 210' is formed.

In the above step, the initial stack layer 210 'includes a plurality of first dielectric layers 211 and a plurality of sacrificial layers 212' alternately disposed. The initial stack layer 210' may be formed on the substrate 300 by any one of Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), and Atomic Layer Deposition (ALD).

It should be noted that, the material of the first dielectric layer 211 may refer to the above, and is not described herein again. The material of the sacrificial layer 212' includes at least one of polysilicon, silicon nitride, and poly-germanium, to which the present disclosure is not limited. Here, the material of the first dielectric layer 211 is different from that of the sacrificial layer 212 'such that the first dielectric layer 211 and the sacrificial layer 212' have different etching selectivity ratios with respect to the same etchant. Illustratively, the material of the first dielectric layer 211 is silicon dioxide, and the material of the sacrificial layer 212' is silicon nitride.

Wherein the substrate 300 may be used to support the initial stack 210' thereon, which may be removed in a subsequent process, as described in detail below. The material of the substrate 300 includes at least one of single crystal silicon, polycrystalline silicon, single crystal germanium, a group III-V compound semiconductor material, a group II-VI compound semiconductor material, or other semiconductor materials known in the art.

In some embodiments, as shown in fig. 7, the substrate 300 may be a composite substrate. Illustratively, the substrate 300 may include a base 310, and a sacrificial silicon oxide layer 320 and a sacrificial polysilicon layer 330 are sequentially formed on the base 310. Wherein the material of the substrate 310 may include at least one of single crystal silicon, polycrystalline silicon, single crystal germanium, a III-V compound semiconductor material, a IIVI compound semiconductor material, or other semiconductor materials known in the art; the material of the sacrificial silicon oxide layer 320 may include silicon oxide; the material of the sacrificial polysilicon layer 330 may include polysilicon.

S120: as shown in fig. 8, a channel hole CH is formed through the initial stack of layers 210'.

In the above step, the channel hole CH may be formed through the initial stack layer 210' by a dry/wet etching process. Illustratively, the channel hole CH is formed using an anisotropic etching (any of dry etching such as ion mill etching, plasma etching, reactive ion etching, laser ablation, etc.) process. The channel hole CH extends into the substrate 300, for example, the substrate 300 is a composite substrate, and the channel hole CH extends into the sacrificial polysilicon layer 330.

S130: as shown in fig. 8 and 12, a channel structure 240 is formed within the channel hole CH.

In the above step, a blocking layer 2411, a charge trapping layer 2412, a tunneling layer 2413 and a semiconductor channel layer 242 may be sequentially deposited along the inner wall of the channel hole CH by using any one of CVD, PVD and ALD thin film deposition processes to form the channel structure 240. The blocking layer 2411, the charge trapping layer 2412 and the tunneling layer 2413 may be referred to as a storage function layer 241.

It should be noted that, the materials of the blocking layer 2211, the charge trapping layer 2212, the tunneling layer 2213 and the semiconductor channel layer 222 may be referred to above, and are not described herein again.

In some embodiments, after the memory function layer 241 and the semiconductor channel layer 242 are sequentially formed in the channel hole CH, a channel filling layer 243 may be further formed in the channel hole CH. For example, a channel structure 240 having the memory function layer 241, the semiconductor channel layer 242, and the channel filling layer 243 may be formed by filling an insulating material, such as silicon oxide, in the channel hole CH in which the memory function layer 241 and the semiconductor channel layer 242 are formed, using any one of a thin film deposition process of CVD, PVD, and ALD.

S140: as shown in fig. 13, a first slit GLS1 is formed through the initial stack of layers 210'.

In the above steps, the first slit GLS1 may be formed through the initial stack layer 210' by a dry/wet etching process. Illustratively, the first slit GLS1 is formed using an anisotropic etching (any one of dry etching such as ion mill etching, plasma etching, reactive ion etching, laser ablation, etc.) process. The first slit GLS1 extends into the substrate 300, for example, the substrate 300 is a composite substrate, and the first slit GLS1 extends into the sacrificial polysilicon layer 330.

The formation of the channel hole CH penetrating the initial stacked layer 210 'in S130 and the formation of the first slit GLS1 penetrating the initial stacked layer 210' in S140 may be performed in different steps or in the same step, and the disclosure is not limited thereto.

S150: as shown in fig. 13, 14 and 15, the sacrificial layer 212' is replaced with the gate line layer 212 via the first slit GLS 1.

In the above steps, referring to fig. 13 and 14, the sacrificial layer 212' may be removed by isotropic etching using the first slit GLS1 as an etchant channel to form a sacrificial gap; referring to fig. 14 and 15, the gate line layer 212 is formed in the sacrificial gap by using any one of CVD, PVD and ALD thin film deposition processes using the first gap GLS1 as a deposition path. It should be noted that, the structure and the material of the gate line layer 212 may be referred to above, and are not described herein again.

Wherein, the isotropic etching can adopt selective wet etching or gas phase etching. Using an etching solution as an etchant in wet etching; etching gas is used as an etchant in the vapor phase etching. Here, in the case that the material of the first dielectric layer 211 is silicon oxide and the material of the sacrificial layer 212' is silicon nitride, a phosphoric acid solution may be used as an etchant in the wet etching; at least one of C4F8, C4F6, and CH2F2 may be employed as an etching gas in the vapor phase etching.

Based on the above, as shown in fig. 15, a stack layer 210 may be formed, the stack layer 210 including first dielectric layers 211 and gate line layers 212 alternately stacked.

S160: referring to fig. 15 and 16, the first isolation structure 220 is formed within the first slit GLS 1.

In the above steps, the first isolation structure 220 may be formed in the first gap GLS1 by using any one of CVD, PVD and ALD thin film deposition processes. The structure and material of the first isolation structure 220 can be referred to above, and are not described herein again.

In some embodiments, referring to fig. 27, between S120 and S130, the above preparation method further includes S121 to S122.

S121: as shown in fig. 9, an edge portion of the first dielectric layer 211 near the channel hole CH is removed through the channel hole CH.

In the above step, the end portion of the first dielectric layer 211 exposed at the channel hole CH is etched using the channel hole CH as an etchant channel, and the etchant is used to etch the first dielectric layer 211. The first dielectric layer 211 is recessed from the boundary of the channel hole CH compared to the sacrificial layer 212' to form a recess.

The etching may be wet etching or vapor etching. Using an etching solution as an etchant in wet etching; etching gas is used as an etchant in the vapor phase etching.

S122: as shown in fig. 9 and 11, a second dielectric layer 260 is formed within the recess.

In the above step, along the direction parallel to the plane of the initial stack layer 210', the second dielectric layer 260 is located between the first dielectric layer 211 and the channel structure 240, and the dielectric constant of the second dielectric layer 260 is smaller than that of the first dielectric layer 211. The second dielectric layer 260 may be formed in the groove by using the channel hole CH as a deposition channel and using any one of CVD, PVD, and ALD thin film deposition processes. Reference may be made to S1221 to S1222, and this disclosure is not described herein.

It should be noted that, the material of the second dielectric layer 260 may be referred to above, and is not described herein again.

In some embodiments, as shown in FIG. 28, S122 includes S1221-S1222.

S1221: as shown in FIG. 10, a target material is deposited to form a second dielectric film 260'.

In the above step, the dielectric constant of the target material is smaller than the dielectric constant of the material of the first dielectric layer 211. Specifically, the target material may be deposited by any of thin film deposition processes of CVD, PVD, and ALD. Wherein, when the target material is deposited, the target material is also formed on the upper side of the initial stack layer 210' and the inner wall of the channel hole CH.

It should be noted that the target material is the material of the second dielectric layer 260, which may be referred to above specifically, and this disclosure is not repeated herein.

S1222: as shown in fig. 10 and 11, a portion of the second dielectric film 260 'covering the initial stack layer 210' and a portion covering the inner wall of the channel hole CH are removed to form a second dielectric layer 260.

In the above steps, the initial stack layer 210 'covered with the second dielectric film 260' may be etched using an etchant, which is used to etch the target material.

In the process of etching the portion of the second dielectric film 260 ' covering the initial stack layer 210 ' and the portion of the second dielectric film 260 ' covering the inner wall of the channel hole CH, the etching time can be controlled to remove the portion of the second dielectric film 260 ' covering the initial stack layer 210 ' and the portion of the second dielectric film 260 ' covering the inner wall of the channel hole CH, and then the etching is stopped, so that the second dielectric layer 260 is away from the boundary of the first dielectric layer 211 and is flush with the boundary of the sacrificial layer 212 ' near the channel hole CH.

In some embodiments, as shown in fig. 29, between S110 and S120, the above preparation method further includes S111.

S111: referring to fig. 7, a capping layer 280 is formed.

In the above steps, the capping layer 280 may be formed on the initial stack layer 210' using any one of CVD, PVD and ALD thin film deposition processes. That is, the cap layer 280 is disposed on the initial stack layer 210'. The material of the covering layer 280 can be referred to above, and the disclosure is not repeated herein.

In this case, in the process of forming the channel hole CH in S120, the channel hole CH also penetrates the capping layer. Similarly, in the process of forming the first gap GLS1 in S140, the first gap GLS1 also penetrates the cover layer 280. At this time, in the case where the material of the capping layer 280 is the same as that of the first dielectric layer 211, in the process of removing the edge portion of the first dielectric layer 211 near the channel hole CH in S121, a portion of the capping layer 280 is also removed, for example, the edge portion of the capping layer 280 near the channel hole CH and a portion of the capping layer 280 far from the initial stacked layer 210' are removed.

On this basis, after S122, as shown in fig. 30, the above preparation method further includes S123.

S123: referring to FIG. 11, a planarization process is performed on the side of the cap layer 280 away from the initial stack 210'.

In the above step, the surface of the covering layer 280 away from the stack layer 210 may be processed by a chemical mechanical polishing process to planarize the surface of the covering layer 280 away from the stack layer 210 globally.

In some embodiments, after S123, the above preparation method further includes S170.

S170: the substrate 300 is removed.

In the above steps, the substrate 300 may be removed by Chemical Mechanical Planarization (CMP), dry/wet etching process.

Illustratively, the substrate 300 is a composite substrate, and the base 310, the sacrificial silicon oxide layer 320, and the sacrificial polysilicon layer 330 may be sequentially removed by a wet etching process to expose a portion of the channel structure 220 extending into the sacrificial polysilicon layer 330.

Embodiments of the present disclosure also provide a method for manufacturing the semiconductor structure 200, as shown in fig. 31, the method includes steps S100 to S300.

S100: referring to FIG. 7, an initial stack 210' is formed.

In the above steps, the process and structure of the initial stack layer 210' can be referred to above, and the disclosure is not repeated herein.

S200: referring to fig. 20, a second isolation structure 230 is formed through the initial stack of layers 210'.

In the above steps, as shown in fig. 5 and 20, the second isolation structures 230 extend along the first direction X to separate the sacrificial layer 212' into a plurality of sub-sacrificial layers. The dielectric constant of the second isolation structure 230 is smaller than that of the first dielectric layer 211.

S300: referring to fig. 21, a channel structure 240 is formed.

In the above steps, referring to fig. 32, S300 includes S310 to S320.

S310: referring to fig. 8, a channel hole CH is formed through the initial stack of layers 210'.

In the above step, the channel hole CH may be formed through the initial stack layer 210' by a dry/wet etching process. Illustratively, the channel hole CH is formed using an anisotropic etching (any of dry etching such as ion mill etching, plasma etching, reactive ion etching, laser ablation, etc.) process.

S320: referring to fig. 8 and 12, a channel structure 240 is formed within the channel hole CH.

In the above step, at least a portion of the channel structure 240 contacts one of the second isolation structures 230 and contacts two sub-sacrificial layers in the planar direction of the sacrificial layer 212'. The process and structure of the channel structure 240 can be referred to above, and the disclosure is not repeated herein.

In some embodiments, referring to FIG. 33, S200 includes S210-S220.

S210: referring to fig. 19, a second slit GLS2 is formed through the initial stack of layers 210'.

In the above steps, referring to fig. 5 and 19, the second slits GLS2 extend in the first direction X to separate the sacrificial layer 212' into a plurality of sub-sacrificial layers. Wherein the second slit GLS2 may be formed through the stack layer 210 by a dry/wet etching process. Illustratively, the second slit GLS2 is formed using an anisotropic etching (any one of dry etching such as ion mill etching, plasma etching, reactive ion etching, laser ablation, etc.) process.

S220: referring to fig. 19 and 20, the target material is filled in the second gap GLS 2.

It should be noted that the target material filled in the second gap GLS2 may be the same as the target material for forming the second dielectric film 260' in S3121.

In some embodiments, as shown in fig. 34, after S300, the above preparation method further includes S400 to S600.

S400: referring to fig. 21, a first slit GLS1 and a third slit GLS3 are formed through the initial stack layer 210'.

In the above steps, referring to fig. 5 and 21, the first slit GLS1 and the third slit GLS3 extend along the first direction X, the first slit GLS1 is located at both sides of the array-arranged channel structures 240, and the third slit GLS3 is located between two adjacent rows of channel structures 240.

In the above steps, the first and third slits GLS1 and GLS3 may be formed through the initial stack layer 210' by a dry/wet etching process. Illustratively, the first and third slits GLS1 and GLS3 are formed using an anisotropic etching (any one of dry etching such as ion mill etching, plasma etching, reactive ion etching, laser ablation, etc.) process.

The first slit GLS1 and the third slit GLS3 may be formed in the same process, that is, the first slit GLS1 and the third slit GLS3 may be formed by a single etching process; the first gap GLS1 and the third gap GLS3 may also be performed in different processes, for example, the first gap GLS1 is formed by one etching process, and the third gap GLS3 is formed by another etching process.

S500: referring to fig. 21, 22 and 23, the sacrificial layer 212' is replaced with the gate line layer 212 via the first and third slits GLS1 and GLS 3.

In the above steps, referring to fig. 21 and 22, the sacrificial layer 212' may be removed by isotropic etching using the first and third slits GLS1 and GLS3 as etchant channels to form a sacrificial gap; referring to fig. 22 and 23, the gate line layer 212 is formed in the sacrificial gap by using any one of CVD, PVD and ALD thin film deposition processes using the first gap GLS1 and the third gap GLS3 as deposition channels. It should be noted that, the structure and the material of the gate line layer 212 may be referred to above, and are not described herein again.

Based on the above, as shown in fig. 23, a stack layer 210 may be formed, the stack layer 210 including first dielectric layers 211 and gate line layers 212 alternately stacked.

S600: referring to fig. 22 and 23, the first and

third isolation structures

220 and 250 are formed in the first and third slits GLS1 and GLS3, respectively.

In the above steps, the first and

third isolation structures

220 and 250 may be formed in the first and third gaps GLS1 and GLS3, respectively, using any one of CVD, PVD, and ALD thin film deposition processes. The structure and material of the first isolation structure 220 and the third isolation structure 250 may be referred to above, and are not described herein again.

In the case that the materials of the first isolation structure 220 and the third isolation structure 250 are the same, the first isolation structure 220 and the third isolation structure 250 may be formed in the same process, that is, the first isolation structure 220 and the third isolation structure 250 are formed through a single deposition process; in the case that the materials of the first isolation structure 220 and the third isolation structure 250 are different, the first isolation structure 220 and the third isolation structure 250 are performed in different processes, for example, the first isolation structure 220 is formed by a deposition process, and the third isolation structure 250 is formed by another deposition process, and the sequence of performing the above two steps is not limited in this disclosure.

In some embodiments, as shown in fig. 35, between S310 and S320, the above preparation method further includes S311 to S312.

S311: referring to fig. 9, an edge portion of the first dielectric layer 211 near the channel hole CH is removed through the channel hole CH.

S312: referring to fig. 9 and 11, a second dielectric layer 260 is formed within the recess.

In the above step, along a direction parallel to the plane of the initial stack layer 210' (i.e. the plane defined by X-Y in the figure), the second dielectric layer 260 is located between the first dielectric layer 211 and the channel structure 240, and the dielectric constant of the second dielectric layer 260 is smaller than that of the first dielectric layer 211. The second dielectric layer 260 may be formed in the groove by using the channel hole CH as a deposition channel and using any one of CVD, PVD, and ALD thin film deposition processes. Reference may be made to S3121 to S3122, which are not described herein in detail.

In some embodiments, as shown in fig. 36, S312 includes S3121 to S3122.

S3121: as shown in FIG. 10, a target material is deposited to form a second dielectric film 260'.

S3122: as shown in fig. 10 and 11, a portion of the second dielectric film 260 'covering the initial stack layer 210' and a portion covering the inner wall of the channel hole CH are removed to form a second dielectric layer 260.

In some embodiments, as shown in fig. 37, between S100 and S310, the above preparation method further includes S110.

S110: referring to fig. 7, a capping layer 280 is formed.

Wherein, the sequence of the S110 and the S200 is not limited. Exemplarily, S200 is performed after S110, and at this time, the second isolation structure 230 also penetrates the capping layer 280.

In this case, in the process of forming the channel hole CH in S310, the channel hole CH also penetrates the capping layer. Similarly, in the process of forming the first and third slits GLS1 and GLS3 in S500, the first and third slits GLS1 and GLS3 also penetrate the cover layer 280. At this time, in the case where the material of the capping layer 280 is the same as that of the first dielectric layer 211, in the process of removing the edge portion of the first dielectric layer 211 near the channel hole CH in S311, a portion of the capping layer 280 is also removed, for example, the edge portion of the capping layer 280 near the channel hole CH and a portion of the capping layer 280 far from the initial stacked layer 210' are removed.

On this basis, after S312, as shown in fig. 37, the above-described production method further includes S313.

S313: referring to FIG. 11, a planarization process is performed on the side of the cap layer 280 away from the initial stack 210'.

FIG. 38 is a block diagram of a storage system according to some embodiments. FIG. 39 is a block diagram of memory systems according to further embodiments.

Referring to fig. 38 and 39, some embodiments of the present disclosure also provide a storage system 1000. The memory system 1000 includes a controller 20, and a memory 10 as in some embodiments above, the controller 20 coupled to the memory 10 to control the memory 10 to store data.

The Storage system 1000 may be integrated into various types of Storage devices, for example, included in the same package (e.g., a Universal Flash Storage (UFS) package or an Embedded multimedia Card (eMMC) package). That is, the storage system 1000 may be applied to and packaged into different types of electronic products, such as a mobile phone (e.g., a cell phone), a desktop computer, a tablet computer, a laptop computer, a server, an in-vehicle device, a game console, a printer, a positioning device, a wearable device, a smart sensor, a mobile power supply, a Virtual Reality (VR) device, an Augmented Reality (AR) device, or any other suitable electronic device having storage therein.

In some embodiments, referring to fig. 38, the memory system 1000 includes a controller 20 and a memory 10, and the memory system 1000 may be integrated into a memory card.

The Memory Card includes any one of a PC Card (PCMCIA), a Compact Flash (CF) Card, a Smart Media (SM) Card, a Memory stick, a Multimedia Card (MMC), a Secure Digital Memory Card (SD), and a UFS.

In other embodiments, referring to fig. 39, the storage system 1000 includes a controller 20 and a plurality of memories 10, and the storage system 1000 is integrated into a Solid State Drive (SSD).

In storage system 1000, in some embodiments, controller 20 is configured for operation in a low duty cycle environment, such as an SD card, CF card, Universal Serial Bus (USB) flash drive, or other media for use in electronic devices such as personal computers, digital cameras, mobile phones, and the like.

In other embodiments, the controller 20 is configured for operation in a high duty cycle environment SSD or eMMC for data storage and enterprise storage arrays of mobile devices such as smart phones, tablets, laptops, and the like.

In some embodiments, the controller 20 may be configured to manage data stored in the memory 10 and communicate with an external device (e.g., a host). In some embodiments, controller 20 may also be configured to control operations of memory 10, such as read, erase, and program operations. In some embodiments, the controller 20 may also be configured to manage various functions with respect to data stored or to be stored in the memory 10, including at least one of bad block management, garbage collection, logical to physical address translation, wear leveling. In some embodiments, controller 20 is also configured to process error correction codes for data read from memory 10 or written to memory 10.

Of course, the controller 20 may also perform any other suitable functions, such as formatting the memory 10; for example, the controller 20 may communicate with an external device (e.g., a host) via at least one of various interface protocols.

It should be noted that the interface protocol includes at least one of a USB protocol, an MMC protocol, a Peripheral Component Interconnect (PCI) protocol, a PCI express (PCI-E) protocol, an Advanced Technology Attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a Small Computer System Interface (SCSI) protocol, an Enhanced Small Disk Interface (ESDI) protocol, an Integrated Drive Electronics (IDE) protocol, and a Firewire protocol.

Some embodiments of the present disclosure also provide an electronic device. The electronic device may be any one of a mobile phone, a desktop computer, a tablet computer, a notebook computer, a server, an in-vehicle device, a wearable device (e.g., a smart watch, a smart bracelet, smart glasses, etc.), a mobile power source, a game console, a digital multimedia player, and the like.

The electronic device may include the storage system 1000 described above, and may further include at least one of a Central Processing Unit (CPU), a cache (cache), and the like.

The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.

Claims

1. A semiconductor structure, comprising:

the stacked layer comprises a plurality of first dielectric layers and a plurality of grid line layers which are alternately stacked;

the first isolation structure penetrates through the stacked layers and extends along a first direction so as to divide the grid line layer into a plurality of grid lines;

a second isolation structure penetrating through the stack layer, the second isolation structure extending along the first direction to divide the gate line into at least two sub-gate lines; the dielectric constant of the second isolation structure is smaller than that of the first dielectric layer;

a channel structure penetrating through the stacked layers, wherein the channel structure is arranged between two adjacent first isolation structures; at least part of the channel structure is located on the straight line where the second isolation structure is located, and the sub-gate lines on the two sides of the second isolation structure are respectively in contact with the channel structure located on the straight line where the second isolation structure is located.

2. The semiconductor structure of claim 1, wherein the second isolation structure penetrates through a corresponding row of channel structures along the first direction to divide the channel structures into a first sub-channel structure and a second sub-channel structure, the first sub-channel structure being in line contact with a first sub-gate, and the second sub-channel structure being in line contact with a second sub-gate.

3. The semiconductor structure of claim 1, wherein along the first direction, the second isolation structure is in contact with an outer surface of a corresponding row of channel structures.

4. The semiconductor structure of claim 3, further comprising:

and a third isolation structure penetrating through the stacked layers, wherein the third isolation structure is positioned between two adjacent second isolation structures.

5. The semiconductor structure of claim 1, wherein the dielectric constant of the second isolation structure is less than or equal to 3.

6. The semiconductor structure of claim 5, wherein the material of the second isolation structure comprises any one of carbon-doped silicon oxide, carbon-doped silicon hydroxide, and fluorine-doped silicon oxide.

7. The semiconductor structure of claim 1, wherein a dimension of the second isolation structure along a second direction is smaller than a diameter of the channel structure, the second direction being perpendicular to the first direction and parallel to a plane in which the stacked layers are located.

8. The semiconductor structure according to any one of claims 1 to 7, wherein the first dielectric layer is recessed closer to the boundary of the channel structure than the sub-gate line;

the semiconductor structure further includes:

a plurality of second dielectric layers, the second dielectric layers being located between the first dielectric layers and the channel structure in a direction parallel to a plane in which the stack of layers is located; and the second dielectric layer is positioned between two adjacent gate layers along the direction vertical to the plane of the stacked layers, and the dielectric constant of the second dielectric layer is smaller than that of the first dielectric layer.

9. The semiconductor structure of claim 8, wherein the second dielectric layer is in contact with the first dielectric layer on one side and the channel structure on the other side.

10. A method for fabricating a semiconductor structure, comprising:

preparing an intermediate semiconductor structure; the middle semiconductor structure comprises a stacking layer, first isolation structures and a channel structure, wherein the first isolation structures and the channel structure penetrate through the stacking layer, the stacking layer comprises a plurality of first dielectric layers and a plurality of grid line layers which are alternately stacked, the first isolation structures extend along a first direction to divide the grid line layers into a plurality of grid lines, and the channel structure is positioned between two adjacent first isolation structures;

forming a second isolation structure penetrating through the stack layer, wherein the second isolation structure extends along the first direction to divide the grid line into at least two sub-grid lines; the dielectric constant of the second isolation structure is smaller than that of the first dielectric layer; at least part of the channel structures are in contact with one second isolation structure and are in contact with the two sub-grid lines in the plane direction of the grid line layer.

11. The method of claim 10, wherein the forming a second isolation structure through the stacked layers comprises:

etching the stacked layer to form a second gap; the second slit extends in the first direction to divide the gate line into sub-gate lines and the channel structure into a first sub-channel structure and a second sub-channel structure;

filling a target material in the second gap to form a second isolation structure; the dielectric constant of the target material is less than the dielectric constant of the material of the first dielectric layer.

12. The method of claim 10, wherein the fabricating an intermediate semiconductor structure comprises:

forming an initial stack layer; the initial stacking layer comprises a plurality of sacrificial layers and a plurality of first dielectric layers which are alternately arranged;

forming a trench hole through the initial stack of layers;

forming a channel structure in the channel hole;

forming a first aperture through the initial stack of layers;

replacing the sacrificial layer with a gate line layer via the first slit;

and forming a first isolation structure in the first gap.

13. The method of claim 12, further comprising, between forming the channel hole and forming the channel structure:

removing the edge part of the first dielectric layer close to the channel hole through the channel hole, so that the boundary of the first dielectric layer close to the channel hole is retracted compared with the boundary of the sacrificial layer close to the channel hole, and a groove is formed;

forming a second dielectric layer in the groove; the dielectric constant of the second dielectric layer is smaller than that of the first dielectric layer.

14. The method of claim 13, wherein the forming a second dielectric layer in the recess comprises:

depositing a target material to form a second dielectric film; the dielectric constant of the target material is smaller than that of the material of the first dielectric layer;

and removing the part of the second dielectric film covering the initial stacking layer and the part of the second dielectric film covering the inner wall of the channel hole to form the second dielectric layer.

15. A method for fabricating a semiconductor structure, comprising:

forming a second isolation structure through the initial stack of layers; the second isolation structure extends along a first direction to divide the sacrificial layer into a plurality of sub-sacrificial layers; the dielectric constant of the second isolation structure is smaller than that of the first dielectric layer;

forming a channel hole penetrating through the initial stacking layer, and forming a channel structure in the channel hole; at least part of the channel structure is in contact with one second isolation structure and is in contact with the two sub-sacrificial layers in the plane direction of the sacrificial layer.

16. The method of claim 15, wherein the forming a second isolation structure through the initial stack of layers comprises:

forming a second aperture through the initial stack of layers; the second slit extends along the first direction to divide the sacrificial layer into a plurality of sub-sacrificial layers;

filling a target material in the second gap; the dielectric constant of the target material is less than the dielectric constant of the material of the first dielectric layer.

17. The method of manufacturing according to claim 15, further comprising, after forming the channel structure: forming a first gap and a third gap through the initial stack of layers; the first gaps and the third gaps extend along a first direction, the first gaps are located on two sides of the channel structures arranged in the array, and the third gaps are located between two adjacent rows of the channel structures;

replacing the sacrificial layer with a gate line layer via the first slit and the third slit;

and respectively forming a first isolation structure and a third isolation structure in the first gap and the third gap.

18. The method of claim 15, further comprising, between forming the channel hole and forming the channel structure:

19. The method of claim 18, wherein forming a second dielectric layer within the recess comprises:

20. A memory, comprising:

a semiconductor structure as claimed in any one of claims 1 to 9;

a peripheral device electrically connected to the semiconductor structure.

21. A storage system, comprising:

a memory as claimed in claim 20;

a controller coupled to the memory to control the memory to store data.

22. An electronic device comprising the storage system of claim 21.