CN114284287A - Semiconductor structure, manufacturing method thereof, memory, storage system and electronic device - Google Patents

Abstract

The disclosure provides a semiconductor structure and a preparation method thereof, a memory, a storage system and electronic equipment, and relates to the technical field of semiconductor chips, so that mutual interference among storage units is reduced, and device performance is improved. The semiconductor structure includes a stack layer, a channel structure, and a plurality of second dielectric layers. The stacked layer includes a plurality of first dielectric layers and a plurality of gate layers that are alternately stacked. The channel structure penetrates through the stacked layers; the first dielectric layer is close to the boundary of the channel structure and is retracted compared with the gate layer close to the boundary of the channel structure. Along the direction parallel to the plane of the stacked layers, the second dielectric layer is positioned between the first dielectric layer and the channel structure; and the second dielectric layer is positioned between two adjacent gate layers along the direction vertical to the plane of the stacked layers, and the dielectric constant of the second dielectric layer is smaller than that of the first dielectric layer. The semiconductor structure is applied to a memory to realize reading and writing operations of data.

Description

Semiconductor structure, manufacturing method thereof, memory, storage system and electronic device

Technical Field

The present disclosure relates to the field of semiconductor chip technologies, and in particular, to a semiconductor structure, a manufacturing method thereof, a memory, a storage system, and an electronic device.

Background

As the feature size of memory cells approaches the lower process limit, planar processes and manufacturing techniques become challenging and costly, which causes the storage density of 2D or planar NAND flash memories to approach the upper limit.

To overcome the limitations imposed by 2D or planar NAND flash memories, memories having a three-dimensional structure (3D NAND) have been developed to increase the storage density by arranging memory cells three-dimensionally over a substrate.

However, in order to increase the storage density, the size of the memory is smaller and smaller, and mutual interference between memory cells is difficult to ignore when programming operation is performed, which affects the performance of the device.

Disclosure of Invention

Embodiments of the present disclosure provide a semiconductor structure, a manufacturing method thereof, a memory, a storage system, and an electronic device, so as to reduce mutual interference between storage units and improve device performance.

In order to achieve the purpose, the embodiment of the disclosure adopts the following technical scheme:

in one aspect, a semiconductor structure is provided. The semiconductor structure comprises a stack layer, a channel structure and a plurality of second dielectric layers. The stacked layer includes a plurality of first dielectric layers and a plurality of gate layers that are alternately stacked. The channel structure penetrates through the stacked layers; the first dielectric layer is close to the boundary of the channel structure and is retracted compared with the gate layer close to the boundary of the channel structure. The second dielectric layer is positioned between the first dielectric layer and the channel structure along the direction parallel to the plane of the stacked layers; the second dielectric layer is positioned between two adjacent gate layers along the direction perpendicular to the plane of the stacked layers; the dielectric constant of the second dielectric layer is smaller than that of the first dielectric layer.

In the semiconductor structure provided by the above embodiment of the present disclosure, the first dielectric layer and the second dielectric layer may be made of different materials, respectively. That is to say, the first dielectric layer and the second dielectric layer can be made of suitable materials according to respective design requirements, and the cost is low. Illustratively, the first dielectric layer may be made of a material with a large elastic modulus to support the stacked layers. The first dielectric layer does not need to consider whether the dielectric constant of the material is too high or not; therefore, the first dielectric layer has more types of selectable materials and lower cost. The second dielectric layer can be made of a material with a low dielectric constant, so that the effect of reducing electric field coupling between transistors in the same memory cell string is achieved, and the performance of the device is improved. The second dielectric layer does not need to consider whether the elastic modulus of the material is too low or not; in this way, the second dielectric layer has more kinds of selectable materials and lower cost.

In some embodiments, one side of the second dielectric layer is in contact with the first dielectric layer and the other side is in contact with the channel structure.

In some embodiments, the dielectric constant of the second dielectric layer is less than or equal to 3.

In some embodiments, the material of the second dielectric layer includes any one of carbon-doped silicon oxide, carbon-doped silicon hydroxide, and fluorine-doped silicon oxide.

In some embodiments, the first dielectric layer has a modulus of elasticity greater than the modulus of elasticity of the second dielectric layer.

In some embodiments, the first dielectric layer has a modulus of elasticity in the range of 70GPa to 100 GPa.

In some embodiments, the distance between the second dielectric layer close to the boundary of the first dielectric layer and the boundary of the second dielectric layer far from the first dielectric layer is 0.5nm to 5 nm.

In another aspect, a method for fabricating a semiconductor structure is provided, including: and forming an initial stacking layer, wherein the initial stacking layer comprises a plurality of sacrificial layers and a plurality of first dielectric layers which are alternately arranged. Forming a trench hole through the initial stack of layers. And removing the edge part of the first dielectric layer close to the channel hole through the channel hole, so that the boundary of the first dielectric layer close to the channel hole is retracted compared with the boundary of the sacrificial layer close to the channel hole, and a groove is formed. Forming a second dielectric layer in the groove; the dielectric constant of the second dielectric layer is smaller than that of the first dielectric layer. Forming a channel structure in the channel hole; and the second dielectric layer is positioned between the first dielectric layer and the channel structure along the direction parallel to the plane of the initial stacking layer.

In some embodiments, the forming a second dielectric layer in the groove includes: depositing a target material to form a second dielectric film; the dielectric constant of the target material is less than the dielectric constant of the material of the first dielectric layer. And removing the part of the second dielectric film covering the initial stacking layer and the part of the second dielectric film covering the inner wall of the channel hole to form the second dielectric layer.

In some embodiments, after forming the channel structure, the method of making further comprises: forming a gate line slit through the initial stack layer. And removing the sacrificial layer through the gate line gap to form a sacrificial gap. And forming a gate layer in the sacrificial gap.

In some embodiments, between forming the initial stack layer and forming the channel hole, the method of making further comprises: forming a covering layer; the capping layer is disposed on the initial stack of layers.

In some embodiments, the channel hole also penetrates through the capping layer during the forming of the channel hole. And in the process of removing the edge part of the first dielectric layer close to the channel hole, removing part of the covering layer. After forming the second dielectric layer, the preparation method further comprises: and carrying out planarization treatment on one side of the covering layer far away from the initial stacking layer.

In yet another aspect, a memory is provided. The memory includes a semiconductor structure as described in some embodiments above, and a peripheral device electrically connected to the semiconductor structure.

In yet another aspect, a storage system is provided, including: a memory as described above, and a controller coupled to the memory to control the memory to store data.

In yet another aspect, an electronic device is provided, which includes the storage system as described above.

It can be understood that, in the manufacturing method of the semiconductor structure, the memory, the storage system and the electronic device provided in the embodiments of the disclosure, reference may be made to the above beneficial effects of the semiconductor structure, and details are not described herein again.

Drawings

In order to more clearly illustrate the technical solutions in the present disclosure, the drawings needed to be used in some embodiments of the present disclosure will be briefly described below, and it is apparent that the drawings in the following description are only drawings of some embodiments of the present disclosure, and other drawings can be obtained by those skilled in the art according to the drawings. Furthermore, the drawings in the following description may be regarded as schematic diagrams, and do not limit the actual size of products, the actual flow of methods, the actual timing of signals, and the like, involved in the embodiments of the present disclosure.

FIG. 1 is a schematic perspective diagram of a memory according to some embodiments;

FIG. 2 is a cross-sectional view of a reservoir according to some embodiments;

FIG. 3 is a cross-sectional view of a memory cell string of the memory of FIG. 1 along section line AA';

FIG. 4 is an equivalent circuit diagram of a memory cell string;

FIGS. 5-14 are diagrams of fabrication steps of methods of fabricating semiconductor structures according to some embodiments;

FIG. 15 is a block diagram of a semiconductor structure according to some embodiments;

FIGS. 16-19 are flow diagrams of methods of fabricating semiconductor structures according to some embodiments;

FIG. 20 is a block diagram of a storage system according to some embodiments;

FIG. 21 is a block diagram of memory systems according to further embodiments.

Detailed Description

Technical solutions in some embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings, and it is obvious that the described embodiments are only a part of the embodiments of the present disclosure, and not all of the embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments provided by the present disclosure belong to the protection scope of the present disclosure.

In the description of the present disclosure, it is to be understood that the terms "center", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like indicate orientations or positional relationships based on those shown in the drawings, and are only for convenience in describing and simplifying the disclosure, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed in a specific orientation, and be operated, and thus, should not be construed as limiting the disclosure.

Throughout the specification and claims, the term "comprising" is to be interpreted in an open, inclusive sense, i.e., as "including, but not limited to," unless the context requires otherwise. In the description herein, the terms "one embodiment," "some embodiments," "an example embodiment," "exemplary" or "some examples" or the like are intended to mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the disclosure. The schematic representations of the above terms are not necessarily referring to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be included in any suitable manner in any one or more embodiments or examples.

In the following, the terms "first", "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the embodiments of the present disclosure, "a plurality" means two or more unless otherwise specified.

In describing some embodiments, expressions of "coupled" and "connected," along with their derivatives, may be used. For example, the term "connected" may be used in describing some embodiments to indicate that two or more elements are in direct physical or electrical contact with each other. As another example, some embodiments may be described using the term "coupled" to indicate that two or more elements are in direct physical or electrical contact. The term "coupled," however, may also mean that two or more elements are not in direct contact with each other, but yet still co-operate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents herein.

"at least one of A, B and C" has the same meaning as "A, B or at least one of C," each including the following combination of A, B and C: a alone, B alone, C alone, a and B in combination, a and C in combination, B and C in combination, and A, B and C in combination.

"A and/or B" includes the following three combinations: a alone, B alone, and a combination of A and B.

The use of "adapted to" or "configured to" herein is meant to be an open and inclusive language that does not exclude devices adapted to or configured to perform additional tasks or steps.

Additionally, the use of "based on" means open and inclusive, as a process, step, calculation, or other action that is "based on" one or more stated conditions or values may in practice be based on additional conditions or values beyond those stated.

As used herein, "about," "approximately," or "approximately" includes the stated values as well as average values that are within an acceptable range of deviation for the particular value, as determined by one of ordinary skill in the art in view of the measurement in question and the error associated with measurement of the particular quantity (i.e., the limitations of the measurement system).

In the context of this disclosure, the meaning of "on … …," above, "and" over "should be interpreted in the broadest manner such that" on.

Example embodiments are described herein with reference to cross-sectional and/or plan views as idealized example figures. In the drawings, the thickness of layers and regions are exaggerated for clarity. Variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, the exemplary embodiments should not be construed as limited to the shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the exemplary embodiments.

As used herein, the term "substrate" refers to a material onto which subsequent layers of material may be added. The substrate itself may be patterned. The material added on the substrate may be patterned or may remain unpatterned. In addition, the substrate may include a variety of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, and the like. Alternatively, the substrate may be made of a non-conductive material such as glass, plastic, or sapphire wafer.

The term "three-dimensional memory" refers to a semiconductor device formed of strings of memory cell transistors (referred to herein as "strings of memory cells," e.g., NAND memory cells) arranged in an array on a major surface of a substrate or a source layer and extending in a direction perpendicular to the substrate or source layer. As used herein, the term "vertically" means nominally perpendicular to a major surface (i.e., a lateral surface) of the substrate or source layer.

Fig. 1 is a schematic perspective view of a memory according to some embodiments of the present disclosure, fig. 2 is a cross-sectional view of the memory, fig. 3 is a cross-sectional view of a memory cell string of the memory shown in fig. 1 along a section line AA', and fig. 4 is an equivalent circuit diagram of the memory cell string shown in fig. 3.

Referring to fig. 1 and 2, some embodiments of the present disclosure provide a memory 10. Memory 10 may include a semiconductor structure 200. The memory 10 may further include a source layer SL coupled to the semiconductor structure 200, and a peripheral device 100 coupled to the semiconductor structure 200. The peripheral device 100 may be disposed on a side of the semiconductor structure 200 away from the source layer SL.

The material of the source layer SL may include a semiconductor material such as monocrystalline silicon, polycrystalline silicon, monocrystalline germanium, a III-V compound semiconductor material, a II-VI compound semiconductor material, and other suitable semiconductor materials. The source layer SL may be partially or fully doped. Illustratively, the source layer SL may include a doped region doped with a p-type dopant. The source layer SL may further include an undoped region.

The semiconductor structure 200 may include memory cell transistor strings 400 (referred to herein as "memory cell strings," e.g., NAND memory cell strings) arranged in an array. The source layer SL may be coupled to sources of the plurality of memory cell strings 400.

Specifically, referring to fig. 3 and 4, the memory cell string 400 may include a plurality of transistors T, and one transistor T (e.g., T1 to T6 in fig. 4) may be provided as one memory cell, and the transistors T are connected together to form the memory cell string 400. One transistor T (e.g., each transistor T) may be formed of a semiconductor channel 241 and one gate line G surrounding the semiconductor channel 241. Wherein the gate line G is configured to control a turn-on state of the transistor T.

It should be noted that the numbers of transistors in fig. 1 to 4 are merely schematic, and the memory cell string of the memory provided by the embodiment of the present disclosure may further include other numbers of transistors, for example, 4, 16, 32, and 64.

Further, along the third direction Z, a lowermost gate line of the gate lines G (e.g., a gate line closest to the source layer SL of the gate lines G) is configured as a source select gate SGS, and the source select gate SGS is configured to control the on-state of the transistor T6, and thus the on-state of the source channel in the memory cell string 400. The uppermost gate line among the plurality of gate lines G (e.g., the gate line farthest from the source layer SL among the plurality of gate lines G) is configured as a drain select gate SGD configured to control the on-state of the transistor T1, thereby controlling the on-state of the drain channel in the memory cell string 400. The gate line in the middle of the plurality of gate lines G may be configured as a plurality of word lines WL, including, for example, word line WL0, word line WL1, word line WL2, and word line WL 3. Writing, reading, and erasing of data to individual memory cells (e.g., transistors T) in the memory cell string 400 may be accomplished by writing different voltages on the word lines WL.

The memory 10 extends in an X-Y plane, and the first direction X and the second direction Y are, for example, two orthogonal directions in a plane (e.g., a plane in which the source layer SL is located) in which the semiconductor structure 200 is located: the first direction X is, for example, an extending direction of the word line WL, and the second direction Y is, for example, an extending direction of the bit line BL. The third direction Z is perpendicular to the plane of the semiconductor structure 200, i.e., perpendicular to the X-Y plane.

As used in this disclosure, whether a component (e.g., a layer, structure, or device) is "on," "above," or "below" another component (e.g., a layer, structure, or device) of a semiconductor device (e.g., a memory) is determined in a third direction Z relative to a substrate or a source layer of the semiconductor device when the substrate or the source layer is located in a lowest plane of the semiconductor device in the third direction Z. Throughout this disclosure, the same concepts are applied to describe spatial relationships.

With continued reference to fig. 1 and 2, in some embodiments, the semiconductor structure 200 may further include an array interconnect layer 290. Array interconnect layer 290 may be coupled with memory cell string 400. The array interconnect layer 290 may include a drain terminal (i.e., a bit line BL) of the memory cell string 400, which may be coupled to a semiconductor channel of each transistor T in at least one memory cell string 400.

The array interconnect layer 290 may include one or more first interlayer insulating layers 292, and may further include a plurality of contacts insulated from each other by the first interlayer insulating layers 292, the contacts including, for example, bit line contacts BL-CNT coupled to the bit lines BL; a drain select gate contact SGD-CNT coupled to drain select gate SGD. The array interconnect layer 290 may also include one or more first interconnect conductor layers 291. The first interconnect conductor layer 291 may include a plurality of connection lines, such as bit lines BL, and word line connection lines WL-CL coupled to word lines WL. The material of the first interconnect conductor layer 291 and the contact may be a conductive material such as a combination of one or more of tungsten, cobalt, copper, aluminum, and metal silicide, and may be other suitable materials. The material of the first interlayer insulating layer 292 is an insulating material, such as silicon oxide, silicon nitride, and a combination of one or more of high-k insulating materials, and may be other suitable materials.

The peripheral device 100 may include peripheral circuitry. The peripheral circuitry is configured to control and sense the array device. The peripheral circuitry may be any suitable digital, analog, and/or mixed signal control and sensing circuitry for supporting array device operation (or working), including but not limited to page buffers, decoders (e.g., row and column decoders), sense amplifiers, drivers (e.g., word line drivers), charge pumps, current or voltage references, or any active or passive component of circuitry (e.g., transistors, diodes, resistors, or capacitors). The peripheral circuits may also include any other circuits compatible with advanced Logic processes, including Logic circuits (e.g., processors and Programmable Logic Devices (PLDs) or Memory circuits (e.g., Static Random-Access memories (SRAMs)).

Specifically, in some embodiments, the peripheral device 100 may include a substrate 110, a transistor 120 disposed on the substrate 110, and a peripheral interconnect layer 130 disposed on the substrate 110. The peripheral circuitry may include a transistor 120.

The material of the substrate 110 may be monocrystalline silicon, or may be other suitable materials, such as silicon germanium, or a silicon-on-insulator thin film.

Peripheral interconnect layer 130 is coupled to transistor 120 to enable the transmission of electrical signals between transistor 120 and peripheral interconnect layer 130. The peripheral interconnection layer 130 may include one or more second interlayer insulating layers 131 and may further include one or more second interconnection conductor layers 132. Different second interconnect conductor layers 132 may be coupled to each other by contacts. The material of the second interconnect conductor layer 132 and the contacts may be a conductive material, such as a combination of one or more of tungsten, cobalt, copper, aluminum, and metal silicide, and may be other suitable materials. The material of the second interlayer insulating layer 131 is an insulating material, such as one or a combination of silicon oxide, silicon nitride, and a high-k insulating material, and may be other suitable materials.

The peripheral interconnect layer 130 may be coupled with the array interconnect layer 290 such that the semiconductor structure 200 and the peripheral device 100 may be coupled. Specifically, since the peripheral interconnect layer 130 is coupled to the array interconnect layer 290, peripheral circuits in the peripheral device 100 may be coupled to the memory cell strings in the semiconductor structure 100 to enable transmission of electrical signals between the peripheral circuits and the memory cell strings. In some possible implementations, a bonding interface 500 may be disposed between the peripheral interconnection layer 130 and the array interconnection layer 290, and the peripheral interconnection layer 130 and the array interconnection layer 290 may be bonded and coupled to each other through the bonding interface 500.

To increase memory density, the size of memory 10 is smaller and smaller, as are the distances between the individual transistors T in the memory cell string 400. In this case, when the transistor T is programmed, threshold voltages of other transistors T adjacent to the transistor T being programmed in the same memory cell string 400 may increase due to electric field coupling, thereby affecting device performance.

Based on this, in some embodiments, as shown in fig. 15, the semiconductor structure 200 includes a stack layer 210, a channel structure 220, and a plurality of second dielectric layers 230.

With reference to fig. 2 and fig. 15, the stack layer 210 may be disposed on the source layer SL, that is, the stack layer 210 is located on one side of the thickness direction of the source layer SL (i.e., the third direction Z in fig. 2). The stack layer 210 includes a plurality of first dielectric layers 211 and a plurality of gate layers 212, and the first dielectric layers 211 and the gate layers 212 are alternately stacked in the third direction Z (see fig. 1).

It should be noted that the material of the first dielectric layer 211 may include an insulating material, and the insulating material includes at least one of silicon oxide, silicon nitride, silicon oxynitride, doped silicon oxide, organosilicate glass, dielectric metal oxide (e.g., aluminum oxide, hafnium oxide, etc.) and silicate thereof, and an organic insulating material.

The gate layer 212 may include a conductor layer 2121, and the material of the conductor layer 2121 may include a conductive material, such as at least one of tungsten, cobalt, copper, aluminum, doped silicon, and silicide.

In some embodiments, as shown in fig. 15, the gate layer 212 may further include a metal compound layer 2122, the metal compound layer 2122 being located between the conductor layer 2121, the channel structure 40 and the first dielectric layer 211, the metal compound layer 2122 being configured as an adhesion layer to improve adhesion between the conductor layer 2121 and the first dielectric layer 211. Wherein the material of the metal compound layer 2122 includes at least one of titanium nitride, tantalum nitride, and tungsten carbide.

In some embodiments, as shown in fig. 15, the gate layer 212 may further include a high dielectric constant layer 2123, the high dielectric constant layer 2123 being located between the metal compound layer 2122, the channel structure 40 and the first dielectric layer 211 to reduce the risk of charges in the channel structure 40 flowing to the conductor layer 2121. Wherein the high-k layer 323 has a dielectric constant value greater than or equal to 7. Illustratively, the material of the high dielectric constant layer 323 includes at least one of aluminum oxide, hafnium oxide, and tantalum oxide.

In some embodiments, the stack layer 210 is in contact with the source layer SL. In other embodiments, other functional layers are disposed between the stack layer 210 and the source layer SL. For example, a semiconductor layer 281 and a third dielectric layer 282 are further disposed between the stack layer 210 and the source layer SL, the semiconductor layer 281 is in contact with the stack layer 210, and the third dielectric layer 282 is in contact with the source layer SL. The layer of the stack 210 closest to the source layer SL may be the first dielectric layer 211.

Note that the material of the semiconductor layer 281 includes a semiconductor material such as single crystal silicon, polycrystalline silicon, single crystal germanium, a group III-V compound semiconductor material, a group II-VI compound semiconductor material, and other suitable semiconductor materials. The material of the third dielectric layer 282 includes an insulating material, which may include at least one of silicon oxide, silicon nitride, silicon oxynitride, doped silicon oxide, organosilicate glass, dielectric metal oxides (e.g., aluminum oxide, hafnium oxide, etc.) and silicates thereof, and organic insulating materials.

The number of layers of the stacked layer 210 is not limited by the embodiments of the present disclosure, for example, the number of layers of the stacked layer 210 may be 8, 64, 128, and the like. It is understood that the greater the number of layers of the stacked layers 210, the higher the integration, the greater the number of transistors T in the memory cell string 400 formed therefrom.

As shown in fig. 15, channel structure 220 extends through stack 210. In the case that the stack layer 210 may be disposed on the source layer SL, and the semiconductor layer 281 and the third dielectric layer 282 are further disposed between the stack layer 210 and the source layer SL, the channel structure 220 further penetrates the semiconductor layer 281 and the third dielectric layer 282, so that the channel structure 220 may be coupled to the source layer SL.

In some embodiments, referring to fig. 15, the channel structure 220 includes a memory function layer 221 and a semiconductor channel layer 222, one side of the memory function layer 221 is in contact with the first dielectric layer 211 and the side of the gate line layer 212, and the other side is in contact with the semiconductor channel layer 222; that is, the memory function layer 221 is located between the semiconductor channel layer 222 and the first dielectric layer 211 and the gate line layer 212.

Note that the material of the semiconductor channel layer 222 includes a semiconductor material such as single crystal silicon, polycrystalline silicon, single crystal germanium, a group III-V compound semiconductor material, a group II-VI compound semiconductor material, and other suitable semiconductor materials.

The memory function layer 221 includes a blocking layer 2211, a charge trapping layer 2212 and a tunneling layer 2213, and the materials of the blocking layer 2211, the charge trapping layer 2212, the tunneling layer 2213 and the semiconductor channel layer 222 may be silicon oxide, silicon nitride, silicon oxide and polysilicon, respectively, so as to form a "SONO" structure.

In some embodiments, as shown in fig. 15, the channel structure 220 further includes a channel filling layer 223, and the channel filling layer 223 is disposed on a side of the semiconductor channel layer 222 away from the storage function layer 221 to provide a mechanical supporting function. It should be noted that the material of the trench filling layer 223 includes an insulating material, and the insulating material may include at least one of silicon oxide, silicon nitride, silicon oxynitride, doped silicon oxide, organosilicate glass, dielectric metal oxide (e.g., aluminum oxide, hafnium oxide, etc.) and silicate thereof, and an organic insulating material.

Wherein the first dielectric layer 211 is recessed near the edge of the channel structure 220, and the second dielectric layer 230 is located between the first dielectric layer 211 and the channel structure 220, and the second dielectric layer 230 is located between two adjacent gate electrode 212 layers along the direction perpendicular to the plane of the stack layer 210 (i.e. the Z direction in fig. 1), compared to the gate electrode layer 212 recessed near the edge of the channel structure 220. The dielectric constant of the second dielectric layer 230 is less than the dielectric constant of the first dielectric layer 211.

Based on this, the first dielectric layer 211 and the second dielectric layer 230 may be made of different materials, respectively. That is, the first dielectric layer 211 and the second dielectric layer 230 can be made of suitable materials according to their respective design requirements, and thus the cost is low.

For example, the first dielectric layer 211 may be made of a material with a large elastic modulus to support the stacked layer 210. The first dielectric layer 211 does not need to consider whether the dielectric constant of the material is too high; in this way, the first dielectric layer 211 can be made of a wide variety of materials at a low cost. The second dielectric layer 230 may be made of a material with a low dielectric constant to reduce the electric field coupling between the transistors T in the same memory cell string 400, thereby improving the device performance. The second dielectric layer 230 does not need to consider whether the elastic modulus of the material is too low; in this way, the second dielectric layer 230 may be made of a wider variety of materials and at a lower cost.

For example, the dielectric constant of the second dielectric layer 230 is less than or equal to 3. Specifically, the material of the second dielectric layer 230 may include any one of carbon-doped silicon hydroxide and fluorine-doped silicon oxide. At this time, the second dielectric layer 230 has a smaller elastic modulus than the first dielectric layer 211.

For example, the elastic modulus of the first dielectric layer 211 is greater than the elastic modulus of the second dielectric layer 230, so as to improve the structural stability of the stacked layer 210 and reduce the risk of the stacked layer 210 falling. The elastic modulus of the first dielectric layer 211 may be 70GPa to 100 GPa. Specifically, the material of the first dielectric layer 211 may be silicon dioxide. At this time, the dielectric constant of the first dielectric layer 211 was 3.9.

In some embodiments, as shown in fig. 15, one side of the second dielectric layer 230 is in contact with the first dielectric layer 211 and the other side is in contact with the channel structure 220. That is, the second dielectric layer 230 fills the gap between the first dielectric layer 211 and the channel structure 22, so as to avoid the problem of short circuit between the gate layers 212 of different layers during the process of manufacturing the semiconductor structure 200, particularly during the process of replacing the gate layers 212.

In some embodiments, as shown in fig. 15, the second dielectric layer 230 is far from the boundary of the first dielectric layer 211 and is flush with the boundary of the gate layer 212 close to the channel structure 220, so that the second dielectric layers 230 with lower dielectric constants are disposed between the edge portions of the different gate layers 212 close to the channel structure 220, thereby reducing the effect of electric field coupling between the transistors T in the same memory cell string 400 as much as possible and improving the device performance.

The distance between the second dielectric layer 230 close to the boundary of the first dielectric layer 211 and the boundary of the second dielectric layer 230 far from the first dielectric layer 211 is 0.5nm to 5nm, that is, the length of the second dielectric layer 230 along the X direction in fig. 15 ranges from 0.5nm to 5 nm; this may avoid the risk of stack layer 210 toppling over due to the oversized second dielectric layer 230; and, the problem that the electric field coupling between the transistors T in the same memory cell string 400 cannot be reduced to a predetermined level due to the undersize of the second dielectric layer 230 is avoided. Illustratively, the second dielectric layer 230 is close to the boundary of the first dielectric layer 211 at any one of a distance of 0.5nm, 1nm, 2nm, 3nm, 4nm, and 5nm from the boundary of the second dielectric layer 230 away from the first dielectric layer 211.

In some embodiments, referring to fig. 15, the semiconductor structure 200 may further include a gate line isolation structure 240, the gate line isolation structure 240 penetrating the stack layer 210. The gate line isolation structure 240 includes an insulating isolation portion 241, and the insulating isolation portion 241 is in contact with the first dielectric layer 211 and the side surface of the gate line layer 212.

In some embodiments, as shown in fig. 15, the gate line isolation structure 240 may further include a gate line filling layer 242. The insulating isolation portion 241 is in contact with the first dielectric layer 211 and the side surface of the gate line layer 212, a cavity is left inside the insulating isolation portion 241, and the gate line filling layer 242 fills the cavity to provide a mechanical support effect. It should be noted that the material of the gate line filling layer 242 may be a conductive material, and may also be an insulating material, which is not specifically limited herein.

In some embodiments, as shown in fig. 15, the semiconductor structure 200 may further include a dummy channel structure 250.

Wherein the dummy channel structure 250 extends through the stack of layers 210, and the dummy channel structure 250 is configured to provide mechanical support to the semiconductor structure 200. It is noted that the dummy channel structure 250 may include an insulating material, such as one or a combination of silicon oxide, silicon nitride, and a high-k insulating material, or other suitable materials. The dummy channel structure 250 may include one or more air gaps 251, and the air gaps 251 may reduce structural stress.

In some embodiments, referring to fig. 15, the semiconductor structure 200 may further include a capping layer 260. The capping layer 260 may cover the stack layer 210 to function as a protection of the semiconductor structure 200. Wherein, the material of the capping layer 260 may include an insulating material, and the insulating material may include at least one of silicon oxide, silicon nitride, and a high dielectric constant insulating material, to which the present disclosure is not limited.

It should be noted that the surface of the covering layer 260 away from the stack layer 210 needs to be processed by a chemical mechanical polishing process to planarize the surface of the covering layer 260 away from the stack layer 210 globally.

Embodiments of the present disclosure also provide a method for manufacturing the semiconductor structure 200, as shown in fig. 16, the method includes steps S100 to S500.

S100: as shown in FIG. 5, an initial stack 210' is formed.

In the above step, the initial stack layer 210 'includes a plurality of first dielectric layers 211 and a plurality of sacrificial layers 212' alternately disposed. The initial stack layer 210' may be formed on the substrate 300 by any one of Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), and Atomic Layer Deposition (ALD).

It should be noted that, the material of the first dielectric layer 211 may refer to the above, and is not described herein again. The material of the sacrificial layer 212' includes at least one of polysilicon, silicon nitride, and poly-germanium, to which the present disclosure is not limited. Here, the material of the first dielectric layer 211 is different from that of the sacrificial layer 212 'such that the first dielectric layer 211 and the sacrificial layer 212' have different etching selectivity ratios with respect to the same etchant. Illustratively, the material of the first dielectric layer 211 is silicon dioxide, and the material of the sacrificial layer 212' is silicon nitride.

Wherein the substrate 300 may be used to support the initial stack 210' thereon, which may be removed in a subsequent process, as described in detail below. The material of the substrate 300 includes at least one of single crystal silicon (Si), polycrystalline silicon, single crystal germanium (Ge), a III-V compound semiconductor material, a II-VI compound semiconductor material, or other semiconductor materials known in the art.

In some embodiments, as shown in fig. 5, the substrate 300 may be a composite substrate. Illustratively, the substrate 300 may include a base 310, and a sacrificial silicon oxide layer 320 and a sacrificial polysilicon layer 330 are sequentially formed on the base 310. Wherein the material of the substrate 310 may include at least one of single crystal silicon (Si), polycrystalline silicon, single crystal germanium (Ge), a III-V compound semiconductor material, a IIVI compound semiconductor material, or other semiconductor materials known in the art; the material of the sacrificial silicon oxide layer 320 may include silicon oxide; the material of the sacrificial polysilicon layer 330 may include polysilicon.

S200: as shown in fig. 6, a channel hole CH is formed through the initial stack of layers 210'.

In the above steps, the channel hole CH penetrating the initial stacked structure 210' may be formed through a dry/wet etching process. Illustratively, the channel hole CH is formed using an anisotropic etching (any of dry etching such as ion mill etching, plasma etching, reactive ion etching, laser ablation, etc.) process. The channel hole CH extends into the substrate 300, for example, the substrate 300 is a composite substrate, and the channel hole CH extends into the sacrificial polysilicon layer 330.

S300: as shown in fig. 7, an edge portion of the first dielectric layer 211 near the channel hole CH is removed through the channel hole CH.

In the above step, the end portion of the first dielectric layer 211 exposed at the channel hole CH is etched using the channel hole CH as an etchant channel, and the etchant is used to etch the first dielectric layer 211. The first dielectric layer 211 is recessed from the boundary of the channel hole CH compared to the sacrificial layer 212' to form a recess.

The etching may be wet etching or vapor etching. Using an etching solution as an etchant in wet etching; etching gas is used as an etchant in the vapor phase etching.

S400: as shown in fig. 8 and 9, a second dielectric layer 230 is formed within the recess.

In the above step, the dielectric constant of the second dielectric layer 230 is smaller than that of the first dielectric layer 211. The second dielectric layer 230 may be formed in the groove by using the channel hole CH as a deposition channel and using any one of CVD, PVD, and ALD thin film deposition processes. Reference may be made to S410 to S420, which is not described herein in detail.

It should be noted that, the material of the second dielectric layer 230 may refer to the above, and is not described herein again.

S500: as shown in fig. 9 and 10, a channel structure 220 is formed within the channel hole CH.

In the above steps, a blocking layer 2211, a charge trapping layer 2212, a tunneling layer 2213 and a semiconductor channel layer 222 may be sequentially deposited along the inner wall of the channel hole CH by using any one of CVD, PVD and ALD thin film deposition processes to form the channel structure 220. Among them, the blocking layer 2211, the charge trapping layer 2212 and the tunneling layer 2213 can be referred to as the storage function layer 221.

Wherein the second dielectric layer 230 is located between the first dielectric layer 211 and the channel structure 220 along a direction parallel to the plane of the initial stack 210' (i.e., the plane defined by X-Y in fig. 1).

It should be noted that, the materials of the blocking layer 2211, the charge trapping layer 2212, the tunneling layer 2213 and the semiconductor channel layer 222 may be referred to above, and are not described herein again.

In some embodiments, after the memory function layer 221 and the semiconductor channel layer 222 are sequentially formed in the channel hole CH, a channel filling layer 223 may be further formed in the channel hole CH. For example, a thin film deposition process of CVD, PVD, ALD may be used to fill an insulating material, such as silicon oxide, in the channel hole CH formed with the memory function layer 221 and the semiconductor channel layer 222, so as to form the channel structure 220 having the memory function layer 221, the semiconductor channel layer 222, and the channel filling layer 223.

In some embodiments, as shown in FIG. 17, S400 includes S410-S420.

S410: as shown in FIG. 8, a target material is deposited to form a second dielectric film 230'.

In the above step, the dielectric constant of the target material is smaller than the dielectric constant of the material of the first dielectric layer 211. Specifically, the target material may be deposited by any of thin film deposition processes of CVD, PVD, and ALD. Wherein, when the target material is deposited, the target material is also formed on the upper side of the initial stack layer 210' and the inner wall of the channel hole CH.

It should be noted that the target material is a material of the second dielectric layer 230, which may be referred to above specifically and is not described herein again.

S420: as shown in fig. 8 and 9, a portion of the second dielectric film 230 'covering the initial stack layer 210' and a portion covering the inner wall of the channel hole CH are removed to form the second dielectric layer 230.

In the above steps, the initial stack layer 210 'covered with the second dielectric film 230' may be etched using an etchant, which is used to etch the target material.

In the process of etching the portion of the second dielectric film 230 'covering the initial stack layer 210' and the portion of the second dielectric film 230 'covering the inner wall of the channel hole CH, the etching time may be controlled to remove the portion of the second dielectric film 230' covering the initial stack layer 210 'and the portion of the second dielectric film covering the inner wall of the channel hole CH, and then the etching is stopped, so that the second dielectric layer 230 is away from the boundary of the first dielectric layer 211 and is flush with the boundary of the sacrificial layer 212' near the channel hole CH.

In some embodiments, as shown in fig. 18, after S500, the above preparation method further includes S600 to S800.

S600: as shown in fig. 11, a gate line slit GLS is formed through the initial stack layer 210'.

In the above step, the gate line slit GLS penetrating the initial stack layer 210' may be formed through a dry/wet etching process. Illustratively, the gate line gap GLS is formed by an anisotropic etching (any one of dry etching such as ion milling etching, plasma etching, reactive ion etching, and laser ablation). The gate line gap GLS extends into the substrate 300, for example, the substrate 300 is a composite substrate, and the gate line gap GLS extends into the sacrificial polysilicon layer 330.

It should be noted that the forming of the channel hole CH penetrating through the initial stack layer 210 ' in S200 and the forming of the gate line gap GLS penetrating through the initial stack layer 210 ' in S600 are performed in different processes to prevent the second dielectric film 230 ' from being formed in the gate line gap GLS; for example, the channel hole CH is formed by one etching process, and the gate line gap GLS is formed by another etching process, and the sequence of the two steps is not limited in the present disclosure.

S700: as shown in fig. 11 and 12, the sacrificial layer 212' is removed through the gate line gap GLS, forming a sacrificial gap.

In the above steps, the gate line gap GLS is used as an etchant channel, and isotropic etching is used to remove the sacrificial layer 212' to form a sacrificial gap. The isotropic etching may employ selective wet etching or vapor etching. Using an etching solution as an etchant in wet etching; etching gas is used as an etchant in the vapor phase etching.

In the case that the material of the first dielectric layer 211 is silicon oxide and the material of the sacrificial layer 212' is silicon nitride, a phosphoric acid solution may be used as an etchant in the wet etching; at least one of C4F8, C4F6, and CH2F2 may be employed as an etching gas in the vapor phase etching.

S800: as shown in fig. 12 and 13, a gate layer 212 is formed within the sacrificial gap.

In the above steps, the gate electrode layer 212 may be formed in the sacrificial gap by using the gate line gap GLS as a deposition channel and using any one of CVD, PVD, and ALD thin film deposition processes.

It should be noted that, the structure and material of the gate layer 212 can be referred to above, and the disclosure is not repeated herein. In addition, after the gate layer 212 is formed, as shown in fig. 13 and 14, a gate line isolation structure 240 may be formed in the gate line gap GLS, and the gate line isolation structure 240 may refer to the above, which is not described herein again.

Based on the above, as shown in fig. 13, a stack layer 210 may be formed, the stack layer 210 including the first dielectric layer 211 and the gate layer 212 alternately stacked.

In some embodiments, as shown in fig. 20, between S100 and S200, the above preparation method further includes S110.

S110: referring to fig. 5, a capping layer 260 is formed.

In the above steps, the capping layer 260 may be formed on the initial stack layer 210' using any one of CVD, PVD and ALD thin film deposition processes. That is, the capping layer 260 is disposed on the initial stack layer 210'. The material of the covering layer 260 may be referred to above, and is not described herein in detail in this disclosure.

In this case, in the process of forming the channel hole CH in S200, the channel hole CH also penetrates the capping layer 260. Similarly, in the process of forming the gate line gap GLS in S600, the gate line gap GLS also penetrates the capping layer 260. At this time, in the case where the material of the capping layer 260 is the same as that of the first dielectric layer 211, in the process of removing the edge portion of the first dielectric layer 211 near the channel hole CH in S300, a portion of the capping layer 260 is also removed, for example, the edge portion of the capping layer 260 near the channel hole CH is removed, and a portion of the capping layer 260 away from the initial stacked layer 210'.

On this basis, after S400, as shown in fig. 19, the above preparation method further includes S120.

S120: referring to FIG. 9, a planarization process is performed on the side of the capping layer 260 away from the initial stack 210'.

In the above step, the surface of the covering layer 260 away from the initial stack 210 'may be treated by a chemical mechanical polishing process to planarize the surface of the covering layer 260 away from the initial stack 210'.

In some embodiments, after S120, the above preparation method further comprises S900.

S900: the substrate 300 is removed.

In the above steps, the substrate 300 may be removed by Chemical Mechanical Planarization (CMP), dry/wet etching process.

Illustratively, the substrate 300 is a composite substrate, and the base 310, the sacrificial silicon oxide layer 320, and the sacrificial polysilicon layer 330 may be sequentially removed by a wet etching process to expose a portion of the channel structure 220 extending into the sacrificial polysilicon layer 330.

FIG. 20 is a block diagram of a storage system according to some embodiments. FIG. 21 is a block diagram of memory systems according to further embodiments.

Referring to fig. 20 and 21, some embodiments of the present disclosure also provide a storage system 1000. The memory system 1000 includes a controller 20, and a memory 10 as in some embodiments above, the controller 20 coupled to the memory 10 to control the memory 10 to store data.

The Storage system 1000 may be integrated into various types of Storage devices, for example, included in the same package (e.g., a Universal Flash Storage (UFS) package or an Embedded multimedia Card (eMMC) package). That is, the storage system 1000 may be applied to and packaged into different types of electronic products, such as a mobile phone (e.g., a cell phone), a desktop computer, a tablet computer, a laptop computer, a server, an in-vehicle device, a game console, a printer, a positioning device, a wearable device, a smart sensor, a mobile power supply, a Virtual Reality (VR) device, an Augmented Reality (AR) device, or any other suitable electronic device having storage therein.

In some embodiments, referring to fig. 20, the memory system 1000 includes a controller 20 and a memory 10, and the memory system 1000 may be integrated into a memory card.

The Memory Card includes any one of a PC Card (PCMCIA), a Compact Flash (CF) Card, a Smart Media (SM) Card, a Memory stick, a Multimedia Card (MMC), a Secure Digital Memory Card (SD), and a UFS.

In other embodiments, referring to fig. 21, the storage system 1000 includes a controller 20 and a plurality of memories 10, and the storage system 1000 is integrated into a Solid State Drive (SSD).

In storage system 1000, in some embodiments, controller 20 is configured for operation in a low duty cycle environment, such as an SD card, CF card, Universal Serial Bus (USB) flash drive, or other media for use in electronic devices such as personal computers, digital cameras, mobile phones, and the like.

In other embodiments, the controller 20 is configured for operation in a high duty cycle environment SSD or eMMC for data storage and enterprise storage arrays of mobile devices such as smart phones, tablets, laptops, and the like.

In some embodiments, the controller 20 may be configured to manage data stored in the memory 10 and communicate with an external device (e.g., a host). In some embodiments, controller 20 may also be configured to control operations of memory 10, such as read, erase, and program operations. In some embodiments, the controller 20 may also be configured to manage various functions with respect to data stored or to be stored in the memory 10, including at least one of bad block management, garbage collection, logical to physical address translation, wear leveling. In some embodiments, controller 20 is also configured to process error correction codes for data read from memory 10 or written to memory 10.

Of course, the controller 20 may also perform any other suitable functions, such as formatting the memory 10; for example, the controller 20 may communicate with an external device (e.g., a host) via at least one of various interface protocols.

It should be noted that the interface protocol includes at least one of a USB protocol, an MMC protocol, a Peripheral Component Interconnect (PCI) protocol, a PCI express (PCI-E) protocol, an Advanced Technology Attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a Small Computer System Interface (SCSI) protocol, an Enhanced Small Disk Interface (ESDI) protocol, an Integrated Drive Electronics (IDE) protocol, and a Firewire protocol.

Some embodiments of the present disclosure also provide an electronic device. The electronic device may be any one of a mobile phone, a desktop computer, a tablet computer, a notebook computer, a server, an in-vehicle device, a wearable device (e.g., a smart watch, a smart bracelet, smart glasses, etc.), a mobile power source, a game console, a digital multimedia player, and the like.

The electronic device may include the storage system 1000 described above, and may further include at least one of a Central Processing Unit (CPU), a cache (cache), and the like.

The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.

Claims (15)

1. A semiconductor structure, comprising:

a stack layer including a plurality of first dielectric layers and a plurality of gate layers alternately stacked;

a channel structure extending through the stack; the first dielectric layer is close to the boundary of the channel structure and is retracted compared with the gate layer close to the boundary of the channel structure;

a plurality of second dielectric layers, the second dielectric layers being located between the first dielectric layers and the channel structure in a direction parallel to a plane in which the stack of layers is located; and the second dielectric layer is positioned between two adjacent gate layers along the direction vertical to the plane of the stacked layers, and the dielectric constant of the second dielectric layer is smaller than that of the first dielectric layer.

2. The semiconductor structure of claim 1, wherein the second dielectric layer is in contact with the first dielectric layer on one side and the channel structure on the other side.

3. The semiconductor structure of claim 1, wherein the dielectric constant of the second dielectric layer is less than or equal to 3.

4. The semiconductor structure of claim 3, wherein the material of the second dielectric layer comprises any one of carbon-doped silicon oxide, carbon-doped silicon hydroxide, and fluorine-doped silicon oxide.

5. The semiconductor structure of claim 1, wherein the first dielectric layer has a modulus of elasticity greater than the modulus of elasticity of the second dielectric layer.

6. The semiconductor structure of claim 5, wherein the first dielectric layer has a modulus of elasticity of 70GPa to 100 GPa.

7. The semiconductor structure according to any one of claims 1 to 6, wherein the second dielectric layer is located at a distance of 0.5nm to 5nm from a boundary of the second dielectric layer close to the first dielectric layer and a boundary of the second dielectric layer far from the first dielectric layer.

8. A method for fabricating a semiconductor structure, comprising:

forming an initial stack layer; the initial stacking layer comprises a plurality of sacrificial layers and a plurality of first dielectric layers which are alternately arranged;

forming a trench hole through the initial stack of layers;

removing the edge part of the first dielectric layer close to the channel hole through the channel hole, so that the boundary of the first dielectric layer close to the channel hole is retracted compared with the boundary of the sacrificial layer close to the channel hole, and a groove is formed;

forming a second dielectric layer in the groove; the dielectric constant of the second dielectric layer is smaller than that of the first dielectric layer;

forming a channel structure in the channel hole; and the second dielectric layer is positioned between the first dielectric layer and the channel structure along the direction parallel to the plane of the initial stacking layer.

9. The method of claim 8, wherein the forming a second dielectric layer in the recess comprises:

depositing a target material to form a second dielectric film; the dielectric constant of the target material is smaller than that of the material of the first dielectric layer;

and removing the part of the second dielectric film covering the initial stacking layer and the part of the second dielectric film covering the inner wall of the channel hole to form the second dielectric layer.

10. The method of manufacturing according to claim 8, further comprising, after forming the channel structure:

forming a gate line gap penetrating the initial stack layer;

removing the sacrificial layer through the gate line gap to form a sacrificial gap;

and forming a gate layer in the sacrificial gap.

11. The method according to any one of claims 8 to 10, further comprising, between forming the initial stacked layer and forming the channel hole:

forming a capping layer overlying the initial stack of layers.

12. The production method according to claim 11, wherein the channel hole also penetrates the cover layer in the process of forming the channel hole; in the process of removing the edge part of the first dielectric layer close to the channel hole, removing part of the covering layer;

after forming the second dielectric layer, the preparation method further comprises:

and carrying out planarization treatment on one side of the covering layer far away from the initial stacking layer.

13. A memory, comprising:

a semiconductor structure according to any one of claims 1 to 7;

a peripheral device electrically connected to the semiconductor structure.

14. A storage system, comprising:

a memory as claimed in claim 13;

a controller coupled to the memory to control the memory to store data.

15. An electronic device, characterized in that it comprises a storage system according to claim 14.

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