CN114678376A

CN114678376A - Semiconductor structure, preparation method thereof and three-dimensional memory

Info

Publication number: CN114678376A
Application number: CN202210302865.8A
Authority: CN
Inventors: 刘文静; 袁伟; 刘磊
Original assignee: Yangtze Memory Technologies Co Ltd
Current assignee: Yangtze Memory Technologies Co Ltd
Priority date: 2022-03-25
Filing date: 2022-03-25
Publication date: 2022-06-28

Abstract

The disclosure provides a semiconductor structure and a preparation method thereof, a three-dimensional memory, a storage system and electronic equipment, relates to the technical field of semiconductor chips, and aims to solve the problem that the conductivity of the semiconductor structure is poor. A method of fabricating a semiconductor structure, comprising: a dielectric stack structure including gate insulating layers and gate sacrificial layers alternately stacked is formed at one side of a substrate. A channel hole is formed through the dielectric stack structure. And filling a sacrificial material in the channel hole. And removing the gate sacrificial layer and forming a gate layer to obtain a storage stack structure comprising alternately stacked gate insulating layers and gate layers. Removing the sacrificial material to expose the channel hole. A dielectric layer is formed within the channel hole. And forming a channel structure in the channel hole. The semiconductor structure is applied to a three-dimensional memory to realize reading and writing operations of data.

Description

Semiconductor structure, preparation method thereof and three-dimensional memory

Technical Field

The present disclosure relates to the field of semiconductor chip technologies, and in particular, to a semiconductor structure, a method for manufacturing the same, a three-dimensional memory, a storage system, and an electronic device.

Background

As the feature size of memory cells approaches the lower process limit, planar processes and fabrication techniques become challenging and costly, which causes the storage density of 2D or planar NAND flash memories to approach the upper limit.

To overcome the limitations imposed by 2D or planar NAND flash memories, memories having a three-dimensional structure (3D NAND) have been developed to increase the storage density by arranging memory cells three-dimensionally over a substrate.

In the related art, the conductivity of the semiconductor structure in some three-dimensional memories is poor.

Disclosure of Invention

The embodiment of the disclosure provides a semiconductor structure, a preparation method thereof and a three-dimensional memory, and aims to solve the problem of poor conductivity of the semiconductor structure in the three-dimensional memory.

In order to achieve the purpose, the embodiment of the disclosure adopts the following technical scheme:

in one aspect, a method of fabricating a semiconductor structure is provided. The preparation method comprises the following steps: a dielectric stack structure including gate insulating layers and gate sacrificial layers alternately stacked is formed at one side of a substrate. A channel hole is formed through the dielectric stack structure. And filling a sacrificial material in the channel hole. And removing the gate sacrificial layer and forming a gate layer to obtain a storage stack structure comprising alternately stacked gate insulating layers and gate layers. Removing the sacrificial material to expose the channel hole. A dielectric layer is formed within the channel hole. And forming a channel structure in the channel hole.

According to the preparation method of the semiconductor structure provided by the embodiment of the disclosure, the gate layer is prepared by filling the sacrificial material in the trench hole; and removing the sacrificial material, and manufacturing a dielectric layer in the channel hole. Because the dielectric layer is not manufactured before the gate layer is manufactured, extra sacrificial layer oxide is not needed to be added to protect the dielectric layer in the process of manufacturing the gate layer, meanwhile, the filling rate of the gate layer between adjacent gate insulating layers can be increased, the conductivity of the gate layer is improved, and further, the conductivity of a semiconductor structure in the three-dimensional memory is improved.

In some embodiments, before filling the sacrificial material into the trench hole, the method further includes: and removing part of the grid sacrificial layer by using the channel hole to form a groove. The filling of the sacrificial material in the trench hole comprises: and filling sacrificial materials in the channel holes and the grooves. The removing the sacrificial material to expose the channel hole includes: removing the sacrificial material to expose the channel hole and the groove. The forming a dielectric layer in the channel hole comprises: and forming a dielectric layer at least filling the groove in the channel hole.

In some embodiments, the forming a dielectric layer in the trench hole at least filling the recess includes: forming a dielectric film covering the groove and the inner wall of the channel hole; and removing the part of the dielectric film covering the inner wall of the channel hole, and reserving the part of the dielectric film positioned in the groove so as to form a dielectric part of the dielectric layer in the groove.

In some embodiments, the removing the gate sacrificial layer and forming a gate layer includes: forming gate spacers through the dielectric stack structure; removing the grid sacrificial layer by using the grid isolation groove to form a grid gap; and forming a gate layer in the gate gap.

In some embodiments, the forming a gate layer in the gate gap includes: forming a protective layer in the grid gap; and forming a gate conductive layer in the protective layer. Wherein the protective layer is located between the sacrificial material and the gate conductive layer.

In some embodiments, forming a channel structure within the channel hole includes: forming a barrier layer covering the inner wall of the channel hole and the dielectric layer; forming a storage layer covering the barrier layer; forming a tunneling layer covering the storage layer; forming a channel layer covering the tunneling layer; and filling an insulating material in the channel layer.

In some embodiments, the material of the gate sacrificial layer comprises silicon nitride, and an etching ratio between the sacrificial material and the silicon nitride is greater than 30.

In some embodiments, at least one of the dielectric layer, the dielectric film, and the dielectric portion comprises a material having a dielectric constant greater than 3.9.

In yet another aspect, a semiconductor structure is provided. The semiconductor structure includes: the memory device includes a substrate, a memory stack structure, a channel structure, and a dielectric layer. A storage stack structure is positioned at one side of the substrate, and the storage stack structure comprises gate insulating layers and gate electrode layers which are alternately stacked. A channel structure extends through the storage stack structure. A dielectric layer located between the gate layer and the channel structure; and the orthographic projection outline of the dielectric layer on the substrate is connected with the orthographic projection outline of the gate layer on the substrate.

In some embodiments, an orthographic projection of the dielectric layer on the substrate at least partially overlaps an orthographic projection of the gate insulating layer on the substrate.

In some embodiments, the dielectric layer includes a plurality of independently disposed dielectric portions, and the dielectric portions are embedded between two adjacent gate insulating layers.

In some embodiments, the gate layer includes a gate conductive layer, and a protective layer disposed around the gate conductive layer. The protective layer is in contact with the dielectric layer and the gate insulating layer, respectively.

In some embodiments, the dielectric layer comprises a material having a dielectric constant greater than 3.9.

In some embodiments, the channel structure includes a channel layer, an insulating material, and a memory functional layer. The insulating material is located on the inner side of the channel layer, and the storage function layer is located on the outer side of the channel layer. The storage function layer comprises a tunneling layer, a storage layer and a blocking layer which are far away from the channel layer; wherein the barrier layer is in contact with the dielectric layer.

In yet another aspect, a three-dimensional memory is provided. The three-dimensional memory includes the semiconductor structure as described in some embodiments above, and a peripheral device electrically connected to the semiconductor structure.

In yet another aspect, a storage system is provided, including: the memory device comprises a three-dimensional memory as described above, and a controller coupled to the three-dimensional memory to control the three-dimensional memory to store data.

In yet another aspect, an electronic device is provided, which includes the storage system as described above.

It can be understood that the semiconductor structure, the three-dimensional memory, the storage system and the electronic device provided in the above embodiments of the disclosure may refer to the above advantageous effects of the semiconductor structure, and are not described herein again.

Drawings

In order to more clearly illustrate the technical solutions in the present disclosure, the drawings needed to be used in some embodiments of the present disclosure will be briefly described below, and it is apparent that the drawings in the following description are only drawings of some embodiments of the present disclosure, and other drawings can be obtained by those skilled in the art according to the drawings. Furthermore, the drawings in the following description may be considered as schematic diagrams, and do not limit the actual size of products, the actual flow of methods, the actual timing of signals, and the like, involved in the embodiments of the present disclosure.

FIG. 1 is a perspective block diagram of a three-dimensional memory according to some embodiments;

FIG. 2 is a cross-sectional view of a three-dimensional memory according to some embodiments;

FIG. 3 is a cross-sectional view of a memory cell string along section line AA' of the three-dimensional memory shown in FIG. 1;

FIG. 4 is an equivalent circuit diagram of a memory cell string;

FIG. 5A is a block diagram of a semiconductor structure according to some embodiments;

FIG. 5B is a block diagram of the semiconductor structure of FIG. 5A at a stage of fabrication;

FIG. 6 is a flow chart of fabrication of a semiconductor structure according to some embodiments;

FIGS. 7A-7J are block diagrams of semiconductor structures at various stages of fabrication according to some embodiments;

FIG. 8 is a flow chart of fabrication of a semiconductor structure according to some embodiments;

FIG. 9 is a fabrication flow diagram of a semiconductor structure according to some embodiments;

FIG. 10 is a block diagram of a semiconductor structure according to some embodiments;

FIG. 11 is a block diagram of a semiconductor structure according to some embodiments;

FIG. 12A is a flow chart of a fabrication of a semiconductor structure according to some embodiments;

FIG. 12B is a flow chart of fabrication of a semiconductor structure according to some embodiments;

FIG. 13 is a flow chart of fabrication of a semiconductor structure according to some embodiments;

FIG. 14 is a block diagram of a semiconductor structure according to some embodiments;

FIG. 15 is a block diagram of a semiconductor structure according to some embodiments;

FIG. 16 is a block diagram of a semiconductor structure according to some embodiments;

FIG. 17 is a block diagram of a storage system according to some embodiments;

FIG. 18 is a block diagram of a memory system according to further embodiments.

Detailed Description

Technical solutions in some embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings, and it is obvious that the described embodiments are only a part of the embodiments of the present disclosure, and not all of the embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments provided by the present disclosure belong to the protection scope of the present disclosure.

In the description of the present disclosure, it is to be understood that the terms "center", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like indicate orientations or positional relationships based on those shown in the drawings, and are only for convenience in describing and simplifying the disclosure, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed in a specific orientation, and be operated, and thus, should not be construed as limiting the disclosure.

Throughout the specification and claims, the term "comprising" is to be interpreted in an open, inclusive sense, i.e., as "including, but not limited to," unless the context requires otherwise. In the description herein, the terms "one embodiment," "some embodiments," "an example embodiment," "exemplary" or "some examples" or the like are intended to mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the disclosure. The schematic representations of the terms used above are not necessarily referring to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be included in any suitable manner in any one or more embodiments or examples.

In the following, the terms "first", "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the embodiments of the present disclosure, "a plurality" means two or more unless otherwise specified.

In describing some embodiments, expressions of "coupled" and "connected," along with their derivatives, may be used. For example, the term "connected" may be used in describing some embodiments to indicate that two or more elements are in direct physical or electrical contact with each other. As another example, some embodiments may be described using the term "coupled" to indicate that two or more elements are in direct physical or electrical contact. The term "coupled," however, may also mean that two or more elements are not in direct contact with each other, but yet still co-operate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents herein.

"at least one of A, B and C" has the same meaning as "A, B or at least one of C", both including the following combination of A, B and C: a alone, B alone, C alone, a and B in combination, a and C in combination, B and C in combination, and A, B and C in combination.

"A and/or B" includes the following three combinations: a alone, B alone, and a combination of A and B.

The use of "adapted to" or "configured to" herein is meant to be an open and inclusive language that does not exclude devices adapted to or configured to perform additional tasks or steps.

Additionally, the use of "based on" is meant to be open and inclusive in that a process, step, calculation, or other action that is "based on" one or more stated conditions or values may, in practice, be based on additional conditions or exceed the stated values.

As used herein, "about," "approximately," or "approximately" includes the stated values as well as average values that are within an acceptable range of deviation for the particular value, as determined by one of ordinary skill in the art in view of the measurement in question and the error associated with measurement of the particular quantity (i.e., the limitations of the measurement system).

In the context of this disclosure, the meaning of "on … …," above, "and" over "should be interpreted in the broadest manner such that" on.

Example embodiments are described herein with reference to cross-sectional and/or plan views as idealized example figures. In the drawings, the thickness of layers and regions are exaggerated for clarity. Variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, the exemplary embodiments should not be construed as limited to the shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of exemplary embodiments.

As used herein, the term "substrate" refers to a material onto which subsequent layers of material may be added. The substrate itself may be patterned. The material added on the substrate may be patterned or may remain unpatterned. In addition, the substrate may include a variety of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, and the like. Alternatively, the substrate may be made of a non-conductive material such as glass, plastic, or sapphire wafer.

The term "three-dimensional memory" refers to a semiconductor device formed of strings of memory cell transistors (referred to herein as "strings of memory cells," e.g., NAND memory cells) arranged in an array on a major surface of a substrate or a source layer and extending in a direction perpendicular to the substrate or source layer. As used herein, the term "vertically" means nominally perpendicular to a major surface (i.e., a lateral surface) of the substrate or source layer.

Fig. 1 is a schematic perspective view of a three-dimensional memory according to some embodiments of the present disclosure, fig. 2 is a cross-sectional view of the three-dimensional memory, fig. 3 is a cross-sectional view of a memory cell string of the three-dimensional memory shown in fig. 1 along a section line AA', and fig. 4 is an equivalent circuit diagram of the memory cell string shown in fig. 3.

Note that, in fig. 1 and 2, the three-dimensional memory 10 extends in an X-Y plane, and the first direction X and the second direction Y are, for example, two orthogonal directions in a plane (for example, a plane in which the source layer SL is located) in which the semiconductor structure 200 is located: the first direction X is, for example, an extending direction of the word line WL, and the second direction Y is, for example, an extending direction of the bit line BL. The third direction Z is perpendicular to the plane of the semiconductor structure 200, i.e., perpendicular to the X-Y plane.

As used in this disclosure, whether a component (e.g., a layer, structure, or device) is "on," "above," or "below" another component (e.g., a layer, structure, or device) of a semiconductor device (e.g., a three-dimensional memory) is determined in a third direction Z relative to a substrate or a source layer of the semiconductor device when the substrate or the source layer is located in a lowest plane of the semiconductor device in the third direction Z. Throughout this disclosure, the same concepts are applied to describe spatial relationships.

In order to show the structure of the device more clearly, in fig. 2, a view of the array area CA and a view of the step area SS are shown, the view of the array area CA is based on a left-side coordinate system, the view of the step area SS is based on a right-side coordinate system, that is, the view of the array area CA shows a cross-sectional structure along the Y direction, and the view of the step area SS shows a cross-sectional structure along the X direction.

Referring to fig. 1 and 2, some embodiments of the present disclosure provide a three-dimensional memory 10. The three-dimensional memory 10 may include a semiconductor structure 200. The semiconductor structure 200 may include a source layer SL and a memory function structure 270. As shown in fig. 2, the three-dimensional memory 10 may further include a peripheral device 100 coupled to the semiconductor structure 200. The peripheral device 100 may be disposed on a side of the memory function structure 270 away from the source layer SL.

The source layer SL may include a semiconductor material such as single crystal silicon, single crystal germanium, a III-V compound semiconductor material, a II-VI compound semiconductor material, and other suitable semiconductor materials. The source layer SL may be partially or fully doped. Illustratively, the source layer SL may include a doped region doped with a p-type dopant. The source layer SL may further include an undoped region.

The semiconductor structure 200 may include memory cell transistor strings (referred to herein as "memory cell strings," e.g., NAND memory cell strings) 400 arranged in an array. The source layer SL may be coupled to source terminals of the plurality of memory cell strings 400.

Specifically, referring to fig. 3 and 4, the memory cell string 400 may include a plurality of transistors T (e.g., T1 to T6 in fig. 4), and one transistor T (e.g., one of T1 to T6) may be provided as one memory cell, and the transistors T are connected together to form a memory cell string having a plurality of memory cells. A transistor T (e.g., each transistor T) may be formed of a semiconductor channel 241 and one gate line G surrounding the semiconductor channel 241. Wherein the gate line G is configured to control a turn-on state of the transistor.

It should be noted that the numbers of the transistors in fig. 1 to fig. 4 are only schematic, and the memory cell string of the three-dimensional memory provided by the embodiment of the present disclosure may further include other numbers of transistors, for example, 4, 16, 32, and 64.

Further, along the third direction Z, a lowermost gate line of the gate lines G (e.g., a gate line closest to the source layer SL of the gate lines G) is configured as a source select gate SGS, and the source select gate SGS is configured to control the on-state of the transistor T6, and thus the on-state of the source channel in the memory cell string 400. The uppermost gate line among the plurality of gate lines G (e.g., the gate line farthest from the source layer SL among the plurality of gate lines G) is configured as a drain select gate SGD configured to control the on-state of the transistor T1, thereby controlling the on-state of the drain channel in the memory cell string 400. The gate line in the middle of the plurality of gate lines G may be configured as a plurality of word lines WL, including, for example, word line WL0, word line WL1, word line WL2, and word line WL 3. Writing, reading, and erasing of data to individual memory cells (e.g., transistors T) in the memory cell string 400 may be accomplished by writing different voltages on the word lines WL.

With continued reference to fig. 1 and 2, in some embodiments, the semiconductor structure 200 may further include an array interconnect layer 290. Array interconnect layer 290 may be coupled with memory cell string 400. The array interconnect layer 290 may include a drain terminal (i.e., a bit line BL) of the memory cell string 400, which may be coupled to a semiconductor channel of each transistor T in at least one memory cell string 400.

The array interconnect layer 290 may include one or more first interlayer insulating layers 292, and may further include a plurality of contacts insulated from each other by the first interlayer insulating layers 292, the contacts including, for example, bit line contacts BL-CNT coupled to the bit lines BL; a drain select gate contact SGD-CNT coupled to drain select gate SGD. The array interconnect layer 290 may also include one or more first interconnect conductor layers 291. The first interconnect conductor layer 291 may include a plurality of connection lines, such as bit lines BL, and word line connection lines WL-CL coupled to word lines WL. The material of the first interconnect conductor layer 291 and the contact may be a conductive material such as a combination of one or more of tungsten, cobalt, copper, aluminum, and metal silicide, and may be other suitable materials. The material of the first interlayer insulating layer 292 is an insulating material, such as silicon oxide, silicon nitride, and a combination of one or more of high-k insulating materials, and may be other suitable materials.

The peripheral device 100 may include peripheral circuitry. The peripheral circuitry is configured to control and sense the array device. The peripheral circuitry may be any suitable digital, analog, and/or mixed signal control and sensing circuitry for supporting array device operation (or working), including but not limited to page buffers, decoders (e.g., row and column decoders), sense amplifiers, drivers (e.g., word line drivers), charge pumps, current or voltage references, or any active or passive component of circuitry (e.g., transistors, diodes, resistors, or capacitors). The peripheral circuits may also include any other circuits compatible with advanced Logic processes, including Logic circuits (e.g., processors and Programmable Logic Devices (PLDs) or Memory circuits (e.g., Static Random-Access memories (SRAMs)).

Specifically, in some embodiments, the peripheral device 100 may include a substrate 110, a transistor 120 disposed on the substrate 110, and a peripheral interconnect layer 130 disposed on the substrate 110. The peripheral circuitry may include a transistor 120.

The material of the substrate 110 may be monocrystalline silicon, or may be other suitable materials, such as silicon germanium, or a silicon-on-insulator thin film.

Peripheral interconnect layer 130 is coupled to transistor 120 to enable the transmission of electrical signals between transistor 120 and peripheral interconnect layer 130. The peripheral interconnection layer 130 may include one or more second interlayer insulating layers 131 and may further include one or more second interconnection conductor layers 132. Different second interconnect conductor layers 132 may be coupled to each other by contacts. The material of the second interconnect conductor layer 132 and the contacts may be a conductive material, such as a combination of one or more of tungsten, cobalt, copper, aluminum, and metal silicide, and may be other suitable materials. The material of the second interlayer insulating layer 131 is an insulating material, such as one or a combination of silicon oxide, silicon nitride, and a high-k insulating material, and may be other suitable materials.

The peripheral interconnect layer 130 may be coupled with the array interconnect layer 290 such that the semiconductor structure 200 and the peripheral device 100 may be coupled. Specifically, since the peripheral interconnect layer 130 is coupled to the array interconnect layer 290, peripheral circuits in the peripheral device 100 may be coupled to the memory cell strings in the semiconductor structure 100 to enable transmission of electrical signals between the peripheral circuits and the memory cell strings. In some possible implementations, a bonding interface 500 may be disposed between the peripheral interconnection layer 130 and the array interconnection layer 290, and the peripheral interconnection layer 130 and the array interconnection layer 290 may be bonded and coupled to each other through the bonding interface 500.

In some related art semiconductor structure manufacturing processes, a portion of the gate sacrificial layer 03 is removed through a channel hole to form a sacrificial layer oxide 01, and then a dielectric layer 02 and a channel structure 06 are formed in the channel hole, as shown in fig. 5A. That is, the sacrificial layer oxide 01 is disposed between the dielectric layer 02 and the gate sacrificial layer 03, the dielectric layer 02 is located between the gate insulating layer 05 and the channel structure 06, and the dielectric layer 02 covers the surfaces of the plurality of gate insulating layers 05 on the side close to the channel structure 06. Wherein the material of the dielectric layer 02 includes a material with a high dielectric constant for preventing leakage of electrons in the channel structure 06. Dielectric layer 02 may include alumina (Al)₂O₃) Hafnium oxide (HfO)₂) Tantalum pentoxide (Ta)₂O₅) Titanium dioxide (TiO)₂) Silicon oxynitride (SiO)_xN_y) Or any combination thereof.

The sacrificial layer oxide 01 is disposed between the dielectric layer 02 and the gate sacrificial layer 03, and is used for preventing the dielectric layer 02 from being damaged in the subsequent process of removing the gate sacrificial layer 03, and the sacrificial layer oxide 01 can be removed together in the process of removing the gate sacrificial layer 03. The method for removing the gate sacrificial layer 03 and the sacrificial layer oxide 01 generally adopts a wet etching process. However, in the case of insufficient etching, the sacrificial layer oxide 01' may remain in the gate gap 04, as shown in fig. 5B, which results in a problem of low filling rate of a gate layer formed in the gate gap 04 later, and further results in poor conductivity of the semiconductor structure in the three-dimensional memory.

Based on this, some embodiments of the present disclosure provide a method of fabricating a semiconductor structure. As shown in fig. 6 and 7A, a method for fabricating a semiconductor structure includes: step S10 to step S16.

Step S10: a dielectric stack structure 800 is formed on one side of the substrate 280. The dielectric stack structure 800 includes gate insulating layers 221 and gate sacrificial layers 222 alternately stacked.

As shown in fig. 7A, a dielectric stack structure 800 is fabricated on a substrate 280. The dielectric stack structure 800 includes a plurality of gate insulating layers 221 and gate sacrificial layers 222 alternately stacked. That is, two adjacent gate sacrificial layers 222 are located on both sides of one gate insulating layer 221 in the third direction Z; two adjacent gate insulating layers 221 are located on both sides of one gate sacrificial layer 222 in the third direction Z.

The gate sacrificial layer 222 may include a material having a high etch selectivity ratio with respect to the gate insulating layer 221. In some examples, each gate insulating layer 221 includes a silicon oxide layer, and each gate sacrificial layer 222 includes a silicon nitride layer. That is, a plurality of silicon nitride layers and a plurality of silicon oxide layers may be alternately deposited over the substrate 280. The gate insulating Layer 221 and the gate sacrificial Layer 222 may be formed using one or more thin film Deposition processes including, but not limited to, Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), or any combination thereof. The silicon oxide and the silicon nitride are a material pair with a high etching selectivity ratio, and particularly, the etching selectivity ratio between the silicon oxide and the silicon nitride is more than 10.

Of course, the gate sacrificial layer 222 and the gate insulating layer 221 may also be other material pairs with high etching selectivity, which is only for illustration and not for limitation.

In some examples, the substrate 280 may be a single layer substrate, and the substrate may include a semiconductor material, such as, for example, silicon (Si), germanium (Ge), SiGe semiconductor, compound semiconductor, alloy semiconductor, or the like. In other examples, a single layer substrate may also be made of a non-conductive material such as glass, plastic, or sapphire wafers. In addition, in some other examples, the substrate 280 may also be a composite substrate, specifically, the composite substrate includes a base layer, a first sacrificial layer, and a stop layer, and the dielectric stack structure 800 may be formed on a side of the stop layer away from the first sacrificial layer. Wherein the base layer may comprise amorphous silicon, polycrystalline silicon, single crystal germanium, group III-V compound semiconductor materials, group II-VI compound semiconductor materials, and other suitable semiconductor materials; the base layer may also be made of a non-conductive material such as glass, plastic, or sapphire wafers. The material of the first sacrificial layer may be an insulating material, such as silicon oxide, silicon nitride, or the like. The material of the stop layer may be a semiconductor material, such as a combination of one or more of amorphous, polycrystalline, or single crystal silicon.

It should be noted that, in some embodiments, a step of fabricating the source layer SL is further included, wherein the source layer SL may be fabricated with the substrate 280, and the base 210 including the substrate 280 and the source layer SL is obtained; alternatively, the source layer SL may be fabricated after the substrate is removed, so as to obtain the base 210 of the source layer SL but without the substrate 280, for example, the substrate is removed after the channel structure is fabricated, which is not limited in this disclosure. The substrate 280 is shown in fig. 7A, and the substrate 280 will be omitted in other figures.

Step S11: a trench hole 300 is formed through the dielectric stack structure 800.

As shown in connection with fig. 7B, photolithography techniques may be used to define the trench hole patterns in the photoresist and/or hard mask layers and form trench holes 300 through the dielectric stack structure 800 in the core region by wet etching and/or dry etching. For example, the Etching process may be Deep Reactive Ion Etching (DRIE).

Step S12: a sacrificial material 320 is filled in the trench hole 300.

As shown in fig. 7D, a sacrificial material 320 is filled in the trench hole 300 to maintain the shape and the inner space of the currently fabricated trench hole 300, and to prevent the shape and the inner space of the trench hole 300 from being changed when other structures are subsequently removed and/or formed.

Sacrificial material 320 may be selected to have a high etch selectivity to gate sacrificial layer 222, such as: gate sacrificial layer 222 comprises silicon nitride and sacrificial material 320 comprises polysilicon. In some examples, the material of gate sacrificial layer 222 includes silicon nitride, and the etch ratio between sacrificial material 320 and silicon nitride is greater than 30, for example: the sacrificial material 320 comprises carbon and the etch ratio between carbon and silicon nitride is greater than 30.

Of course, sacrificial material 320 and gate sacrificial layer 222 may be other materials with high etching selectivity, which are only illustrative and not limiting.

Step S13: the gate sacrificial layer 222 is removed and the gate layer 260 is formed to obtain a memory stack structure including the gate insulating layer 221 and the gate layer 260 alternately stacked.

The gate sacrificial layer 222 may be removed by removing the gate sacrificial layer 222 by using a wet etching process. For example: the gate sacrificial layer 222 is etched at the exposed position of the gate sacrificial layer 222 by using an etching solution.

As shown in fig. 7F, after removing the gate sacrificial layer 222, a gate gap 340 is formed where the gate sacrificial layer 222 is originally located, that is, the gate gap 340 is formed between two adjacent gate insulating layers 221. Since the channel hole 300 is filled with the sacrificial material 320, the sacrificial material 320 is connected to the gate insulating layer 221, so that the gate insulating layer 221 can be supported without collapsing and the gate gap 340 can be maintained.

As shown in connection with fig. 7G, the gate layer 260 may be formed by one or more thin film deposition processes including, but not limited to, Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), thermal oxidation, electroplating, electroless plating, or any combination thereof, in the gate gap 340 between two adjacent gate insulating layers 221.

Gate layer 260 comprises a conductive material including, but not limited to, tungsten, cobalt, copper, aluminum, doped silicon, and/or silicide. In some examples, the material of the gate layer 260 is tungsten. The gate layer 260 extends in the first direction X.

After forming the gate electrode layer 260 in the gate gap 340, the memory stack structure 220 in which the gate electrode layer 260 and the gate insulating layer 221 are alternately stacked is obtained. The gate layer 260 occupies the original space of the gate sacrificial layer 222.

Since the dielectric layer 240 is not formed when the gate layer 260 is formed, an additional sacrificial layer oxide is not needed to be added to protect the dielectric layer 240, the problem that the sacrificial layer oxide occupies the inner space of the gate gap 340 due to insufficient etching does not exist, and the filling rate of the gate layer 260 in the gate gap 340 can be improved.

Step S14: the sacrificial material 320 is removed exposing the channel hole 300.

After the gate layer 260 is formed, two adjacent gate insulating layers 221 may be supported by the gate layer 260 to be spaced apart from each other, so that the sacrificial material 320 may be removed.

The sacrificial material 320 may be removed by wet etching and/or dry etching. After removal of the sacrificial material 320, the resulting trench hole 300 produced in step 11 is exposed, as shown in fig. 7H.

Step S15: a dielectric layer 240 is formed within the trench hole 300.

As shown in connection with fig. 7I and 7J, dielectric layer 240 may be formed by one or more thin film deposition processes including, but not limited to, Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), thermal oxidation, electroplating, electroless plating, or any combination thereof. Dielectric layer 240 is in contact with at least gate layer 260.

Dielectric layer 240 may comprise a high dielectric constant material. In the semiconductor industry, high dielectric constants generally have the meaning: the dielectric constant k of the material is higher than that of silicon dioxide, i.e. 3.9. The dielectric constant of the material of the dielectric layer 240 may be 4.0, 4.6, 5.2, 5.5, 6.0, 6.3, 6.7, 7.2, 8.5, 9.1, 9.8, 10.4, etc. The material of the dielectric layer 240 includes, but is not limited to, aluminum oxide (Al)₂O₃) Hafnium oxide (HfO)₂) Tantalum pentoxide (Ta)₂O₅) Titanium dioxide (TiO)₂) Silicon oxynitride (SiO)_xN_y)Or any combination thereof.

The dielectric layer 240 is located between the gate layer 260 and the channel structure 230, and can prevent electrons from leaking from the channel structure 230, thereby improving the reliability of the semiconductor structure 200.

Step S16: a channel structure 230 is formed within the channel hole 300.

As shown in conjunction with fig. 14 to 16, the channel structure 230 may include a channel layer 231, an insulating material 232 located inside the channel layer 231, and a memory function layer 233 located outside the channel layer 231. Specifically, the memory function layer 233 may be formed on the inner wall (inner wall including the side wall and the bottom wall) of the channel hole 300; then, a channel layer 231 is formed on the inner wall of the memory function layer 233; then, the inner wall of the channel layer 231 is filled with an insulating material 232.

Wherein channel structure 230 is located inside dielectric layer 240. After the channel structure 230 is formed, the channel structure 230, and the plurality of gate layers 260 and the gate insulating layer 221 disposed around the channel structure 230 together constitute the semiconductor structure 200. Specifically, a channel structure 230, and a plurality of gate layers 260 and gate insulating layers 221 surrounding the channel structure 230 constitute the memory cell string 400.

The insulating material 232 may play a role of supporting inside the channel layer 231, so as to enhance the structural strength of the storage stack structure 220.

In addition, the preparation method of the semiconductor structure can further comprise the following steps: removing the bottom substrate 280 to expose the portion of the memory function layer 233 extending into the substrate 280; removing portions of the blocking layer 2333, the storage layer 2332, and the tunneling layer 2331 in the storage function layer 233 extending into the substrate 280 to expose the channel layer 231; the source layer SL is formed to cover the bottom of the memory stack 220 and electrically contact the channel layer 231, as shown in fig. 14 to 16.

In summary, in the method for manufacturing a semiconductor structure according to the above embodiment of the present disclosure, the gate layer 260 is manufactured by filling the sacrificial material 320 into the channel hole 300; sacrificial material 320 is removed and dielectric layer 240 is formed within trench hole 300. Because the dielectric layer 240 is not manufactured before the gate layer 260 is manufactured, extra sacrificial layer oxide is not needed to be added to protect the dielectric layer in the process of manufacturing the gate layer 260, the problem that the filling rate of the gate layer 260 is reduced by the residual sacrificial layer oxide can be avoided, the filling rate of the gate layer between the adjacent gate insulating layers is improved, the conductivity of the gate layer is further improved, and the conductivity of a semiconductor structure in the three-dimensional memory is improved.

As shown in fig. 8 and 7C, in some embodiments, prior to step 12, step 17 is also included.

And step 17: using the channel hole 300, a portion of the gate sacrificial layer 222 is removed, forming a groove 310.

That is, inside the channel hole 300, a portion of the gate sacrificial layer 222 near the channel hole 300 is removed, so that a groove 310 is formed at the position of the removed portion of the gate sacrificial layer 222, as shown in fig. 7C. The groove bottom of the groove 310 is the remaining gate sacrificial layer 222, and two groove walls of the groove 310 are two adjacent gate insulating layers 221.

In some examples, portions of gate sacrificial layer 222 may be removed by wet etching.

Step S12 includes: a sacrificial material 320 is filled in the trench hole 300 and the groove 310.

As shown in fig. 7D, a sacrificial material 320 is filled in the trench hole 300 and the groove 310 to maintain the shape and the inner space of the trench hole 300 and the groove 310 that are currently fabricated, and to prevent the shape and the inner space of the trench hole 300 and the groove 310 from being changed when other structures are removed and/or formed later.

Step S14 includes: the sacrificial material 320 is removed exposing the channel hole 300 and the recess 310.

After removal of the sacrificial material 320, the trench hole 300 and the recess 310, which were originally filled with the sacrificial material 320, are exposed, as shown in fig. 7H. The removal method of the sacrificial material 320 is described in detail above, and is not described herein.

Step S15 includes: a dielectric layer 240 filling at least the recess 310 is formed within the trench hole 300.

Dielectric layer 240 fills at least recess 310, e.g., dielectric layer 240 is only within recess 310, as shown in FIG. 7J; also for example, the dielectric layer 240 is located both within the recess 310 and on the inner wall of the channel hole 300, as shown in fig. 7I; and is not limited herein.

In some related art, as shown in fig. 11, a dielectric layer 02 is located between a gate electrode layer 07 and a gate insulating layer 05, and occupies more space between two adjacent gate insulating layers 05, resulting in a low filling ratio of the gate electrode layer 07. Compared with the semiconductor structure manufactured in the embodiment of the disclosure shown in fig. 11, the semiconductor structure manufactured in the embodiment of the disclosure does not occupy the space between the gate insulating layer 221 and the gate layer 260, so that the filling rate of the gate layer 260 between two adjacent gate insulating layers 221 is improved, the conductivity of the gate layer 260 in the semiconductor structure provided in the embodiment of the disclosure can be improved, and further, the performance of the semiconductor structure in the three-dimensional memory is improved.

In addition, the recess 310 is formed by removing a part of the gate sacrificial layer 222, and the dielectric layer 240 is formed in the recess 310 subsequently, so that the dimension of the portion, located in the recess, of the dielectric layer 240 in the first direction X can be increased, the performance of the dielectric layer 240 for preventing electrons in the channel structure 230 from leaking out of the channel structure 230 is improved, and the reliability of the semiconductor structure 200 is improved.

As shown in fig. 9, 7I and 7J, in some embodiments, step S15 includes step S151 and step S152.

Step S151: a dielectric film 600 is formed to cover the inner walls of the recess 310 and the channel hole 300.

Dielectric film 600 can be formed using one or more thin film deposition processes including, but not limited to, Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), thermal oxidation, electroplating, electroless plating, or any combination thereof.

Here, as shown in fig. 7I, the dielectric film 600 includes a first portion 610 facing the groove 310, and a second portion 620 except for the first portion 610. Wherein a surface of the first portion 610 on a side away from the gate layer 260 may form a continuous surface with a surface of the second portion 620 on a side away from the gate layer 260, that is, the first portion 610 includes a first sub-portion 611 located in the groove 310, and a second sub-portion 612 located on a side of the first sub-portion 611 away from the gate layer 260, and a dimension of the second sub-portion 612 in the first direction X is equal to a dimension of the second portion 620 in the first direction X.

Step S152: the portion of the dielectric film 600 covering the inner wall of the channel hole 300 is removed and the portion 241 of the dielectric film 600 located in the groove 310 remains to form the dielectric portion 241 of the dielectric layer 240 within the groove 310.

As shown in fig. 7J, the dielectric film 600 covers the inner wall of the channel hole 300, i.e., the second portion 620 and the second sub-portion 612. The second portion 620 and the second sub-portion 612 may be removed using a wet etch process, thereby leaving the first sub-portion 611 located within the recess, forming the dielectric portion 241.

Specifically, a curing process or the like may be used in the process of forming the dielectric portion 241 on the first sub-portion 611, which is not limited herein.

In the related art, as shown in fig. 10, electrons (trap electrons) are captured by the dielectric layer 02, and the area of the dielectric layer 02 capturing the electrons in fig. 10 is large, and after a plurality of program/erase (P/E) cycles, the number of electrons that tunnel back into the dielectric layer 02 is large, which results in a decrease in the speed of P/E. Meanwhile, the electric field generated in the P/E process may cause the movement of carriers in the dielectric layer 02 (late Migration), and as the extension length of the dielectric layer 02 is long, the carriers may migrate across the memory cell as shown in fig. 10, which may cause a Data Retention word problem.

In the present embodiment, a plurality of dielectric portions 241 spaced apart from each other are formed by removing a portion of the dielectric film 600 covering the inner wall of the channel hole 300 so that the dielectric portion 241 remaining in one groove 310 is separated from the dielectric portions 241 remaining in the other grooves 310. Since the plurality of dielectric portions 241 are provided independently of each other, an area of the dielectric portion 241 for trapping electrons is reduced compared to the dielectric layer 02 in fig. 10. Therefore, after a number of program/erase (P/E) cycles, fewer electrons are reverse tunneled into dielectric portion 241, which has a lower impact on the speed of the P/E and improves the endurance of the semiconductor structure.

In addition, since the plurality of dielectric portions 241 are independently provided from each other, the movement of carriers in the dielectric portions 241 is restricted, and carriers of one memory cell do not migrate to other memory cells, thereby preventing data abnormality and improving the reliability of the semiconductor structure 200.

It should be noted that, in comparison with fig. 11, the present embodiment also increases the filling rate of the gate layer 260 between two adjacent gate insulating layers 221, and can increase the conductivity of the gate layer 260 in the semiconductor structure provided in the embodiment of the present disclosure, so as to improve the performance of the semiconductor structure in the three-dimensional memory.

At least one of the dielectric layer 240, the dielectric film 600, and the dielectric portion 241 includes a material having a dielectric constant greater than 3.9, that is, a high dielectric constant material. The high-k dielectric material is described in detail above and will not be described herein.

As shown in fig. 12A, in some embodiments, step S13 includes: step S131 to step S133.

Step S131: gate spacers 330 are formed through the dielectric stack structure 800.

As shown in fig. 7E, the extending direction of the gate spacer 330 is the first direction X. The gate spacer 330 divides one gate sacrificial layer 222 into a plurality of gate sacrificial lines arranged in the second direction Y. By forming the gate spacer 330, the exposed area of the gate sacrificial layer 222 is increased, facilitating the removal of the gate sacrificial layer 222.

The gate spacer 330 may be formed by a dry etching process or a combination of a dry etching process and a wet etching process. The gate spacer 330 may extend through the dielectric stack structure 800.

Step S132: the gate sacrificial layer 222 is removed by using the gate spacer 330 to form a gate gap 340.

The gate spacer 330 increases the exposed area of the gate sacrificial layer 222, so that the removal rate of the gate sacrificial layer 222 can be increased by removing the remaining gate sacrificial layer 222 through the gate spacer 330.

Illustratively, the gate sacrificial layer 222 may be removed by a wet etching process.

After the gate sacrificial layer 222 is completely removed, only a portion of the sacrificial material 320 is located between two adjacent gate insulating layers 221, and the gate insulating layers 221 are supported by the portion of the sacrificial material 320 to be spaced apart from each other, so as to form a gate gap, as shown in fig. 7F.

Step S133: gate layer 260 is formed within gate gap 340.

As shown in fig. 7G, the gate layer 260 may include a gate conductive layer 261 and a protective layer 262 disposed to surround the gate conductive layer 261.

In some examples, as shown in fig. 12B, step S133 may include: step S1331 and step S1332.

Step S1331: a protective layer 262 is formed within the gate gap 340.

Step S1332: a gate conductive layer 261 is formed within the protective layer 262.

As shown in fig. 7F and 7G, the protection layer 262 may be formed by depositing a protection material on the inner surface of the gate gap 340. The gate conductive layer 261 may be formed by depositing a conductive material on the inner surface of the protection layer 262. Specifically, the inner surface of the gate gap 340 includes the surface of the gate insulating layer 221 and the surface of the sacrificial material 320.

The protective material may be a conductive material, including but not limited to: at least one of a metal (e.g., titanium (Ti), tantalum (Ta), chromium (Cr), tungsten (W), etc.), a metal compound (e.g., titanium nitride (TiNx), tantalum nitride (TaNx), chromium nitride (CrNx), tungsten nitride (WNx), etc.), and a metal alloy (e.g., TiSixNy, TaSixNy, CrSixNy, WSixNy, etc.). In practical cases, the specific material of the protection layer 262 may be determined based on the material of the gate conductive layer 261 to be subsequently fabricated.

The deposition process includes, but is not limited to, Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), thermal oxidation, electroplating, electroless plating, or any combination thereof.

The conductive material of the gate conductive layer 261 includes, but is not limited to, tungsten, cobalt, copper, aluminum, doped silicon, and/or silicide. In some examples, the material of the gate conductive layer 261 is tungsten.

As shown in fig. 7G, the protection layer 262 is positioned between the gate conductive layer 261 and the sacrificial material 320. In addition, the protective layer 262 is also positioned between the gate conductive layer 261 and the gate insulating layer 221.

The protective layer 262 has higher adhesiveness than the gate conductive layer 261, and thus the protective layer 262 surrounds the gate conductive layer 261, which can protect the gate conductive layer 261, and can enhance the connection strength between the gate layer 260 and other structures (the gate insulating layer 221 and/or the dielectric layer 240), thereby enhancing the structural strength of the semiconductor structure 200.

As shown in fig. 13, in some embodiments, step S16 includes: step S161 to step S165.

Step S161: a barrier layer is formed overlying the trench hole inner wall and the dielectric layer.

Step S162: a memory layer is formed overlying the barrier layer.

Step S163: a tunneling layer is formed overlying the memory layer.

Step S164: and forming a channel layer covering the tunneling layer.

Step S165: and filling an insulating material in the channel layer.

A blocking layer 2333, a storage layer 2332, a tunneling layer 2331, and a channel layer 231 are sequentially formed along the inner wall of the channel hole. In some examples, dielectric layers such as silicon oxide, silicon nitride, and silicon oxide are sequentially deposited along the inner walls of the channel holes using one or more thin film deposition processes including, but not limited to, Physical Vapor Deposition (PVD), Chemical Vapor Deposition (CVD), ALD, or any combination thereof, forming the barrier layer 2333, the electrical storage layer 2332, and the tunneling layer 2331.

In some examples, a conformal coating process (such as ALD) may be employed to deposit any of the blocking layer 2333, the storage layer 2332, the tunneling layer 2331, and the channel layer 231 such that any of the blocking layer 2333, the storage layer 2332, the tunneling layer 2331, and the channel layer 231, the thus-fabricated film layers (the blocking layer 2333, the storage layer 2332, the tunneling layer 2331, and the channel layer 231) may be uniform in thickness. In some examples, the thickness of the channel layer 231 may be controlled to be between about 10nm to about 15nm, for example, 9.8nm, 10nm, 11nm, 12.2nm, 13.5nm, 14nm, 14.6nm, 15nm, or 15.3nm, by controlling the deposition rate and/or time.

After the fabrication of the barrier layer 2333, the memory layer 2332, and the tunneling layer 2331 is completed, a layer of semiconductor material, such as polysilicon, may be deposited on the inner walls of the silicon oxide (tunneling layer 2331) using one or more thin film deposition processes, including but not limited to PVD, CVD, ALD, or any combination thereof, to form the channel layer 231.

The material of the blocking layer 2333 may include silicon oxide, silicon nitride, a high dielectric constant material, or a combination thereof. In some examples, barrier layer 2333 can be a single layer dielectric, such as: a silicon oxide layer. In other examples, barrier layer 2333 may be a composite dielectric layer, such as: a silicon nitride layer and an aluminum oxide layer. The material of the memory layer 2332 may include silicon nitride or silicon oxynitride. The material of the tunneling layer 2331 may include silicon oxide, silicon oxynitride, or a combination thereof. In some examples, the tunneling layer 2331 may be a single layer dielectric, such as: a silicon oxide layer. In other examples, the tunneling layer 2331 may be a composite dielectric layer, such as: the silicon nitride layer comprises a first silicon oxide layer, a first silicon oxynitride layer, a second silicon oxynitride layer and a second silicon oxide layer.

After the channel layer 231 is fabricated, the inside of the channel layer 231 may be filled with an insulating material 232. The height of the insulating material 232 in the third direction Z may be equal to the height of the channel layer 231 in the third direction Z. The channel layer 231 may serve as a support to enhance the structural strength of the storage stack structure 220.

In some embodiments, the filled insulating material 232 may also include an air gap inside. The number of air gaps may be one or more. In the case of one air gap, the shape of the air gap may be a long strip. In the case where the air gap is plural, the shape of the air gap may be spherical, and the plural spherical air gaps may be uniformly distributed in the insulating material 232.

By providing an air gap inside the insulating material 232, structural stress generated during the manufacturing or using process of the semiconductor structure 200 can be buffered, and the reliability of the semiconductor structure 200 can be improved.

The disclosed embodiments provide a semiconductor structure. As shown in connection with fig. 14, the semiconductor structure 200 includes: a substrate 210, a storage stack structure 220, a channel structure 230, and a dielectric layer 240. The memory stack structure 220 is located at one side of the substrate 210, and the memory stack structure 220 includes gate insulating layers 221 and gate electrode layers 260 that are alternately stacked. The channel structure 230 penetrates the storage stack structure 220. Dielectric layer 240 is located between gate layer 260 and channel structure 230. The orthographic projection profile of the dielectric layer 240 on the substrate 210 is contiguous with the orthographic projection profile of the gate layer 260 on the substrate 210.

The substrate 210 includes a source layer SL, and a channel structure 230 penetrates the memory stack structure 220. In addition, the base 210 may or may not include a substrate. The disclosed embodiments are not so limited.

The storage stack structure 220 may include a core region CA and a step region SS having a step profile at the step region SS. The storage stack structure 220 includes a plurality of gate insulating layers 221 and gate electrode layers 260 alternately stacked. That is, two adjacent gate electrode layers 260 are located on both sides of one gate insulating layer 221 in the third direction Z; two adjacent gate insulating layers 221 are located on both sides of one gate layer 260 in the third direction Z.

In some examples, gate layer 260 includes a conductive material including, but not limited to, tungsten, cobalt, copper, aluminum, doped silicon, and/or a silicide. The gate insulating layer 221 includes an insulating material including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, or combinations thereof.

The gate electrode layer 260 and the gate insulating layer 221 extend in the first direction X. In the third direction Z, the lowermost gate layer 260 of the multi-layer gate layers 260 is configured as a source-side select gate SGS, the uppermost gate layer 260 of the multi-layer gate layers 260 is configured as a drain-side select gate SGD, and the intermediate gate layer 260 of the multi-layer gate layers 260 is configured as a plurality of word lines WL.

The channel structure 230 penetrates the memory stack structure 220 in a stacking direction (i.e., the third direction Z) of the plurality of gate electrode layers 260 and the plurality of gate insulating layers 221. In some examples, the channel structure 230 may extend into the source layer SL, and a portion of the channel structure 230 extending into the source layer SL is surrounded by the source layer SL. The channel structure 230 is surrounded by the gate electrode layers 260 and the gate insulating layers 221 in the memory stack structure 220 except for the source layer SL. Among them, the portion of the channel structure 230 surrounded by the plurality of gate electrode layers 260 and the plurality of gate insulating layers 221 in the memory stack structure 220 forms a memory cell string 400.

The dielectric layer 240 is located between the channel structure 230 and the storage stack structure 220. One side surface of the dielectric layer 240 in the first direction X is in contact with the channel structure 230. The other side surface of the dielectric layer 240 in the first direction X is at least in contact with the gate layer 260, for example, the dielectric layer 240 is only in contact with the gate layer 260, and for example, the dielectric layer 240 is in contact with both the gate layer 260 and the gate insulating layer 221.

Wherein, the orthographic projection outline of the dielectric layer 240 on the substrate 210 is connected with the orthographic projection outline of the gate layer 260 on the substrate 210. It is to be understood that the dielectric layer 240 is not located on the side of the gate layer 260 in the third direction Z, i.e. the dielectric layer 240 is not located between the gate layer 260 and the gate insulating layer 221.

Dielectric layer 240 may include a plurality of dielectric materials, wherein at least one dielectric material is different from the material of channel structure 230. In other words, dielectric layer 240 may include a material absent from channel structure 230.

Illustratively, the dielectric layer 240 includes a high dielectric constant material. The material of the dielectric layer 240 includes, but is not limited to, aluminum oxide (Al)₂O₃) Hafnium oxide (HfO)₂) Tantalum pentoxide (Ta)₂O₅) Titanium dioxide (TiO)₂) Silicon oxynitride (SiO)_xN_y) Or any combination thereof.

The dielectric layer 240 may be formed by one or more thin film deposition processes including, but not limited to, Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), thermal oxidation, electroplating, electroless plating, or any combination thereof. In some embodiments, ALD may be used. The dielectric layer 240 formed by the ALD process has the advantages of high uniformity and high precision.

The dielectric layer 240 is located between the gate layer 260 and the channel structure 230, and can prevent electrons in the channel structure 230 from leaking, thereby improving the reliability of the semiconductor structure 200.

Compared to the related art shown in fig. 5A, the semiconductor structure provided in the embodiment of the present disclosure can improve the filling rate of the gate layer 260 in the semiconductor structure, improve the conductive performance of the gate layer 260, and further improve the performance of the semiconductor structure 200 in the three-dimensional memory.

As shown in fig. 15, in some embodiments, an orthographic projection of the dielectric layer 240 on the substrate 210 at least partially overlaps with an orthographic projection of the gate insulating layer 221 on the substrate 210.

In this embodiment, the extension length of the gate insulating layer 221 in the first direction X is greater than the extension length of the gate layer 260 in the first direction X. For example, the gate insulating layer 221 protrudes from the end portion of the memory stack structure 220 close to the channel structure 230 compared to the gate layer 260, so that a groove with the gate layer 260 as a bottom wall and the gate insulating layer 221 as a sidewall is formed on the side of the memory stack structure 220 close to the channel structure 230.

Wherein, the outline of the orthographic projection of the dielectric layer 240 on the substrate 210 at least partially overlaps with the orthographic projection of the gate insulating layer 221 on the substrate 210. It is to be understood that the dielectric layer 240 is at least partially located on a side of the gate insulation layer 221 in the third direction Z. For example: dielectric layer 240 is at least partially disposed within the recess.

As shown in fig. 15, at least a portion of the dielectric layer 240 is filled in the groove, so that the dimension of the portion of the dielectric layer 240 corresponding to the groove in the first direction X is larger than the dimension of the portion of the dielectric layer 240 corresponding to the gate insulating layer 221 in the first direction X.

The portion of the dielectric layer 240 corresponding to the recess is located between the channel structure 230 and the gate layer 260, so that the performance of the dielectric layer 240 for preventing electrons from leaking out of the channel structure 230 can be improved, and the reliability of the semiconductor structure 200 can be improved.

As shown in fig. 16, in some embodiments, the dielectric layer 240 includes a plurality of independently disposed dielectric portions 241, and the dielectric portions 241 are embedded between two adjacent gate insulating layers 221.

That is, in the present embodiment, the dielectric layer 240 includes only the dielectric portion 241 located in the groove. The plurality of dielectric portions 241 are separated from each other and independently provided.

The dielectric portion 241 is located between two adjacent gate insulating layers 221. The dimension of one dielectric portion 241 in the third direction Z is equal to the spacing distance between two adjacent gate insulating layers 221 in the third direction Z.

Since the plurality of dielectric portions 241 are provided independently of each other, an area of the dielectric portion 241 for trapping electrons is reduced compared to the dielectric layer 02 in fig. 10. Therefore, after a plurality of program/erase (P/E) cycles, fewer electrons are reverse tunneled into dielectric portion 241, which has a lower impact on the speed of the P/E and improves the endurance of the semiconductor structure.

In addition, compared to fig. 11, the semiconductor structure manufactured in the embodiment of the present disclosure does not occupy the space between the gate insulating layer 221 and the gate layer 260, so that the filling rate of the gate layer 260 between two adjacent gate insulating layers 221 is improved, the conductivity of the gate layer 260 in the semiconductor structure formed in the embodiment of the present disclosure can be improved, and further, the performance of the semiconductor structure in the three-dimensional memory is improved.

In some embodiments, the gate layer 260 includes a gate conductive layer 261, and a protective layer 262 disposed around the gate conductive layer 261. The protective layer 262 is in contact with the dielectric layer 240 and the gate insulating layer 221, respectively.

The protective layer 262 may be a conductive material including, but not limited to: metals (e.g., titanium (Ti), tantalum (Ta), chromium (Cr), tungsten (W), etc.), metal compounds (e.g., titanium nitride (TiN)_x) Tantalum nitride (TaN)_x) Chromium nitride (CrN)_x) Tungsten nitride (WN)_x) Etc.) and metal alloys (e.g., TiSi)_xN_y、TaSi_xN_y、CrSi_xN_y、WSi_xN_yEtc.). In a practical case, the specific material of the protective layer 262 may be determined based on the material of the gate conductive layer 261.

The protective layer 262 has higher viscosity than the gate conductive layer, so that the protective layer 262 surrounds the gate conductive layer, thereby not only protecting the gate conductive layer 261, but also enhancing the connection strength between the gate layer 260 and the gate insulating layer 221 and the dielectric layer 240, and improving the structural strength of the semiconductor structure 200.

In some embodiments, dielectric layer 240 comprises a material having a dielectric constant greater than 3.9. For example: the dielectric constant of the material of the dielectric layer 240 may be 4.0, 4.6, 5.2, 5.5, 6.0, 6.3, 6.7, 7.2, 8.5, 9.1, 9.8, 10.4, etc.

The higher the dielectric constant of the material of the dielectric layer 240, the higher the performance of the dielectric layer 240 in preventing electron leakage in the channel structure 230, and the higher the reliability of the semiconductor structure 200.

In some embodiments, as shown in fig. 14-16, channel structure 230 includes a channel layer 231, an insulating material 232, and a storage function layer 233. The insulating material 232 is located inside the channel layer 231, and the memory function layer 233 is located outside the channel layer 231. The memory function layer 233 includes a tunneling layer 2331, a memory layer 2332, and a blocking layer 2333, which are sequentially distant from the channel layer 231.

The channel layer 231 may include a semiconductor material, for example: may be amorphous silicon, polycrystalline silicon or monocrystalline silicon. The memory function layer 233 is located outside the channel layer 231 and disposed to surround the channel layer 231. The memory functional layer 233 includes a tunneling layer 2331, a memory layer 2332, and a blocking layer 2333. Carriers (electrons or holes) in the channel layer 231 may tunnel through the tunneling layer 2331 into the storage layer 2332, and the storage layer 2332 is used to store the carriers.

The tunneling layer 2331 may be made of silicon oxide, silicon oxynitride, or any combination thereof. In some examples, the tunneling layer 2331 may be a single layer dielectric, such as: a silicon oxide layer. In other examples, the tunneling layer 2331 may be a composite dielectric layer, such as: the silicon nitride layer comprises a first silicon oxide layer, a first silicon oxynitride layer, a second silicon oxynitride layer and a second silicon oxide layer.

The memory layer 2332 may be made of silicon nitride or silicon oxynitride. The material of the barrier layer 2333 may include silicon oxide, silicon nitride, high dielectric constant materials, or combinations thereof.

The material of the barrier layer 2333 may include silicon oxide, silicon oxynitride, or any combination thereof. In some examples, barrier layer 2333 can be a single layer dielectric, such as: a silicon oxide layer. In other examples, barrier layer 2333 may be a composite dielectric layer, such as: a silicon nitride layer and an aluminum oxide layer.

In some examples, the barrier layer 2333, the storage layer 2332, the tunneling layer 2331, and the channel layer 231 may collectively comprise an ONOP (oxide-nitride-oxide-polysilicon) structure.

The insulating material 232 may include silicon oxide, silicon nitride, silicon oxynitride, and the like, which is not limited herein. The insulating material 232 is filled inside the channel layer 231, and can serve as a support. In some examples, an air gap may be further formed inside the insulating material 232, and the air gap can buffer structural stress generated during the manufacturing or using process of the semiconductor structure, thereby improving the reliability of the semiconductor structure.

FIG. 17 is a block diagram of a storage system according to some embodiments. FIG. 18 is a block diagram of memory systems according to further embodiments.

Referring to fig. 17 and 18, some embodiments of the present disclosure also provide a storage system 1000. The memory system 1000 includes a controller 20, and the three-dimensional memory 10 of some embodiments as above, the controller 20 being coupled to the three-dimensional memory 10 to control the three-dimensional memory 10 to store data.

The Storage system 1000 may be integrated into various types of Storage devices, for example, included in the same package (e.g., a Universal Flash Storage (UFS) package or an Embedded multimedia Card (eMMC) package). That is, the storage system 1000 may be applied to and packaged into different types of electronic products, such as a mobile phone (e.g., a cell phone), a desktop computer, a tablet computer, a laptop computer, a server, an in-vehicle device, a game console, a printer, a positioning device, a wearable device, a smart sensor, a mobile power supply, a Virtual Reality (VR) device, an Augmented Reality (AR) device, or any other suitable electronic device having storage therein.

In some embodiments, referring to fig. 17, the memory system 1000 includes a controller 20 and a three-dimensional memory 10, and the memory system 1000 may be integrated into a memory card.

The Memory Card includes any one of a PC Card (PCMCIA), a Compact Flash (CF) Card, a Smart Media (SM) Card, a Memory stick, a Multimedia Card (MMC), a Secure Digital Memory Card (SD), and a UFS.

In other embodiments, referring to fig. 18, the storage system 1000 includes a controller 20 and a plurality of three-dimensional memories 10, and the storage system 1000 is integrated into a Solid State Drive (SSD).

In storage system 1000, in some embodiments, controller 20 is configured for operation in a low duty cycle environment, such as an SD card, CF card, Universal Serial Bus (USB) flash drive, or other media for use in electronic devices such as personal computers, digital cameras, mobile phones, and the like.

In other embodiments, the controller 20 is configured for operation in a high duty cycle environment SSD or eMMC for data storage and enterprise storage arrays of mobile devices such as smart phones, tablets, laptops, and the like.

In some embodiments, the controller 20 may be configured to manage data stored in the three-dimensional memory 10 and communicate with an external device (e.g., a host). In some embodiments, the controller 20 may also be configured to control operations of the three-dimensional memory 10, such as read, erase, and program operations. In some embodiments, the controller 20 may be further configured to manage various functions with respect to data stored or to be stored in the three-dimensional memory 10, including at least one of bad block management, garbage collection, logical to physical address translation, wear leveling. In some embodiments, the controller, 20 is further configured to process error correction codes with respect to data read from the three-dimensional memory 10 or written to the three-dimensional memory 10.

Of course, the controller 20 may also perform any other suitable functions, such as formatting the three-dimensional memory 10; for example, the controller 20 may communicate with an external device (e.g., a host) via at least one of various interface protocols.

It should be noted that the interface protocol includes at least one of a USB protocol, an MMC protocol, a Peripheral Component Interconnect (PCI) protocol, a PCI express (PCI-E) protocol, an Advanced Technology Attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a Small Computer System Interface (SCSI) protocol, an Enhanced Small Disk Interface (ESDI) protocol, an Integrated Drive Electronics (IDE) protocol, and a Firewire protocol.

Some embodiments of the present disclosure also provide an electronic device. The electronic device may be any one of a mobile phone, a desktop computer, a tablet computer, a notebook computer, a server, an in-vehicle device, a wearable device (e.g., a smart watch, a smart bracelet, smart glasses, etc.), a mobile power supply, a game machine, a digital multimedia player, and the like.

The electronic device may include the storage system 1000 described above, and may further include at least one of a Central Processing Unit (CPU), a cache (cache), and the like.

The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.

Claims

1. A method for fabricating a semiconductor structure, comprising:

forming a dielectric stack structure on one side of a substrate, the dielectric stack structure including gate insulating layers and gate sacrificial layers that are alternately stacked;

forming a channel hole through the dielectric stack structure;

filling a sacrificial material in the channel hole;

removing the gate sacrificial layer and forming a gate layer to obtain a storage stack structure comprising alternately stacked gate insulating layers and gate layers;

removing the sacrificial material to expose the channel hole;

forming a dielectric layer in the channel hole; and the number of the first and second groups,

and forming a channel structure in the channel hole.

2. The method for preparing a semiconductor device according to claim 1, further comprising, before filling the sacrificial material into the trench hole:

removing part of the grid sacrificial layer by using the channel hole to form a groove;

the filling of the sacrificial material in the trench hole comprises:

filling sacrificial materials in the channel holes and the grooves;

the removing the sacrificial material to expose the channel hole, comprising:

removing the sacrificial material to expose the channel hole and the groove;

the forming a dielectric layer in the channel hole comprises:

and forming a dielectric layer at least filling the groove in the channel hole.

3. The method according to claim 2, wherein the forming a dielectric layer in the trench hole at least filling the recess comprises:

forming a dielectric film covering the groove and the inner wall of the channel hole;

and removing the part of the dielectric film covering the inner wall of the channel hole, and reserving the part of the dielectric film positioned in the groove so as to form a dielectric part of the dielectric layer in the groove.

4. The method according to any one of claims 1 to 3, wherein the removing the gate sacrificial layer and forming a gate layer comprises:

forming gate spacers through the dielectric stack structure;

removing the grid sacrificial layer by using the grid isolation groove to form a grid gap;

and forming a gate layer in the gate gap.

5. The method of claim 4, wherein the forming a gate layer in the gate gap comprises:

forming a protective layer in the grid gap;

forming a gate conductive layer in the protective layer;

wherein the protective layer is located between the sacrificial material and the gate conductive layer.

6. The method according to any one of claims 1 to 3, wherein forming a trench structure in the trench hole comprises:

forming a barrier layer covering the inner wall of the channel hole and the dielectric layer;

forming a storage layer covering the barrier layer;

forming a tunneling layer covering the storage layer;

forming a channel layer covering the tunneling layer; and the number of the first and second groups,

and filling an insulating material in the channel layer.

7. The preparation method according to any one of claims 1 to 3, wherein the material of the gate sacrificial layer comprises silicon nitride, and the etching ratio between the sacrificial material and the silicon nitride is greater than 30.

8. The production method according to any one of claims 1 to 3, wherein at least one of the dielectric layer, the dielectric film, and the dielectric portion comprises a material having a dielectric constant of more than 3.9.

9. A semiconductor structure, comprising:

a substrate;

a storage stack structure on one side of the substrate, the storage stack structure including gate insulating layers and gate electrode layers alternately stacked;

a channel structure extending through the storage stack structure; and (c) a second step of,

a dielectric layer between the gate layer and the channel structure; and the orthographic projection outline of the dielectric layer on the substrate is connected with the orthographic projection outline of the gate layer on the substrate.

10. The semiconductor structure of claim 9, wherein an orthographic projection of the dielectric layer on the substrate at least partially overlaps an orthographic projection of the gate insulating layer on the substrate.

11. The semiconductor structure of claim 10, wherein the dielectric layer comprises a plurality of independently disposed dielectric portions, the dielectric portions being interposed between two adjacent gate insulating layers.

12. The semiconductor structure according to any one of claims 9 to 11, wherein the gate layer comprises a gate conductive layer and a protective layer provided so as to surround the gate conductive layer;

the protective layer is in contact with the dielectric layer and the gate insulating layer, respectively.

13. The semiconductor structure of any of claims 9-11, wherein the dielectric layer comprises a material having a dielectric constant greater than 3.9.

14. The semiconductor structure of any of claims 9-11, wherein the channel structure comprises:

a channel layer;

an insulating material located inside the channel layer; and the number of the first and second groups,

the memory function layer is positioned on the outer side of the channel layer and comprises a tunneling layer, a memory layer and a blocking layer which are far away from the channel layer;

wherein the barrier layer is in contact with the dielectric layer.

15. A three-dimensional memory, comprising:

a semiconductor structure as claimed in any one of claims 9 to 14;

a peripheral device electrically connected to the semiconductor structure.

16. A storage system, comprising:

a three-dimensional memory, the three-dimensional memory of claim 15;

a controller coupled to the three-dimensional memory to control the three-dimensional memory to store data.

17. An electronic device, comprising:

the storage system of claim 16.