CN114678376A - Semiconductor structure, preparation method thereof and three-dimensional memory - Google Patents

Abstract

The disclosure provides a semiconductor structure and a preparation method thereof, a three-dimensional memory, a storage system and electronic equipment, relates to the technical field of semiconductor chips, and aims to solve the problem that the conductivity of the semiconductor structure is poor. A method of fabricating a semiconductor structure, comprising: a dielectric stack structure including gate insulating layers and gate sacrificial layers alternately stacked is formed at one side of a substrate. A channel hole is formed through the dielectric stack structure. And filling a sacrificial material in the channel hole. And removing the gate sacrificial layer and forming a gate layer to obtain a storage stack structure comprising alternately stacked gate insulating layers and gate layers. Removing the sacrificial material to expose the channel hole. A dielectric layer is formed within the channel hole. And forming a channel structure in the channel hole. The semiconductor structure is applied to a three-dimensional memory to realize reading and writing operations of data.

Description

Semiconductor structure and preparation method thereof, and three-dimensional memory

technical field

The present disclosure relates to the technical field of semiconductor chips, and in particular, to a semiconductor structure and a preparation method thereof, a three-dimensional memory, a storage system, and an electronic device.

Background technique

As the feature size of the memory cell approaches the lower process limit, planar processes and fabrication techniques become challenging and costly, causing the storage density of 2D or planar NAND flash memory to approach the upper limit.

To overcome the limitations imposed by 2D or planar NAND flash memory, the industry has developed memories with a three-dimensional structure (3D NAND), which increases storage density by arranging memory cells three-dimensionally on a substrate.

In the related art, some semiconductor structures in three-dimensional memories have poor electrical conductivity.

SUMMARY OF THE INVENTION

Embodiments of the present disclosure provide a semiconductor structure, a method for fabricating the same, and a three-dimensional memory, aiming to solve the problem of poor electrical conductivity of the semiconductor structure in the three-dimensional memory.

In order to achieve the above object, the embodiments of the present disclosure adopt the following technical solutions:

In one aspect, a method for fabricating a semiconductor structure is provided. The preparation method includes: forming a dielectric stack structure on one side of a substrate, the dielectric stack structure including alternately stacked gate insulating layers and gate sacrificial layers. A channel hole is formed through the dielectric stack structure. A sacrificial material is filled in the channel hole. The gate sacrificial layer is removed and a gate layer is formed to obtain a memory stack structure including alternately stacked gate insulating layers and gate layers. The sacrificial material is removed, exposing the channel hole. A dielectric layer is formed within the channel hole. A channel structure is formed in the channel hole.

In the method for preparing a semiconductor structure provided by the above embodiments of the present disclosure, a gate layer is fabricated by first filling a channel hole with a sacrificial material; then, the sacrificial material is removed, and a dielectric layer is fabricated in the channel hole. Since the dielectric layer is not formed before the gate layer is formed, there is no need to add an additional sacrificial oxide layer to protect the dielectric layer during the production of the gate layer, and at the same time, the gate layer between adjacent gate insulating layers can be increased. The filling rate improves the conductivity of the gate layer, thereby improving the conductivity of the semiconductor structure in the three-dimensional memory.

In some embodiments, before filling the channel hole with the sacrificial material, the method further includes: using the channel hole to remove part of the gate sacrificial layer to form a groove. The filling of the channel hole with the sacrificial material includes: filling the channel hole and the groove with the sacrificial material. The removing the sacrificial material to expose the channel hole includes: removing the sacrificial material to expose the channel hole and the groove. The forming a dielectric layer in the channel hole includes: forming a dielectric layer in the channel hole that fills at least the groove.

In some embodiments, the forming a dielectric layer filling at least the groove in the channel hole includes: forming a dielectric film covering the groove and the inner wall of the channel hole; removing the dielectric film A portion of the inner wall of the channel hole is covered in the duct hole, and a portion of the dielectric film located in the groove is reserved, so as to form a dielectric portion of the dielectric layer in the groove.

In some embodiments, the removing the gate sacrificial layer and forming the gate layer includes: forming a gate spacer through the dielectric stack structure; and removing the gate sacrificial using the gate spacer layer to form a gate gap; and a gate layer is formed in the gate gap.

In some embodiments, the forming a gate layer in the gate gap includes: forming a protective layer in the gate gap; and forming a gate conductive layer in the protective layer. Wherein, the protective layer is located between the sacrificial material and the gate conductive layer.

In some embodiments, forming a channel structure in the channel hole includes: forming a barrier layer covering the inner wall of the channel hole and the dielectric layer; forming a storage layer covering the barrier layer; forming a barrier layer covering the forming a tunnel layer of the storage layer; forming a channel layer covering the tunnel layer; and filling the channel layer with an insulating material.

In some embodiments, the material of the gate sacrificial layer includes silicon nitride, and an etch ratio between the sacrificial material and the silicon nitride is greater than 30.

In some embodiments, at least one of the dielectric layer, the dielectric film, and the dielectric portion includes a material with a dielectric constant greater than 3.9.

In yet another aspect, a semiconductor structure is provided. The semiconductor structure includes a substrate, a memory stack structure, a channel structure, and a dielectric layer. A memory stack structure is located on one side of the substrate, and the memory stack structure includes alternately stacked gate insulating layers and gate layers. A channel structure penetrates the memory stack structure. A dielectric layer is located between the gate layer and the channel structure; the contour of the orthographic projection of the dielectric layer on the substrate is in contact with the contour of the orthographic projection of the gate layer on the substrate .

In some embodiments, the orthographic projection of the dielectric layer on the substrate at least partially overlaps the orthographic projection of the gate insulating layer on the substrate.

In some embodiments, the dielectric layer includes a plurality of independently disposed dielectric parts, and the dielectric parts are embedded between two adjacent gate insulating layers.

In some embodiments, the gate layer includes a gate conductive layer, and a protective layer disposed surrounding the gate conductive layer. The protective layer is in contact with the dielectric layer and the gate insulating layer, respectively.

In some embodiments, the dielectric layer includes a material with a dielectric constant greater than 3.9.

In some embodiments, the channel structure includes a channel layer, an insulating material, and a memory function layer. The insulating material is located inside the channel layer, and the memory function layer is located outside the channel layer. The storage functional layer includes a tunneling layer, a storage layer and a barrier layer away from the channel layer; wherein the barrier layer is in contact with the dielectric layer.

In yet another aspect, a three-dimensional memory is provided. The three-dimensional memory includes a semiconductor structure as described in some embodiments above, and a peripheral device electrically connected to the semiconductor structure.

In yet another aspect, a storage system is provided, comprising: a three-dimensional memory as described above, and a controller coupled to the three-dimensional memory to control the three-dimensional memory to store data.

In yet another aspect, an electronic device is provided, characterized in that it includes the storage system as described above.

It is understandable that the beneficial effects of the semiconductor structure, three-dimensional memory, storage system and electronic device provided by the above-mentioned embodiments of the present disclosure can refer to the beneficial effects of the semiconductor structure above, which will not be repeated here.

Description of drawings

In order to illustrate the technical solutions in the present disclosure more clearly, the following briefly introduces the accompanying drawings that need to be used in some embodiments of the present disclosure. Obviously, the accompanying drawings in the following description are only the appendixes of some embodiments of the present disclosure. For those of ordinary skill in the art, other drawings can also be obtained from these drawings. In addition, the accompanying drawings in the following description may be regarded as schematic diagrams, and are not intended to limit the actual size of the product involved in the embodiments of the present disclosure, the actual flow of the method, the actual timing of signals, and the like.

FIG. 1 is a perspective structural diagram of a three-dimensional memory according to some embodiments;

2 is a cross-sectional view of a three-dimensional memory according to some embodiments;

Fig. 3 is a cross-sectional view of a memory cell string along section line AA' in the three-dimensional memory shown in Fig. 1;

4 is an equivalent circuit diagram of a memory cell string;

5A is a structural diagram of a semiconductor structure in accordance with some embodiments;

5B is a structural diagram of the semiconductor structure of FIG. 5A in a fabrication stage;

6 is a flow chart of fabrication of a semiconductor structure in accordance with some embodiments;

7A-7J are structural diagrams of semiconductor structures at different fabrication stages according to some embodiments;

8 is a flow diagram of the fabrication of a semiconductor structure according to some embodiments;

9 is a flow chart of fabrication of a semiconductor structure according to some embodiments;

10 is a structural diagram of a semiconductor structure in accordance with some embodiments;

11 is a structural diagram of a semiconductor structure in accordance with some embodiments;

12A is a flow chart of fabrication of a semiconductor structure in accordance with some embodiments;

12B is a flow chart of the fabrication of a semiconductor structure according to some embodiments;

13 is a flow chart of fabrication of a semiconductor structure in accordance with some embodiments;

14 is a structural diagram of a semiconductor structure in accordance with some embodiments;

15 is a structural diagram of a semiconductor structure in accordance with some embodiments;

16 is a structural diagram of a semiconductor structure in accordance with some embodiments;

17 is a block diagram of a storage system in accordance with some embodiments;

18 is a block diagram of a storage system according to other embodiments.

Detailed ways

The technical solutions in some embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, but not all of the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments provided by the present disclosure fall within the protection scope of the present disclosure.

In the description of the present disclosure, it should be understood that the terms "center", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", The orientation or positional relationship indicated by "top", "bottom", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present disclosure and simplifying the description, rather than indicating or implying References to devices or elements must have, be constructed, and operate in a particular orientation and are therefore not to be construed as limitations of the present disclosure.

Throughout the specification and claims, the term "comprising" is to be interpreted in an open, inclusive sense, ie, "including, but not limited to," unless the context requires otherwise. In the description of the specification, the terms "one embodiment," "some embodiments," "exemplary embodiment," "exemplarily" or "some examples" and the like are intended to indicate specific features associated with the embodiment or example , structure, material or characteristic are included in at least one embodiment or example of the present disclosure. The schematic representations of the above terms are not necessarily referring to the same embodiment or example. Furthermore, the particular features, structures, materials or characteristics described may be included in any suitable manner in any one or more embodiments or examples.

Hereinafter, the terms "first" and "second" are only used for descriptive purposes, and should not be construed as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Thus, a feature defined as "first" or "second" may expressly or implicitly include one or more of that feature. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

In describing some embodiments, the expressions "coupled" and "connected" and their derivatives may be used. For example, the term "connected" may be used in describing some embodiments to indicate that two or more components are in direct physical or electrical contact with each other. As another example, the term "coupled" may be used in describing some embodiments to indicate that two or more components are in direct physical or electrical contact. However, the term "coupled" may also mean that two or more components are not in direct contact with each other, but yet still co-operate or interact with each other. The embodiments disclosed herein are not necessarily limited by the content herein.

"At least one of A, B, and C" has the same meaning as "at least one of A, B, or C", and both include the following combinations of A, B, and C: A only, B only, C only, A and B , A and C, B and C, and A, B, and C.

"A and/or B" includes the following three combinations: A only, B only, and a combination of A and B.

The use of "adapted to" or "configured to" herein means open and inclusive language that does not preclude devices adapted or configured to perform additional tasks or steps.

Additionally, the use of "based on" is meant to be open and inclusive, as a process, step, calculation or other action "based on" one or more of the stated conditions or values may in practice be based on additional conditions or beyond the stated values.

As used herein, "about", "approximately" or "approximately" includes the stated value as well as the average value within an acceptable range of deviation from the specified value, as described by one of ordinary skill in the art Determined taking into account the measurement in question and the errors associated with the measurement of a particular quantity (ie, limitations of the measurement system).

In the context of this disclosure, the meanings of "on", "over", and "over" should be interpreted in the broadest possible manner, such that "on" does not only mean "directly on something" ", but also "on" with intervening features or layers, and "over" or "over" means not only "over" or "over" something, but also without intervening The meaning of a feature or layer being "over" or "over" something (ie, directly on something).

Exemplary embodiments are described herein with reference to cross-sectional and/or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and regions are exaggerated for clarity. Accordingly, variations from the shapes of the drawings due to, for example, manufacturing techniques and/or tolerances, are contemplated. Thus, example embodiments should not be construed as limited to the shapes of the regions shown herein, but to include deviations in shapes due, for example, to manufacturing. For example, an etched area shown as a rectangle will typically have curved features. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of example embodiments.

As used herein, the term "substrate" refers to a material upon which subsequent layers of material may be added. The substrate itself can be patterned. The material added to the substrate may be patterned or may remain unpatterned. Additionally, the substrate may include various semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, and the like. Alternatively, the substrate may be made of a non-conductive material such as glass, plastic or sapphire wafer.

The term "three-dimensional memory" refers to strings of memory cell transistors (referred to herein as "memory cells") arranged in an array on the main surface of a substrate or source layer and extending in a direction perpendicular to the substrate or source layer. string", such as a string of NAND memory cells), a semiconductor device formed. As used herein, the term "vertically/vertically" means nominally perpendicular to a major surface (ie, lateral surface) of the substrate or source layer.

1 is a schematic three-dimensional structure diagram of a three-dimensional memory provided by some embodiments of the present disclosure, FIG. 2 is a cross-sectional view of the three-dimensional memory, FIG. 3 is a cross-sectional view of a memory cell string of the three-dimensional memory in FIG. 1 along the section line AA′, and FIG. 4 is a The equivalent circuit diagram of the memory cell string in FIG. 3 .

It should be noted that, in FIGS. 1 and 2 , the three-dimensional memory 10 extends in the X-Y plane, and the first direction X and the second direction Y are, for example, two directions in the plane where the semiconductor structure 200 is located (eg, the plane where the source layer SL is located). orthogonal directions: the first direction X is, for example, the extension direction of the word line WL, and the second direction Y is, for example, the extension direction of the bit line BL. The third direction Z is perpendicular to the plane where the semiconductor structure 200 is located, that is, perpendicular to the X-Y plane.

As used in this disclosure, whether a feature (eg, a layer, structure, or device) is "on," "over," or "under" another feature (eg, a layer, structure, or device) of a semiconductor device (eg, a three-dimensional memory), is determined in the third direction Z relative to the substrate or source layer of the semiconductor device when the substrate or source layer is located in the third direction Z in the lowest plane of the semiconductor device. Throughout this disclosure, the same concepts are applied to describe spatial relationships.

Among them, in order to show the structure of the device more clearly, in FIG. 2, the view of the array area CA and the view of the step area SS are shown, the view of the array area CA is based on the left coordinate system, and the view of the step area SS is based on the right side The coordinate system, that is, the view of the array area CA shows the cross-sectional structure along the Y direction, and the view of the stepped area SS shows the cross-sectional structure along the X direction.

Referring to FIGS. 1 and 2 , some embodiments of the present disclosure provide a three-dimensional memory 10 . Three-dimensional memory 10 may include semiconductor structure 200 . The semiconductor structure 200 may include a source layer SL, and a storage function structure 270 . As shown in FIG. 2 , the three-dimensional memory 10 may further include peripheral devices 100 coupled to the semiconductor structure 200 . The peripheral device 100 may be disposed on a side of the memory function structure 270 away from the source layer SL.

The source layer SL may include semiconductor materials, such as single crystal silicon, single crystal germanium, group III-V compound semiconductor materials, group II-VI compound semiconductor materials, and other suitable semiconductor materials. The source layer SL may be partially or fully doped. Exemplarily, the source layer SL may include a doped region doped with a p-type dopant. The source layer SL may also include a non-doped region.

The semiconductor structure 200 may include memory cell transistor strings (referred to herein as "memory cell strings", eg, NAND memory cell strings) 400 arranged in an array. The source layer SL may be coupled with source terminals of the plurality of memory cell strings 400 .

Specifically, referring to FIGS. 3 and 4 , the memory cell string 400 may include a plurality of transistors T (eg, T1 to T6 in FIG. 4 ), and one transistor T (eg, one of T1 to T6 ) may be configured as one memory cell , these transistors T are connected together to form a memory cell string with a plurality of memory cells. A transistor T (eg, each transistor T) may be formed by the semiconductor channel 241 and a gate line G surrounding the semiconductor channel 241 . Wherein, the gate line G is configured to control the conduction state of the transistor.

It should be noted that the numbers of transistors in FIGS. 1 to 4 are only illustrative, and the memory cell string of the three-dimensional memory provided by the embodiments of the present disclosure may also include other numbers of transistors, such as 4, 16, 32, and 64.

Further, along the third direction Z, the lowermost gate line among the plurality of gate lines G (for example, the gate line closest to the source layer SL among the plurality of gate lines G) is configured as a source terminal selection gate SGS, and the source terminal The select gate SGS is configured to control the conduction state of the transistor T6 and thus control the conduction state of the source channel in the memory cell string 400 . The uppermost gate line among the plurality of gate lines G (for example, the gate line farthest from the source layer SL among the plurality of gate lines G) is configured as a drain selection gate SGD, and the drain selection gate SGD is configured as a control transistor T1 to control the conduction state of the drain channel in the memory cell string 400 . A gate line located in the middle among the plurality of gate lines G may be configured as a plurality of word lines WL, for example, including a word line WL0, a word line WL1, a word line WL2, and a word line WL3. By writing different voltages on the word line WL, data writing, reading, and erasing of each memory cell (eg, transistor T) in the memory cell string 400 can be accomplished.

Continuing to refer to FIGS. 1 and 2 , in some embodiments, the semiconductor structure 200 may further include an array interconnect layer 290 . The array interconnect layer 290 may be coupled with the memory cell strings 400 . The array interconnect layer 290 may include drain terminals (ie, bit lines BL) of the memory cell strings 400 , and the drain terminals may be coupled with semiconductor channels of respective transistors T in at least one memory cell string 400 .

The array interconnection layer 290 may include one or more first interlayer insulating layers 292, and may also include a plurality of contacts insulated from each other by these first interlayer insulating layers 292, for example, the contacts include bit line contacts BL-CNT, It is coupled to the bit line BL; the drain selection gate contact SGD-CNT is coupled to the drain selection gate SGD. The array interconnect layer 290 may also include one or more first interconnect conductor layers 291 . The first interconnect conductor layer 291 may include a plurality of connection lines, such as a bit line BL, and word line connection lines WL-CL coupled to the word line WL. The materials of the first interconnection conductor layer 291 and the contacts can be conductive materials, such as tungsten, cobalt, copper, aluminum, and a combination of one or more of metal silicides, or other suitable materials. The material of the first interlayer insulating layer 292 is an insulating material, such as a combination of one or more of silicon oxide, silicon nitride, and high dielectric constant insulating materials, or other suitable materials.

The peripheral device 100 may include peripheral circuits. Peripheral circuits are configured to control and sense the array devices. The peripheral circuits may be any suitable digital, analog, and/or mixed-signal control and sensing circuits for supporting the operation (or operation) of the array devices, including but not limited to page buffers, decoders (eg, row decoders and column decoder), sense amplifiers, drivers (eg word line drivers), charge pumps, current or voltage references, or any active or passive component of a circuit (eg transistors, diodes, resistors or capacitors). Peripheral circuits may also include any other circuits compatible with advanced logic processes, including logic circuits (such as processors and Programmable Logic Devices (PLDs) or memory circuits (such as Static Random-Access Memory) Memory, referred to as SRAM)).

Specifically, in some embodiments, the peripheral device 100 may include a substrate 110 , a transistor 120 disposed on the substrate 110 , and a peripheral interconnect layer 130 disposed on the substrate 110 . The peripheral circuit may include transistor 120 .

The material of the substrate 110 may be monocrystalline silicon, or may be other suitable materials, such as silicon germanium, germanium, or silicon-on-insulator thin film.

The peripheral interconnection layer 130 is coupled to the transistor 120 to transmit electrical signals between the transistor 120 and the peripheral interconnection layer 130 . The peripheral interconnection layer 130 may include one or more second interlayer insulating layers 131 , and may further include one or more second interconnection conductor layers 132 . Different second interconnect conductor layers 132 may be coupled through contacts. The materials of the second interconnection conductor layer 132 and the contacts may be conductive materials, such as one or a combination of tungsten, cobalt, copper, aluminum, and metal silicide, or other suitable materials. The material of the second interlayer insulating layer 131 is an insulating material, such as a combination of one or more of silicon oxide, silicon nitride, and high dielectric constant insulating materials, or other suitable materials.

The peripheral interconnection layer 130 may be coupled with the array interconnection layer 290 such that the semiconductor structure 200 and the peripheral device 100 may be coupled. Specifically, since the peripheral interconnection layer 130 is coupled with the array interconnection layer 290 , the peripheral circuits in the peripheral device 100 can be coupled with the memory cell strings in the semiconductor structure 100 to realize electrical signals between the peripheral circuits and the memory cell strings transmission. In some possible implementations, an adhesive interface 500 may be provided between the peripheral interconnection layer 130 and the array interconnection layer 290 , and through the adhesive interface 500 , the peripheral interconnection layer 130 and the array interconnection layer 290 may be adhered and coupled to each other .

In some related technologies, in the manufacturing process of the semiconductor structure, a channel hole is used to remove part of the gate sacrificial layer 03 to form a sacrificial layer oxide 01, and then a dielectric layer 02 and a channel structure 06 are formed in the channel hole, as shown in Figure 5A shown. That is, the sacrificial oxide 01 is disposed between the dielectric layer 02 and the gate sacrificial layer 03 , the dielectric layer 02 is located between the gate insulating layer 05 and the channel structure 06 , and the dielectric layer 02 covers the plurality of gate insulating layers 05 The surface close to the side of the channel structure 06 . Wherein, the material of the dielectric layer 02 includes a material with a high dielectric constant, which is used to prevent the leakage of electrons in the channel structure 06 . The dielectric layer 02 may include aluminum oxide (Al ₂ O ₃ ), hafnium dioxide (HfO ₂ ), tantalum pentoxide (Ta ₂ O ₅ ), titanium dioxide (TiO ₂ ), silicon oxynitride (SiO _x N _y ), or the like random combination.

The sacrificial layer oxide 01 is disposed between the dielectric layer 02 and the gate sacrificial layer 03 to prevent damage to the dielectric layer 02 during the subsequent removal of the gate sacrificial layer 03, and the process of removing the gate sacrificial layer 03 can be a And remove the sacrificial layer oxide 01. The method of removing the gate sacrificial layer 03 and the sacrificial layer oxide 01 is usually a wet etching process. However, in the case of insufficient etching, the sacrificial layer oxide 01 ′ will remain in the gate gap 04 , as shown in FIG. 5B , resulting in the problem of low filling rate of the gate layer formed in the gate gap 04 subsequently, and further This results in poor electrical conductivity of semiconductor structures in three-dimensional memories.

Based on this, some embodiments of the present disclosure provide a method for fabricating a semiconductor structure. As shown in FIG. 6 and FIG. 7A , the method for fabricating a semiconductor structure includes steps S10 to S16 .

Step S10 : forming a dielectric stack structure 800 on one side of the substrate 280 . The dielectric stack structure 800 includes alternately stacked gate insulating layers 221 and gate sacrificial layers 222 .

As shown in FIG. 7A , the dielectric stack structure 800 is fabricated on the substrate 280 . The dielectric stack structure 800 includes multiple alternately stacked gate insulating layers 221 and gate sacrificial layers 222 . That is, two adjacent gate sacrificial layers 222 are located on both sides of one gate insulating layer 221 in the third direction Z; two adjacent gate insulating layers 221 are located on two sides of one gate sacrificial layer 222 in the third direction Z side.

The gate sacrificial layer 222 may include a material having a high etch selectivity ratio to the gate insulating layer 221 . In some examples, each gate insulating layer 221 includes a silicon oxide layer, and each gate sacrificial layer 222 includes a silicon nitride layer. That is, a plurality of silicon nitride layers and a plurality of silicon oxide layers may be alternately deposited over the substrate 280 . The gate insulating layer 221 and the gate sacrificial layer 222 may be formed using one or more thin film deposition processes, including but not limited to chemical vapor deposition (Chemical Vapor Deposition, CVD), physical vapor deposition (Physical Vapor Deposition, PVD), atomic layer deposition Atomic Layer Deposition (ALD) or any combination thereof. Wherein, silicon oxide and silicon nitride are a material pair with a high etching selectivity ratio. Specifically, the etching selectivity ratio between silicon oxide and silicon nitride is greater than 10.

Of course, the gate sacrificial layer 222 and the gate insulating layer 221 may also be other pairs of materials with high etching selectivity ratio, which are only illustrative and not limiting.

In some examples, the substrate 280 may be a single-layer substrate, and the substrate may include a semiconductor material, for example, a semiconductor material such as silicon (Si), germanium (Ge), SiGe semiconductor, compound semiconductor, alloy semiconductor, etc. . In some other examples, the single-layer substrate can also be made of non-conductive materials such as glass, plastic, or sapphire wafers. In addition, in some other examples, the substrate 280 may also be a composite substrate, specifically, the composite substrate includes a base layer, a first sacrificial layer and a stop layer, and the dielectric stack structure 800 may be formed where the stop layer is far from the first sacrificial layer side. Wherein, the base layer can include amorphous silicon, polycrystalline silicon, single crystal silicon, single crystal germanium, III-V group compound semiconductor materials, II-VI group compound semiconductor materials and other suitable semiconductor materials; the base layer can also be made of materials such as Made of non-conductive materials such as glass, plastic or sapphire wafers. The material of the first sacrificial layer may be an insulating material, such as silicon oxide, silicon nitride, and the like. The material of the stop layer may be a semiconductor material, such as a combination of one or more of amorphous, polycrystalline, or monocrystalline silicon.

It should be noted that, in some embodiments, a subsequent step of fabricating the source layer SL is included, wherein the source layer SL may be fabricated in the presence of the substrate 280 to obtain the substrate 280 and the source layer SL. The source layer SL can also be fabricated after the substrate is removed to obtain the substrate 210 with the source layer SL but without the substrate 280. For example, the substrate is removed after the fabrication of the channel structure is completed. Not limited. Substrate 280 is shown in FIG. 7A and will be omitted in other figures.

Step S11 : forming the channel hole 300 penetrating the dielectric stack structure 800 .

As shown in FIG. 7B, photolithography techniques can be used to define channel hole patterns in the photoresist and/or hard mask layers, and through wet etching and/or dry etching to form a through-dielectric stack structure in the core region 800 of the channel hole 300. For example, the etching process may be Deep Reactive Ion Etching (DRIE).

Step S12 : filling the channel hole 300 with a sacrificial material 320 .

As shown in FIG. 7D , the sacrificial material 320 is filled in the channel hole 300 to maintain the shape and internal space of the currently fabricated channel hole 300 , preventing subsequent removal of other structures and/or formation of other structures. 300 Changes in form and interior space.

The sacrificial material 320 can be selected from a material having a high etching selectivity ratio to the gate sacrificial layer 222, for example, the gate sacrificial layer 222 includes silicon nitride, and the sacrificial material 320 includes polysilicon. In some examples, the material of the gate sacrificial layer 222 includes silicon nitride, and the etching ratio between the sacrificial material 320 and the silicon nitride is greater than 30, for example, the sacrificial material 320 includes carbon, and the etching ratio between the carbon and the silicon nitride is greater than 30. The eclipse ratio is greater than 30.

Of course, the sacrificial material 320 and the gate sacrificial layer 222 may also be other materials with high etching selectivity ratio, and the above is only an example, not a limitation.

Step S13 : removing the gate sacrificial layer 222 and forming a gate layer 260 to obtain a memory stack structure including alternately stacked gate insulating layers 221 and gate layers 260 .

The way to remove the gate sacrificial layer 222 may be to use a wet etching process to remove the gate sacrificial layer 222 . For example, the gate sacrificial layer 222 is etched at the exposed position of the gate sacrificial layer 222 by using an etchant.

As shown in FIG. 7F , after the gate sacrificial layer 222 is removed, a gate gap 340 is formed where the gate sacrificial layer 222 is originally located, that is, a gate gap 340 is formed between two adjacent gate insulating layers 221 . Wherein, since the channel hole 300 is filled with the sacrificial material 320 , the sacrificial material 320 is connected to the gate insulating layer 221 , so as to support the gate insulating layer 221 from collapse and maintain the gate gap 340 .

As shown in FIG. 7G , within the gate gap 340 between two adjacent gate insulating layers 221 , the gate layer 260 may be formed by one or more thin film deposition processes, including but not limited to chemical vapor deposition processes. Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), Thermal Oxidation, Electroplating, Electroless Plating, or any combination thereof.

The gate layer 260 includes a conductive material including, but not limited to, tungsten, cobalt, copper, aluminum, doped silicon, and/or suicide. In some examples, the material of gate layer 260 is tungsten. The gate layer 260 extends along the first direction X.

After the gate layer 260 is formed in the gate gap 340, the memory stack structure 220 in which the gate layer 260 and the gate insulating layer 221 are alternately stacked is obtained. The gate layer 260 occupies the original space of the gate sacrificial layer 222 .

Since the dielectric layer 240 has not yet been formed when the gate layer 260 is formed, there is no need to add an additional sacrificial layer oxide to protect the dielectric layer 240, and there will not be insufficient etching of the sacrificial layer oxide to occupy the inner space of the gate gap 340. However, the filling rate of the gate layer 260 in the gate gap 340 can be improved.

Step S14 : removing the sacrificial material 320 to expose the channel hole 300 .

After the gate layer 260 is formed, the two adjacent gate insulating layers 221 can be supported by the gate layer 260 to achieve mutual spacing, so the sacrificial material 320 can be removed.

The sacrificial material 320 may be removed by wet etching and/or dry etching. After the sacrificial material 320 is removed, the channel hole 300 fabricated in step 11 is exposed, as shown in FIG. 7H .

Step S15 : forming the dielectric layer 240 in the channel hole 300 .

7I and 7J, the dielectric layer 240 may be formed by one or more thin film deposition processes, including but not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), thermal Oxidation, electroplating, electroless plating, or any combination thereof. The dielectric layer 240 is in contact with at least the gate layer 260 .

The dielectric layer 240 may include a high dielectric constant material. In the semiconductor industry, high dielectric constant usually means that the dielectric constant k of a material is higher than that of silicon dioxide, which is 3.9. The dielectric constant of the material of the dielectric layer 240 may be 4.0, 4.6, 5.2, 5.5, 6.0, 6.3, 6.7, 7.2, 8.5, 9.1, 9.8, 10.4, and the like. Materials of the dielectric layer 240 include, but are not limited to: aluminum oxide (Al ₂ O ₃ ), hafnium dioxide (HfO ₂ ), tantalum pentoxide (Ta ₂ O ₅ ), titanium dioxide (TiO ₂ ), silicon oxynitride (SiO _x N _y) or any combination thereof.

The dielectric layer 240 is located between the gate layer 260 and the channel structure 230 , which can prevent electron leakage of the channel structure 230 and improve the reliability of the semiconductor structure 200 .

Step S16 : forming the channel structure 230 in the channel hole 300 .

14 to 16 , the channel structure 230 may include a channel layer 231 , an insulating material 232 located inside the channel layer 231 , and a memory function layer 233 located outside the channel layer 231 . Specifically, the storage function layer 233 may be first formed on the inner wall of the channel hole 300 (the inner wall includes the sidewall and the bottom wall); then, the channel layer 231 may be formed on the inner wall of the storage function layer 233; The inner wall of the channel layer 231 is filled with an insulating material 232 .

The channel structure 230 is located inside the dielectric layer 240 . After the channel structure 230 is formed, the channel structure 230 , the plurality of gate layers 260 and the gate insulating layers 221 disposed surrounding the channel structure 230 together form the semiconductor structure 200 . Specifically, a channel structure 230 , a plurality of gate layers 260 and gate insulating layers 221 surrounding the channel structure 230 constitute a memory cell string 400 .

The insulating material 232 can play a supporting role on the inner side of the channel layer 231 to improve the structural strength of the memory stack structure 220 .

In addition, the preparation method of the semiconductor structure may further include the following steps: removing the bottom substrate 280 to expose the portion where the memory functional layer 233 extends into the substrate 280 ; removing the barrier layer 2333 , the memory layer 2332 and the memory functional layer 233 The tunneling layer 2331 extends into the portion of the substrate 280 to expose the channel layer 231; and then the source layer SL is formed so that the source layer SL covers the bottom of the memory stack structure 220 and is in electrical contact with the channel layer 231, as shown in the figure 14 to 16.

To sum up, in the fabrication method of the semiconductor structure provided by the above-mentioned embodiments of the present disclosure, the gate layer 260 is fabricated by first filling the channel hole 300 with the sacrificial material 320 ; then the sacrificial material 320 is removed, and the A dielectric layer 240 is formed in the channel hole 300 . Since the dielectric layer 240 is not formed before the gate layer 260 is formed, there is no need to add an additional sacrificial layer oxide to protect the dielectric layer during the production of the gate layer 260, and at the same time, the residual sacrificial layer oxide can be prevented from reducing the gate electrode In order to solve the problem of the filling rate of the layer 260, the filling rate of the gate layer between the adjacent gate insulating layers is improved, thereby improving the conductivity of the gate layer, so as to improve the conductivity of the semiconductor structure in the three-dimensional memory.

As shown in FIG. 8 and FIG. 7C , in some embodiments, before step 12 , step 17 is further included.

Step 17: Using the channel hole 300, part of the gate sacrificial layer 222 is removed to form a groove 310.

That is, inside the channel hole 300 , a portion of the gate sacrificial layer 222 close to the channel hole 300 is removed, thereby forming a groove 310 at the position of the removed part of the gate sacrificial layer 222 , as shown in FIG. 7C . The bottom of the groove 310 is the remaining gate sacrificial layer 222 , and the two groove walls of the groove 310 are two adjacent gate insulating layers 221 .

In some examples, portions of the gate sacrificial layer 222 may be removed by wet etching.

Step S12 includes: filling the channel hole 300 and the groove 310 with a sacrificial material 320 .

With reference to FIG. 7D , the sacrificial material 320 is filled in the channel hole 300 and the groove 310 to maintain the shape and internal space of the channel hole 300 and the groove 310 that have been fabricated, preventing subsequent removal of other structures and/or When other structures are formed, the shape and inner space of the channel hole 300 and the groove 310 are changed.

Step S14 includes: removing the sacrificial material 320 to expose the channel hole 300 and the groove 310 .

As shown in FIG. 7H , after the sacrificial material 320 is removed, the channel hole 300 and the groove 310 originally filled with the sacrificial material 320 are exposed. The removal method of the sacrificial material 320 has been described in detail before, and will not be repeated here.

Step S15 includes: forming a dielectric layer 240 filling at least the groove 310 in the channel hole 300 .

The dielectric layer 240 at least fills the groove 310. For example, the dielectric layer 240 is only located in the groove 310, as shown in FIG. 7J; for example, the dielectric layer 240 is located both in the groove 310 and on the inner wall of the channel hole 300, as shown in FIG. 7J. 7I; not limited here.

In some related technologies, as shown in FIG. 11, the dielectric layer 02 is located between the gate layer 07 and the gate insulating layer 05, occupying more space between two adjacent gate insulating layers 05, resulting in the gate The fill rate of layer 07 is low. Compared with FIG. 11 , the semiconductor structure fabricated by the embodiment of the present disclosure does not occupy the space between the gate insulating layer 221 and the gate layer 260 , and the gate layer between two adjacent gate insulating layers 221 is improved. The filling rate of 260 can improve the conductivity of the gate layer 260 in the semiconductor structure provided by the embodiments of the present disclosure, thereby improving the performance of the semiconductor structure in the three-dimensional memory.

In addition, by removing part of the gate sacrificial layer 222 to form the groove 310, and subsequently forming the dielectric layer 240 in the groove 310, the size of the part of the dielectric layer 240 located in the groove in the first direction X can be increased, thereby increasing the dielectric layer 240 prevents electrons in the channel structure 230 from leaking out of the performance of the channel structure 230 and improves the reliability of the semiconductor structure 200 .

As shown in FIG. 9 , FIG. 7I and FIG. 7J , in some embodiments, step S15 includes step S151 and step S152 .

Step S151 : forming a dielectric film 600 covering the groove 310 and the inner wall of the channel hole 300 .

Dielectric film 600 may be formed using one or more thin film deposition processes, including but not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), thermal oxidation, electroplating, electroless plating, or any of these. combination.

Wherein, as shown in FIG. 7I , the dielectric film 600 includes a first portion 610 facing the groove 310 , and a second portion 620 other than the first portion 610 . The surface of the first portion 610 on the side away from the gate layer 260 may form a continuous surface with the surface of the second portion 620 on the side away from the gate layer 260 , that is, the first portion 610 includes the first sub-portion 611 located in the groove 310 , and the second sub-portion 612 located on the side of the first sub-portion 611 away from the gate layer 260 , the size of the second sub-portion 612 in the first direction X is equal to the size of the second sub-portion 620 in the first direction X.

Step S152 : removing the part of the dielectric film 600 covering the inner wall of the channel hole 300 and leaving the part 241 of the dielectric film 600 in the groove 310 to form the dielectric part 241 of the dielectric layer 240 in the groove 310 .

Referring to FIG. 7J , the parts of the dielectric film 600 covering the inner wall of the channel hole 300 , that is, the above-mentioned second part 620 and the second sub-part 612 . The second portion 620 and the second sub-portion 612 may be removed by a wet etching process, thereby leaving the first sub-portion 611 in the groove and forming the dielectric portion 241 .

Specifically, in the process of forming the dielectric portion 241 in the first sub-section 611 , processes such as a curing process may also be used, which is not limited here.

In the related art, as shown in FIG. 10 , the dielectric layer 02 traps electrons. In FIG. 10 , the area of the dielectric layer 02 for trapping electrons is large. The number of reverse tunneling into the dielectric layer 02 is large, which will reduce the speed of P/E. At the same time, the electric field generated in the P/E process will cause the movement of carriers in the dielectric layer 02 (Lateral Migration), and since the extension length of the dielectric layer 02 is long, as shown in FIG. 10 , the carriers will cross the storage Cell migration, causing data retention issues (Data Retention Worse).

In this embodiment, by removing the part of the dielectric film 600 covering the inner wall of the channel hole 300, the dielectric portion 241 remaining in one groove 310 is separated from the dielectric portion 241 remaining in the other grooves 310, forming a multi-layered The dielectric parts 241 are separated from each other. Since the plurality of dielectric parts 241 are arranged independently of each other, compared with the dielectric layer 02 in FIG. 10 , the area of the dielectric part 241 for capturing electrons is reduced. Therefore, after multiple program/erase (P/E) cycles, less electrons reverse tunneling into the dielectric portion 241 , less impact on the speed of P/E, and improved durability of the semiconductor structure.

In addition, since the plurality of dielectric parts 241 are arranged independently of each other, the movement of carriers in the dielectric part 241 is restricted, and the carriers of one memory cell will not migrate to other memory cells, preventing data abnormality and improving the semiconductor structure. 200 reliability.

It should be noted that, compared with FIG. 11 , this embodiment also improves the filling rate of the gate layer 260 between two adjacent gate insulating layers 221 , which can improve the gate in the semiconductor structure provided by the embodiment of the present disclosure. The conductivity of the electrode layer 260 is improved, thereby improving the performance of the semiconductor structure in the three-dimensional memory.

In addition, at least one of the dielectric layer 240 , the dielectric film 600 and the dielectric portion 241 includes a material with a dielectric constant greater than 3.9, ie, a high dielectric constant material. The high dielectric constant material has been described in detail before, and will not be repeated here.

As shown in FIG. 12A , in some embodiments, step S13 includes steps S131 to S133 .

Step S131 : forming the gate spacer 330 penetrating the dielectric stack structure 800 .

Referring to FIG. 7E , the extending direction of the gate spacer 330 is the first direction X. As shown in FIG. The gate spacer 330 divides one gate sacrificial layer 222 into a plurality of gate sacrificial lines arranged along the second direction Y. By forming the gate spacer 330 , the exposed area of the gate sacrificial layer 222 is increased, which facilitates the removal of the gate sacrificial layer 222 .

The gate spacer 330 may be formed by a dry etching process or a combination of the dry etching process and the wet etching process. The gate spacer 330 may extend through the dielectric stack structure 800 .

Step S132 : using the gate spacer 330 to remove the gate sacrificial layer 222 to form a gate gap 340 .

The gate spacer 330 increases the exposed area of the gate sacrificial layer 222 , so that the remaining gate sacrificial layer 222 is removed through the gate spacer 330 , which can improve the removal speed of the gate sacrificial layer 222 .

Exemplarily, the gate sacrificial layer 222 may be removed by a wet etching process.

After all the gate sacrificial layers 222 are removed, there is only a part of the sacrificial material 320 between two adjacent gate insulating layers 221, and the plurality of gate insulating layers 221 are supported by the part of the sacrificial material 320, so as to be spaced apart from each other to form a gate pole gap, as shown in Figure 7F.

Step S133 : forming the gate layer 260 in the gate gap 340 .

As shown in FIG. 7G , the gate layer 260 may include a gate conductive layer 261 and a protective layer 262 disposed surrounding the gate conductive layer 261 .

In some examples, as shown in FIG. 12B , step S133 may include: step S1331 and step S1332.

Step S1331 : forming a protective layer 262 in the gate gap 340 .

Step S1332 : forming a gate conductive layer 261 in the protective layer 262 .

As shown in FIG. 7F and FIG. 7G , the protective layer 262 may be formed by depositing a protective material on the inner surface of the gate gap 340 . The gate conductive layer 261 may be formed by depositing a conductive material on the inner surface of the protective layer 262 . Specifically, the inner surface of the gate gap 340 is formed by including the surface of the gate insulating layer 221 and the surface of the sacrificial material 320 .

The protective material may be a conductive material, including but not limited to: metals (eg, titanium (Ti), tantalum (Ta), chromium (Cr), tungsten (W), etc.), metal compounds (eg, titanium nitride (TiNx), At least one of tantalum nitride (TaNx), chromium nitride (CrNx), tungsten nitride (WNx), etc.) and metal alloys (eg, TiSixNy, TaSixNy, CrSixNy, WSixNy, etc.). In practical situations, the specific material of the protective layer 262 may be determined based on the material of the gate conductive layer 261 to be fabricated subsequently.

The deposition processes described above include, but are not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), thermal oxidation, electroplating, electroless plating, or any combination thereof.

The conductive material of the gate conductive layer 261 includes, but is not limited to, tungsten, cobalt, copper, aluminum, doped silicon and/or silicide. In some examples, the material of the gate conductive layer 261 is tungsten.

As shown in FIG. 7G , the protective layer 262 is located between the gate conductive layer 261 and the sacrificial material 320 . In addition, the protective layer 262 is also located between the gate conductive layer 261 and the gate insulating layer 221 .

The viscosity of the protective layer 262 is higher than that of the gate conductive layer 261, so the protective layer 262 is arranged around the gate conductive layer 261, which can not only protect the gate conductive layer 261, but also strengthen the gate layer 260 and other structures (gate insulating layer 221 and and/or the connection strength between the dielectric layers 240 ) to improve the structural strength of the semiconductor structure 200 .

As shown in FIG. 13 , in some embodiments, step S16 includes steps S161 to S165.

Step S161 : forming a barrier layer covering the inner wall of the channel hole and the dielectric layer.

Step S162: forming a storage layer covering the barrier layer.

Step S163: forming a tunneling layer covering the storage layer.

Step S164: forming a channel layer covering the tunneling layer.

Step S165: Filling the channel layer with insulating material.

A barrier layer 2333 , a storage layer 2332 , a tunnel layer 2331 and a channel layer 231 are sequentially formed along the inner wall of the channel hole. In some examples, layers such as silicon oxide are sequentially deposited along the inner walls of the channel holes using one or more thin film deposition processes including, but not limited to, physical vapor deposition (PVD), chemical vapor deposition (CVD), ALD, or any combination thereof , a silicon nitride layer and a silicon oxide layer to form a barrier layer 2333 , an electrical storage layer 2332 and a tunneling layer 2331 .

In some examples, any of barrier layer 2333 , storage layer 2332 , tunneling layer 2331 , and channel layer 231 may be deposited using a conformal coating process, such as ALD, such that barrier layer 2333 , storage layer 2332 , any one of the tunneling layer 2331 and the channel layer 231 , the film layers (the barrier layer 2333 , the storage layer 2332 , the tunneling layer 2331 and the channel layer 231 ) thus fabricated may have a uniform thickness. In some examples, the thickness of the channel layer 231 can be controlled to be between about 10 nm and about 15 nm, eg, 9.8 nm, 10 nm, 11 nm, 12.2 nm, 13.5 nm, 14 nm, 14.6nm, 15nm or 15.3nm.

After the barrier layer 2333, the storage layer 2332 and the tunneling layer 2331 are fabricated, one or more thin film deposition processes including but not limited to PVD, CVD, ALD or any combination thereof may be used on the silicon oxide (tunneling layer 2331) A layer of semiconductor material (such as polysilicon) is deposited on the inner wall of the channel layer 231 to form the channel layer 231 .

The material of the blocking layer 2333 may include silicon oxide, silicon nitride, high dielectric constant material or a combination thereof. In some examples, the barrier layer 2333 may be a single-layer dielectric, eg, a silicon oxide layer. In other examples, the barrier layer 2333 may be a composite dielectric layer such as a silicon nitride layer and an aluminum oxide layer. The material of the storage layer 2332 may include silicon nitride or silicon oxynitride. The material of the tunneling layer 2331 may include silicon oxide, silicon oxynitride, or a combination thereof. In some examples, the tunneling layer 2331 may be a single-layer dielectric, eg, a silicon oxide layer. In other examples, the tunneling layer 2331 may be a composite dielectric layer such as a first silicon oxide layer, a first silicon oxynitride layer, a second silicon oxynitride layer, and a second silicon dioxide layer.

After the channel layer 231 is fabricated, an insulating material 232 may be filled in the channel layer 231 . The height of the insulating material 232 in the third direction Z may be equal to the height of the channel layer 231 in the third direction Z. The channel layer 231 can play a supporting role and improve the structural strength of the memory stack structure 220 .

In some embodiments, the interior of the filled insulating material 232 may also include air gaps. The number of air gaps may be one or more. In the case where there is one air gap, the shape of the air gap may be an elongated shape. In the case of a plurality of air gaps, the shape of the air gaps may be spherical, and the plurality of spherical air gaps may be uniformly distributed in the insulating material 232 .

By arranging an air gap inside the insulating material 232 , the structural stress generated during the fabrication or use of the semiconductor structure 200 can be buffered, and the reliability of the semiconductor structure 200 can be improved.

Embodiments of the present disclosure provide a semiconductor structure. As shown in FIG. 14 , the semiconductor structure 200 includes: a substrate 210 , a memory stack structure 220 , a channel structure 230 and a dielectric layer 240 . The memory stack structure 220 is located on one side of the substrate 210 , and the memory stack structure 220 includes a gate insulating layer 221 and a gate electrode layer 260 which are alternately stacked. The channel structure 230 penetrates the memory stack structure 220 . The dielectric layer 240 is located between the gate layer 260 and the channel structure 230 . The contour of the orthographic projection of the dielectric layer 240 on the substrate 210 is in contact with the contour of the orthographic projection of the gate layer 260 on the substrate 210 .

The aforementioned substrate 210 includes a source layer SL, and the channel structure 230 penetrates through the memory stack structure 220 . In addition, the base 210 may or may not include a substrate. This embodiment of the present disclosure does not limit this.

The memory stack structure 220 may include a core area CA and a step area SS, where the step area SS has a step topography. The memory stack structure 220 includes a plurality of alternately stacked gate insulating layers 221 and gate layers 260 . That is, two adjacent gate layers 260 are located on both sides of one gate insulating layer 221 in the third direction Z; two adjacent gate insulating layers 221 are located on both sides of one gate layer 260 in the third direction Z.

In some examples, gate layer 260 includes a conductive material including, but not limited to, tungsten, cobalt, copper, aluminum, doped silicon, and/or suicide. The gate insulating layer 221 includes insulating materials, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof.

The gate layer 260 and the gate insulating layer 221 extend along the first direction X. Along the third direction Z, the lowermost gate layer 260 of the multi-layer gate layers 260 is configured as the source selection gate SGS, and the uppermost gate layer 260 of the multi-layer gate layers 260 is configured as the drain terminal For the selection gate SGD, the gate layer 260 in the middle layer among the multi-layer gate layers 260 is configured as a plurality of word lines WL.

The channel structure 230 penetrates the memory stack structure 220 along the stacking direction of the plurality of gate layers 260 and the plurality of gate insulating layers 221 (ie, the third direction Z). In some examples, the channel structure 230 may extend into the source layer SL, and the portion of the channel structure 230 extending into the source layer SL is surrounded by the source layer SL. A portion of the channel structure 230 located outside the source layer SL is surrounded by the plurality of gate layers 260 and the plurality of gate insulating layers 221 in the memory stack structure 220 . The portion of the channel structure 230 surrounded by the plurality of gate layers 260 and the plurality of gate insulating layers 221 in the memory stack structure 220 forms the memory cell string 400 .

The dielectric layer 240 is located between the channel structure 230 and the memory stack structure 220 . One surface of the dielectric layer 240 in the first direction X is in contact with the channel structure 230 . The other side surface of the dielectric layer 240 in the first direction X is at least in contact with the gate layer 260, for example, the dielectric layer 240 is only in contact with the gate layer 260, and for example, the dielectric layer 240 is in contact with both the gate layer 260 and the gate The insulating layer 221 is in contact.

The outline of the orthographic projection of the dielectric layer 240 on the substrate 210 is in contact with the outline of the orthographic projection of the gate layer 260 on the substrate 210 . It can be understood that the dielectric layer 240 is not located on the side of the gate layer 260 in the third direction Z, that is, the dielectric layer 240 is not located between the gate layer 260 and the gate insulating layer 221 .

The dielectric layer 240 may include a variety of dielectric materials, wherein at least one of the dielectric materials is different from the material of the channel structure 230 . In other words, the dielectric layer 240 may include materials that the channel structure 230 does not have.

Illustratively, the dielectric layer 240 includes a high dielectric constant material. Materials of the dielectric layer 240 include, but are not limited to: aluminum oxide (Al ₂ O ₃ ), hafnium dioxide (HfO ₂ ), tantalum pentoxide (Ta ₂ O ₅ ), titanium dioxide (TiO ₂ ), silicon oxynitride (SiO _{x )} N _y ) or any combination thereof.

The dielectric layer 240 may be formed by one or more thin film deposition processes, including but not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), thermal oxidation, electroplating, electroless plating, or any of these. combination. In some embodiments, ALD can be used. The dielectric layer 240 formed by the ALD process has the advantages of high uniformity and high precision.

The dielectric layer 240 is located between the gate layer 260 and the channel structure 230 , which can prevent electron leakage in the channel structure 230 and improve the reliability of the semiconductor structure 200 .

Compared with the related art shown in FIG. 5A, the semiconductor structure provided by the embodiment of the present disclosure can improve the filling rate of the gate layer 260 in the semiconductor structure, improve the conductivity of the gate layer 260, and further improve the semiconductor structure in the three-dimensional memory. Performance of Structure 200.

As shown in FIG. 15 , in some embodiments, the orthographic projection of the dielectric layer 240 on the substrate 210 at least partially overlaps the orthographic projection of the gate insulating layer 221 on the substrate 210 .

In this embodiment, the extension length of the gate insulating layer 221 in the first direction X is greater than the extension length of the gate layer 260 in the first direction X. For example, the gate insulating layer 221 protrudes at the end close to the channel structure 230 compared to the gate layer 260 at the end close to the channel structure 230 , so that the memory stack structure 220 is at the side close to the channel structure 230 . A groove is formed with the gate layer 260 as the bottom wall and the gate insulating layer 221 as the side wall.

The outline of the orthographic projection of the dielectric layer 240 on the substrate 210 at least partially overlaps with the orthographic projection of the gate insulating layer 221 on the substrate 210 . It can be understood that the dielectric layer 240 is at least partially located on one side of the gate insulating layer 221 in the third direction Z. As shown in FIG. For example, the dielectric layer 240 is at least partially located within the aforementioned groove.

In some related technologies, as shown in FIG. 11, the dielectric layer 02 is located between the gate layer 07 and the gate insulating layer 05, occupying more space between two adjacent gate insulating layers 05, resulting in the gate The fill rate of layer 07 is low. Compared with FIG. 11 , the semiconductor structure fabricated by the embodiment of the present disclosure does not occupy the space between the gate insulating layer 221 and the gate layer 260 , and the gate layer between two adjacent gate insulating layers 221 is improved. The filling rate of 260 can improve the conductivity of the gate layer 260 in the semiconductor structure provided by the embodiments of the present disclosure, thereby improving the performance of the semiconductor structure in the three-dimensional memory.

In addition, as shown in FIG. 15 , at least part of the dielectric layer 240 is filled in the above-mentioned groove, so that the dimension of the part of the dielectric layer 240 corresponding to the groove in the first direction X is larger than that of the part of the dielectric layer 240 corresponding to the gate insulating layer 221 Dimensions in the first direction X.

The portion of the dielectric layer 240 corresponding to the groove is located between the channel structure 230 and the gate layer 260 , which can improve the performance of the dielectric layer 240 to prevent electron leakage of the channel structure 230 and improve the reliability of the semiconductor structure 200 .

As shown in FIG. 16 , in some embodiments, the dielectric layer 240 includes a plurality of independently disposed dielectric parts 241 , and the dielectric parts 241 are embedded between two adjacent gate insulating layers 221 .

That is, in this embodiment, the dielectric layer 240 only includes the dielectric portion 241 located in the groove. The plurality of dielectric parts 241 are separated from each other and provided independently.

The dielectric portion 241 is located between two adjacent gate insulating layers 221 . The dimension of one dielectric portion 241 in the third direction Z is equal to the distance between two adjacent gate insulating layers 221 in the third direction Z.

Since the plurality of dielectric parts 241 are arranged independently of each other, compared with the dielectric layer 02 in FIG. 10 , the area of the dielectric part 241 for capturing electrons is reduced. Therefore, after multiple program/erase (P/E) cycles, less electrons reverse tunneling into the dielectric portion 241 , less impact on the speed of P/E, and improved durability of the semiconductor structure.

In addition, since the plurality of dielectric parts 241 are arranged independently of each other, the movement of carriers in the dielectric part 241 is restricted, and the carriers of one memory cell will not migrate to other memory cells, preventing data abnormality and improving the semiconductor structure. 200 reliability.

In addition, compared with FIG. 11 , the semiconductor structure fabricated by the embodiment of the present disclosure does not occupy the space between the gate insulating layer 221 and the gate layer 260 , and the gate between the two adjacent gate insulating layers 221 is improved. The filling rate of the electrode layer 260 can improve the conductivity of the gate layer 260 in the semiconductor structure formed by the embodiments of the present disclosure, thereby improving the performance of the semiconductor structure in the three-dimensional memory.

In some embodiments, the gate layer 260 includes a gate conductive layer 261 and a protective layer 262 disposed surrounding the gate conductive layer 261 . The protective layer 262 is in contact with the dielectric layer 240 and the gate insulating layer 221, respectively.

The protective layer 262 may be a conductive material including, but not limited to, metals (eg, titanium (Ti), tantalum (Ta), chromium (Cr), tungsten (W), etc.), metal compounds (eg, titanium nitride (TiN _{x )} ), tantalum nitride ( _TaNx ), chromium nitride ( _CrNx ), tungsten nitride ( _{WNx )} , etc.) and metal _alloys ( _eg , _TiSixNy , _TaSixNy , _CrSixNy , _WSix at least one of N _y etc.). In practical situations, the specific material of the protective layer 262 may be determined based on the material of the gate conductive layer 261 .

The viscosity of the protective layer 262 is higher than that of the gate conductive layer, so the protective layer 262 is arranged around the gate conductive layer, which can not only protect the gate conductive layer 261 but also strengthen the gap between the gate layer 260 and the gate insulating layer 221 and the dielectric layer 240 The connection strength is increased, and the structural strength of the semiconductor structure 200 is improved.

In some embodiments, the dielectric layer 240 includes a material with a dielectric constant greater than 3.9. For example, the dielectric constant of the material of the dielectric layer 240 may be 4.0, 4.6, 5.2, 5.5, 6.0, 6.3, 6.7, 7.2, 8.5, 9.1, 9.8, 10.4, and so on.

The higher the dielectric constant of the material of the dielectric layer 240 is, the higher the performance of the dielectric layer 240 in preventing electron leakage in the channel structure 230 is, and the higher the reliability of the semiconductor structure 200 is.

In some embodiments, as shown in FIGS. 14 to 16 , the channel structure 230 includes a channel layer 231 , an insulating material 232 and a memory function layer 233 . The insulating material 232 is located inside the channel layer 231 , and the memory function layer 233 is located outside the channel layer 231 . The storage function layer 233 includes a tunnel layer 2331 , a storage layer 2332 and a barrier layer 2333 which are separated from the channel layer 231 in sequence.

The above-mentioned channel layer 231 may comprise a semiconductor material, for example, may be amorphous silicon, polycrystalline silicon or single crystal silicon. The memory functional layer 233 is located outside the channel layer 231 and is provided to surround the channel layer 231 . The storage functional layer 233 includes a tunneling layer 2331 , a storage layer 2332 and a blocking layer 2333 . Carriers (electrons or holes) in the channel layer 231 may be tunneled into the storage layer 2332 through the tunneling layer 2331, and the storage layer 2332 is used to store carriers.

The material of the above-mentioned tunneling layer 2331 may include silicon oxide, silicon oxynitride or any combination thereof. In some examples, the tunneling layer 2331 may be a single-layer dielectric, eg, a silicon oxide layer. In other examples, the tunneling layer 2331 may be a composite dielectric layer such as a first silicon oxide layer, a first silicon oxynitride layer, a second silicon oxynitride layer, and a second silicon dioxide layer.

The material of the above-mentioned storage layer 2332 may include silicon nitride or silicon oxynitride. The material of the above-mentioned barrier layer 2333 may include silicon oxide, silicon nitride, high dielectric constant material, or a combination thereof.

The material of the above-mentioned barrier layer 2333 may include silicon oxide, silicon oxynitride or any combination thereof. In some examples, the barrier layer 2333 may be a single-layer dielectric, eg, a silicon oxide layer. In other examples, the barrier layer 2333 may be a composite dielectric layer such as a silicon nitride layer and an aluminum oxide layer.

In some examples, the blocking layer 2333, the storage layer 2332, the tunneling layer 2331, and the channel layer 231 may collectively form an ONOP (oxide-nitride-oxide-polysilicon) structure.

The above-mentioned insulating material 232 may include silicon oxide, silicon nitride, silicon oxynitride, etc., which is not limited herein. The insulating material 232 is filled inside the channel layer 231 and can play a supporting role. In some examples, an air gap may also be formed inside the insulating material 232, and the air gap can buffer the structural stress generated during the fabrication or use of the semiconductor structure, thereby improving the reliability of the semiconductor structure.

17 is a block diagram of a storage system in accordance with some embodiments. 18 is a block diagram of a storage system according to other embodiments.

Referring to FIGS. 17 and 18 , some embodiments of the present disclosure further provide a storage system 1000 . The storage system 1000 includes a controller 20, which is coupled to the three-dimensional storage 10 to control the three-dimensional storage 10 to store data, and a three-dimensional memory 10 as in some embodiments above.

The storage system 1000 can be integrated into various types of storage devices, for example, including in the same package (for example, Universal Flash Storage (UFS) package or Embedded Multi Media Card (eMMC for short) ) package). That is, the storage system 1000 can be applied to and packaged into different types of electronic products, eg, mobile phones (eg, cell phones), desktop computers, tablets, laptops, servers, in-vehicle devices, game consoles, printers, positioning A device, a wearable device, a smart sensor, a power bank, a Virtual Reality (VR) device, an Augmented Reality (AR) device, or any other suitable electronic device having a memory therein.

In some embodiments, referring to FIG. 17, the storage system 1000 includes the controller 20 and a three-dimensional memory 10, and the storage system 1000 may be integrated into a memory card.

Among them, the memory card includes PC card (PCMCIA, Personal Computer Memory Card International Association), Compact Flash (Compact Flash, referred to as CF) card, Smart Media (Smart Media, referred to as SM) card, memory stick, Multimedia Card (Multimedia Card, MMC for short), Secure Digital Memory Card (SD) card, UFS.

In other embodiments, referring to FIG. 18 , the storage system 1000 includes a controller 20 and a plurality of three-dimensional memories 10 , and the storage system 1000 is integrated into a solid state drive (Solid State Drives, SSD for short).

In storage system 1000, in some embodiments, controller 20 is configured to operate in a low duty cycle environment, eg, SD card, CF card, Universal Serial Bus (USB) flash memory drives or other media used in electronic devices such as personal calculators, digital cameras, mobile phones, etc.

In other embodiments, the controller 20 is configured for operation in a high duty cycle environment SSD or eMMC for data storage and enterprise storage in mobile devices such as smartphones, tablets, laptops, etc. array.

In some embodiments, the controller 20 may be configured to manage data stored in the three-dimensional memory 10 and communicate with an external device (eg, a host). In some embodiments, the controller 20 may also be configured to control operations of the three-dimensional memory 10, such as read, erase, and program operations. In some embodiments, controller 20 may also be configured to manage various functions with respect to data stored or to be stored in three-dimensional memory 10, including bad block management, garbage collection, logical to physical address translation, wear leveling among at least one of. In some embodiments, the controller, 20 is also configured to process error correction codes for data read from or written to the three-dimensional memory 10 .

Of course, the controller 20 may also perform any other suitable function, such as formatting the three-dimensional memory 10; for example, the controller 20 may communicate with an external device (eg, a host) through at least one of various interface protocols.

It should be noted that the interface protocols include USB protocol, MMC protocol, Peripheral Component Interconnect (PCI) protocol, PCI Express (PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small At least one of Small Computer Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Drive Electronics (IDE) protocol, Firewire protocol.

Some embodiments of the present disclosure also provide an electronic device. Electronic devices can be mobile phones, desktop computers, tablet computers, laptop computers, servers, in-vehicle devices, wearable devices (such as smart watches, smart bracelets, smart glasses, etc.), power banks, game consoles, digital multimedia players, etc. either.

The electronic device may include the storage system 1000 described above, and may also include at least one of a central processing unit (CPU) (Central Processing Unit, central processing unit) and a cache (cache).

The above are only specific embodiments of the present invention, but the protection scope of the present invention is not limited to this. Any person skilled in the art who is familiar with the technical scope disclosed by the present invention can easily think of changes or substitutions. should be included within the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims (17)

1. a preparation method of a semiconductor structure, is characterized in that, comprises: forming a dielectric stack structure on one side of the substrate, the dielectric stack structure including alternately stacked gate insulating layers and gate sacrificial layers; forming a channel hole through the dielectric stack structure; filling the channel hole with a sacrificial material; removing the gate sacrificial layer and forming a gate layer to obtain a memory stack structure including alternately stacked gate insulating layers and gate layers; removing the sacrificial material to expose the channel hole; forming a dielectric layer within the channel hole; and, A channel structure is formed in the channel hole. 2 . The preparation method according to claim 1 , wherein before filling the channel hole with a sacrificial material, the method further comprises: 3 . Using the channel hole, part of the gate sacrificial layer is removed to form a groove; The filling of the sacrificial material in the channel hole includes: filling the channel hole and the groove with a sacrificial material; The removing the sacrificial material to expose the channel hole includes: removing the sacrificial material to expose the channel hole and the groove; The forming a dielectric layer in the channel hole includes: A dielectric layer is formed within the channel hole to fill at least the recess. 3 . The preparation method according to claim 2 , wherein the forming a dielectric layer filling at least the groove in the channel hole comprises: 3 . forming a dielectric film covering the groove and the inner wall of the channel hole; A portion of the dielectric film covering the inner wall of the channel hole is removed, and a portion of the dielectric film located in the groove is left to form a dielectric portion of the dielectric layer in the groove. 4 . The preparation method according to claim 1 , wherein the removing the gate sacrificial layer and forming the gate layer comprises: 5 . forming a gate spacer through the dielectric stack structure; Using the gate spacer, removing the gate sacrificial layer to form a gate gap; A gate layer is formed within the gate gap. 5. The preparation method according to claim 4, wherein the forming a gate layer in the gate gap comprises: forming a protective layer within the gate gap; forming a gate conductive layer in the protective layer; Wherein, the protective layer is located between the sacrificial material and the gate conductive layer. 6 . The preparation method according to claim 1 , wherein forming a channel structure in the channel hole comprises: 6 . forming a barrier layer covering the inner wall of the channel hole and the dielectric layer; forming a storage layer overlying the barrier layer; forming a tunneling layer overlying the storage layer; forming a channel layer overlying the tunneling layer; and, An insulating material is filled in the channel layer. 7 . The preparation method according to claim 1 , wherein the material of the gate sacrificial layer comprises silicon nitride, and the etching between the sacrificial material and the silicon nitride ratio greater than 30. 8 . The preparation method according to claim 1 , wherein at least one of the dielectric layer, the dielectric film and the dielectric part comprises a material with a dielectric constant greater than 3.9 . 9. A semiconductor structure, characterized in that it comprises: base; a memory stack structure, located on one side of the substrate, the memory stack structure comprising alternately stacked gate insulating layers and gate layers; a channel structure penetrating the memory stack structure; and, a dielectric layer located between the gate layer and the channel structure; the contour of the orthographic projection of the dielectric layer on the substrate is the same as the contour of the orthographic projection of the gate layer on the substrate catch. 10. The semiconductor structure of claim 9, wherein an orthographic projection of the dielectric layer on the substrate at least partially overlaps an orthographic projection of the gate insulating layer on the substrate. 11 . The semiconductor structure of claim 10 , wherein the dielectric layer comprises a plurality of independently disposed dielectric portions, and the dielectric portions are embedded between two adjacent gate insulating layers. 12 . 12. The semiconductor structure according to any one of claims 9 to 11, wherein the gate layer comprises a gate conductive layer and a protective layer disposed surrounding the gate conductive layer; The protective layer is in contact with the dielectric layer and the gate insulating layer, respectively. 13 . The semiconductor structure of claim 9 , wherein the dielectric layer comprises a material with a dielectric constant greater than 3.9. 14 . 14. The semiconductor structure according to any one of claims 9 to 11, wherein the channel structure comprises: channel layer; an insulating material inside the channel layer; and, a storage function layer located outside the channel layer, the storage function layer comprising a tunneling layer, a storage layer and a barrier layer away from the channel layer; Wherein, the barrier layer is in contact with the dielectric layer. 15. A three-dimensional memory, comprising: a semiconductor structure, which is the semiconductor structure according to any one of claims 9 to 14; A peripheral device is electrically connected to the semiconductor structure. 16. A storage system, comprising: Three-dimensional memory, the three-dimensional memory is the three-dimensional memory as claimed in claim 15; A controller, coupled to the three-dimensional memory, controls the three-dimensional memory to store data. 17. An electronic device, characterized in that, comprising: The storage system of claim 16.

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