CN118215298A

CN118215298A - Semiconductor structure, three-dimensional memory, preparation method of three-dimensional memory and memory system

Info

Publication number: CN118215298A
Application number: CN202211616055.6A
Authority: CN
Inventors: 张坤; 周文犀; 夏志良
Original assignee: Yangtze Memory Technologies Co Ltd
Current assignee: Yangtze Memory Technologies Co Ltd
Priority date: 2022-12-15
Filing date: 2022-12-15
Publication date: 2024-06-18

Abstract

The disclosure provides a semiconductor structure, a three-dimensional memory, a preparation method thereof, a memory system and electronic equipment, and relates to the technical field of semiconductor chips, so as to improve the stability of the semiconductor structure and the production yield. The semiconductor structure includes a stacked structure, a support layer, a channel structure, and a dummy channel structure. The stacked structure includes a plurality of first dielectric layers and a plurality of gate layers alternately stacked, and has a first side and a second side disposed opposite to each other. The support layer is arranged on the first side of the stacking structure. The channel structure penetrates through the stacked structure. The virtual channel structure penetrates through the stacking structure and the supporting layer, and one end of the virtual channel structure extends out of the surface, away from the stacking structure, of the supporting layer. The semiconductor structure is applied to a three-dimensional memory to realize the reading and writing of data.

Description

Semiconductor structure, three-dimensional memory, preparation method of three-dimensional memory and memory system

Technical Field

The disclosure relates to the technical field of semiconductor chips, and in particular relates to a semiconductor structure, a three-dimensional memory, a preparation method of the three-dimensional memory, a storage system and electronic equipment.

Background

As the feature size of the memory cells approaches the lower process limit, planar processes and fabrication techniques become challenging and costly, which results in a storage density of 2D or planar NAND flash memory approaching the upper limit.

To overcome the limitation imposed by the 2D or planar NAND flash memory, three-dimensional memories (3D NAND) having a three-dimensional structure have been developed to increase the memory density by three-dimensionally disposing memory cells over a substrate. Among them, how to improve the production yield of the three-dimensional memory is a problem to be solved at present.

Disclosure of Invention

The embodiment of the disclosure provides a semiconductor structure, a three-dimensional memory, a preparation method thereof, a memory system and electronic equipment, so that the stability of the semiconductor structure is improved, and the production yield is improved.

In order to achieve the above object, the embodiments of the present disclosure adopt the following technical solutions:

In one aspect, a semiconductor structure is provided. The semiconductor structure includes a stacked structure, a channel structure, a support layer, and a dummy channel structure. The stacked structure includes a plurality of first dielectric layers and a plurality of gate layers alternately stacked. The stacked structure has oppositely disposed first and second sides. The support layer is disposed on a first side of the stacked structure. The channel structure extends through the stacked structure. The virtual channel structure penetrates through the stacking structure and the supporting layer, and one end of the virtual channel structure extends out of the surface, away from the stacking structure, of the supporting layer.

In the semiconductor structure provided in the above embodiment of the present disclosure, the portion of the channel structure extending out of the stack structure is etched back to expose the first semiconductor channel layer, and the portion of the virtual channel structure extending out of the stack structure is supported by the support layer, so that the risk of collapse of the virtual channel structure can be reduced, the stability of the semiconductor structure is improved, and the product yield is improved.

In some embodiments, the support layer does not overlap the channel structure.

In some embodiments, the semiconductor structure has a storage region and a connection region, the support layer being located at the connection region.

In some embodiments, one end of the channel structure protrudes from a surface of the first side of the stack structure, and a length of the virtual channel structure that protrudes from a surface of the support layer away from the stack structure is less than or equal to a length of the channel structure that protrudes from the surface of the first side of the stack structure.

In some embodiments, the semiconductor structure further comprises a second dielectric layer disposed between the support layer and the stacked structure, and an orthographic projection of the second dielectric layer onto a reference plane at least partially overlapping with an orthographic projection of the support layer onto the reference plane; the reference surface is a plane where a surface of the first side of the stacked structure is located.

In some embodiments, the material of the support layer comprises a semiconductor material.

In some embodiments, the channel structure includes a first memory function layer and a first semiconductor channel layer. The first memory function layer penetrates from the surface of the second side of the stacked structure to the surface of the first side of the stacked structure. The first semiconductor channel layer penetrates through the stacked structure, and one end of the first semiconductor channel layer protrudes from the surface of the first side of the stacked structure. And/or the virtual channel structure comprises a second memory function layer and a second semiconductor channel layer. The second storage function layer penetrates through the surface of the second side of the stacked structure to the surface of the supporting layer away from the stacked structure. The second semiconductor channel layer penetrates through the stacked structure and the supporting layer, and one end of the second semiconductor channel layer extends out from the surface, away from the stacked structure, of the supporting layer.

In another aspect, a three-dimensional memory is provided. The three-dimensional memory includes the semiconductor structure of some embodiments described above and a peripheral device coupled to the semiconductor structure.

In some embodiments, the three-dimensional memory further includes a source layer disposed on a side of the semiconductor structure remote from the peripheral device. The source layer covers a portion of the first semiconductor channel layer of the channel structure extending beyond a surface of the first side of the stack structure, and a portion of the dummy channel structure extending beyond a surface of the support layer away from the stack structure and covering the support layer.

In some embodiments, the source layer is uniform in thickness.

In some embodiments, a surface of the source layer remote from the semiconductor structure is parallel to a reference plane; the reference surface is a plane where a surface of the first side of the stacked structure is located.

In some embodiments, the three-dimensional memory further includes a first interlayer insulating layer, a connection post, a channel contact, and an insulating spacer layer. The first interlayer insulating layer is arranged on one side of the source electrode layer far away from the semiconductor structure. The connecting column penetrates through the first interlayer insulating layer and is connected with the source electrode layer. The channel contact is arranged on one side of the first interlayer insulating layer, which is far away from the semiconductor structure; the channel contact is connected with the connecting column. The insulating spacer layer is disposed on a side of the first interlayer insulating layer away from the semiconductor structure and surrounds the channel contact.

In yet another aspect, a method of fabricating a three-dimensional memory is provided. The preparation method of the three-dimensional memory comprises the following steps: forming an intermediate semiconductor structure; the intermediate semiconductor structure comprises a stacked structure, a channel structure, a virtual channel structure and a substrate; the stacked structure is arranged on the substrate and comprises a plurality of first dielectric layers and a plurality of grid layers which are alternately stacked; the channel structure penetrates through the stacking structure; the dummy channel structure extends through the stack structure and has one end extending into the substrate. The intermediate semiconductor structure is coupled with a peripheral device. Removing part of the substrate to form a supporting layer; the virtual channel structure penetrates through the supporting layer.

In some embodiments, the intermediate semiconductor structure has a storage region and a connection region. The substrate includes a first semiconductor layer including a first sub-portion located in the storage region and a second sub-portion located in the connection region.

The removing part of the substrate to form a supporting layer comprises the following steps: and carrying out ion doping on the first sub-part. The first sub-portion and the second sub-portion are etched simultaneously until the first sub-portion is completely removed. In the synchronous etching, the etching rate of the first sub-portion is greater than that of the second sub-portion, a part of the second sub-portion remains, and the portion of the second sub-portion remains forms the supporting layer.

In some embodiments, the ion doped portion of the first sub-portion is located on a side of the channel structure remote from the stacked structure.

The removing part of the substrate to form a supporting layer comprises the following steps: forming a photoresist pattern; the photoresist pattern exposes the first sub-portion and covers the second sub-portion. And etching the first sub-portion based on the photoresist pattern such that the thickness of the first sub-portion is smaller than the thickness of the second sub-portion. And stripping the photoresist pattern. Simultaneously etching the first sub-portion and the second sub-portion until the first sub-portion is completely removed and a portion of the second sub-portion remains; the remaining portion of the second sub-portion forms the support layer.

In some embodiments, the difference in thickness between the first sub-portion and the second sub-portion is greater than or equal to a set difference; the set difference is a difference between a length of a portion of the dummy channel structure extending out of the support layer and a length of a portion of the channel structure extending out of the stack structure.

In some embodiments, the substrate further comprises a base and a fourth dielectric layer. The removing part of the substrate to form a supporting layer, and the method further comprises the following steps: and removing the substrate and the fourth dielectric layer.

In yet another aspect, a storage system is provided comprising a three-dimensional memory as described above and a controller coupled to the three-dimensional memory to control the three-dimensional memory to store data.

In yet another aspect, an electronic device is provided, comprising a storage system as described above.

It can be appreciated that, the three-dimensional memory, the method for manufacturing the three-dimensional memory, the memory system and the electronic device provided in the foregoing embodiments of the present disclosure may refer to the beneficial effects of the semiconductor structure described above, and are not described herein again.

Drawings

In order to more clearly illustrate the technical solutions of the present disclosure, the drawings that need to be used in some embodiments of the present disclosure will be briefly described below, and it is apparent that the drawings in the following description are only drawings of some embodiments of the present disclosure, and other drawings may be obtained according to these drawings to those of ordinary skill in the art. Furthermore, the drawings in the following description may be regarded as schematic diagrams, not limiting the actual size of the products, the actual flow of the methods, the actual timing of the signals, etc. according to the embodiments of the present disclosure.

FIG. 1 is a cross-sectional view of a three-dimensional memory according to some embodiments;

FIG. 2 is a cross-sectional view of another three-dimensional memory according to some embodiments;

FIG. 3 is a cross-sectional view of a string of memory cells of the three-dimensional memory of FIG. 1;

FIG. 4 is an equivalent circuit diagram of the memory cell string of FIG. 3;

Fig. 5A is a top view of a semiconductor structure according to some embodiments;

Fig. 5B is a top view of another semiconductor structure in accordance with some embodiments;

FIG. 6 is a cross-sectional view taken along section line A-A' of FIG. 5A;

FIGS. 7-11B are diagrams of steps in a method of fabricating a three-dimensional memory, according to some embodiments;

FIGS. 12-15 are flowcharts of a method of fabricating a three-dimensional memory according to some embodiments;

FIG. 16 is a block diagram of a storage system according to some embodiments;

FIG. 17 is a block diagram of a storage system according to further embodiments.

Detailed Description

The following description of the embodiments of the present disclosure will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all, of the embodiments of the present disclosure. All other embodiments obtained by one of ordinary skill in the art based on the embodiments provided by the present disclosure are within the scope of the present disclosure.

In the description of the present disclosure, it should be understood that the terms "center," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," and the like indicate orientations or positional relationships based on the orientation or positional relationships shown in the drawings, merely to facilitate description of the present disclosure and simplify the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present disclosure.

Throughout the specification and claims, the term "comprising" is to be interpreted as an open, inclusive meaning, i.e. "comprising, but not limited to, unless the context requires otherwise. In the description of the present specification, the terms "one embodiment," "some embodiments," "example embodiments," "exemplary," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with the embodiment or example is included in at least one embodiment or example of the present disclosure. The schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics may be combined in any suitable manner in any one or more embodiments or examples.

The terms "first" and "second" are used below for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the embodiments of the present disclosure, unless otherwise indicated, the meaning of "a plurality" is two or more.

In describing some embodiments, expressions of "coupled" and "connected" and their derivatives may be used. For example, the term "connected" may be used in describing some embodiments to indicate that two or more elements are in direct physical or electrical contact with each other. As another example, the term "coupled" may be used in describing some embodiments to indicate that two or more elements are in direct physical or electrical contact. However, the term "coupled" may also mean that two or more elements are not in direct contact with each other, but yet still co-operate or interact with each other. The embodiments disclosed herein are not necessarily limited to the disclosure herein.

At least one of "A, B and C" has the same meaning as at least one of "A, B or C" and includes the following combinations of A, B and C: a alone, B alone, C alone, a combination of a and B, a combination of a and C, a combination of B and C, and a combination of A, B and C.

"A and/or B" includes the following three combinations: only a, only B, and combinations of a and B.

The use of "adapted" or "configured to" herein is meant to be an open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

In addition, the use of "based on" is intended to be open and inclusive in that a process, step, calculation, or other action "based on" one or more of the stated conditions or values may be based on additional conditions or beyond the stated values in practice.

As used herein, "about," "approximately" or "approximately" includes the stated values as well as average values within an acceptable deviation range of the particular values as determined by one of ordinary skill in the art in view of the measurement in question and the errors associated with the measurement of the particular quantity (i.e., limitations of the measurement system).

In the present disclosure, the meaning of "on" … …, "over," and "over" should be interpreted in the broadest sense such that "on" means not only "directly on" something but also includes the meaning of "on" something with intermediate features or layers therebetween, and "over" or "over" means not only "over" or "over" something, but also includes the meaning of "over" or "over" something (i.e., directly on) without intermediate features or layers therebetween.

Exemplary embodiments are described herein with reference to cross-sectional and/or plan views as idealized exemplary figures. In the drawings, the thickness of layers and regions are exaggerated for clarity. Thus, variations from the shape of the drawings due to, for example, manufacturing techniques and/or tolerances, are to be expected. Thus, the exemplary embodiments should not be construed as limited to the shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of example embodiments.

As used herein, the term "substrate" refers to a material to which subsequent layers of material may be added. The substrate itself may be patterned. The material added to the substrate may be patterned or may remain unpatterned. In addition, the substrate may include a variety of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, and the like. Alternatively, the substrate may be made of a non-conductive material such as glass, plastic, or sapphire wafer.

Fig. 1 is a cross-sectional view of a three-dimensional memory according to some embodiments, fig. 2 is a cross-sectional view of another three-dimensional memory according to some embodiments, fig. 3 is a cross-sectional view of one memory cell string of the three-dimensional memory of fig. 1, and fig. 4 is an equivalent circuit diagram of the memory cell string of fig. 3.

In fig. 1, the three-dimensional memory 10 extends in an X-Y plane, and the first direction X and the second direction Y are, for example, two orthogonal directions in a plane in which the semiconductor structure 100 is located (for example, a plane in which the source layer SL is located): referring to fig. 1 and 3, the first direction X may be an extending direction of the word lines WL0 to WL3, and the second direction Y may be an extending direction of the bit lines BL. The third direction Z is perpendicular to the plane in which the semiconductor structure 100 lies, i.e., perpendicular to the X-Y plane.

As used in this disclosure, whether a component is "on", "above/upper side" or "below/lower side" of another component (e.g., a layer, structure, or device) of the three-dimensional memory 10 is determined in a third direction Z relative to the substrate 190 (see fig. 7) or source layer SL of the semiconductor structure 100 when the substrate 190 (see fig. 7) or source layer SL is located in a lowest plane of the semiconductor structure 100 in the third direction Z. Throughout this disclosure, the same concepts are applied to describe spatial relationships.

In order to more clearly show the structure of the device, in fig. 1, a view of the storage area C and a view of the connection area S are shown, the view of the storage area C is based on the left coordinate system, the view of the connection area S is based on the right coordinate system, that is, the view of the storage area C shows the cross-sectional structure of the storage area C of the three-dimensional memory 10 in the Y direction, and the view of the connection area S shows the cross-sectional structure of the connection area S of the three-dimensional memory 10 in the X direction.

Referring to fig. 1, some embodiments of the present disclosure provide a three-dimensional memory 10. The three-dimensional memory 10 may include a semiconductor structure 100.

Illustratively, referring to fig. 1, the three-dimensional memory 10 may further include a source layer SL coupled with the semiconductor structure 100, and a peripheral device 200 coupled with the semiconductor structure 100. The peripheral device 200 may be disposed at a side of the semiconductor structure 100 remote from the source layer SL.

In some examples, as shown in fig. 1, a surface of the source layer SL remote from the semiconductor structure 100 is parallel to the reference plane. Wherein the reference plane is a plane where a surface of the first side of the stacked structure 110 is located. The surface of the first side of the stack structure 110 is the surface of the stack structure 110 remote from the peripheral device 200.

In other examples, as shown in fig. 2, the thickness of the source layer SL is uniform, so that the source layer SL has a similar profile to the surface of the semiconductor structure 100 near the source layer SL as the surface of the semiconductor structure 100 near the source layer SL is stepped.

The source layer SL may include a semiconductor material, which may include single crystal silicon, polycrystalline silicon, single crystal germanium, III-V compound semiconductor material, II-VI compound semiconductor material, and other suitable semiconductor materials. The source layer SL may be partially or fully doped. Illustratively, the source layer SL may include a doped region doped with a P-type dopant. The source layer SL may further include an undoped region.

Wherein the peripheral device 200 may include peripheral circuitry. The peripheral circuitry is configured to control and sense the array device. The peripheral circuitry may be any suitable digital, analog, and/or mixed signal control and sensing circuitry for supporting the operation (or operation) of the array device including, but not limited to, page buffers, decoders (e.g., row and column decoders), sense amplifiers, drivers (e.g., gate line drivers), charge pumps, current or voltage references, or any active or passive component of the circuitry (e.g., transistors, diodes, resistors, or capacitors). The peripheral circuitry may also include any other circuitry compatible with advanced logic processes, including logic circuitry (e.g., processors and programmable logic devices (Programmable Logic Device, PLDs) or Memory circuitry (e.g., static Random-Access Memory (SRAM)).

In some embodiments, referring to fig. 1 and 2, the three-dimensional memory 10 may further include a first interlayer insulating layer 510 and a connection pillar 511, the first interlayer insulating layer 510 is disposed at a side of the source layer SL away from the semiconductor structure 100, and the connection pillar 511 penetrates the first interlayer insulating layer 510 and is connected with the source layer SL.

The material of the first interlayer insulating layer 510 is an insulating material, and the insulating material includes at least one of silicon oxide, silicon nitride, silicon oxynitride, doped silicon oxide, organosilicate glass, dielectric metal oxide (e.g., aluminum oxide, hafnium oxide, etc.) and silicate thereof, and an organic insulating material, which is not limited thereto.

The material of the connection post 511 may be a conductive material, and the conductive material may include at least one of tungsten, cobalt, copper, aluminum, and metal silicide, and may be other suitable materials.

As shown in fig. 1 and 2, the three-dimensional memory 10 may further include an insulating spacer layer 520 and a channel contact 521, each of the insulating spacer layer 520 and the channel contact 521 being disposed on a side of the first interlayer insulating layer 510 remote from the semiconductor structure 100.

Wherein the channel contact 521 is connected with the connection post 511 to realize electrical connection with the channel structure 130 in contact with the source layer SL. The channel contact 521 may serve as a pickup region (Pick up Area) for an array common source (source layer SL) of the three-dimensional memory 10. Arranged in this manner, the array common source (source layer SL) is drawn from the side of the semiconductor structure 100 remote from the peripheral device 200, which is advantageous in saving memory space.

In addition, the insulating spacer layer 520 surrounds the channel contacts 521 to reduce the risk of cross-talk with other signals as the channel contacts 521 receive and transmit signals.

The insulating spacer 520 is made of an insulating material including at least one of silicon oxide, silicon nitride, silicon oxynitride, doped silicon oxide, organosilicate glass, dielectric metal oxide (e.g., aluminum oxide, hafnium dioxide, etc.) and silicate thereof, and organic insulating material, which is not limited thereto.

The material of the channel contact 521 may be a conductive material, which may include at least one of tungsten, cobalt, copper, aluminum, and metal silicide, and may be other suitable materials.

In some embodiments, as shown in fig. 1, a peripheral device 200 may include a substrate 201, peripheral circuitry disposed on the substrate 201, and a peripheral interconnect layer 203 disposed on the substrate 201. The peripheral circuitry may include a transistor 202.

The material of the substrate 201 may be monocrystalline silicon, or may be other suitable materials, such as silicon germanium, or a silicon-on-insulator film.

The peripheral interconnect layer 203 is coupled to the transistor 202 to enable transmission of electrical signals between the transistor 202 and the peripheral interconnect layer 203. The peripheral interconnect layer 203 may include one or more second interlayer insulating layers 204, and may further include one or more first interconnect conductor layers 205, and the different first interconnect conductor layers 205 may be coupled by contacts.

The material of the first interconnection conductor layer 205 and the contact may be a conductive material, and the conductive material may include at least one of tungsten, cobalt, copper, aluminum, and metal silicide, and may be other suitable materials.

The material of the second interlayer insulating layer 204 is an insulating material, and the insulating material may include at least one of silicon oxide, silicon nitride, and a high dielectric constant insulating material, and may be other suitable materials.

Referring to fig. 1, a semiconductor structure 100 may include an array of memory cell strings 400 (referred to herein as "memory cell strings," e.g., NAND memory cell strings). The source layer SL may be coupled to source terminals of the plurality of memory cell strings 400.

Specifically, referring to fig. 3 and 4, the memory cell string 400 may include a plurality of transistors T, and one transistor T (e.g., T1 to T6 in fig. 4) may be provided as one memory cell, and the transistors T are connected together to form the memory cell string 400. One transistor T (e.g., each transistor T) may be formed of the first semiconductor channel layer 131 and one gate G surrounding the first semiconductor channel layer 131. Wherein the gate G is configured to control the on state of the transistor T.

It should be noted that the numbers of transistors in fig. 1,2 and 3 are only illustrative, and the memory cell string 400 of the semiconductor structure 100 provided in the embodiments of the present disclosure may further include other numbers of transistors, for example, 4, 16, 32 and 64.

Referring to fig. 3 and 4, in the third direction Z, a gate located at the lowermost of the plurality of gates G (e.g., a gate closest to the source layer SL of the plurality of gates G) may be configured as a source select gate SGS configured to control the on state of the transistor T6, and thus the on state of one source channel in the memory cell string 400.

Referring to fig. 3 and 4, in the third direction Z, the gate located at the uppermost of the plurality of gates G (e.g., the gate furthest from the source layer SL among the plurality of gates G) may be configured as a drain select gate SGD configured to control the on state of the transistor T1, and thus the on state of one drain channel in the memory cell string 400.

Referring to fig. 3 and 4, in the third direction Z, the gates located in the middle of the plurality of gates G may be configured as a plurality of word lines WL, including, for example, word line WL0, word line WL1, word line WL2, and word line WL3. By writing different voltages on the word line WL, data writing, reading, and erasing of each memory cell (e.g., transistor T) in the memory cell string 400 can be completed.

In some embodiments, referring to fig. 1, semiconductor structure 100 may further include an array interconnect layer 300. The array interconnect layer 300 may be coupled to the memory cell string 400.

As shown in fig. 1,3 and 4, the array interconnection layer 300 may include a drain terminal (i.e., bit line BL) of the memory cell string 400, and the drain terminal may be coupled with a semiconductor channel 241 of each transistor T in at least one memory cell string 400.

Illustratively, as shown in fig. 1 and 3, the array interconnect layer 300 may include one or more third interlayer insulating layers 310, and may further include a plurality of contacts insulated from each other by the third interlayer insulating layers 310, the contacts including, for example, a bit line contact BL-CNT coupled to the bit line BL; the drain select gate contact SGD-CNT is coupled to the drain select gate SGD.

The material of the third interlayer insulating layer 310 is an insulating material, and the insulating material includes at least one of silicon oxide, silicon nitride, silicon oxynitride, doped silicon oxide, organosilicate glass, dielectric metal oxide (e.g., aluminum oxide, hafnium oxide, etc.) and silicate thereof, and organic insulating material, which is not limited thereto.

As shown in fig. 1 and 3, the array interconnect layer 300 may further include one or more second interconnect conductor layers 320. The second interconnection conductor layer 320 may include a plurality of connection lines, such as bit lines BL, and word line connection lines coupled to the word lines WL0 to WL 3.

The material of the second interconnection conductor layer 320 and the contact may be a conductive material, and the conductive material may include at least one of tungsten, cobalt, copper, aluminum, and metal silicide, and may be other suitable materials.

As shown in fig. 1, the peripheral interconnect layer 203 may be coupled to the array interconnect layer 300, so as to couple the semiconductor structure 100 and the peripheral device 200.

Here, since the peripheral interconnect layer 203 is coupled with the array interconnect layer 300, peripheral circuits in the peripheral device 200 may be coupled with the memory cell string 400 in the semiconductor structure 100 to enable transmission of electrical signals between the peripheral circuits and the memory cell string 400.

In some possible implementations, referring to fig. 1 and 2, an adhesive interface 500 may be provided between the peripheral interconnect layer 203 and the array interconnect layer 300, and the peripheral interconnect layer 203 and the array interconnect layer 300 may be adhered and coupled to each other through the adhesive interface 500.

As the number of 3D NAND layers increases, the process difficulty of etching the channel holes becomes greater. In the related art, a low-temperature etching process is adopted to etch the channel hole and the virtual channel hole, and a channel structure and a virtual channel structure are formed in the channel hole.

But the depth of the virtual channel hole etched by the low-temperature etching process is deeper than the depth of the channel hole, namely the length of the virtual channel structure extending out of the stacked structure is greater than the length of the virtual channel structure extending out of the stacked structure. When the portions of the channel structure and the dummy channel structure extending out of the stacked structure are etched back, the dummy channel structure is liable to collapse, resulting in a reduction in yield of the three-dimensional memory.

Based on this, some embodiments of the present disclosure provide a semiconductor structure 100, referring to fig. 5A and 6, including a stack structure 110, a support layer 120, a channel structure 130, and a dummy channel structure 140.

As shown in fig. 6, the stacked structure 110 includes a plurality of first dielectric layers 111 and gate layers 112 alternately arranged. The stacking structure 110 has a first side and a second side that are opposite to each other in the stacking direction, and the first side and the second side are opposite sides of the stacking structure 100 in the stacking direction.

The material of the first dielectric layer 111 may include an insulating material, where the insulating material includes at least one of silicon oxide, silicon nitride, silicon oxynitride, doped silicon oxide, organosilicate glass, dielectric metal oxide (such as aluminum oxide, hafnium oxide, etc.) and silicate thereof, and an organic insulating material.

Referring to fig. 6, the gate layer 112 includes a conductive layer 1121, and the material of the conductive layer 1121 may include a conductive material, and the conductive material may include at least one of tungsten, cobalt, copper, aluminum, doped silicon, and silicide.

In some embodiments, as shown in fig. 6, the gate layer 112 may further include a metal compound layer 1122, where the metal compound layer 1122 encapsulates the conductive layer 1121, and the metal compound layer 1122 is used to improve adhesion between the conductive layer 1121 and the first dielectric layer 111. The material of the metal compound layer 1122 includes at least one of titanium nitride, tantalum nitride, and tungsten carbide.

In some embodiments, as shown in fig. 6, the gate layer 112 may further include a third dielectric layer 1123, the third dielectric layer 1123 encasing the metal compound layer 1122 to reduce the risk of charge in the memory cell string 400 (see fig. 2) flowing to the conductive layer 1121. Wherein the dielectric constant value of the third dielectric layer 1123 is greater than or equal to 7. Illustratively, the material of the third dielectric layer 1123 includes at least one of aluminum oxide, hafnium oxide, and tantalum oxide.

As shown in fig. 6, the channel structure 130 extends through the stack structure 110. Illustratively, the channel structure 130 may extend through the stack structure 110 with one end protruding from a surface of the first side of the stack structure 110.

As shown in fig. 6, the channel structure 130 may include, for example, a first semiconductor channel layer 131 and a first memory function layer 132, and the first memory function layer 132 is disposed around the first semiconductor channel layer 131.

The material of the first semiconductor channel layer 131 includes a semiconductor material, which may include single crystal silicon, polycrystalline silicon, single crystal germanium, III-V compound semiconductor material, II-VI compound semiconductor material, and other suitable semiconductor materials.

Referring to fig. 3, the first memory function layer 132 may include, for example, a blocking layer 1321, a charge trapping layer 1322 and a tunneling layer 1323, where the blocking layer 1321, the charge trapping layer 1322, the tunneling layer 1323 and the first semiconductor channel layer 131 may be made of silicon oxide, silicon nitride, silicon oxide and polysilicon, respectively, so as to form an ONOP structure.

The materials of the first dielectric layer 111 and the barrier layer 1321 in the first memory function layer 132 may be different or the same. Illustratively, the material of the first dielectric layer 111 and the barrier layer 1321 in the first storage function layer 132 are the same. For example, the material of the first dielectric layer 111 and the barrier layer 1321 in the first storage function layer 132 is silicon oxide.

As shown in fig. 6, the first storage functional layer 132 extends from the surface of the second side of the stacked structure to the surface of the first side of the stacked structure 110. The first semiconductor channel layer 131 penetrates the stack structure 110, and one end protrudes from a surface of the first side of the stack structure 110.

At this time, referring to fig. 1, the source layer SL wraps the portion of the first semiconductor channel layer 131 of the channel structure 130 protruding from the surface of the first side of the stacked structure 110.

In some embodiments, referring to fig. 6, the channel structure 130 may further include a first channel filling layer 133, where the first channel filling layer 133 is disposed on a side of the first semiconductor channel layer 131 away from the first memory function layer 132 to provide mechanical support.

The material of the first channel filling layer 133 includes an insulating material, and the insulating material may include at least one of silicon oxide, silicon nitride, silicon oxynitride, doped silicon oxide, organosilicate glass, dielectric metal oxide (e.g., aluminum oxide, hafnium oxide, etc.) and silicate thereof, and an organic insulating material.

As shown in fig. 6, the support layer 120 is disposed on a first side of the stacked structure 110. Here, referring to fig. 1, the source layer SL further covers the support layer 120.

Referring to fig. 5A, 5B, and 6, the support layer 120 does not overlap the channel structure 130. For example, the semiconductor structure 100 has a storage region C and a connection region S, and the support layer 120 is located at the connection region S.

It should be noted that, as shown in fig. 5A, the connection area S may be located at the periphery of the storage area C, as shown in fig. 5B, or may be located between adjacent storage areas C, which is not limited herein.

The support layer 120 may include a plurality of support portions disposed at intervals. The supporting layer 120 may also be a continuous film structure, i.e. the supporting layer 120 covers the whole connecting area S; for example, the support layer 120 is a continuous film structure, and has a simple structure and is convenient to prepare.

The material of the support layer 120 includes a semiconductor material, which may include single crystal silicon, polycrystalline silicon, single crystal germanium, III-V compound semiconductor materials, II-VI compound semiconductor materials, and other suitable semiconductor materials.

The materials of the support layer 120 and the source layer SL may be different or the same. Illustratively, the material of the support layer 120 and the source layer SL are the same. For example, the material of the support layer 120 and the source layer SL is polysilicon.

As shown in fig. 6, the dummy channel structure 140 penetrates through the stack structure 110 and the support layer 120, and one end protrudes from a surface of the support layer 120 away from the stack structure 110.

It should be noted that the length of the dummy channel structure 140 extending out of the stack structure 110 is greater than the length of the channel structure 130 extending out of the stack structure 110.

In this case, in the process of etching back the portion of the channel structure 130 extending out of the stack structure 110 to expose the first semiconductor channel layer 131, the portion of the dummy channel structure 140 extending out of the stack structure 110 may reduce the risk of collapse of the dummy channel structure 140 due to the support provided by the support layer 120, improve the stability of the semiconductor structure 100, and improve the yield of products.

As shown in fig. 6, the dummy channel structure 140 may include, for example, a second semiconductor channel layer 141 and a second memory function layer 142, the second memory function layer 142 being disposed around the second semiconductor channel layer 141.

It should be noted that the material of the second semiconductor channel layer 141 may be the same as that of the first semiconductor channel layer 131, which is not described herein. The second memory function layer 142 may have the same structure and material as the first memory function layer 132, and the embodiments of the disclosure will not be described herein.

As shown in fig. 6, the second storage functional layer 142 extends from the surface of the second side of the stacked structure 110 to the surface of the supporting layer 120 away from the stacked structure 110. The second semiconductor channel layer 141 penetrates the stack structure 110 and the support layer 120, and one end protrudes from a surface of the support layer 120 away from the stack structure 110.

At this time, referring to fig. 1, the source layer SL further encapsulates a portion of the virtual channel structure 140 extending out of the surface of the support layer 120 away from the stacked structure 110.

In some embodiments, referring to fig. 6, the dummy channel structure 140 may further include a second channel fill layer 143, the second channel fill layer 143 being disposed on a side of the second semiconductor channel layer 141 remote from the second memory function layer 142 to provide mechanical support.

The material of the second trench filling layer 143 includes an insulating material, and the insulating material may include at least one of silicon oxide, silicon nitride, silicon oxynitride, doped silicon oxide, organosilicate glass, dielectric metal oxide (e.g., aluminum oxide, hafnium oxide, etc.) and silicate thereof, and an organic insulating material.

In some embodiments, referring to fig. 6, the length of the dummy channel structure 140 protruding from the surface of the support layer 120 away from the stack structure 110 is less than or equal to the length of the surface of the channel structure 130 protruding from the first side of the stack structure 110, to further reduce the risk of collapse of the dummy channel structure 140 when the channel structure 130 and the dummy channel structure 140 are etched back.

In some embodiments, referring to fig. 6, the semiconductor structure 100 further includes a second dielectric layer 150, where the second dielectric layer 150 is disposed between the support layer 120 and the stacked structure 110, and an orthographic projection of the second dielectric layer 150 onto the reference plane at least partially overlaps with an orthographic projection of the support layer 120 onto the reference plane. For example, the orthographic projection of the second dielectric layer 150 onto the reference plane completely overlaps the orthographic projection of the support layer 120 onto the reference plane.

The material of the second dielectric layer 150 includes an insulating material, and the insulating material may include at least one of silicon oxide, silicon nitride, silicon oxynitride, doped silicon oxide, organosilicate glass, dielectric metal oxide (such as aluminum oxide, hafnium oxide, etc.) and silicate thereof, and an organic insulating material.

The materials of the barrier layers in the first dielectric layer 111, the second dielectric layer 150, and the second memory function layer 142 may be different or the same. Illustratively, the materials of the barrier layers in the first dielectric layer 111, the second dielectric layer 150, and the second storage function layer 142 are the same. For example, the material of the barrier layers in the first dielectric layer 111, the second dielectric layer 150, and the second memory function layer 142 is silicon oxide.

In some embodiments, referring to fig. 6, the stacked structure 110 of the connection region S further includes a plurality of third dielectric layers 113, and the plurality of third dielectric layers 113 and the plurality of first dielectric layers 111 are alternately arranged. That is, the third dielectric layer 113 is located at the connection region S, the gate layer 112 and the third dielectric layer 113 are provided in the same layer, and the gate layer 112 is located at least at the storage region C, for example, the gate layer 112 extends from the storage region C partially to the connection region S.

On the basis, as shown in fig. 6, the semiconductor structure 100 further includes a contact pillar 180, where the contact pillar 180 penetrates a portion of the stacked structure 110 and is connected to the gate layer 112 to draw out the gate layer 112.

It should be noted that each gate layer 112 is electrically connected to a corresponding word line connection line through one contact pillar 180, that is, each gate layer 112 is correspondingly connected to one contact pillar 180.

The contact pillar 180 includes a first conductive portion 181 and a second conductive portion 182, the first conductive portion 181 extends along a stacking direction of the stacked structure 110 and penetrates through a portion of the stacked structure 110, the second conductive portion 182 extends along a horizontal direction (X-Y plane in fig. 1) and is disposed in the same layer as the gate layer 112, and the second conductive portion 182 is connected to the gate layer 112 and the first conductive portion 181. In this case, the difficulty of the process of etching the contact hole (the region where the contact pillar 180 is located) for extracting the gate layer 112 can be reduced.

In fig. 6, in the orthographic projection of the film layer of the gate layer 112 connected to the contact stud 180 onto the reference surface, the portion overlapping the orthographic projection of the third dielectric layer 113 adjacent thereto onto the reference surface is the second conductive portion 182 of the contact stud 180, and the portion not overlapping is the gate layer 112.

In some embodiments, referring to fig. 6, the semiconductor structure 100 further includes a gate line isolation structure 170, the gate line isolation structure 170 penetrating the stack structure 110 and dividing the stack structure 110 into at least one memory block.

Wherein the gate line isolation structure 170 includes an insulating isolation portion 171.

The material of the insulating spacer 171 includes an insulating material, and the insulating material may include at least one of silicon oxide, silicon nitride, silicon oxynitride, doped silicon oxide, organosilicate glass, dielectric metal oxide (e.g., aluminum oxide, hafnium oxide, etc.) and silicate thereof, and an organic insulating material, for example.

On this basis, as shown in fig. 6, the gate line isolation structure 170 may further include an intermediate filling layer 172. The insulating spacer 171 is left with a cavity inside and the intermediate filling layer 172 fills the cavity to provide mechanical support.

Note that the material of the intermediate filling layer 172 may be a conductive material or an insulating material, which is not particularly limited herein.

Based on this, the embodiment of the present disclosure also provides a method for manufacturing a three-dimensional memory, as shown in fig. 12, including S100 to S300.

S100: referring to fig. 7, an intermediate semiconductor structure 100' is formed.

In the above steps, as shown in fig. 7, the intermediate semiconductor structure 100' includes the stack structure 110, the channel structure 130, the dummy channel structure 140, and the substrate 190.

As shown in fig. 7, a stack structure 110 is disposed on a substrate 190, the stack structure 110 including a plurality of first dielectric layers 111 and a plurality of gate layers 112 alternately stacked. The channel structure 130 extends through the stack structure 110, and one end may, for example, protrude from the surface of the stack structure 110 and extend into the substrate 190, i.e., be surrounded by the substrate 190. The dummy channel structure 140 penetrates through the stack structure 110, and one end of the dummy channel structure extends out of the surface of the stack structure 110 and into the substrate 190, i.e. is covered by the substrate 190.

Wherein, as shown in fig. 8, in the process of S100, a substrate 190 is used to support the stacked structure 110 thereon to provide a bearing function.

In some embodiments, referring to fig. 7, the substrate 190 includes a first semiconductor layer 193.

The material of the first semiconductor layer 193 includes a semiconductor material, which may include single crystal silicon, polycrystalline silicon, single crystal germanium, a group III-V compound semiconductor material, a group II-VI compound semiconductor material, and other suitable semiconductor materials.

In other embodiments, referring to fig. 7, the substrate 190 may be a composite substrate.

Illustratively, as shown in fig. 7, the substrate 190 may include a base 191, and a fourth dielectric layer 192 and a first semiconductor layer 193 are sequentially formed on the base 191. The first semiconductor layer 193 is relatively close to the stack structure 110. At this time, the channel structure 130 and the dummy channel structure 140 extend to the first semiconductor layer 193.

The material of the above substrate 191 may include at least one of single crystal silicon, polycrystalline silicon, single crystal germanium, a III-V compound semiconductor material, a IIVI group compound semiconductor material, or other semiconductor materials known in the art.

The material of the fourth dielectric layer 192 may include an insulating material, and the insulating material may include at least one of silicon oxide, silicon nitride, silicon oxynitride, doped silicon oxide, organosilicate glass, dielectric metal oxide (e.g., aluminum oxide, hafnium oxide, etc.) and silicate thereof, and an organic insulating material.

In addition, referring to fig. 7, other functional layers may be disposed between the stacked structure 110 and the substrate 190, and the stacked structure 110 may also be directly disposed on the substrate 190.

Illustratively, as shown in fig. 7, the intermediate semiconductor structure 100' is further provided with a second dielectric layer 150 and a second semiconductor layer 160, the second dielectric layer 150 and the second semiconductor layer 160 are disposed between the stacked structure 110 and the substrate 190, and the second semiconductor layer 160 is located at a side of the second dielectric layer 150 away from the substrate 190.

It should be noted that the second dielectric layer 150 may serve as an etch stop layer for etching the substrate 190 (see fig. 7) to help control process uniformity during removal of the substrate 190. The second semiconductor layer 160 may act as an etch stop layer during etching of the portions of the channel structure 130 and the dummy channel structure 140 extending out of the stack structure 110, helping to control process uniformity of removing the memory function layer of the portions of the channel structure 130 and the dummy channel structure 140 extending out of the stack structure 110.

The material of the second semiconductor layer 160 includes a semiconductor material, which may include single crystal silicon, polycrystalline silicon, single crystal germanium, a group III-V compound semiconductor material, a group II-VI compound semiconductor material, and other suitable semiconductor materials.

The materials of the second semiconductor layer 160 and the source layer SL may be different or the same. Illustratively, the second semiconductor layer 160 and the source layer SL are the same material. For example, the materials of the second semiconductor layer 160 and the source layer SL are polysilicon.

In some embodiments, the S100 may specifically include, for example: forming an initial stacking structure; forming a channel structure 130 and a dummy channel structure 140 penetrating the initial stack structure; forming a gate line slit penetrating through the initial stacked structure; part of the third dielectric layer 113 (see fig. 7) is replaced with the gate layer 112 (see fig. 7) via the gate line slit. Further, after forming the gate layer 112, a gate line isolation structure 170 may be formed in the gate line slit (see fig. 7).

It should be noted that the initial stacked structure includes a plurality of first dielectric layers 111 and a plurality of third dielectric layers 113 alternately arranged. The channel structure 130, the dummy channel structure 140 and the gate line isolation structure 170 may be referred to above, and the embodiments of the disclosure are not described herein.

S200: referring to fig. 7, the intermediate semiconductor structure 100' is coupled with a peripheral device 200.

In the above steps, the intermediate semiconductor structure 100' provides support using the substrate 201 of the peripheral device 200.

S300: referring to fig. 7 and 10, a portion of the substrate 190 is removed to form the support layer 120.

In the above steps, the dummy channel structure 140 penetrates through the support layer 120, and the support layer 120 may, for example, not overlap with the channel structure 130.

Referring to fig. 8, the intermediate semiconductor structure 100' has a storage region C and a connection region S, the substrate 190 includes a semiconductor layer 193, and the semiconductor layer 193 includes a first sub-portion 1931 located in the storage region C and a second sub-portion 1932 located in the connection region S.

In some embodiments, referring to FIG. 13, S300 includes S310-S320.

S310: referring to fig. 9A, the first sub-portion 1931 is ion doped.

In the above steps, the plasma implantation process may be used to implant ions into the first sub-portion 1931, so that the etching rates of the first sub-portion 1931 and the second sub-portion 1932 for the same etchant are different.

The type of the doped ions is not limited to a single type, and the etching rates of the first and second sub-portions 1931 and 1932 may be different for the same etchant. Illustratively, the ions include tungsten ions and/or oxygen ions.

As shown in fig. 9A, the ion doped portion of the first sub-portion 1931 is located on a side of the channel structure 130 away from the stacked structure 110, so as to avoid ion doping into the channel structure 130, which affects subsequent etching of the channel structure 130.

S320: referring to fig. 9A and 10, the first sub-portion 1931 and the second sub-portion 1932 are etched simultaneously until the first sub-portion 1931 is completely removed.

In the above step, in the synchronous etching, the etching rate for the first sub-portion 1931 is greater than the etching rate for the second sub-portion 1932. Wherein a portion of the second sub-portion 1932 remains, and the portion of the second sub-portion 1932 remains forms the support layer 120.

Wherein the first and second sub-portions 1931 and 1932 may be etched by a dry/wet etching process. For example, the first sub-portion 1931 and the second sub-portion 1932 are anisotropically etched using a dry etching process, forming the support layer 120.

In S310, the second sub-portion 1932 may be ion doped, and in S320, the etching rate of the first sub-portion 1931 may be greater than the etching rate of the second sub-portion 1932 in the synchronous etching.

In other embodiments, referring to FIG. 14, S300 includes S330-S360.

S330: a photoresist pattern is formed.

In the above step, the photoresist pattern exposes the first sub-portion 1931 and covers the second sub-portion 1932.

S340: referring to fig. 9B, the first sub-portion 1931 is etched based on the photoresist pattern such that the thickness of the first sub-portion 1931 is smaller than the thickness of the second sub-portion 1932.

In the above step, the first sub-portion 1931 may be etched by a dry/wet etching process. For example, the first sub-portion 1931 is anisotropically etched using a dry etching process such that the thickness of the first sub-portion 1931 is less than the thickness of the second sub-portion 1932.

Referring to fig. 9B and fig. 10, the difference in thickness between the first sub-portion 1931 and the second sub-portion 1932 may be greater than or equal to a set difference, for example. The difference is set to be the difference between the length of the portion of the virtual channel structure 140 extending out of the supporting layer 120 and the length of the portion of the channel structure 130 extending out of the stacked structure 110, so that after the first sub-portion 1931 and the second sub-portion 1932 are etched synchronously in the subsequent process, the thickness of the supporting layer 120 formed is larger, and the supporting effect on the virtual channel structure 140 is better.

S350: the photoresist pattern is stripped.

In the above step, referring to fig. 9B, the photoresist pattern may be stripped by using a stripping solution, so that the surface of the exposed second sub-portion 1932 away from the stacked structure 110 is exposed.

S360: the first sub-portion 1931 and the second sub-portion 1932 are etched simultaneously until the first sub-portion 1931 is completely removed.

In the above step, in the synchronous etching, the etching rate for the first sub-portion 1931 is the same as the etching rate for the second sub-portion 1932. Wherein a portion of the second sub-portion 1932 remains, and the portion of the second sub-portion 1932 remains forms the support layer 120.

In the case where the substrate 190 further includes the base 191 and the fourth dielectric layer 192, as shown in fig. 7, the S300 further includes S370.

S370: referring to fig. 7 and 8, the substrate 191 and the fourth dielectric layer 192 are removed.

In the above steps, the substrate 191 and the fourth dielectric layer 192 may be removed using chemical mechanical polishing, dry/wet etching processes. For example, the substrate 191 and the fourth dielectric layer 192 are removed using a wet etching process.

In some embodiments, after S300, referring to fig. 15, the above preparation method further includes S400 to S800.

S400: referring to fig. 6 and 10, the first memory function layer 132 of the portion of the channel structure 130 protruding from the stack structure 110 and the second memory function layer 142 of the portion of the dummy channel structure 140 protruding from the support layer 120 are removed.

In the above steps, the portion of the channel structure 130 protruding from the stack structure 110 and the portion of the dummy channel structure 140 protruding from the support layer 120 may be etched by a dry/wet etching process. For example, a wet etching process is used to isotropically etch a portion of the channel structure 130 protruding from the stack structure 110 and a portion of the dummy channel structure 140 protruding from the support layer 120 such that the first semiconductor channel layer 131 and the second semiconductor channel layer 141 are exposed.

Where the material of the second dielectric layer 150 is the same as the material of any one of the blocking layer 1321, the charge trapping layer 1322 and the tunneling layer 1323 in the first memory function layer 132, for example, the material of the second dielectric layer 150 is the same as the material of the blocking layer 1321, in the process of S400, a portion of the second dielectric layer 150 located in the storage region C is also removed.

S500: referring to fig. 6 and 11A, ion doping is performed on the first semiconductor channel layer 131 and the second semiconductor channel layer 141 at a side of the stack structure 110 near the support layer 120.

In the above steps, ions may be implanted into the first semiconductor channel layer 131 and the second semiconductor channel layer 141 by using a plasma implantation process to improve adhesion and conductivity between the source layer SL and the first semiconductor channel layer 131 and the second semiconductor channel layer 141. The ions may include metal ions, for example, tungsten ions.

As shown in fig. 11A, the depth H1 of the ion doping may be less than or equal to the maximum distance between the surface of the portion of the channel structure 130 extending out of the stack structure 110 away from the stack structure 110 and the nearest gate layer 112.

S600: referring to fig. 6 and 11A, a source layer SL is formed.

In the above steps, the source layer SL is disposed on a side of the semiconductor structure 100 away from the peripheral device 200, and covers a portion of the first semiconductor channel layer 131 of the channel structure 130 extending out of the surface of the first side of the stack structure 110 and a portion of the second semiconductor channel layer 141 of the dummy channel structure 140 extending out of the support layer 120 extending out of the surface of the stack structure 110, and covers the support layer 120.

In some examples, as shown in fig. 11A, the thickness of the source layer SL is uniform. For example, the source layer SL may be formed using any one of a thin film deposition process of chemical vapor deposition (Chemical Vapor Deposition, CVD for short), physical vapor deposition (Physical Vapor Deposition, PVD for short), atomic layer deposition (Atomic Layer Deposition, ALD for short).

In other examples, as shown in fig. 11B, a surface of the source layer SL away from the semiconductor structure 100 is parallel to a surface of the stacked structure 110 close to the source layer SL. For example, the source layer SL may be formed by forming an initial source layer using any one of a CVD, PVD, and ALD thin film deposition process, and then planarizing the surface of the initial source layer using a planarization process.

S700: referring to fig. 1 and 2, a first interlayer insulating layer 510 and a connection post 511 are formed.

In the above steps, the first interlayer insulating layer 510 is disposed on the side of the source layer SL away from the semiconductor structure 100, and the connection pillar 511 penetrates through the first interlayer insulating layer 510 and is coupled to the source layer SL.

Wherein the first interlayer insulating layer 510 may be formed using any one of CVD, PVD and ALD thin film deposition processes, and the first interlayer insulating layer 510 may be etched to form the first connection hole. Then, a connection post 511 is formed in the first connection hole.

S800: referring to fig. 1 and 2, an insulating spacer 520 and a channel contact 521 are formed.

In the above steps, as shown in fig. 1 and 2, the insulating spacer layer 520 and the channel contact 521 are disposed on the side of the first interlayer insulating layer 510 away from the semiconductor structure 100. The channel contact 521 is connected with the connection post 511 to realize electrical connection with the channel structure 130 contacting the source layer SL.

Wherein the insulating spacer 520 may be formed using any one of a CVD, PVD and ALD thin film deposition process, and etching the insulating spacer 520 to form the second connection hole. Then, a channel contact 521 is formed in the second connection hole.

FIG. 16 is a block diagram of a storage system according to some embodiments. FIG. 17 is a block diagram of a storage system according to further embodiments.

Referring to fig. 16 and 17, some embodiments of the present disclosure also provide a storage system 1000. The memory system 1000 includes a controller 20, and the three-dimensional memory 10 of some embodiments as described above, the controller 20 being coupled to the three-dimensional memory 10 to control the three-dimensional memory 10 to store data.

The storage system 1000 may be integrated into various types of storage devices, for example, included in the same package (e.g., universal flash storage (Universal Flash Storage, UFS) package or Embedded multimedia card (eMMC) package). That is, the storage system 1000 may be applied to and packaged into different types of electronic products, such as mobile phones (e.g., cell phones), desktop computers, tablet computers, notebook computers, servers, in-vehicle devices, game consoles, printers, positioning devices, wearable devices, smart sensors, mobile power supplies, virtual Reality (VR) devices, augmented Reality (Augmented Reality, AR) devices, or any other suitable electronic device having a memory therein.

In some embodiments, referring to FIG. 16, the memory system 1000 includes a controller 20 and a three-dimensional memory 10, and the memory system 1000 may be integrated into a three-dimensional memory card.

The three-dimensional memory Card comprises any one of a PC Card (PCMCIA, personal computer three-dimensional memory Card International Association), a Compact Flash (CF) Card, an intelligent media (SMART MEDIA SM) Card, a three-dimensional memory, a Multimedia Card (MMC), a secure digital (Secure Digital Memory Card SD) Card and a UFS Card.

In other embodiments, referring to fig. 17, a storage system 1000 includes a controller 20 and a plurality of three-dimensional memories 10, and the storage system 1000 is integrated into a Solid state disk (Solid STATE DRIVES, SSD for short).

In the storage system 1000, in some embodiments, the controller 20 is configured for operation in a low duty cycle environment, such as an SD card, CF card, universal serial bus (Universal Serial Bus, abbreviated USB) flash drive, or other medium for use in electronic devices such as personal computers, digital cameras, mobile phones, and the like.

In other embodiments, the controller 20 is configured to operate in a high duty cycle environment SSD or eMMC for data storage and enterprise storage arrays of mobile devices such as smartphones, tablets, notebooks, and the like.

In some embodiments, the controller 20 may be configured to manage data stored in the three-dimensional memory 10 and communicate with an external device (e.g., a host). In some embodiments, the controller 20 may also be configured to control operations of the three-dimensional memory 10, such as read, erase, and program operations. In some embodiments, the controller 20 may also be configured to manage various functions with respect to data stored or to be stored in the three-dimensional memory 10, including at least one of bad block management, garbage collection, logical-to-physical address translation, wear leveling. In some embodiments, the controller 20 is further configured to process error correction codes with respect to data read from the three-dimensional memory 10 or written to the three-dimensional memory 10.

Of course, the controller 20 may also perform any other suitable function, such as formatting the three-dimensional memory 10; for example, the controller 20 may communicate with an external device (e.g., a host) via at least one of various interface protocols.

It should be noted that the interface protocol includes at least one of USB protocol, MMC protocol, peripheral Component Interconnect (PCI) protocol, PCI express (PCI-E) protocol, advanced Technology Attachment (ATA) protocol, serial ATA protocol, parallel ATA protocol, small Computer Small Interface (SCSI) protocol, enhanced Small Disk Interface (ESDI) protocol, integrated Drive Electronics (IDE) protocol, and Firewire protocol.

Some embodiments of the present disclosure also provide an electronic device. The electronic device may be any of a cell phone, a desktop computer, a tablet computer, a notebook computer, a server, a vehicle-mounted device, a wearable device (e.g., a smart watch, a smart bracelet, smart glasses, etc.), a mobile power supply, a game console, a digital multimedia player, etc.

The electronic device may include the storage system 1000 described above, and may further include at least one of a central processing unit CPU (Central Processing Unit ), a cache (cache), and the like.

The foregoing is merely illustrative of the present invention, and the present invention is not limited thereto, and any changes or substitutions easily contemplated by those skilled in the art within the scope of the present invention should be included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1. A semiconductor structure, comprising:

a stacked structure including a plurality of first dielectric layers and a plurality of gate layers alternately stacked; the stacked structure has oppositely disposed first and second sides;

The support layer is arranged on the first side of the stacking structure;

A channel structure penetrating the stacked structure;

And the virtual channel structure penetrates through the stacking structure and the supporting layer, and one end of the virtual channel structure extends out of the surface, away from the stacking structure, of the supporting layer.

2. The semiconductor structure of claim 1, wherein the support layer does not overlap the channel structure.

3. The semiconductor structure of claim 2, wherein the semiconductor structure has a storage region and a connection region; the supporting layer is positioned in the connecting area.

4. The semiconductor structure of claim 3, wherein one end of the channel structure protrudes from a surface of the first side of the stack structure, and wherein a length of the virtual channel structure that protrudes from a surface of the support layer away from the stack structure is less than or equal to a length of the channel structure that protrudes from the surface of the first side of the stack structure.

5. The semiconductor structure of any one of claims 1-4, further comprising:

The second medium layer is arranged between the supporting layer and the stacking structure, and the orthographic projection of the second medium layer to the reference surface is at least partially overlapped with the orthographic projection of the supporting layer to the reference surface; the reference surface is a plane where a surface of the first side of the stacked structure is located.

6. The semiconductor structure of any one of claims 1-4, wherein the material of the support layer comprises a semiconductor material.

7. The semiconductor structure of claim 1, wherein the channel structure comprises:

A first memory function layer penetrating from a surface of the second side of the stacked structure to a surface of the first side of the stacked structure;

A first semiconductor channel layer penetrating the stack structure and having one end protruding from a surface of a first side of the stack structure;

And/or, the virtual channel structure comprises:

A second memory function layer penetrating from the surface of the second side of the stacked structure to the surface of the support layer away from the stacked structure;

And a second semiconductor channel layer penetrating the stack structure and the support layer, and having one end protruding from a surface of the support layer away from the stack structure.

8. A three-dimensional memory, comprising:

a semiconductor structure as claimed in any one of claims 1 to 7;

And a peripheral device coupled to the semiconductor structure.

9. The three-dimensional memory of claim 8, further comprising:

The source electrode layer is arranged on one side of the semiconductor structure, which is far away from the peripheral device; the source layer covers a portion of the first semiconductor channel layer of the channel structure extending beyond a surface of the first side of the stack structure, and a portion of the dummy channel structure extending beyond a surface of the support layer away from the stack structure and covering the support layer.

10. The three-dimensional memory of claim 9, wherein the source layer is of uniform thickness.

11. The three-dimensional memory of claim 9, wherein a surface of the source layer remote from the semiconductor structure is parallel to a reference plane; the reference surface is a plane where a surface of the first side of the stacked structure is located.

12. The three-dimensional memory according to any one of claims 9 to 11, further comprising:

the first interlayer insulating layer is arranged on one side of the source electrode layer, which is far away from the semiconductor structure;

a connection post penetrating the first interlayer insulating layer and connected to the source electrode layer;

a channel contact disposed on a side of the first interlayer insulating layer away from the semiconductor structure; the channel contact is connected with the connecting column;

And the insulating spacer layer is arranged on one side of the first interlayer insulating layer away from the semiconductor structure and surrounds the channel contact.

13. A method for manufacturing a three-dimensional memory, comprising:

Forming an intermediate semiconductor structure; the intermediate semiconductor structure comprises a stacked structure, a channel structure, a virtual channel structure and a substrate; the stacked structure is arranged on the substrate and comprises a plurality of first dielectric layers and a plurality of grid layers which are alternately stacked; the channel structure penetrates through the stacking structure; the virtual channel structure penetrates through the stacking structure, and one end of the virtual channel structure extends into the substrate;

coupling the intermediate semiconductor structure with a peripheral device;

Removing part of the substrate to form a supporting layer; the virtual channel structure penetrates through the supporting layer.

14. The method of manufacturing a three-dimensional memory according to claim 13, wherein the intermediate semiconductor structure has a memory region and a connection region, the substrate comprising a first semiconductor layer comprising a first sub-portion located in the memory region and a second sub-portion located in the connection region;

the removing part of the substrate to form a supporting layer comprises the following steps:

Ion doping is carried out on the first sub-part;

simultaneously etching the first sub-portion and the second sub-portion until the first sub-portion is completely removed;

in the synchronous etching, the etching rate of the first sub-portion is greater than that of the second sub-portion, a part of the second sub-portion remains, and the portion of the second sub-portion remains forms the supporting layer.

15. The method of claim 14, wherein the ion doped portion of the first sub-portion is located on a side of the channel structure away from the stacked structure.

16. The method of manufacturing a three-dimensional memory according to claim 13, wherein the intermediate semiconductor structure has a memory region and a connection region, the substrate comprising a first semiconductor layer comprising a first sub-portion located in the memory region and a second sub-portion located in the connection region;

forming a photoresist pattern; the photoresist pattern exposes the first sub-portion and covers the second sub-portion;

Etching the first sub-portion based on the photoresist pattern such that a thickness of the first sub-portion is smaller than a thickness of the second sub-portion;

Stripping the photoresist pattern;

Simultaneously etching the first sub-portion and the second sub-portion until the first sub-portion is completely removed and a portion of the second sub-portion remains; the remaining portion of the second sub-portion forms the support layer.

17. The method of claim 16, wherein a thickness difference between the first sub-portion and the second sub-portion is greater than or equal to a set difference; the set difference is a difference between a length of a portion of the dummy channel structure extending out of the support layer and a length of a portion of the channel structure extending out of the stack structure.

18. The method for manufacturing a three-dimensional memory according to any one of claims 13 to 17, wherein the substrate further comprises a base and a fourth dielectric layer, the removing part of the substrate to form a supporting layer, further comprising:

And removing the substrate and the fourth dielectric layer.

19. A storage system, comprising:

a three-dimensional memory as claimed in any one of claims 8 to 12;

and a controller coupled to the three-dimensional memory to control the three-dimensional memory to store data.

20. An electronic device comprising the storage system of claim 19.