CN114551342A

CN114551342A - Semiconductor structure, preparation method thereof and three-dimensional memory

Info

Publication number: CN114551342A
Application number: CN202210129267.5A
Authority: CN
Inventors: 吴建中; 刘隆冬; 肖梦; 长江
Original assignee: Yangtze Memory Technologies Co Ltd
Current assignee: Yangtze Memory Technologies Co Ltd
Priority date: 2022-02-11
Filing date: 2022-02-11
Publication date: 2022-05-27

Abstract

The disclosure provides a semiconductor structure, a preparation method thereof and a three-dimensional memory, relates to the technical field of semiconductor chips, and aims to solve the problem of how to optimize the preparation process of a contact column. The preparation method comprises the following steps: a stacked structure is formed on a substrate, the stacked structure including a plurality of dielectric layers and a plurality of sacrificial layers alternately stacked, the stacked structure forming a step structure including a plurality of steps in a step region. And forming the lining layer at least covering the step structure. And performing modification treatment on a target part of the lining layer, wherein the target part of the lining layer at least comprises a part of the lining layer, which is positioned above the step surfaces of the steps. And removing the sacrificial layer to form a first cavity, and removing a target part of the lining layer to form a second cavity, wherein the first cavity is communicated with the second cavity. And filling the first cavity and the second cavity with a conductive material to form a gate layer. The semiconductor structure prepared by the preparation method is applied to a three-dimensional memory to realize the reading and writing operations of data.

Description

Semiconductor structure, preparation method thereof and three-dimensional memory

Technical Field

The disclosure relates to the technical field of semiconductor chips, in particular to a semiconductor structure, a manufacturing method thereof and a three-dimensional memory.

Background

As the feature size of memory cells approaches the lower process limit, planar processes and manufacturing techniques become challenging and costly, which causes the storage density of 2D or planar NAND flash memories to approach the upper limit.

To overcome the limitations imposed by 2D or planar NAND flash memories, memories having a three-dimensional structure (3D NAND) have been developed to increase the storage density by arranging memory cells three-dimensionally over a substrate.

In the related art, a three-dimensional memory includes a plurality of gate layers arranged in a stack with an insulating layer disposed between adjacent gate layers, thereby forming a stacked structure. The problem to be solved is how to optimize the preparation process of the contact column by leading out each layer of gate layer through the contact column so as to improve the performance of the three-dimensional memory.

Disclosure of Invention

Embodiments of the present disclosure provide a semiconductor structure, a method for manufacturing the same, and a three-dimensional memory, and aim to solve the problem of how to optimize a manufacturing process of a contact pillar.

In order to achieve the purpose, the embodiment of the disclosure adopts the following technical scheme:

in one aspect, a method of fabricating a semiconductor structure is provided. The semiconductor structure comprises an array region and a step region, and the preparation method comprises the following steps: forming a stacked structure on a substrate, the stacked structure including a plurality of dielectric layers and a plurality of sacrificial layers alternately stacked, the stacked structure forming a step structure including a plurality of steps in the step region. And forming an inner liner layer at least covering the step structure. And modifying the target part of the lining layer, wherein the target part of the lining layer at least comprises the part, positioned above the step surfaces of the steps, in the lining layer. And removing the sacrificial layer to form a first cavity, and removing a target part of the lining layer to form a second cavity, wherein the first cavity is communicated with the second cavity. And filling a conductive material in the first cavity and the second cavity to form a gate layer.

In the method for manufacturing a semiconductor structure according to the above embodiment of the present disclosure, after the stacked structure is formed on the substrate, the liner layer at least covering the step structure is formed, and the target portion of the liner layer is modified, so that the property of the target portion of the liner layer meets the requirement of being etched by a specific etchant. Then, the sacrificial layer in the stacked structure is removed to form a first cavity, and a target portion of the liner layer is removed to form a second cavity. And finally, filling a conductive material in the first cavity and the second cavity to form a gate layer, wherein the formed gate layer is thicker at the end part of the step region due to the communication between the first cavity and the second cavity.

In addition, in the process of preparing the contact holes with different depths by adopting a one-time mask process, because the end part of the gate layer, which is positioned in the step area, is thick, the gate layer is not easy to be etched and penetrated, and the process yield of the device is improved.

In some embodiments, the stacked structure includes a plurality of film layer pairs, each film layer pair including an adjacent dielectric layer and a sacrificial layer, and each film layer pair forming one step of the step structure. In the film layer pair, the dielectric layer is farther away from the substrate relative to the sacrificial layer.

In the process of modifying the target portion of the liner layer, modifying the target portion of the dielectric layer. The target portion of the dielectric layer is a portion of the dielectric layer located between the target portion of the liner layer and the step surfaces of the plurality of steps.

In some embodiments, during the removing of the sacrificial layer to form the first cavity and the removing of the target portion of the liner layer to form the second cavity, the target portion of the dielectric layer is also removed to form a third cavity. Wherein, along the direction perpendicular to the substrate, the third cavity is located between the first cavity and the second cavity, and the first cavity and the second cavity are communicated through the third cavity.

In some embodiments, during the filling of the first cavity and the second cavity with the conductive material, the third cavity is also filled with the conductive material.

In some embodiments, the stacked structure includes a plurality of film layer pairs, each film layer pair including an adjacent dielectric layer and a sacrificial layer, and each film layer pair forming one step of the step structure. In the film layer pair, the sacrificial layer is farther away from the substrate relative to the dielectric layer. The first cavity and the second cavity are in direct communication.

In some embodiments, the material of the sacrificial layer comprises silicon nitride. The modification treatment of the target part of the lining layer comprises the following steps: and implanting nitrogen ions into the target part of the lining layer by adopting an ion implantation process. And removing the sacrificial layer to form a first cavity, and removing a target part of the lining layer to form a second cavity by using the same etchant.

In some embodiments, the material of the sacrificial layer comprises silicon nitride and the modification treatment comprises a nitridation process. And removing the sacrificial layer to form a first cavity, and removing a target part of the lining layer to form a second cavity by using the same etchant.

In some embodiments, during the modifying treatment of the target portion of the liner layer, at least a portion of a sidewall of the liner layer covering the plurality of steps is not modified, forming a plurality of spacers. Wherein the isolation portion is connected with the dielectric layer below the sacrificial layer corresponding to the isolation portion.

In some embodiments, the target portion of the liner layer further includes a portion of the liner layer that is located above the partition.

In some embodiments, the liner layer covers the stacked structure. Before the modifying treatment is performed on the target portion of the inner liner layer, the preparation method further includes: and forming a mask layer which covers the part except the target part in the lining layer.

In some embodiments, the forming a liner layer covering at least the step structure comprises: forming a liner film covering the stacked structure. And removing the part of the lining film positioned in the array area to form a lining layer.

In some embodiments, the stacked structure includes a plurality of film layer pairs, each film layer pair including an adjacent dielectric layer and a sacrificial layer forming a film layer pair, and each film layer pair forming one step of the stepped structure. In the film layer pair, the dielectric layer is farther away from the substrate relative to the sacrificial layer. In the process of removing the part of the lining film, which is positioned in the array area, the part of the dielectric layer, which is positioned in the film layer pair farthest away from the substrate, is also removed.

In some embodiments, after the modifying treatment of the target portion of the innerliner layer, the method of making further comprises: forming a filling layer covering the stacked structure.

After filling a conductive material in the first cavity and the second cavity to form a gate layer, the preparation method further includes: and forming a plurality of contact columns, wherein each contact column penetrates through the filling layer and is electrically connected with a corresponding gate layer, and the orthographic projection of the contact column on the substrate is positioned in the orthographic projection of the part, positioned in the second cavity, of the gate layer on the substrate.

In some embodiments, the material of the liner layer is the same as the material of the dielectric layer.

In another aspect, a semiconductor structure is provided. The semiconductor structure comprises an array region and a step region, and comprises a substrate, a stacked structure and a plurality of contact columns. The stacked structure is arranged on the substrate and comprises a plurality of dielectric layers and a plurality of gate layers which are alternately arranged. Each gate layer includes a conductive portion extending from the array region to the stepped region, and a contact portion located in the stepped region, the conductive portion being electrically connected to the contact portion. The largest dimension of the contact portion is larger than the largest dimension of the conductive portion in a direction perpendicular to the substrate. A plurality of contact pillars are disposed in the step region, each of the contact pillars being electrically connected to a contact portion of one of the gate layers.

In yet another aspect, a three-dimensional memory is provided. The three-dimensional memory includes: the semiconductor structure as described in the above embodiments.

In yet another aspect, a storage system is provided. The storage system comprises a controller and the three-dimensional memory of the above embodiment, wherein the controller is coupled to the three-dimensional memory and is used for controlling the three-dimensional memory to store data.

In another aspect, an electronic device is provided, which includes the storage system described in the above embodiments.

In some embodiments, the electronic device comprises at least one of: the mobile phone, the desktop computer, the tablet computer, the notebook computer, the server, the vehicle-mounted equipment, the wearable equipment, the portable power source.

It can be understood that the semiconductor structure, the three-dimensional memory, the storage system and the electronic device provided in the embodiments of the disclosure may refer to the above-mentioned advantages of the semiconductor structure, and thus are not described herein again.

Drawings

In order to more clearly illustrate the technical solutions in the present disclosure, the drawings needed to be used in some embodiments of the present disclosure will be briefly described below, and it is apparent that the drawings in the following description are only drawings of some embodiments of the present disclosure, and other drawings can be obtained by those skilled in the art according to the drawings. Furthermore, the drawings in the following description may be regarded as schematic diagrams, and do not limit the actual size of products, the actual flow of methods, the actual timing of signals, and the like, involved in the embodiments of the present disclosure.

FIG. 1 is a block diagram of a semiconductor structure according to some embodiments;

FIG. 2 is a cross-sectional view of the semiconductor structure of FIG. 1 along line A-A';

FIG. 3 is another cross-sectional view of the semiconductor structure shown in FIG. 1 along a sectional line A-A';

FIGS. 4A-4E are flow diagrams of various methods of fabricating semiconductor structures according to some embodiments;

FIGS. 5A-5J are diagrams of steps in the fabrication of a semiconductor structure according to some embodiments;

FIGS. 6A-6E are diagrams of steps for fabricating another semiconductor structure, according to some embodiments;

FIGS. 7A-7J are diagrams of steps for fabricating yet another semiconductor structure, according to some embodiments;

FIG. 8 is a perspective diagram of a three-dimensional memory according to some embodiments;

FIG. 9 is a block diagram of a memory system according to some embodiments;

FIG. 10 is a block diagram of another storage system in accordance with some embodiments;

FIG. 11 is a block diagram of an electronic device according to some embodiments.

Detailed Description

Technical solutions in some embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings, and it is obvious that the described embodiments are only a part of the embodiments of the present disclosure, and not all of the embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments provided by the present disclosure belong to the protection scope of the present disclosure.

In the description of the present disclosure, it is to be understood that the terms "center", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like indicate orientations or positional relationships based on those shown in the drawings, and are only for convenience in describing and simplifying the disclosure, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed in a specific orientation, and be operated, and thus, should not be construed as limiting the disclosure.

Throughout the specification and claims, the term "comprising" is to be interpreted in an open, inclusive sense, i.e., as "including, but not limited to," unless the context requires otherwise. In the description herein, the terms "one embodiment," "some embodiments," "an example embodiment," "exemplary" or "some examples" or the like are intended to mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the disclosure. The schematic representations of the terms used above are not necessarily referring to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be included in any suitable manner in any one or more embodiments or examples.

In the following, the terms "first", "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the embodiments of the present disclosure, "a plurality" means two or more unless otherwise specified.

In describing some embodiments, the expression "connected" and its derivatives may be used. For example, the term "electrically connected" may be used in describing some embodiments to indicate that two or more elements are in direct physical or electrical contact with each other. The embodiments disclosed herein are not necessarily limited to the contents herein.

"A and/or B" includes the following three combinations: a alone, B alone, and a combination of A and B.

Additionally, the use of "based on" means open and inclusive, as a process, step, calculation, or other action that is "based on" one or more stated conditions or values may in practice be based on additional conditions or values beyond those stated.

As used herein, "substantially" includes the stated values as well as average values that are within an acceptable deviation range for the particular value, as determined by one of ordinary skill in the art in view of the measurement in question and the error associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

In the context of this disclosure, the meaning of "on … …," above, "and" over "should be interpreted in the broadest manner such that" on.

Example embodiments are described herein with reference to cross-sectional and/or plan views as idealized example figures. In the drawings, the thickness of layers and regions are exaggerated for clarity. Variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, example embodiments should not be construed as limited to the shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the exemplary embodiments.

As used herein, the term "substrate" refers to a material onto which subsequent layers of material may be added. The substrate itself may be patterned. The material added on the substrate may be patterned or may remain unpatterned. In addition, the substrate may include a variety of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, and the like. Alternatively, the substrate may be made of a non-conductive material such as glass, plastic, or sapphire wafer.

The term "three-dimensional memory" refers to a semiconductor device formed of memory cell transistor strings (referred to herein as "memory cell strings", e.g., NAND memory cell strings) arranged in an array on a major surface of a substrate and extending in a direction perpendicular to the substrate. As used herein, the term "perpendicular" means nominally perpendicular to a major surface (i.e., a lateral surface) of a substrate.

As used in this disclosure, whether a component (e.g., a layer, structure, or device) is "on," "over," or "under" another component (e.g., a layer, structure, or device) of a semiconductor device (e.g., a three-dimensional memory) is determined in a third direction Z relative to a substrate of the semiconductor device when the substrate is located in a lowest plane of the semiconductor device in the third direction Z. Throughout this disclosure, the same concepts are applied to describe spatial relationships.

In the related art, a memory includes a plurality of gate layers arranged in a stack with an insulating layer disposed between adjacent gate layers, thereby forming a stacked structure. With the development of three-dimensional memory technology, the thickness of the stack structure in the memory is thinner, which makes the thickness of the gate layer in the stack structure thinner.

The stacked structure of the memory comprises a plurality of steps in a step area, and a gate layer on the surface of each step is electrically connected with one contact pillar. Because the heights of the step surfaces are different, the lengths of the contact posts electrically connected with different step surfaces are different. In the process of manufacturing the contact pillars with different lengths, contact holes with different depths need to be formed in the stacked structure to expose the gate layers on different step surfaces. By adopting a mask process, in the process of preparing contact holes with different depths, a gate layer positioned at the top of the stack structure is easy to penetrate due to over-etching, and then in the process of forming a contact column in the contact hole, the contact column penetrates through the gate layer and is in short circuit with the gate layer positioned below the gate layer.

In order to avoid the above problems, multiple mask processes can be used to prepare contact holes with different depths, so as to avoid the problem that the gate layer on the top of the stack structure is penetrated due to over-etching, which, however, also increases the preparation cost of the memory.

To solve the above problems, some embodiments of the present disclosure provide a method of manufacturing a semiconductor structure, which is applied to the semiconductor structure 100 illustrated in fig. 1 to 3, the semiconductor structure 100 including an array region a1 and a step region a 2.

As shown in fig. 4A, the method for fabricating the semiconductor structure 100 includes the following steps S10 to S50:

s10: as shown in fig. 5A and 5B, a stacked structure 2 is formed on a substrate 1.

The above-described stacked structure 2 includes a plurality of dielectric layers 21 and a plurality of sacrificial layers 22 alternately stacked, and the stacked structure 2 forms a step structure 20 including a plurality of steps T in the step region a 2.

It should be noted that, as shown in fig. 5B, the stacked structure 2 includes a plurality of film layer pairs 23 (which may also be referred to as sacrificial layer-dielectric layer film layer pairs, such as nitride-oxide film layer pairs), each film layer pair 23 includes an adjacent dielectric layer 21 and a sacrificial layer 22, and each film layer pair 23 forms one step T of the step structure 20. In the pair of film layers 23, the sacrificial layer 22 is farther from the substrate 1 than the dielectric layer 21.

Alternatively, as shown in fig. 7B, the stacked structure 2 includes a plurality of film layer pairs 23 ', each film layer pair 23 ' includes an adjacent dielectric layer 21 and a sacrificial layer 22, and each film layer pair 23 ' forms one step T of the stepped structure 20. In the pair of film layers 23', the dielectric layer 21 is further away from the substrate 1 with respect to the sacrificial layer 22.

S20: as shown in fig. 5C to 5D, the inner liner layer 3 is formed to cover at least the step structure 20.

In some examples, the material of the liner layer 3 is the same as the material of the dielectric layer 21, for example, the material of the liner layer 3 and the material of the dielectric layer 21 both include silicon oxide.

S30: as shown in fig. 5E, the target portion 31 of the inner liner 3 is subjected to modification treatment.

Wherein the target portion 31 of the inner liner 3 includes at least a portion 32 of the inner liner 3 located above a step surface T1 of the plurality of steps T.

It should be noted that the "modification treatment" is to change the properties of the target portion 31 of the liner layer 3 so that the properties of the target portion 31 of the liner layer 3 meet the requirements of being etched by a specific etchant, so as to remove the target portion 31 of the liner layer 3 in a subsequent preparation step. The modification treatment will be specifically described below.

Further, referring to fig. 5E, "step surface T1 of step T" means a surface of step T distant from substrate 1, and step surface T1 is substantially parallel to a plane of substrate 1.

In some examples, as shown in fig. 4B, at S30: after the modification treatment of the target portion 31 of the inner liner 3, the production method further includes S31:

s31: as shown in fig. 5F, a filling layer 4 is formed to cover the stacked structure 2. The filling layer 4 serves to protect the stacked structure 2 and to improve the flatness of the top surface (surface on the side away from the substrate 1) of the stacked structure 2.

In some examples, referring to fig. 1, a plurality of Gate Line Slits (GLS) G are formed on the semiconductor structure 100. Based on this, as shown in fig. 4B, at S31: after forming the filling layer 4 covering the stacked structure 2, the preparation method further includes S32:

s32: a gate line slit G penetrating the stacked structure 2 is formed. In a subsequent manufacturing step, a dielectric material is filled in the gate line slit G to form a gate line isolation pattern, and the gate line isolation pattern may be used to cut each gate electrode layer into a plurality of portions.

S40: as shown in fig. 5F to 5H, the sacrificial layer 22 is removed to form the first cavity 220. And, the target portion 31 of the inner liner 3 is removed to form a second cavity 310, and the first cavity 220 and the second cavity 310 communicate.

It is understood that the gate line slits G penetrate the stacked structure 2, and thus, the gate line slits G may expose the plurality of sacrificial layers 22 in the stacked structure 2, so that the sacrificial layers 22 and the target portion 31 of the liner layer 3 may be etched away through the gate line slits G using an etchant.

In some examples, the material of the sacrificial layer 22 includes silicon nitride, based on which, as shown in fig. 4D, S30: the target portion 31 of the inner liner 3 is subjected to modification processing including the following S301:

s301: a target portion 31 of the liner layer 3 is implanted with nitrogen ions using an ion implantation process.

In the case where the material of the liner layer 3 includes silicon oxide, nitrogen ions are implanted into the target portion 31 of the liner layer 3 by using an ion implantation process, so that the property of the target portion 31 of the liner layer 3 is made close to that of silicon oxynitride, thereby satisfying the condition that the sacrificial layer 22 and the target portion 31 of the liner layer 3 are etched by the same etchant. Accordingly, as shown in fig. 5F to 5H, the sacrificial layer 22 may be removed to form the first cavity 220 and the target portion 31 of the liner layer 3 may be removed to form the second cavity 310 using the same etchant.

For example, phosphoric acid may be used to remove the sacrificial layer 22 to form the first cavity 220 and to remove the target portion 31 of the liner layer 3 to form the second cavity 310.

In some examples, the material of the sacrificial layer 22 includes silicon nitride, and based on this, the above-mentioned "modification treatment" includes a nitridation process, and in the case where the material of the liner layer 3 includes silicon oxide, the target portion 31 of the liner layer 3 is subjected to nitridation treatment by using the nitridation process, so that the property of the target portion 31 of the liner layer 3 is made close to that of silicon nitride, thereby satisfying the condition that the sacrificial layer 22 and the target portion 31 of the liner layer 3 are etched by the same etchant. Accordingly, as shown in fig. 5F to 5H, the sacrificial layer 22 may be removed to form the first cavity 220 and the target portion 31 of the liner layer 3 may be removed to form the second cavity 310 using the same etchant.

It is understood that in the case where the material of the liner layer 3 is the same as the material of the dielectric layer 21, for example, the material of the liner layer 3 and the material of the dielectric layer 21 both include silicon oxide, as shown in fig. 5G and 5H, during the process of removing the sacrificial layer 22 and the target portion 31 of the liner layer 3, the unmodified portion of the liner layer 3 (the isolation portion 33, which will be described in detail later) may remain together with the dielectric layer 21.

S50: as shown in fig. 5H and 5I, a conductive material is filled in the first cavity 220 and the second cavity 310 to form the gate layer 5.

In the related art, after a stacked structure is formed on a substrate, a flat filling layer is directly formed on the stacked structure, then a gate line slit penetrating through the stacked structure is formed, a sacrificial layer in the stacked structure is removed through the gate line slit to form a cavity, and finally a conductive material is filled in the cavity to form a gate electrode layer with uniform thickness.

In the above manufacturing method of the present disclosure, after the stacked structure 2 is formed on the substrate 1, the liner layer 3 at least covering the step structure 20 is formed, and the target portion 31 of the liner layer 3 is modified, so that the property of the target portion 31 of the liner layer 3 meets the requirement of being etched by a specific etchant. Then, the sacrificial layer 22 in the stacked structure 2 is removed to form the first cavity 220, and the target portion 31 of the liner layer 3 is removed to form the second cavity 310. Finally, the first cavity 220 and the second cavity 310 are filled with a conductive material to form the gate layer 5, and since the first cavity 220 is communicated with the second cavity 310, the end of the formed gate layer 5 located in the step region a2 is thicker, i.e., a "step big end" of the gate layer 5 is formed.

In addition, referring to fig. 5J, in the process of preparing the contact holes H with different depths by using a mask process, since the end portion of the gate layer 5 located in the step region a2 is thick, the gate layer 5 is not easily etched through, and the process yield of the device is improved.

It should be noted that in the step of forming the stacked structure 2 on the substrate 1, the structure of the formed stacked structure 2 may be different, and there are some differences in the subsequent preparation methods based on the different stacked structures 2. The following examples will describe two stacked structures 2 and a method of manufacturing based on the two stacked structures 2.

In some examples, as shown in fig. 5B, the stacked structure 2 includes a plurality of film layer pairs 23, each film layer pair 23 includes an adjacent dielectric layer 21 and a sacrificial layer 22, and each film layer pair 23 forms one step T of the stepped structure 20. In the pair of film layers 23, the sacrificial layer 22 is farther from the substrate 1 than the dielectric layer 21.

It is to be understood that, as shown in fig. 5A, in the process of forming the stacked structure 2 on the substrate 1, one dielectric film 21L is formed on the substrate 1, then the sacrificial film 22L is formed on the side of the dielectric film 21L away from the substrate 1, and the foregoing preparation steps are repeated to form a plurality of dielectric films 21L and a plurality of sacrificial films 22L alternately stacked. Then, the plurality of dielectric films 21L and the plurality of sacrificial films 22L are etched using an etching process to form the step structure 20 shown in fig. 5B, that is, the stacked structure 2 is formed.

In the pair of film layers 23, since the sacrifice layer 22 is located farther from the substrate 1 than the dielectric layer 21 and the sacrifice layer 22 serves as a mask for the dielectric layer 21, the orthographic projection of the dielectric layer 21 formed by etching on the substrate 1 substantially coincides with the orthographic projection of the sacrifice layer 22 on the substrate 1.

In some examples, as shown in fig. 4C, the above S20: forming an inner liner layer 3 covering at least the step structure 20, including the following S201 to S202:

s201: as shown in fig. 5C, a liner film 30 is formed to cover the stacked structure 2.

S202: as shown in fig. 5C and 5D, the portion of the liner film 30 located at the array region a1 is removed to form the liner layer 3.

Based on this, as shown in fig. 5E, after the liner layer 3 covering at least the step structure 20 is formed, the target portion 31 of the liner layer 3 (including at least the portion 32 of the liner layer 3 located above the step surfaces T1 of the plurality of steps T) is subjected to the modification treatment, and since the portion 32 of the liner layer 3 located above the step surfaces T1 of the plurality of steps T is in direct contact with the sacrificial layer 22, as shown in fig. 5F to 5H, after the sacrificial layer 22 and the target portion 31 of the liner layer 3 are removed, the first cavity 220 and the second cavity 310 can be directly communicated. Finally, as shown in fig. 5H and 5I, a conductive material is filled in the first cavity 220 and the second cavity 310 to form the gate layer 5.

In the above manufacturing method of the present disclosure, after the stacked structure 2 is formed on the substrate 1, the liner layer 3 at least covering the step structure 20 is formed, and the liner layer 3 is in direct contact with the sacrificial layer 22 in the step T. The target portion 31 of the liner layer 3 is subjected to the modification treatment, and the portion (target portion 31) of the liner layer 3 located above the step surface T1 of the plurality of steps T is in direct contact with the sacrificial layer 22. Then, the sacrificial layer 22 in the stacked structure 2 is removed to form a first cavity 220, and the target portion 31 of the liner layer 3 is removed to form a second cavity 310, the first cavity 220 being in direct communication with the second cavity 310. Finally, the first cavity 220 and the second cavity 310 are filled with a conductive material to form the gate layer 5, a portion of the gate layer 5 located in the second cavity 310 and a portion located in the first cavity 220 form an end portion of the gate layer 5 located in the step region a2, and the end portion has a larger thickness.

In some examples, as shown in fig. 5E, during the modification treatment of the target portion 31 of the liner layer 3, at least a portion of the sidewall of the liner layer 3 covering the plurality of steps T is not modified, forming a plurality of spacers 33. For example, the portions of the liner layer 3 covering the sidewalls of the plurality of steps T are not modified, and the isolation portion 33 is the portion of the liner layer 3 covering the sidewalls of the plurality of steps T.

As shown in fig. 5E, the isolation portion 33 is connected to the dielectric layer 21 under the sacrificial layer 22 corresponding to the isolation portion 33. The "sacrificial layer 22 corresponding to the spacer 33" means the sacrificial layer 22 in the step T covered by the spacer 33, and the sacrificial layer 22 and the dielectric layer 21 located therebelow belong to one film layer pair 23.

With the above arrangement, referring to fig. 5F to 5H, in the process of removing the sacrificial layer 22 and the target portion 31 of the liner layer 3, the isolation portion 33 remains together with the dielectric layer 21, and referring to fig. 5I, the isolation portion 33 is connected to the dielectric layer 21 below the corresponding sacrificial layer 22, and is used for blocking two adjacent gate layers 5 along the direction Z perpendicular to the substrate 1 to insulate the two adjacent gate layers 5.

Also, referring to fig. 5E, the thickness of the liner layer 3 is thin, which facilitates control of the depth of the modification treatment of the target portion 31 of the liner layer 3, and control of the thickness (dimension in the direction Z) of the portion of the liner layer 3 that is not modified, so as to ensure the thickness of the isolation portion 33, thereby ensuring that the isolation portion 33 can block two adjacent gate electrode layers 5 in the direction Z perpendicular to the substrate 1.

In some examples, as shown in fig. 5E, the target portion 31 of the inner liner 3 further includes a portion of the inner liner 3 located above the isolation portion 33, i.e., the target portion 31 includes a portion 32 of the inner liner 3 located above a step surface T1 of the plurality of steps T, and a portion of the inner liner 3 located above the isolation portion 33. It is understood that the range of action of the modification treatment is mainly a portion of the liner layer 3 extending in a direction parallel to the plane of the substrate 1, i.e., the target portion 31 of the liner layer 3 shown in fig. 5E. The target portion 31 of the inner liner 3 forms a shield to the spacer 33 so that the spacer 33 can be not modified.

In some examples, as shown in fig. 4B, S50: after filling the first cavity 220 and the second cavity 310 with the conductive material to form the gate layer 5, the method further includes the following step S51:

s51: as shown in fig. 5J, a plurality of contact pillars 7 are formed.

Each contact pillar 7 penetrates through the filling layer 4 and is electrically connected with the corresponding gate electrode layer 5, and the contact pillars 7 are used for transmitting a voltage signal provided by an external circuit to the gate electrode layer 5 electrically connected with the contact pillars.

Also, as shown in fig. 5H and 5I, an orthogonal projection of the contact stud 7 on the substrate 1 is within an orthogonal projection of a portion of the gate layer 5 located in the second cavity 310 on the substrate 1.

Through the arrangement mode, the contact holes H with different depths can be prepared by adopting a mask process, and the orthographic projection of the contact holes H on the substrate 1 is ensured to be positioned, and the part of the grid layer 5, which is positioned in the second cavity 310, is positioned in the orthographic projection of the substrate 1. Because the end part of the gate layer 5 located in the step area a2 is thick, the gate layer 5 is not easy to etch through, and thus, in the process of forming the contact pillar 7 in the contact hole H, the contact pillar 7 cannot penetrate through the gate layer 5 and is electrically connected with the gate layer 5 located below the contact pillar, and the problem of short circuit between two adjacent gate layers 5 is avoided.

In some examples, as shown in fig. 6A, the liner layer 3 covers the stacked structure 2. In this case, as shown in fig. 4E, at S30: before the modification treatment of the target portion 31 of the inner liner layer 3, the above preparation method further includes the following S21:

s21: as shown in fig. 6B and 6C, a mask layer 6 is formed. The masking layer 6 covers the portion of the liner layer 3 other than the target portion 31 (the masking layer 6 may not cover the isolation portion 33 of the liner layer 3).

It can be understood that, referring to fig. 6C, during the modification process of the target portion 31 of the liner layer 3, the mask layer 6 can block the portion of the liner layer 3 except for the target portion 31, so as to prevent the portion of the liner layer 3 covered by the mask layer 6 from being modified.

Referring to fig. 6D, after the modification process is completed, the mask layer 6 is removed, and then the filling layer 4 covering the stack structure 2 is formed. The material of the liner layer 3 is the same as that of the filling layer 4, and for example, the material of the liner layer 3 and the material of the filling layer 4 both include silicon oxide. Thus, referring to fig. 6D and 6E, during the process of removing the sacrificial layer 22 and the target portion 31 of the liner layer 3, the portion of the liner layer 3 covered by the mask layer 6 may remain together with the filling layer 4, forming the first cavity 220 and the second cavity 310 shown in fig. 6E.

Some embodiments of the present disclosure also provide another stacked structure 2, as shown in fig. 7B, the stacked structure 2 includes a plurality of film layer pairs 23 ' (which may also be referred to as dielectric layer-sacrificial layer film layer pairs, such as oxide-nitride film layer pairs), each film layer pair 23 ' includes an adjacent dielectric layer 21 and a sacrificial layer 22, and each film layer pair 23 ' forms one step T of the stepped structure 20. In the pair of film layers 23', the dielectric layer 21 is further away from the substrate 1 with respect to the sacrificial layer 22.

It is to be understood that, as shown in fig. 7A, in the process of forming the stacked structure 2 on the substrate 1, a sacrificial film 22L is formed on the substrate 1, then a dielectric film 21L is formed on the side of the sacrificial film 22L away from the substrate 1, and the foregoing preparation steps are repeated to form a plurality of dielectric films 21L and a plurality of sacrificial films 22L alternately stacked. Then, the plurality of dielectric films 21L and the plurality of sacrificial films 22L are etched using an etching process to form the step structure 20 shown in fig. 7B, that is, the stacked structure 2 is formed.

In the pair of film layers 23', since the dielectric layer 21 is located farther from the substrate 1 than the sacrifice layer 22 and the dielectric layer 21 is used as a mask for the sacrifice layer 22, the orthographic projection of the dielectric layer 21 formed by etching on the substrate 1 substantially coincides with the orthographic projection of the sacrifice layer 22 on the substrate 1.

In some examples, as shown in fig. 7C, a liner film 30 is formed covering the stacked structure 2. As shown in fig. 7C and 7D, the portion of the liner film 30 located at the array region a1 is removed to form the liner layer 3.

Note that, referring to fig. 7C and 7D, in the process of removing the portion of the liner film 30 located in the array region a1, the portion of the dielectric layer 21 located in the array region a1 in the pair of film layers 23' farthest from the substrate 1, that is, the dielectric layer 21 located on the top of the stacked structure 2 (the portion located in the array region a 1) is also removed. In this way, during the modification process of the target portion 31 of the liner layer 3 (including at least the portion 32 of the liner layer 3 located above the step surface T1 of the plurality of steps T), the dielectric layer 21 (the portion located in the array region a 1) located at the top of the stacked structure 2 can be prevented from being modified, so that a large cavity due to the removal of the dielectric layer 21 (the portion located in the array region a 1) located at the top of the stacked structure 2 during the removal of the sacrificial layer 22 and the target portion 31 of the liner layer 3 can be prevented from being formed, and the strength of the semiconductor structure 100 can be prevented from being reduced.

In some examples, as shown in fig. 7E, in the modification treatment of the target portion 31 of the liner layer 3 (including at least the portion 32 of the liner layer 3 above the step surface T1 of the plurality of steps T), the target portion 210 of the dielectric layer 21 is also subjected to the modification treatment. The target portion 210 of the dielectric layer 21 is a portion of the dielectric layer 21 located between the target portion 31 of the liner layer 3 and the step surface T1 of the plurality of steps T.

It should be noted that, according to the foregoing, the material of the liner layer 3 is the same as the material of the dielectric layer 21 (for example, the material of the liner layer 3 and the material of the dielectric layer 21 both include silicon oxide), and therefore, the "modification process" may also change the property of the target portion 210 of the dielectric layer 21, so that the property of the target portion 210 of the dielectric layer 21 meets the requirement of being etched by a specific etchant, so as to facilitate the removal of the target portion 210 of the dielectric layer 21 in the subsequent preparation step.

In some examples, as shown in fig. 7F to 7H, in the process of removing the sacrificial layer 22 to form the first cavity 220 and removing the target portion 31 of the liner layer 3 to form the second cavity 310, the target portion 210 of the dielectric layer 21 is also removed, forming the third cavity 211.

Wherein, along the direction Z perpendicular to the substrate 1, the third cavity 211 is located between the first cavity 220 and the second cavity 310, and the first cavity 220 and the second cavity 310 are communicated through the third cavity 211.

In some examples, as shown in fig. 7H and 7I, in the process of filling the first cavity 220 and the second cavity 310 with the conductive material, the third cavity 211 is also filled with the conductive material to form the gate layer 5.

According to the preparation method of the present disclosure, after the stacked structure 2 is formed on the substrate 1, the liner layer 3 at least covering the step structure 20 is formed, the liner layer 3 is located on one side of the dielectric layer 21 away from the sacrificial layer 22, and the liner layer 3 is not in direct contact with the sacrificial layer 22 in the step T. In this case, the target portion 31 of the liner layer 3 and the target portion 210 of the dielectric layer 21 are subjected to modification treatment, and then, the sacrificial layer 22 in the stacked structure 2 is removed to form the first cavity 220, the target portion 31 of the liner layer 3 is removed to form the second cavity 310, the target portion 210 of the dielectric layer 21 is removed, and the third cavity 211 is formed, and the first cavity 220 and the second cavity 310 are communicated through the third cavity 211. Finally, the first cavity 220, the second cavity 310 and the third cavity 211 are filled with a conductive material to form the gate layer 5, and the portion of the gate layer 5 located in the second cavity 310 and the third cavity 211 and the portion located in the first cavity 220 form an end portion of the gate layer 5 located in the stepped region a2, thereby further increasing the thickness of the gate layer 5 located at the end portion of the stepped region a 2.

In some examples, as shown in fig. 7E, during the modification treatment of the target portion 31 of the liner layer 3, at least a portion of the sidewall of the liner layer 3 covering the plurality of steps T is not modified, forming a plurality of spacers 33. For example, in the portion of the liner layer 3 covering the side walls of the plurality of steps T, a portion (upper half) distant from the substrate 1 is modified, a portion (lower half) close to the substrate 1 is not modified, and the lower half is the partition 33.

As shown in fig. 7E, the isolation portion 33 is connected to the dielectric layer 21 under the sacrificial layer 22 corresponding to the isolation portion 33. The "sacrificial layer 22 corresponding to the spacer 33" refers to the sacrificial layer 22 in the step T covered by the spacer 33, and the "dielectric layer 21 below the sacrificial layer 22" belongs to the pair of layers 23 'below the pair of layers 23' where the sacrificial layer 22 is located.

With the above arrangement, referring to fig. 7F to 7H, in the process of removing the sacrificial layer 22, the target portion 210 of the dielectric layer 21, and the target portion 31 of the liner layer 3, the isolation portion 33 remains together with the dielectric layer 21, and referring to fig. 7E and 7I, the isolation portion 33 is connected to the dielectric layer 21 under the corresponding sacrificial layer 22, and is used for blocking two adjacent gate layers 5 in the direction Z perpendicular to the substrate 1 to insulate the two adjacent gate layers 5.

In some examples, as shown in fig. 7E, the target portion 31 of the inner liner 3 further includes a portion of the inner liner 3 located above the partition 33, that is, the target portion 31 includes a portion 32 of the inner liner 3 located above a step surface T1 of the plurality of steps T, and a portion of the inner liner 3 located above the partition 33. The target portion 31 of the inner liner 3 is located above the spacer 33, and acts as a shield to the spacer 33, so that the spacer 33 can be left unmodified.

In some examples, after filling the first cavity 220, the second cavity 310, and the third cavity 211 with a conductive material to form the gate layer 5, as shown in fig. 7J, a plurality of contact pillars 7 are formed. Each contact pillar 7 penetrates through the filling layer 4 and is electrically connected with the corresponding gate electrode layer 5, and the contact pillars 7 are used for transmitting a voltage signal provided by an external circuit to the gate electrode layer 5 electrically connected with the contact pillars.

Also, as shown in fig. 7I, an orthogonal projection of the contact post 7 on the substrate 1 is within an orthogonal projection of a portion of the gate layer 5 located in the second cavity 310 on the substrate 1.

Some embodiments of the present disclosure also provide a semiconductor structure, as shown in fig. 2 and 3, the semiconductor structure 100 including an array region a1 and a step region a 2.

As shown in fig. 2 and 3, the semiconductor structure 100 includes a substrate 1, and a stacked structure 2 disposed on the substrate 1. The stack structure 2 includes a plurality of dielectric layers 21 and a plurality of gate layers 5 alternately arranged, each gate layer 5 includes a conductive portion 51 extending from the array region a1 to the stepped region a2, and a contact portion 52 located in the stepped region a2, and the conductive portion 51 is electrically connected to the contact portion 52. The largest dimension of the contact portion 52 is larger than the largest dimension of the conductive portion 51 in a direction Z perpendicular to the substrate 1.

As shown in fig. 2 and 3, the semiconductor structure 100 further includes a plurality of contact pillars 7 disposed in the step region a2, each contact pillar 7 being electrically connected to a corresponding contact portion 52 of one of the gate layers 5.

In the semiconductor structure 100 of the present disclosure, the gate layer 5 includes the conductive portion 51 extending from the array region a1 to the step region a2, and the contact portion 52 located in the step region a2, and a maximum dimension of the contact portion 52 in the direction Z is greater than a maximum dimension of the conductive portion 51 in the direction Z, where the contact portion 52 is an end portion of the gate layer 5 located in the step region a 2. By adopting a mask process, in the process of preparing the contact holes H with different depths, because the thickness of the contact part 52 of the gate layer 5 is larger, the gate layer 5 is not easy to be etched and penetrated, and the process yield of the device is improved.

In some examples, as shown in fig. 2, the semiconductor structure 100 further includes a channel structure 8, the channel structure 8 penetrating the stacked structure 2 and stringing the gate layers 5.

Illustratively, the channel structure 8 includes a memory functional layer and a channel layer formed in sequence, which are disposed adjacent to each other. The memory function layer may be an Oxide-Nitride-Oxide (ONO) stack. For example, the memory function layer includes a blocking layer, a charge storage layer, and a tunneling layer formed by the arrangement.

Referring to fig. 8, fig. 8 is a schematic perspective view of a three-dimensional memory according to some embodiments of the present disclosure.

As shown in fig. 8, the three-dimensional memory 200 includes a stacked structure 2, and the stacked structure 2 has a step profile and includes a plurality of gate layers 5 and insulating layers (not shown in the figure) stacked alternately. The gate layer 5 and the insulating layer extend in the first direction X. In the third direction (direction perpendicular to the substrate 1) Z, the gate layer 5 positioned lowermost of the plurality of gate layers 5 is configured as a source-side select gate SGS, the gate layer 5 positioned uppermost of the plurality of gate layers 5 is configured as a drain-side select gate SGD, the gate layer 5 positioned intermediate of the plurality of gate layers 5 is configured as a plurality of word lines WL (WL1 to WL4), and the source-side select gate SGS, the drain-side select gate SGD, and the word lines WL are collectively referred to as the gate layers 5.

The three-dimensional memory 200 further includes an array of channel structures 8 extending in the third direction Z through the drain side select gate SGD, the word lines WL, and the source side select gate SGS. The channel structure 8 connects the word lines WL of each layer in series to form a memory cell string 80. One memory cell string 80 corresponds to the memory capacity of a plurality of planar memory cells. Therefore, the three-dimensional memory 200 can provide a large storage capacity.

As shown in fig. 8, the three-dimensional memory 200 includes an array of memory cell strings 80 in the X-Y plane.

With continued reference to fig. 8, the three-dimensional memory 200 further includes a source layer 9 located below the source select gate SGS. In some examples, the array of memory cell strings 80 shares the source layer 9.

The three-dimensional memory 200 further includes a drain select gate contact SGD CNT, a source select gate contact SGS CNT, a source contact SL CNT, a word line contact WL CNT, and a bit line contact BL CNT. The drain terminal selection gate contact SGD CNT is electrically connected with the drain terminal selection gate SGD; the source end selection gate contact SGS CNT is electrically connected with the source end selection gate SGS; the source end contact SL CNT is electrically connected with a source end SL; each word line contact WL CNT is electrically connected to one word line WL, whereby the word line contacts WL CNT can be addressed separately in each memory cell string 80; each bitline contact BL CNT is electrically connected to the top of one memory cell string 80, whereby each memory cell string 80 can be individually addressed by the bitline contact BL CNT.

The three-dimensional memory 200 further includes a bit line BL electrically connected to the memory cell string 80 through a bit line contact BL CNT.

As shown in fig. 8, in order to implement the block storage of the storage region of the three-dimensional memory 200, the three-dimensional memory 200 further includes therein a gate line slit G for dividing the stacked structure 2 into a plurality of storage blocks. In some examples, the gate line slit G penetrates the stacked structure 2 in the third direction Z, and extends at least in the first direction X.

The source layer 9 extends in an X-Y plane, and the first direction X and the second direction Y are, for example, two orthogonal directions in the plane of the source layer 9: the first direction X is, for example, an extending direction of the word line WL, and the second direction Y is, for example, an extending direction of the bit line BL. The third direction Z is perpendicular to the source layer 9, i.e. perpendicular to the X-Y plane.

The three-dimensional memory 200 of the present disclosure, including the semiconductor structure 100 according to any of the embodiments, improves the process yield of the device.

As shown in fig. 9 and 10, some embodiments of the present disclosure also provide a storage system 300, the storage system 300 including a controller 301, and the three-dimensional memory 200 as described in any of the above embodiments. The controller 301 may be coupled to the three-dimensional memory 200 and configured to control the three-dimensional memory 200 to store data.

Illustratively, the Storage system 300 described above may be integrated into various types of Storage devices, for example, included in the same package (e.g., Universal Flash Storage (UFS) package or Embedded multimedia Card (eMMC) package). That is, the storage system 300 may be applied to and packaged into different types of electronic products, such as mobile phones, computers (including but not limited to desktop computers, laptop computers, tablet computers, vehicle computers, and the like), televisions, set-top boxes, gaming consoles, printers, positioning devices, in-vehicle devices, wearable electronic devices, smart sensors, Virtual Reality (VR) devices, Augmented Reality (AR) devices, or any other suitable electronic device having storage therein.

Illustratively, as shown in fig. 9, the storage system 300 may include: a controller 301 and a three-dimensional memory 200. The memory system 300 may be integrated into a memory card.

The Memory Card includes any one of a PC Card (PCMCIA), a Compact Flash (CF) Card, a Smart Media (SM) Card, a Memory stick, a Multimedia Card (MMC), a Secure Digital Memory Card (SD), and a UFS.

Illustratively, as shown in fig. 10, the storage system 300 may include: a controller 301 and a plurality of three-dimensional memories 200. The storage system 300 may be integrated into a Solid State Drive (SSD).

In some embodiments, in storage system 300, for example, controller 301 may be configured to operate in a low duty cycle environment, such as an SD card, CF card, Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, mobile phones, and so forth.

As another example, the controller 301 is configured to operate in a high duty cycle environment SSD or eMMC for data storage and enterprise storage arrays of mobile devices such as smart phones, tablets, laptops, and the like.

In some embodiments, the controller 301 may be configured to manage data stored in the three-dimensional memory 200 and communicate with an external device (e.g., a host). In some embodiments, the controller 301 may also be configured to control operations of the three-dimensional memory 200, such as read, erase, and program operations. In some embodiments, the controller 301 may also be configured to manage various functions with respect to data stored or to be stored in the three-dimensional memory 200, including at least one of bad block management, garbage collection, logical-to-physical address translation, wear leveling. In some embodiments, the controller 301 is further configured to process error correction codes with respect to data read from the three-dimensional memory 200 or written to the three-dimensional memory 200.

Of course, the controller 301 may also perform any other suitable function, such as formatting the three-dimensional memory 200. For example, the controller 301 may communicate with an external device (e.g., a host) through at least one of various interface protocols.

It should be noted that the interface protocol includes at least one of a USB protocol, an MMC protocol, a Peripheral Component Interconnect (PCI) protocol, a PCI express (PCI E) protocol, an Advanced Technology Attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a Small Computer System Interface (SCSI) protocol, an Enhanced Small Disk Interface (ESDI) protocol, an Integrated Drive Electronics (IDE) protocol, and a Firewire protocol.

In the above embodiments of the present disclosure, the memory system 300 includes the semiconductor structure 100 or the three-dimensional memory 200 provided in any of the above embodiments, so that the process yield of manufacturing a device is improved.

Some embodiments of the present disclosure also provide an electronic device, as shown in fig. 11, the electronic device 400 including the storage system 300 as described in the above embodiments.

In the above embodiments of the present disclosure, the electronic device 400 includes the memory system 300 provided in the above embodiments, so that the process yield of manufacturing devices is improved.

Illustratively, the electronic device 400 described above includes at least one of: the mobile phone, the desktop computer, the tablet computer, the notebook computer, the server, the vehicle-mounted equipment, the wearable equipment, the portable power source.

The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.

Claims

1. The preparation method of the semiconductor structure is characterized in that the semiconductor structure comprises an array region and a step region;

the preparation method comprises the following steps:

forming a stacked structure on a substrate; the stacked structure comprises a plurality of dielectric layers and a plurality of sacrificial layers which are alternately stacked, and the stacked structure forms a step structure comprising a plurality of steps in the step area;

forming a lining layer at least covering the step structure;

modifying a target portion of the liner layer; the target part of the lining layer at least comprises a part of the lining layer, which is positioned above the step surfaces of the steps;

removing the sacrificial layer to form a first cavity; removing a target portion of the liner layer to form a second cavity; the first cavity is communicated with the second cavity;

and filling a conductive material in the first cavity and the second cavity to form a gate layer.

2. The method of claim 1, wherein the stacked structure comprises a plurality of film layer pairs, each film layer pair comprising an adjacent dielectric layer and a sacrificial layer, and each film layer pair forming one step of the stepped structure; in the film layer pair, the dielectric layer is farther away from the substrate relative to the sacrificial layer;

in the process of modifying the target part of the lining layer, modifying the target part of the dielectric layer; the target portion of the dielectric layer is a portion of the dielectric layer located between the target portion of the liner layer and the step surfaces of the plurality of steps.

3. The method of claim 2, wherein during the removing the sacrificial layer to form a first cavity and the removing the target portion of the liner layer to form a second cavity, the target portion of the dielectric layer is also removed to form a third cavity;

wherein, along the direction perpendicular to the substrate, the third cavity is located between the first cavity and the second cavity, and the first cavity and the second cavity are communicated through the third cavity.

4. The method according to claim 3, wherein a conductive material is further filled in the third cavity during the filling of the conductive material in the first cavity and the second cavity.

5. The method of claim 1, wherein the stacked structure comprises a plurality of film layer pairs, each film layer pair comprising an adjacent dielectric layer and a sacrificial layer, and each film layer pair forming one step of the stepped structure; in the film layer pair, the sacrificial layer is farther away from the substrate relative to the dielectric layer;

the first cavity and the second cavity are in direct communication.

6. The production method according to claim 1, wherein a material of the sacrificial layer includes silicon nitride;

the modification treatment of the target part of the lining layer comprises the following steps:

injecting nitrogen ions into the target part of the lining layer by adopting an ion injection process;

and removing the sacrificial layer to form a first cavity, and removing a target part of the lining layer to form a second cavity by using the same etchant.

7. The method according to claim 1, wherein the material of the sacrificial layer comprises silicon nitride, and the modification treatment comprises a nitridation process;

8. The production method according to claim 1, characterized in that, in the process of modifying a target portion of the inner liner layer, at least a portion of a side wall of the inner liner layer covering the plurality of steps is not modified to form a plurality of partitions;

wherein the isolation portion is connected with the dielectric layer below the sacrificial layer corresponding to the isolation portion.

9. The method of making as defined in claim 8, wherein the target portion of the innerliner layer further includes a portion of the innerliner layer that is above the partition.

10. The manufacturing method according to any one of claims 1 to 9, characterized in that the inner liner covers the stacked structure;

before the modifying treatment is performed on the target portion of the inner liner layer, the preparation method further includes:

forming a mask layer; the mask layer covers a portion of the liner layer except for a target portion.

11. The manufacturing method according to any one of claims 1 to 9, wherein the forming of the inner liner layer covering at least the step structure includes:

forming a liner film covering the stacked structure;

and removing the part of the lining film positioned in the array area to form a lining layer.

12. The method of claim 11, wherein the stacked structure comprises a plurality of film layer pairs, each film layer pair comprising an adjacent dielectric layer and a sacrificial layer forming a film layer pair, and each film layer pair forming one step of the step structure; in the film layer pair, the dielectric layer is farther away from the substrate relative to the sacrificial layer;

in the process of removing the portion of the lining film located in the array region, the portion of the dielectric layer in the film layer pair farthest from the substrate located in the array region is also removed.

13. The production method according to any one of claims 1 to 9, characterized by further comprising, after the modification treatment of the target portion of the inner liner layer:

forming a filling layer covering the stacked structure;

after filling a conductive material in the first cavity and the second cavity to form a gate layer, the preparation method further includes:

forming a plurality of contact pillars; each contact pillar penetrates through the filling layer and is electrically connected with the corresponding gate layer, and the orthographic projection of the contact pillar on the substrate is positioned in the orthographic projection of the part, located in the second cavity, of the gate layer on the substrate.

14. The preparation method according to any one of claims 1 to 9, characterized in that the material of the inner liner layer is the same as the material of the dielectric layer.

15. A semiconductor structure, comprising an array region and a step region;

the semiconductor structure includes:

a substrate;

a stack structure disposed on the substrate, including a plurality of dielectric layers and a plurality of gate layers alternately disposed; each gate layer comprises a conductive part extending from the array region to the step region and a contact part located in the step region, wherein the conductive part is electrically connected with the contact part; a maximum dimension of the contact portion is larger than a maximum dimension of the conductive portion in a direction perpendicular to the substrate;

a plurality of contact pillars disposed in the step region; each contact pillar is electrically connected to a contact portion of one gate layer.

16. A three-dimensional memory comprising the semiconductor structure of claim 15.

17. A memory system, comprising the three-dimensional memory of claim 16 and a controller, the controller coupled to the three-dimensional memory and configured to control the three-dimensional memory to store data.

18. An electronic device, comprising: the storage system of claim 17.

19. The electronic device of claim 18, wherein the electronic device comprises at least one of: the mobile phone, the desktop computer, the tablet computer, the notebook computer, the server, the vehicle-mounted equipment, the wearable equipment, the portable power source.