CN113921524A

CN113921524A - Semiconductor structure and preparation method thereof, integrated circuit, three-dimensional memory and system

Info

Publication number: CN113921524A
Application number: CN202111039790.0A
Authority: CN
Inventors: 张权; 姚兰; 石艳伟
Original assignee: Yangtze Memory Technologies Co Ltd
Current assignee: Yangtze Memory Technologies Co Ltd
Priority date: 2021-09-06
Filing date: 2021-09-06
Publication date: 2022-01-11

Abstract

The invention provides a semiconductor structure, a manufacturing method thereof, an integrated circuit, a three-dimensional memory and a system, relates to the technical field of semiconductor chips, and aims to reduce the process difficulty of etching a gate conducting layer to form a gate. The semiconductor structure comprises a substrate and a high-voltage transistor arranged in a first area of the substrate, wherein the high-voltage transistor comprises a first source electrode, a first drain electrode, a first gate dielectric layer, a first grid electrode and a first protective layer. The first gate dielectric layer comprises a first part covering the first source electrode and the first drain electrode and a second part staggered with the first source electrode and the first drain electrode, and the thickness of the first part is smaller than that of the second part; the first grid is arranged on one side of the second part far away from the substrate; the first protective layer covers the surface of the first grid electrode, which is far away from the substrate, and the thickness of the first protective layer is smaller than that of the second part. The semiconductor structure is applied to a three-dimensional memory to realize reading and writing operations of data.

Description

Semiconductor structure and preparation method thereof, integrated circuit, three-dimensional memory and system

Technical Field

The present disclosure relates to the field of semiconductor chip technologies, and in particular, to a semiconductor structure, a method for manufacturing the same, an integrated circuit, a three-dimensional memory, and a system.

Background

As the feature size of memory cells approaches the lower process limit, planar processes and manufacturing techniques become challenging and costly, which causes the storage density of 2D or planar NAND flash memories to approach the upper limit. To overcome the limitations imposed by 2D or planar NAND flash memories, memories having a three-dimensional structure (3D NAND) have been developed to increase the storage density by arranging memory cells three-dimensionally over a substrate.

In the 3D NAND, a peripheral circuit is used to perform logic operations and control and detect the on-off state of each memory cell string to implement data storage and reading. The peripheral circuit usually employs a symmetric or asymmetric Metal Oxide Semiconductor (MOS) Field Effect Transistor (FET), and in order to fully exert the advantages of high speed of the low-voltage Transistor and high withstand voltage of the high-voltage Transistor, the peripheral circuit has both the low-voltage Transistor and the high-voltage Transistor.

However, in the peripheral circuit, the process window between the protective layers on the upper sides of the gates of the adjacent transistors is small, so that when the protective layers are used as masks to etch the gate conductive layer to form the gate, the process difficulty is high, and the equipment requirement is high.

Disclosure of Invention

The embodiment of the disclosure provides a semiconductor structure, a manufacturing method thereof, an integrated circuit, a three-dimensional memory and a system, and aims to reduce the process difficulty of etching a gate conductive layer to form a gate.

In order to achieve the purpose, the embodiment of the disclosure adopts the following technical scheme:

in one aspect, a semiconductor structure is provided. The semiconductor structure includes a substrate and a high voltage transistor. The substrate includes a first region. The high-voltage transistor is arranged in the first area and comprises a first source electrode, a first drain electrode, a first grid dielectric layer, a first grid electrode and a first protective layer. The first source electrode and the first drain electrode are arranged at intervals and extend from the first surface of the substrate into the substrate; the first surface is one of two opposing major surfaces of the substrate. The first gate dielectric layer is arranged on the first surface of the substrate; the first gate dielectric layer comprises a first part covering the first source electrode and the first drain electrode and a second part staggered with the first source electrode and the first drain electrode, and the thickness of the first part is smaller than that of the second part. The first gate is disposed on a side of the second portion away from the substrate. The first protective layer covers the surface of the first grid electrode far away from the substrate, and the thickness of the first protective layer is smaller than that of the second portion.

In the semiconductor structure provided by the above embodiment of the present disclosure, the thickness of the first portion of the first gate dielectric layer is smaller than the thickness of the second portion of the first gate dielectric layer, that is, the thickness of the first gate dielectric layer above the first source and the first drain of the high-voltage transistor is smaller than the thickness of the first gate dielectric layer below the first gate of the high-voltage transistor. Compared with the prior art, in the process of forming the first source electrode and the first drain electrode by carrying out ion doping on the substrate, the thickness of the first gate dielectric layer above the first source electrode and the first drain electrode of the high-voltage transistor is reduced, so that the thickness of the first protective layer can be correspondingly reduced on the premise of ensuring that the first protective layer prevents ions from being injected into the first gate electrode. That is, the thickness of the first protective layer is smaller than the thickness of the second portion. The thickness of the first protection layer is reduced, namely the thickness of the protection film for forming the first protection layer is reduced, so that a process window between a plurality of protection layers (including the first protection layer) formed by patterning the protection film is enlarged, the process difficulty of etching the gate conductive layer to form the gate by taking the protection layer as a mask is reduced, and the equipment requirement is reduced.

In some embodiments, the high voltage transistor further includes a first gate spacer covering a side surface of the first gate.

In some embodiments, an outer boundary of an orthographic projection of the first gate sidewall on the substrate coincides with a boundary of an orthographic projection of the second portion on the substrate.

In some embodiments, the material of the first gate sidewall spacer comprises silicon nitride.

In some embodiments, the thickness of the first protective layer is 5nm to 6nm less than the thickness of the second portion.

In some embodiments, the material of the first protective layer comprises silicon nitride; and/or the material of the first gate dielectric layer comprises silicon oxide.

In some embodiments, the substrate further comprises a second region. The semiconductor device structure further comprises a low-voltage transistor, wherein the low-voltage transistor is arranged in the second area. The low-voltage transistor comprises a second source electrode, a second drain electrode, a second grid dielectric layer, a second grid electrode and a second protective layer. The second source electrode and the second drain electrode are arranged at intervals and extend from the first surface of the substrate into the substrate. The second gate dielectric layer is arranged on the first surface of the substrate, and the thickness of the second gate dielectric layer is equal to that of the first portion. The second grid electrode is arranged on one side, far away from the substrate, of the second grid dielectric layer. The second protective layer covers the surface of the second grid electrode far away from the substrate.

In some embodiments, the low voltage transistor further includes a second gate sidewall covering a side surface of the second gate.

In another aspect, a method for fabricating a semiconductor structure is provided, including:

preparing an intermediate semiconductor structure; the intermediate semiconductor structure includes a first region; the intermediate semiconductor structure comprises a substrate, a gate insulating film arranged on the first surface of the substrate, a first grid arranged on one side, far away from the substrate, of the gate insulating film, and a first protective layer covering the surface, far away from the substrate, of the first grid. The first surface is one of two opposing major surfaces of the substrate; the first grid electrode is positioned in the first area, and the thickness of the first protective layer is smaller than that of the part, positioned below the first grid electrode, in the grid insulating film.

Etching the part of the gate insulating film, which is positioned in the target area, so that the thickness of the part of the gate insulating film, which is positioned in the target area, is reduced to the target thickness; the target region is a region of the first region not covered by the first gate.

In some embodiments, the etching of the portion of the gate insulating film in the target region uses a chemical gas etching process.

In some embodiments, the preparing the intermediate semiconductor structure comprises: forming a gate insulating film on a first surface of the substrate; forming a gate conductive layer on one side of the gate insulating film, which is far away from the substrate; forming the first protective layer on one side of the gate conductive layer away from the substrate; the orthographic projection of the first protective layer on the substrate is a region corresponding to the first grid electrode which is formed in a preset mode; and etching the gate conductive layer by taking the first protective layer as a mask to form the first gate.

In some embodiments, the intermediate semiconductor structure further includes a second region, and in the process of forming the first protection layer on the side of the gate conductive layer away from the substrate, a second protection layer is further formed, and an orthographic projection of the second protection layer on the substrate is a region corresponding to a second gate electrode which is formed in advance. In the process of etching the gate conductive layer by taking the first protective layer as a mask to form the first gate, etching the gate conductive layer by taking the second protective layer as a mask to form the second gate; the second gate is located in the second region.

In some embodiments, the forming of the gate insulating film on the first surface of the substrate includes: forming an initial gate insulating film on a first surface of the substrate; and thinning the thickness of the part of the initial gate insulating film, which is positioned in the second area, to form the gate insulating film.

In some embodiments, the target thickness is equal to a thickness of a portion of the gate insulating film covering the second region.

In some embodiments, between the preparing the intermediate semiconductor structure and the etching the portion of the gate thin film located in the target region, the preparing method further comprises: and forming a photoresist layer covering the second region.

In some embodiments, before the forming a photoresist layer covering the second region, the method of preparing further comprises: and forming a first grid side wall covering the side surface of the first grid and a second grid side wall covering the side surface of the second grid.

In some embodiments, after the etching the portion of the gate insulating film located in the target region, the method further includes: and removing the photoresist layer. And carrying out ion doping on the substrate, forming a first source electrode and a first drain electrode on two sides of the first grid electrode in the target area, and forming a second source electrode and a second drain electrode on two sides of the second grid electrode in the second area.

In yet another aspect, an integrated circuit is provided. The integrated circuit includes a semiconductor structure that is or is prepared by a method of making a semiconductor structure as described in some embodiments above.

In yet another aspect, a three-dimensional memory is provided. The three-dimensional memory includes an integrated circuit as described in some embodiments above and a memory array device coupled to the integrated circuit.

In yet another aspect, a storage system is provided. The storage system includes a three-dimensional memory as described in some embodiments above and a controller coupled to the three-dimensional memory to control the three-dimensional memory to store data.

It can be understood that the beneficial effects of the method for manufacturing a semiconductor structure, the integrated circuit, the three-dimensional memory and the memory system provided by the embodiments of the disclosure can refer to the beneficial effects of the semiconductor structure described above, and are not described herein again.

Drawings

In order to more clearly illustrate the technical solutions in the present disclosure, the drawings needed to be used in some embodiments of the present disclosure will be briefly described below, and it is apparent that the drawings in the following description are only drawings of some embodiments of the present disclosure, and other drawings can be obtained by those skilled in the art according to the drawings. Furthermore, the drawings in the following description may be regarded as schematic diagrams, and do not limit the actual size of products, the actual flow of methods, the actual timing of signals, and the like, involved in the embodiments of the present disclosure.

FIG. 1 is a block diagram of a storage system according to some embodiments;

FIG. 2 is a block diagram of a memory system according to further embodiments;

FIG. 3 is a cross-sectional view of a device structure during fabrication of a semiconductor structure according to the related art;

FIG. 4 is a cross-sectional view of a three-dimensional memory according to some embodiments;

FIG. 5 is a top view of an integrated circuit (peripheral circuitry) of a three-dimensional memory according to some embodiments;

FIG. 6 is a cross-sectional view of the peripheral circuit shown in FIG. 5 along section line AA';

FIG. 7 is a cross-sectional view of the peripheral circuit shown in FIG. 5 along section line BB';

FIG. 8 is a flow chart of a method of fabricating a semiconductor structure according to some embodiments;

FIG. 9 is a diagram of a manufacturing step of the manufacturing method shown in FIG. 8;

FIG. 10 is a diagram of a manufacturing step of the manufacturing method shown in FIG. 8;

FIG. 11 is a diagram of a manufacturing step of the manufacturing method shown in FIG. 8;

FIG. 12 is a flow chart of a method of fabricating a semiconductor structure according to some embodiments;

FIG. 13 is a diagram of a manufacturing step of the manufacturing method shown in FIG. 12;

FIG. 14 is a diagram of a manufacturing step of the manufacturing method shown in FIG. 12;

FIG. 15 is a diagram of a manufacturing step of the manufacturing method shown in FIG. 12;

FIG. 16 is a diagram of a manufacturing step of the manufacturing method shown in FIG. 12;

FIG. 17 is a diagram of a manufacturing step of the manufacturing method shown in FIG. 12;

FIG. 18 is a flow chart of a method of fabricating a semiconductor structure according to some embodiments;

FIG. 19 is a flow chart of a method of fabricating a semiconductor structure according to some embodiments;

FIG. 20 is a flow chart of a method of fabricating a semiconductor structure according to some embodiments;

FIG. 21 is a diagram of a manufacturing step of the manufacturing method shown in FIG. 20;

FIG. 22 is a flow chart of a method of fabricating a semiconductor structure according to some embodiments;

FIG. 23 is a view showing a production step of the production method shown in FIG. 22;

FIG. 24 is a diagram of a manufacturing step of the manufacturing method shown in FIG. 22;

FIG. 25 is a flow chart of a method of fabricating a semiconductor structure according to some embodiments;

FIG. 26 is a flow chart of a method of fabricating a semiconductor structure according to some embodiments;

figure 27 is a flow chart of a method of fabricating a semiconductor structure according to some embodiments.

Detailed Description

Technical solutions in some embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings, and it is obvious that the described embodiments are only a part of the embodiments of the present disclosure, and not all of the embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments provided by the present disclosure belong to the protection scope of the present disclosure.

In the description of the present disclosure, it is to be understood that the terms "center", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like indicate orientations or positional relationships based on those shown in the drawings, and are only for convenience in describing and simplifying the disclosure, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed in a specific orientation, and be operated, and thus, should not be construed as limiting the disclosure.

Throughout the specification and claims, the term "comprising" is to be interpreted in an open, inclusive sense, i.e., as "including, but not limited to," unless the context requires otherwise. In the description herein, the terms "one embodiment," "some embodiments," "an example embodiment," "exemplary" or "some examples" or the like are intended to mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the disclosure. The schematic representations of the above terms are not necessarily referring to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be included in any suitable manner in any one or more embodiments or examples.

In the following, the terms "first", "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the embodiments of the present disclosure, "a plurality" means two or more unless otherwise specified.

In describing some embodiments, expressions of "coupled" and "connected," along with their derivatives, may be used. For example, the term "connected" may be used in describing some embodiments to indicate that two or more elements are in direct physical or electrical contact with each other. As another example, some embodiments may be described using the term "coupled" to indicate that two or more elements are in direct physical or electrical contact. The term "coupled," however, may also mean that two or more elements are not in direct contact with each other, but yet still co-operate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents herein.

"at least one of A, B and C" has the same meaning as "A, B or at least one of C," each including the following combination of A, B and C: a alone, B alone, C alone, a and B in combination, a and C in combination, B and C in combination, and A, B and C in combination.

"A and/or B" includes the following three combinations: a alone, B alone, and a combination of A and B.

As used herein, "about," "approximately," or "approximately" includes the stated values as well as average values that are within an acceptable range of deviation for the particular value, as determined by one of ordinary skill in the art in view of the measurement in question and the error associated with measurement of the particular quantity (i.e., the limitations of the measurement system).

In the context of this disclosure, the meaning of "on … …," above, "and" over "should be interpreted in the broadest manner such that" on.

Example embodiments are described herein with reference to cross-sectional and/or plan views as idealized example figures. In the drawings, the thickness of layers and regions are exaggerated for clarity. Variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, the exemplary embodiments should not be construed as limited to the shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the exemplary embodiments.

As used herein, the term "substrate" refers to a material onto which subsequent layers of material may be added. The substrate itself may be patterned. The material added on the substrate may be patterned or may remain unpatterned. In addition, the substrate may include a variety of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, and the like. Alternatively, the substrate may be made of a non-conductive material such as glass, plastic, or sapphire wafer.

The term "three-dimensional memory" refers to a semiconductor device formed of memory cell transistor strings (referred to herein as "memory cell strings", e.g., NAND memory cell strings) arranged in an array on a major surface of a substrate and extending in a direction perpendicular to the substrate. As used herein, the term "perpendicular" means nominally perpendicular to a major surface (i.e., a lateral surface) of a substrate.

Fig. 3 is a cross-sectional view of a device structure of a semiconductor structure 100' in a fabrication process in accordance with the related art.

As shown in fig. 3, the semiconductor structure 100 ' includes a substrate 110 ' and a plurality of transistors formed on the substrate 110 ', for example, a High Voltage (HV) MOS, a Low Voltage (LV) MOS, and an LLV (LLV) MOS.

In order to meet the performance requirements of each transistor, the thickness of the gate dielectric layer of different MOS transistors may be different. For example, as shown in FIG. 3, the gate dielectric layer 120 'of the HV MOS is thicker than the gate dielectric layer 121' of the LV MOS and the LLV MOS.

In order to ensure that the process of forming the source and drain electrodes by ion doping does not influence the grid electrode, a protective layer is arranged on the upper side of the grid electrode. In the related art, as shown in fig. 1, the thickness of the protection layer 140 'on the upper side of the gate 130' of the HV MOS is thicker, and is usually greater than or approximately equal to the thickness of the gate dielectric layer 120 'of the HV MOS, so as to ensure that the subsequent process of forming the source/drain by ion doping does not affect the gate 130'.

In the process of forming the gate of the MOS transistor, the protective layer 140 'having the pattern of the gate to be formed is first formed by etching, and then the gate conductive layer below is etched using the protective layer 140' as a mask to form the gate. However, during the process of forming the protection layer 140 ' by etching, the process window between the protection layers 140 ' of adjacent MOS transistors is small due to the large thickness of the protection layer 140 '. Since the side surface of the protection layer 140 'formed by etching is a slope, the opening at the end close to the gate conductive layer below in the process window between the adjacent protection layers 140' is smaller than the opening at the end far from the gate conductive layer. Thus, when the gate 130 'is formed by etching the gate conductive layer using the passivation layer 140' as a mask, the process difficulty is high and the equipment requirement is high.

Based on this, referring to fig. 6, some embodiments of the present disclosure provide a semiconductor structure 100, where the semiconductor structure 100 includes a substrate 110, a high voltage transistor 120, and a low voltage transistor 130. The low voltage transistor 130 may also be a low voltage transistor, and the disclosure is not limited thereto.

It is noted that the semiconductor structure 100 provided by the embodiments of the present disclosure may be used to construct peripheral devices in a three-dimensional memory. Referring to fig. 4, fig. 4 shows a cross-sectional structure of a three-dimensional memory 300, wherein the three-dimensional memory 300 includes a memory array device 400 and an integrated circuit 200 (i.e., the peripheral devices) electrically connected to each other. Referring to fig. 5, fig. 5 shows a top view of the integrated circuit 200, and it can be seen that the integrated circuit 200 includes at least one of the semiconductor structures 100.

Fig. 6 shows a cross-sectional structure of the integrated circuit 200 of fig. 5 along a section line AA'. Referring to fig. 6, the substrate 110 includes a first region HV, a second region LV, and an isolation region S configured to electrically isolate the first region HV and the second region LV from at least a portion of transistors adjacent all around. Illustratively, the isolation region S of the substrate 110 is provided with an isolation groove extending from the first surface 111 of the substrate 110 into the substrate 110 to divide the substrate 110 into a first region HV and a second region LV, the first surface 111 being one of two opposite main surfaces of the substrate 110. Wherein the isolation grooves are filled with an insulating material to form isolation structures 112, thereby electrically isolating the first and second regions HV and LV from the neighboring transistors. The substrate 110 may be made of at least one of silicon, silicon germanium, and a silicon-on-insulator thin film, but is not limited thereto.

It should be noted that, a distance may be left between the boundary of the isolation region S and the boundary of the first region HV and the boundary of the second region LV, or may be directly adjacent to each other, which is not limited in this disclosure. The first region HV is a high voltage region configured to dispose a high voltage device, for example, the high voltage transistor 120; the second region LV is a low voltage region configured to provide low voltage devices, for example, a low voltage transistor 130.

The high voltage transistor 120 is disposed in the first region HV, the high voltage transistor 120 includes a first source 121, a first drain 122, a first gate dielectric layer 123, a first gate 124, and a first protection layer 125, and the first source 121 and the first drain 122 are disposed at an interval and extend from the first surface 111 of the substrate 110 into the substrate 110.

The first gate dielectric layer 123 is disposed on the first surface 111 of the substrate 110, the first gate dielectric layer 123 includes a first portion 1231 covering the first source 121 and the first drain 122, and a second portion 1232 disposed to be offset from the first source 121 and the first drain 122, and a thickness of the first portion 1231 is smaller than a thickness of the second portion 1232. This can ensure that the thickness of the first gate dielectric layer 123 above the first source 121 and the first drain 122 is reduced under the condition that the performance requirement of the high voltage transistor 120 is satisfied, so that ions can penetrate through the first portion 1231 of the first gate dielectric layer 123 and be implanted into the substrate 110 to form the first source 121 and the first drain 122.

The first gate 124 is disposed on a side of the second portion 1232 of the first gate dielectric layer 123 away from the substrate 110; the first protection layer 125 covers a surface of the first gate 124 away from the substrate 110. The first protection layer 125 may serve as a mask for forming the first gate 124, and may protect the first gate 124 at a surface of the first gate 124 away from the substrate 110 during the process of forming the first source 121 and the first drain 122, so as to prevent ion implantation into the first gate 124. Wherein the thickness of the first protection layer 125 is less than the thickness of the second portion 1232 of the first gate dielectric layer 123.

As can be seen from the above description, in the semiconductor structure 100 provided by the above embodiments of the present disclosure, the thickness of the first portion 1231 of the first gate dielectric layer 123 is smaller than the thickness of the second portion 1232 of the first gate dielectric layer 123, that is, the thickness of the first gate dielectric layer 123 under the first source 121 and the first drain 122 of the high-voltage transistor 120 is smaller than the thickness of the first gate dielectric layer 123 over the first gate 124 of the high-voltage transistor 120.

Compared with the related art, in the process of forming the first source electrode 121 and the first drain electrode 122 by ion doping the substrate 110, since the thickness of the first gate dielectric layer 123 above the first source electrode 121 and the first drain electrode 122 of the high-voltage transistor 120 is reduced, the thickness of the first protection layer 125 can be reduced correspondingly on the premise that the first protection layer 125 is ensured to prevent ion implantation into the first gate electrode 124. That is, the thickness of the first protection layer 125 is less than the thickness of the second portion 1232 of the first gate dielectric layer 123.

Fig. 7 shows a cross-sectional structure of the integrated circuit 200 of fig. 5 along a section line BB'. Referring to fig. 7, since the thickness of the first protection layer 125 is smaller than the thickness of the second portion 1232 of the first gate dielectric layer 123, the thickness of the first protection layer 125 is reduced, that is, the thickness of the protection film used for forming the first protection layer 125 is reduced, so that the process window between the plurality of protection layers (including the first protection layer 125) formed by patterning the protection film is enlarged, thereby reducing the process difficulty of forming the gate (including the first gate 124) by etching the gate conductive layer using the protection layer as a mask, and reducing the equipment requirement.

As shown in fig. 6, the low voltage transistor 130 is disposed in the second region LV, the low voltage transistor 130 includes a second source 131, a second drain 132, a second gate dielectric layer 133, a second gate 134 and a second passivation layer 135, and the second source 131 and the second drain 132 are disposed at an interval and extend from the first surface 111 of the substrate 110 into the substrate 110.

The second gate dielectric layer 133 is disposed on the first surface 111 of the substrate 110, and the thickness of the second gate dielectric layer 133 is substantially equal to the thickness of the first portion 1231 of the first gate dielectric layer 123, so that the second gate dielectric layer 133 and the first gate dielectric layer 123 may be made of the same material and manufactured in the same process, thereby simplifying the process steps.

It should be noted that the material of the first gate dielectric layer 123 and the second gate dielectric layer 133 includes silicon oxide, but is not limited thereto.

The second gate 134 is disposed on a side of the second gate dielectric layer 123 away from the substrate 110, and the second protective layer 135 covers a surface of the second gate 134 away from the substrate 110. The second protective layer 135 may serve as a mask for forming the second gate 134, and may protect the second gate 134 at a surface of the second gate 134 away from the substrate 110 during the process of forming the second source 131 and the second drain 132.

Referring to fig. 6, in some embodiments, the thickness of the first protective layer 125 is 5nm to 6nm less than the thickness of the second portion 1232 of the first gate dielectric layer 123. For example, the thickness of the first protective layer 125 is less than the thickness of the second portion 1232 of the first gate dielectric layer 123 by any one of 5nm, 5.2nm, 5.4nm, 5.6nm, 5.8nm, and 6 nm.

In addition, the thickness of the first protection layer 125 is greater than the thickness of the first portion 1231 of the first gate dielectric layer 123, so as to prevent the first protection layer 125 from being too thin to effectively protect the first gate 124.

Similarly, the thickness of the second passivation layer 135 is greater than that of the second gate dielectric layer 133, so as to prevent the second passivation layer 135 from being too thin to effectively protect the second gate 134.

In some embodiments, the material of the first protective layer 125 and the second protective layer 135 includes, but is not limited to, silicon nitride. For example, the materials of the first protection layer 125 and the second protection layer 135 are the same, and the thicknesses of the first protection layer 125 and the second protection layer 135 are substantially equal, so that the first protection layer 125 and the second protection layer 135 can be manufactured by using the same materials and using the same process, thereby simplifying the process steps.

In the process of forming the first gate dielectric layer 123, and in the process of forming the first source electrode 121 and the first drain electrode 122, in order to protect the first gate electrode 124 at the side of the first gate electrode 124 and prevent a large amount of ions from being implanted into the substrate 110, the first source electrode 121 and the first drain electrode 122 are too close to the channel, so that the channel is too short, and even the first source electrode 121 and the first drain electrode 122 are connected. Referring to fig. 6, in some embodiments, the high voltage transistor 120 further includes a first gate sidewall spacer 126, and the first gate sidewall spacer 126 covers a side surface of the first gate 124. The first gate sidewall spacer 126 may have a single-layer structure or a stacked structure. Illustratively, the first gate sidewall spacers 126 have a single-layer structure, and the material of the first gate sidewall spacers 126 includes silicon nitride.

In some embodiments, an outer boundary of an orthographic projection of the first gate sidewall spacer 126 on the substrate 110 substantially coincides with an outer boundary of an orthographic projection of the second portion 1232 of the first gate dielectric layer 123 on the substrate 110.

In the process of forming the second gate dielectric layer 133 and in the process of forming the second source 131 and the second drain 132, in order to protect the second gate 134 at the side of the second gate 134 and prevent a large amount of ions from being implanted into the substrate 110, the second source 131 and the second drain 132 are too close to the channel, so that the channel is too short, and even the second source 131 and the second drain 132 are connected. Referring to fig. 6, in some embodiments, the low voltage transistor 120 further includes a second gate sidewall spacer 136, and the second gate sidewall spacer 136 covers a side surface of the second gate 134. The second gate sidewall spacer 136 may have a single-layer structure or a stacked structure. Illustratively, the second gate sidewall spacers 136 have a single-layer structure, and the material of the second gate sidewall spacers 136 includes silicon nitride.

As shown in fig. 6, in some embodiments, the semiconductor structure 100 further includes a gate oxide layer 140, and the gate oxide layer 140 is disposed on a side of the first protective layer 125 and the second protective layer 135 away from the substrate 110 to protect the first gate 123 and the second gate 124 and reduce contact resistance. The material of the gate oxide layer 140 includes silicon oxide, but is not limited thereto.

Illustratively, the gate oxide layer 140 may cover a first portion 1231 of the first gate dielectric layer 123 (i.e., a portion of the first gate dielectric layer 123 not covered by the first gate electrode 124) and a portion of the second gate dielectric layer 133 not covered by the second gate electrode 134, in addition to the first protective layer 125 and the second protective layer 135. Under the condition that the high-voltage transistor 120 further includes the first gate sidewall spacer 126 and the low-voltage transistor 130 further includes the second gate sidewall spacer 136, the gate oxide layer 140 may further cover the first gate sidewall spacer 126 and the second gate sidewall spacer 136.

As shown in fig. 6, in order to reduce the drain region electric field for improving hot electron degradation, in some embodiments, the high voltage transistor 120 further includes a lightly doped drain region 127, the lightly doped drain region 127 extends from the first surface 111 of the substrate 110 into the substrate 110, and the first source 121 and the first drain 122 of the high voltage transistor 120 are located in the lightly doped drain region 127. In this way, the lightly doped drain region 127 is also subjected to a partial voltage, thereby preventing the hot electron degradation effect.

Wherein the lightly doped drain region 127 may be formed by ion implantation. Illustratively, a mask layer is formed on the first surface 111 of the substrate 110, the mask layer exposes the region for forming the lightly doped region 127, and ion implantation is performed on the exposed region to form the lightly doped region 127. The implanted ions may be arsenic ions.

As shown in fig. 6, in some embodiments, the semiconductor structure 100 further includes a first well region 150 and a second well region 160, the first well region 150 is located in the first region HV and extends from the first surface 111 of the substrate 110 into the substrate 110. The first source 121 and the first drain 122 of the high voltage transistor 120 are located in the first well region 150. In the case where the high voltage transistor 120 further includes a lightly doped region 127, the lightly doped region 127 is located in the first well region 150. The second well region 160 is located in the second region LV and extends from the first surface 111 of the substrate 110 into the substrate 110. The second source 131 and the second drain 132 are located in the second well region 160.

Wherein the first well region 150 and the second well region 160 may be formed by implanting impurity ions in the substrate 110. Illustratively, a patterned mask layer is formed on the first surface 111 of the substrate 110, and the patterned mask layer exposes the predetermined formation regions of the first well region 150 and the second well region 160; impurity ions are implanted into a predetermined formation region of the substrate 110 through an ion implantation process to form the first well region 150 and the second well region 160.

It should be noted that the doping type of the first well region 150 is different from the doping type of the second well region 160. The doping type of the first well 150 is N-type, and the N-type impurity includes, but is not limited to, phosphorous ion or arsenic ion; the doping type of the second well 160 is P-type, and the P-type impurity includes, but is not limited to, boron ions or gallium ions.

As shown in fig. 8, some embodiments of the present disclosure also provide a method for fabricating a semiconductor structure 100 (see fig. 6), including S1 to S2.

S1: referring to fig. 8 and 9, an intermediate semiconductor structure 101 is prepared.

In the above step, the intermediate semiconductor structure 101 comprises the first region 120. The intermediate semiconductor structure includes a substrate 110, a gate insulating film 1230 disposed on the first surface 111 of the substrate 110, a first gate electrode 124 disposed on a side of the gate insulating film 1230 away from the substrate 110, and a first protection layer 125 covering a surface of the first gate electrode 124 away from the substrate 110. Note that the first surface 111 is one of two opposite main surfaces of the substrate 110; the material of the gate insulating film 1230 includes silicon oxide, but is not limited thereto; the first region HV is a high voltage region configured to provide high voltage devices, e.g., high voltage transistor 120.

The first gate electrode 124 is located in the first region HV, and the thickness of the first protection layer 125 is smaller than that of the portion of the gate insulating film 123 located below the first gate electrode 124.

S2: referring to fig. 8 and 11, a portion of the gate insulating film 1230 located in the target region M is etched to reduce the thickness of the portion of the gate insulating film 1230 located in the target region M to a target thickness.

In the above step, the target region M is a region of the first region HV not covered by the first gate 124.

In addition, a chemical gas etching process is used to etch a portion of the gate insulating film 1230, which is located in the target region M. Illustratively, the first region HV is etched using a certas (chemical gas etching) tool. Compared with Plasma etching, chemical gas etching has no Plasma, so that the problem of charged particles gathering in the substrate 110 and the first gate 124 is avoided, Plasma Induced large (PID) is avoided, and the product yield is improved.

Referring to FIG. 12, in some embodiments, S1 includes S11-S14.

S11: referring to fig. 12 and 13, a gate insulating film 1230 is formed on the first surface 111 of the substrate 110.

S12: referring to fig. 12 and 15, a gate conductive layer 1241 is formed on a side of the gate insulating film 1230 remote from the substrate 110.

In the above steps, the gate conductive layer 1241 may be formed by atomic layer deposition, physical vapor deposition, or chemical vapor deposition. Illustratively, a polysilicon layer is formed on the side of the gate insulating film 1230 remote from the substrate 110 by plasma chemical vapor deposition, and the polysilicon layer is doped to form a gate conductive layer.

S13: referring to fig. 12 and 16, a first protective layer 125 is formed on a side of the gate conductive layer 1241 away from the substrate 110.

The orthographic projection of the first protection layer 125 on the substrate 110 is a region corresponding to the first gate 124 formed in advance.

S14: referring to fig. 12 and 17, the gate conductive layer 1241 is etched using the first protective layer 125 as a mask, so as to form the first gate 124.

Illustratively, the gate conductive layer 1241 is etched using a anisotropic plasma etcher to form the first gate electrode 124.

Referring to fig. 9, in some embodiments, the intermediate semiconductor structure 101 further includes a second region LV and an isolation region S. Wherein the second region LV is a low voltage region configured to provide low voltage devices, for example, the low voltage transistor 130; the isolation region S is configured to electrically isolate the first region HV and the second region LV from at least part of the transistors that are circumferentially adjacent.

In this case, referring to fig. 16, in the process of S13, a second protective layer 135 is also formed. The orthographic projection of the second protection layer 135 on the substrate 110 is a region corresponding to the second gate 134 formed in advance.

On this basis, referring to fig. 17, in the process of S14, the gate conductive layer 1241 is further etched with the second passivation layer 135 as a mask, so as to form a second gate 134; the second gate 134 is located in the second region LV.

Referring to FIG. 18, in some embodiments, S11 includes S111-S112.

S111: referring to fig. 13 and 18, an initial gate insulating film 1230 is formed on the first surface 111 of the substrate 110.

Illustratively, as shown in fig. 13, the above steps include sequentially forming a first sub-gate insulating film 1233 and a second sub-gate insulating film 1234, both covering the first region HV and the second region LV, which constitute the initial gate insulating film 1230. The first sub gate insulating film 1233 and the second sub gate insulating film 1234 may be deposited by chemical vapor deposition, physical vapor deposition, plasma enhanced, or the like.

Illustratively, the initial gate insulating film 1230 may be directly formed, and the thickness of the initial gate insulating film 1230 is equal to the predetermined thickness of the gate dielectric layer 123 under the gate electrode of the high voltage transistor 120.

S112: referring to fig. 13, 14 and 18, the thickness of the portion of the initial gate insulating film 1230 located in the second region LV is reduced to form a gate insulating film 1235.

For example, in the case where the initial gate insulating film 1230 includes the first sub-gate insulating film 1233 and the second sub-gate insulating film 1234, the step includes: the portion of the second sub-gate insulating film 1234 located in the second region LV is removed, and the remaining second sub-gate insulating film 1234 forms a gate insulating film 1235 with the underlying first sub-gate insulating film 1233. It can be seen that this corresponds to a reduction in the thickness of the portion of the initial gate insulating film 1230 located in the second region LV with respect to the entirety of the initial gate insulating film 1230, thereby obtaining the gate insulating film 1235. That is, the thickness of the portion of the gate insulating film 123 covering the first region HV is greater than the thickness of the portion covering the second region LV.

Note that the target thickness in S2 is substantially equal to the thickness of the portion of the gate insulating film 1230 covering the second region LV.

Referring to fig. 19, in some embodiments, between S1 and S2, the above preparation method further comprises S3.

S3: referring to fig. 10 and 19, a photoresist layer 170 is formed to cover the second region LV.

In the above steps, the photoresist layer 170 covers the second protective layer 135, and a portion of the gate insulating film 1230 that is not covered by the second gate electrode 124 in a portion that covers the second region LV. In this way, when the target region M is etched in S2, the gate insulating film 1230 on the second region LV is prevented from being etched away by covering the second region LV with the photoresist layer 170, thereby preventing the substrate 110 from being damaged.

Referring to fig. 20, in some embodiments, prior to S3, the above preparation method further comprises S4.

S4: referring to fig. 20 and 21, first gate spacers 126 covering the sides of the first gate 124 and second gate spacers 136 covering the sides of the second gate 134 are formed.

Illustratively, a chemical vapor deposition method is adopted to deposit silicon nitride on the side of the first surface 111 of the substrate 110, and then dry etching is adopted to remove the silicon nitride on the first surface 111 of the substrate 110 and the surface of the first gate 124 away from the substrate 110, thereby forming the first gate sidewall 126 and the second gate sidewall 136.

Note that after the step S4 is completed, referring to fig. 23 and fig. 24, the target region M in S2 is the region of the first region HV not covered by the first gate 124 and the first gate sidewall 126 thereof.

Referring to fig. 22, in some embodiments, after S2, the method of making further includes S5-S6.

S5: referring to fig. 22 and 23, the photoresist layer 170 (see fig. 11) is removed.

S6: referring to fig. 22 and 24, the substrate 110 is ion-doped, and a first source electrode 121 and a first drain electrode 122 are formed at both sides of the first gate electrode 124 in the target region M, and a second source electrode 131 and a second drain electrode 132 are formed at both sides of the second gate electrode 134 in the second region LV. The ion doping method may adopt ion implantation or ion diffusion.

In some embodiments, referring to fig. 6, the semiconductor structure 100 further comprises an isolation structure 112. Referring to fig. 25, the above steps further include S15 before S11.

S15: isolation structures 112 are formed on substrate 110.

In the above step, the isolation structure 112 may be formed by oxidizing local silicon, and the isolation structure 112 may also be a Shallow Trench Isolation (STI). Illustratively, an isolation groove is formed on the first surface of the substrate 110 by using photolithography and etching, and the isolation groove is filled with an insulating material, which may include at least one of silicon oxide, silicon oxynitride, ethoxysilane, low-temperature oxide, high-temperature oxide, and silicon nitride, but is not limited thereto.

In some embodiments, referring to fig. 6, the semiconductor structure 100 further includes a first well region 150 and a second well region 160. Referring to FIG. 26, before S11, the above steps further include S16-S17.

S16: the first region HV on the substrate 110 forms a first well region 150, the first well region 150 extending from the first surface 111 of the substrate 110 into the substrate 110.

In the above steps, the first well region 150 may be formed by implanting impurity ions in the substrate 110. Illustratively, a patterned mask layer is formed on the first surface 111 of the substrate 110, and the patterned mask layer exposes a predetermined formation region of the first well region 150; impurity ions are implanted into a predetermined formation region of the substrate 110 through an ion implantation process to form the first well region 150.

It should be noted that the doping type of the first well region 150 is N type, that is, impurity ions including phosphorus ions or arsenic ions are implanted into the predetermined formation region of the substrate 110 by an ion implantation process, but not limited thereto.

S17: a second well region 160 is formed on the substrate 110 at a second region LV, the second well region 160 extending from the first surface 111 of the substrate 110 into the substrate 110.

In the above steps, the second well region 160 may be formed by implanting impurity ions in the substrate 110. Illustratively, a patterned mask layer is formed on the first surface 111 of the substrate 110, and the patterned mask layer exposes a predetermined formation region of the second well region 160; impurity ions are implanted into a predetermined formation region of the substrate 110 through an ion implantation process to form the second well region 160.

It should be noted that the doping type of the second well 160 is P-type, that is, impurity ions including boron ions or gallium ions are implanted into the predetermined formation region of the substrate 110 by an ion implantation process, but not limited thereto.

It should be noted that, the execution order of S16 and S17 is not limited, S16 may be executed first and then S17 may be executed, or S17 may be executed first and then S16 may be executed.

In some embodiments, referring to fig. 6, the semiconductor structure 100 further comprises a lightly doped region 127. Referring to fig. 27, the above steps further include S7 before S5.

S7: the substrate 110 is ion doped to form lightly doped regions 127 in the target region M on both sides of the first gate 124.

In the above step, the lightly doped drain region 127 may be formed by ion implantation. Illustratively, a mask layer is formed on the first surface 111 of the substrate 110, the mask layer exposes the region for forming the lightly doped region 127, and ion implantation is performed on the exposed region to form the lightly doped region 127. The implanted ions may be arsenic ions.

Referring to fig. 5, some embodiments of the present disclosure also provide an integrated circuit 200, the integrated circuit 200 including the semiconductor structure 100, the semiconductor structure 100 being the semiconductor structure 100 of some embodiments as above or prepared by the method of preparing the semiconductor structure 100 of some embodiments as above. The integrated circuit 200 may be, for example, a peripheral device in the three-dimensional memory 300 (see fig. 4) for controlling and detecting the switch states of the memory cell string arrays 410 (see fig. 4) to store and read data.

The peripheral device may include, for example, a series of circuits 210 (see fig. 4) such as page buffers, decoders (e.g., row and column decoders), sense amplifiers, drivers (e.g., word line drivers), charge pumps, current or voltage references, etc., at least one of the series of circuits 210 (see fig. 4) included in the peripheral device including the semiconductor structure 100 described above.

Referring to fig. 4, some embodiments of the disclosure further provide a three-dimensional memory 300, where the three-dimensional memory 300 includes the integrated circuit 200 and the memory array device 400 of some embodiments, and the memory array device 400 is electrically connected to the integrated circuit 200 to implement functional support of the memory array device 400 by the integrated circuit 200, such as reading, writing, and erasing data of memory cells.

Referring to fig. 4, in some embodiments, the memory array device 400 includes a memory cell string array 410, and an array interconnect layer 420 disposed on a side of the memory cell string array 410 adjacent to the integrated circuit 200, the memory cell string array 410 being electrically connected to the array interconnect layer 420. The integrated circuit 200 includes a series of circuits 210, such as page buffers, and a peripheral interconnect layer 220 disposed on a side of the series of circuits 210 adjacent to the memory array device 400, the series of circuits 210 being electrically connected to the peripheral interconnect layer 220. The memory array device 400 is electrically coupled to the integrated circuit 200 through the array interconnect layer 420 and the peripheral interconnect layer 220, thereby electrically coupling the memory cell string array 410 to the series of circuits 210.

FIG. 1 is a block diagram of a memory system 10 according to some embodiments. FIG. 2 is a block diagram of memory system 10 according to further embodiments. Referring to fig. 1 and 2, some embodiments of the present disclosure also provide a storage system 10. The storage system 10 includes a controller 500 and the three-dimensional memory 300 of some embodiments as above, the controller 500 being coupled to the three-dimensional memory 300 to control the three-dimensional memory 300 to store data.

The Storage system 10 may be integrated into various types of Storage devices, for example, included in the same package (e.g., a Universal Flash Storage (UFS) package or an Embedded multimedia Card (eMMC) package). That is, the storage system 10 may be applied to and packaged into different types of electronic products, such as mobile phones, desktop computers, laptop computers, tablet computers, vehicle computers, game consoles, printers, positioning devices, wearable electronic devices, smart sensors, Virtual Reality (VR) devices, Augmented Reality (AR) devices, or any other suitable electronic device having storage therein.

In some embodiments, referring to fig. 1, the memory system 10 includes a controller 500 and a three-dimensional memory 300, and the memory system 10 may be integrated into a memory card.

The Memory Card includes any one of a PC Card (PCMCIA), a Compact Flash (CF) Card, a Smart Media (SM) Card, a Memory stick, a Multimedia Card (MMC), a Secure Digital Memory Card (SD), and a UFS.

In other embodiments, referring to fig. 2, the storage system 10 includes a controller 500 and a plurality of three-dimensional memories 300, and the storage system 10 is integrated into a Solid State Drive (SSD).

In storage system 10, in some embodiments, controller 500 is configured for operation in a low duty cycle environment, such as an SD card, CF card, Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, mobile phones, and the like.

In other embodiments, the controller 500 is configured for operation in a high duty cycle environment SSD or eMMC for data storage and enterprise storage arrays of mobile devices such as smart phones, tablets, laptops, and the like.

In some embodiments, the controller 500 may be configured to manage data stored in the three-dimensional memory 300 and communicate with an external device (e.g., a host). In some embodiments, the controller 500 may also be configured to control operations of the three-dimensional memory 300, such as read, erase, and program operations. In some embodiments, the controller 500 may also be configured to manage various functions with respect to data stored or to be stored in the three-dimensional memory 300, including at least one of bad block management, garbage collection, logical-to-physical address translation, wear leveling. In some embodiments, the controller 500 is further configured to process error correction codes with respect to data read from the three-dimensional memory 300 or written to the three-dimensional memory 300.

Of course, the controller 500 may also perform any other suitable function, such as formatting the three-dimensional memory 300. For example, the controller 500 may communicate with an external device (e.g., a host) through at least one of various interface protocols.

It should be noted that the interface protocol includes at least one of a USB protocol, an MMC protocol, a Peripheral Component Interconnect (PCI) protocol, a PCI express (PCI-E) protocol, an Advanced Technology Attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a Small Computer System Interface (SCSI) protocol, an Enhanced Small Disk Interface (ESDI) protocol, an Integrated Drive Electronics (IDE) protocol, and a Firewire protocol.

The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.

Claims

1. A semiconductor structure, comprising:

a substrate comprising a first region;

a high voltage transistor disposed in the first region, comprising:

the first source electrode and the first drain electrode are arranged at intervals and extend from the first surface of the substrate into the substrate; the first surface is one of two opposing major surfaces of the substrate;

the first gate dielectric layer is arranged on the first surface of the substrate; the first gate dielectric layer comprises a first part covering the first source electrode and the first drain electrode and a second part staggered with the first source electrode and the first drain electrode, and the thickness of the first part is smaller than that of the second part;

the first grid is arranged on one side of the second part far away from the substrate;

and the first protective layer covers the surface of the first grid electrode, which is far away from the substrate, and the thickness of the first protective layer is smaller than that of the second part.

2. The semiconductor structure of claim 1, wherein the high voltage transistor further comprises:

and the first grid side wall covers the side surface of the first grid.

3. The semiconductor structure of claim 2, wherein an outer boundary of an orthographic projection of the first gate sidewall on the substrate coincides with a boundary of an orthographic projection of the second portion on the substrate.

4. The semiconductor structure of claim 2, wherein the material of the first gate sidewall spacer comprises silicon nitride.

5. The semiconductor structure of claim 1, wherein a thickness of the first protective layer is 5nm to 6nm less than a thickness of the second portion.

6. The semiconductor structure of claim 1, wherein a thickness of the first protective layer is greater than a thickness of the first portion.

7. The semiconductor structure of claim 1, wherein the material of the first protective layer comprises silicon nitride; and/or the material of the first gate dielectric layer comprises silicon oxide.

8. The semiconductor structure of any of claims 1-7, wherein the substrate further comprises a second region; the semiconductor device structure further includes:

a low voltage transistor disposed in the second region, comprising:

the second source electrode and the second drain electrode are arranged at intervals and extend from the first surface of the substrate into the substrate;

the second gate dielectric layer is arranged on the first surface of the substrate, and the thickness of the second gate dielectric layer is equal to that of the first part;

the second grid electrode is arranged on one side, far away from the substrate, of the second grid dielectric layer;

and the second protective layer covers the surface of the second grid electrode, which is far away from the substrate.

9. The semiconductor structure of claim 8, wherein the low voltage transistor further comprises:

and the second grid side wall covers the side face of the second grid.

10. A method for fabricating a semiconductor structure, comprising:

preparing an intermediate semiconductor structure; the intermediate semiconductor structure includes a first region; the intermediate semiconductor structure includes: the device comprises a substrate, a gate insulating film arranged on the first surface of the substrate, a first grid arranged on one side, far away from the substrate, of the gate insulating film, and a first protective layer covering the surface, far away from the substrate, of the first grid; the first surface is one of two opposing major surfaces of the substrate; the first grid electrode is positioned in the first area, and the thickness of the first protective layer is smaller than that of the part, positioned below the first grid electrode, in the grid insulating film;

11. The method for manufacturing a semiconductor structure according to claim 10, wherein a chemical gas etching process is used for etching a portion of the gate insulating film, which is located in the target region.

12. The method of claim 10, wherein said fabricating an intermediate semiconductor structure comprises:

forming a gate insulating film on a first surface of the substrate;

forming a gate conductive layer on one side of the gate insulating film, which is far away from the substrate;

forming the first protective layer on one side of the gate conductive layer away from the substrate; the orthographic projection of the first protective layer on the substrate is a region corresponding to the first grid electrode which is formed in a preset mode;

and etching the gate conductive layer by taking the first protective layer as a mask to form the first gate.

13. The method for manufacturing a semiconductor structure according to claim 12, wherein the intermediate semiconductor structure further comprises a second region, and a second protective layer is further formed in the process of forming the first protective layer on the side of the gate conductive layer away from the substrate, and an orthographic projection of the second protective layer on the substrate is a region corresponding to a second gate electrode which is formed in advance;

in the process of etching the gate conductive layer by taking the first protective layer as a mask to form the first gate, etching the gate conductive layer by taking the second protective layer as a mask to form the second gate; the second gate is located in the second region.

14. The method of manufacturing a semiconductor structure according to claim 13, wherein the forming a gate insulating film over the first surface of the substrate comprises:

forming an initial gate insulating film on a first surface of the substrate;

and thinning the thickness of the part of the initial gate insulating film, which is positioned in the second area, to form the gate insulating film.

15. The method for manufacturing a semiconductor structure according to claim 14, wherein the target thickness is equal to a thickness of a portion of the gate insulating film covering the second region.

16. The method for manufacturing a semiconductor structure according to any one of claims 13 to 15, further comprising, between the manufacturing of the intermediate semiconductor structure and the etching of the portion of the gate thin film located in the target region:

and forming a photoresist layer covering the second region.

17. The method of claim 16, further comprising, prior to said forming a photoresist layer overlying said second region:

and forming a first grid side wall covering the side surface of the first grid and a second grid side wall covering the side surface of the second grid.

18. The method for manufacturing a semiconductor structure according to claim 16, further comprising, after the etching a portion of the gate insulating film located in a target region:

removing the photoresist layer;

and carrying out ion doping on the substrate, forming a first source electrode and a first drain electrode on two sides of the first grid electrode in the target area, and forming a second source electrode and a second drain electrode on two sides of the second grid electrode in the second area.

19. An integrated circuit comprising a semiconductor structure, wherein the semiconductor structure is the semiconductor structure of any one of claims 1 to 9 or is prepared by the method of any one of claims 10 to 18.

20. A three-dimensional memory, comprising:

the integrated circuit of claim 19;

a memory array device coupled to the integrated circuit.

21. A storage system comprising a three-dimensional memory as claimed in claim 20 and a controller coupled to the three-dimensional memory to control the three-dimensional memory to store data.