CN114023751A

CN114023751A - Semiconductor structure, preparation method thereof and three-dimensional memory

Info

Publication number: CN114023751A
Application number: CN202111258514.3A
Authority: CN
Inventors: 吴林春; 张坤; 周文犀
Original assignee: Yangtze Memory Technologies Co Ltd
Current assignee: Yangtze Memory Technologies Co Ltd
Priority date: 2021-10-27
Filing date: 2021-10-27
Publication date: 2022-02-08

Abstract

The disclosure provides a semiconductor structure, a preparation method thereof and a three-dimensional memory, relates to the technical field of semiconductor chips, and aims to solve the problem of how to form a plurality of top selection gate tangents between two adjacent gate isolation grooves. The preparation method comprises the following steps: forming a plurality of film layer pairs arranged in a stacked manner on a substrate, wherein each film layer pair comprises an adjacent insulating layer and a first sacrificial layer; forming a plurality of grid separating grooves and a plurality of selection grid grooves, wherein the plurality of selection grid grooves are arranged between every two adjacent grid separating grooves, the grid separating grooves penetrate through the stacked structure, and the selection grid grooves penetrate through at least one insulating layer and at least one first sacrificial layer on one side, far away from the substrate, in the stacked structure; removing the first sacrificial layer to form a cavity, and depositing a gate conductive material to form a gate conductive layer in the cavity; removing the gate conductive material in the selective gate trench; a top select gate tangent is formed within the select gate trench. The semiconductor structure is applied to a three-dimensional memory to realize reading and writing operations of data.

Description

Semiconductor structure, preparation method thereof and three-dimensional memory

Technical Field

The disclosure relates to the technical field of semiconductor chips, in particular to a semiconductor structure, a manufacturing method thereof and a three-dimensional memory.

Background

As the feature size of memory cells approaches the lower process limit, planar processes and manufacturing techniques become challenging and costly, which causes the storage density of 2D or planar NAND flash memories to approach the upper limit.

To overcome the limitations of 2D or planar NAND flash memories, memories having a three-dimensional structure (3D NAND) have been developed, and the 3D NAND memories have Gate Line Slots (GLS) to divide a plurality of memory blocks on the memories.

In the related art, a Top Select Gate Cut (TSG Cut for short) is formed between two adjacent Gate isolation trenches, so that the memory block can be further divided into a plurality of sub-memory blocks, the number of effective Channel holes (CH for short) is increased, and the memory density of the memory is increased. How to form a plurality of top selection gate tangents between two adjacent gate isolation grooves on the premise of ensuring the yield of devices and reasonable process difficulty becomes a problem to be solved urgently in the field.

Disclosure of Invention

Embodiments of the present disclosure provide a semiconductor structure, a method for manufacturing the same, and a three-dimensional memory, which aim to at least partially solve the problem of how to form a plurality of top selection gate tangents between two adjacent gate isolation trenches.

In order to achieve the purpose, the embodiment of the disclosure adopts the following technical scheme:

in one aspect, a method of fabricating a semiconductor structure is provided. The preparation method comprises the following steps: forming a stacked structure on a substrate, the stacked structure comprising a plurality of film layer pairs arranged in a stack, each film layer pair comprising an adjacent insulating layer and a first sacrificial layer; forming a plurality of grid separating grooves and a plurality of selection grid grooves, wherein the plurality of selection grid grooves are arranged between every two adjacent grid separating grooves, the grid separating grooves penetrate through the stacked structure, and the selection grid grooves penetrate through at least one insulation layer and at least one first sacrificial layer on one side, far away from the substrate, of the stacked structure; removing the first sacrificial layer to form a cavity, and depositing a gate conductive material to form a gate conductive layer in the cavity; removing the gate conductive material in the selective gate trench; and forming a top selection gate tangent in the selection gate groove.

In some embodiments, the forming a plurality of gate spacers and a plurality of select gate trenches comprises: forming the plurality of select gate trenches in the stacked structure; forming a second sacrificial layer, wherein the second sacrificial layer fills the plurality of selection gate grooves and covers the surface of the stacking structure far away from the substrate; forming the plurality of gate spacers in the stacked structure.

In some embodiments, the second sacrificial layer is the same material as the first sacrificial layer.

In some embodiments, before said removing the gate conductive material in the select gate trench, further comprising: removing the gate conductive material in the gate isolation groove and on the surface of the stacked structure far away from the substrate; and forming a first protective layer covering the inner surface of the grid isolation groove.

In some embodiments, the removing the gate conductive material within the gate spacer and on a surface of the stack structure remote from the substrate comprises: removing the gate conductive material on the side wall and the bottom of the gate separation groove and on the surface of the stacking structure far away from the substrate; and removing the part of the gate conductive layer close to the gate isolation groove to form a first recess.

In some embodiments, the forming a first protection layer covering the inner surface of the gate spacer comprises: forming a first protective film, wherein the first protective film covers the grid isolation groove, the selection grid groove and the surface of the stacked structure far away from the substrate; and removing the parts of the first protective film, which cover the surfaces of the selection gate grooves and the stacking structures far away from the substrate, to form the first protective layer.

In some embodiments, the gate conductive material fills the select gate trench during deposition of the gate conductive material, forming a sacrificial fill. In the process of removing the gate conductive material in the gate isolation groove and on the surface of the stacked structure far away from the substrate, the part of the sacrificial filling part far away from the substrate is removed to form a second recess.

In some embodiments, before the removing the gate conductive material within the gate spacer and on the surface of the stacked structure away from the substrate, further comprising: forming a second protective film covering the gate isolation grooves, the selection gate grooves and the gate conductive material on the surface of the stacking structure far away from the substrate; and removing the part, which covers the grid separating groove and the grid conducting material on the surface of the stacking structure far away from the substrate, of the second protective film to form a second protective layer.

In some embodiments, during deposition of the gate conductive material, the gate conductive material covers the interior surfaces of the select gate trenches forming a sacrificial capping layer, the select gate trenches having a gap therein. In the process of forming the second protective film, the second protective film fills the gap. And in the process of removing the gate conductive material in the gate isolation groove and on the surface of the stacked structure far away from the substrate, removing the part of the sacrificial covering layer far away from the substrate to form a third recess.

In some embodiments, the removing the gate conductive material in the select gate trench includes: removing the gate conductive material in the selective gate trench; and removing the part, close to the selection gate groove, of the gate conducting layer, so that the side face, close to the selection gate groove, of the gate conducting layer is retracted inwards relative to the side face, close to the selection gate groove, of the insulating layer, and a fourth recess is formed.

In some embodiments, forming a top select gate tangent within the select gate trench includes: depositing a dielectric material, wherein the dielectric material filled in the selection gate groove forms the top selection gate tangent. Wherein, during the deposition of the dielectric material, the dielectric material is also deposited on the inner surfaces of the gate spacers.

In some embodiments, after forming a top select gate tangent within the select gate trench, further comprising: and forming filling patterns in the gate isolation grooves.

In some embodiments, before forming the stacked structure on the substrate, further comprising: at least one stop layer is formed on the substrate. Between the step of forming a stacked structure on the substrate and the step of forming the plurality of gate spacers and the plurality of select gate trenches, the method further comprises: a plurality of channel structures are formed.

In some embodiments, the channel structure extends through the stack structure and the at least one stop layer and into the substrate, the channel structure including a storage function layer and a channel layer, the storage function layer and the channel layer being disposed adjacent to each other. After forming a top select gate tangent in the select gate trench, further comprising: sequentially removing the substrate and the part, extending into the substrate, of the memory function layer of the channel structure to expose the channel layer of the channel structure; forming a source layer covering the exposed portion of the channel layer to be electrically connected with the channel layer.

In some embodiments, the forming a source layer comprises: forming a doped polysilicon layer; and annealing the polycrystalline silicon layer to form the source electrode layer.

In some embodiments, after the forming a source layer, the method further comprises: forming an interlayer dielectric layer on one side of the source layer far away from the stacking structure, wherein the interlayer dielectric layer is provided with at least one through hole; and forming a metal interconnection layer on one side of the interlayer dielectric layer far away from the stacking structure, wherein the metal interconnection layer is electrically connected with the source layer through at least one through hole of the interlayer dielectric layer.

In another aspect, a semiconductor structure is provided. The semiconductor structure comprises a source electrode layer and a stacked structure arranged on the source electrode layer, wherein the stacked structure comprises a plurality of film layer pairs which are arranged in a stacked mode, and each film layer pair comprises an adjacent insulating layer and a grid conducting layer. The stacked structure is provided with a plurality of grid separating grooves and a plurality of selection grid grooves, and a plurality of selection grid grooves are arranged between every two adjacent grid separating grooves. The gate separation groove penetrates through the stacked structure, and the selection gate groove penetrates through at least one insulating layer and at least one gate conducting layer on the side, far away from the source layer, of the stacked structure. The semiconductor structure also includes a top select gate tangent disposed within the select gate trench.

In another aspect, a three-dimensional memory is provided. The three-dimensional memory includes: the semiconductor structure as described in the above embodiments.

In yet another aspect, a storage system is provided. The storage system comprises a controller and the memory of the above embodiments, wherein the controller is coupled to the memory and is used for controlling the memory to store data.

In another aspect, an electronic device is provided, which includes the storage system described in the above embodiments.

In some embodiments, the electronic device comprises at least one of: the mobile phone, the desktop computer, the tablet computer, the notebook computer, the server, the vehicle-mounted equipment, the wearable equipment, the portable power source.

Some embodiments of the present disclosure provide a method for manufacturing a semiconductor structure, in which a plurality of gate isolation trenches and a plurality of selection gate trenches are formed on a stacked structure, and a plurality of selection gate trenches are disposed between two adjacent gate isolation trenches. Before forming top selection gate tangents in the selection gate grooves, the first sacrificial layer is removed through the gate separation grooves to form a cavity, so that the problem that the first sacrificial layer between every two adjacent top selection gate tangents cannot be removed through the gate separation grooves due to blocking of the top selection gate tangents can be solved, and the yield of devices is improved; and before the gate conductive material is deposited to form the gate conductive layer, a plurality of selection gate grooves are formed on the stacked structure, so that the insulating layer and the gate conductive layer in the stacked structure are prevented from being etched in the process of forming the plurality of selection gate grooves, and the difficulty of the preparation process is reduced.

And depositing a gate conductive material in the cavity through the selection gate trench and the gate spacer to form a gate conductive layer within the cavity, thereby replacing the plurality of first sacrificial layers with the plurality of gate conductive layers. Then, removing the gate conductive material in the selection gate groove, and forming a top selection gate tangent line in the selection gate groove so as to form a plurality of top selection gate tangents between two adjacent gate grooves.

Some embodiments of the present disclosure further provide a semiconductor structure, a plurality of select gate trenches are disposed between two adjacent gate isolation trenches, and top select gate tangents are disposed in the select gate trenches, that is, a plurality of top select gate tangents are disposed between two adjacent gate isolation trenches, which can further divide a memory block into a plurality of sub-memory blocks, so as to increase the number of effective channel holes of the semiconductor structure, thereby increasing the memory density of the memory.

It can be understood that the three-dimensional memory, the memory system and the electronic device provided by the embodiments of the disclosure can achieve the beneficial effects of the semiconductor structure and the manufacturing method thereof, which are not described herein again.

Drawings

In order to more clearly illustrate the technical solutions in the present disclosure, the drawings needed to be used in some embodiments of the present disclosure will be briefly described below, and it is apparent that the drawings in the following description are only drawings of some embodiments of the present disclosure, and other drawings can be obtained by those skilled in the art according to the drawings. Furthermore, the drawings in the following description may be regarded as schematic diagrams, and do not limit the actual size of products, the actual flow of methods, the actual timing of signals, and the like, involved in the embodiments of the present disclosure.

FIG. 1A is a schematic diagram of a three-dimensional memory according to some embodiments;

FIG. 1B is a cross-sectional view of the three-dimensional memory of FIG. 1A along section line A-A';

FIGS. 2A-2K are flow diagrams of a method of fabricating a semiconductor structure according to some embodiments;

figure 2L is a flow diagram of another method of fabricating a semiconductor structure according to some embodiments;

FIG. 3A is a top view of another semiconductor structure according to some embodiments;

FIG. 3B is a cross-sectional view of the semiconductor structure of FIG. 3A along section line B-B';

FIGS. 4A-4S are diagrams of steps in a method of fabricating a semiconductor structure according to some embodiments;

FIGS. 5A-5F are diagrams of steps in another method of fabricating a semiconductor structure, according to some embodiments;

FIGS. 6A-6C are diagrams of steps in yet another method of fabricating a semiconductor structure, according to some embodiments;

FIG. 7 is a block diagram of a memory system according to some embodiments;

FIG. 8 is a block diagram of another storage system in accordance with some embodiments;

FIG. 9 is a block diagram of an electronic device according to some embodiments.

Detailed Description

Technical solutions in some embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings, and it is obvious that the described embodiments are only a part of the embodiments of the present disclosure, and not all of the embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments provided by the present disclosure belong to the protection scope of the present disclosure.

In the description of the present disclosure, it is to be understood that the terms "center", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like indicate orientations or positional relationships based on those shown in the drawings, and are only for convenience in describing and simplifying the disclosure, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed in a specific orientation, and be operated, and thus, should not be construed as limiting the disclosure.

Throughout the specification and claims, the term "comprising" is to be interpreted in an open, inclusive sense, i.e., as "including, but not limited to," unless the context requires otherwise. In the description herein, the terms "one embodiment," "some embodiments," "an example embodiment," "exemplary" or "some examples" or the like are intended to mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the disclosure. The schematic representations of the above terms are not necessarily referring to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be included in any suitable manner in any one or more embodiments or examples.

In the following, the terms "first", "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the embodiments of the present disclosure, "a plurality" means two or more unless otherwise specified.

In describing some embodiments, the expression "connected" and its derivatives may be used. For example, the term "electrically connected" may be used in describing some embodiments to indicate that two or more elements are in direct physical or electrical contact with each other. The embodiments disclosed herein are not necessarily limited to the contents herein.

"at least one of A, B and C" has the same meaning as "A, B or at least one of C," each including the following combination of A, B and C: a alone, B alone, C alone, a and B in combination, a and C in combination, B and C in combination, and A, B and C in combination.

"A and/or B" includes the following three combinations: a alone, B alone, and a combination of A and B.

Additionally, the use of "based on" means open and inclusive, as a process, step, calculation, or other action that is "based on" one or more stated conditions or values may in practice be based on additional conditions or values beyond those stated.

In the context of this disclosure, the meaning of "on … …," above, "and" over "should be interpreted in the broadest manner such that" on.

Example embodiments are described herein with reference to cross-sectional and/or plan views as idealized example figures. In the drawings, the thickness of layers and regions are exaggerated for clarity. Variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, the exemplary embodiments should not be construed as limited to the shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the exemplary embodiments.

As used herein, the term "substrate" refers to a material onto which subsequent layers of material may be added. The substrate itself may be patterned. The material added on the substrate may be patterned or may remain unpatterned. In addition, the substrate may include a variety of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, and the like. Alternatively, the substrate may be made of a non-conductive material such as glass, plastic, or sapphire wafer.

The term "three-dimensional memory" refers to a semiconductor device formed of memory cell transistor strings (referred to herein as "memory cell strings", e.g., NAND memory cell strings) arranged in an array on a major surface of a substrate and extending in a direction perpendicular to the substrate. As used herein, the term "perpendicular" means nominally perpendicular to a major surface (i.e., a lateral surface) of a substrate.

Referring to fig. 1A and fig. 1B, fig. 1A is a schematic perspective view of a three-dimensional memory according to some embodiments of the disclosure, and fig. 1B is a cross-sectional view of the three-dimensional memory of fig. 1A along a sectional line a-a'.

As shown in fig. 1A and 1B, the three-dimensional memory 100 includes a stacked structure 4, and the stacked structure 4 has a step profile and includes a plurality of gate conductive layers 43 and insulating layers (not shown in the figure) stacked alternately. The gate conductive layer 43 and the insulating layer extend in the first direction X. In the third direction Z, the lowermost gate conductive layer 43 of the multi-layer gate conductive layers 43 is configured as a source side select gate SGS, the uppermost gate conductive layer 43 of the multi-layer gate conductive layers 43 is configured as a drain side select gate SGD, the intermediate gate conductive layer 43 of the multi-layer gate conductive layers 43 is configured as a plurality of word lines WL (e.g., WL1 to WL4 shown in fig. 1B), and the source side select gate SGS, the drain side select gate SGD, and the word lines WL are collectively referred to as a gate line.

It should be noted that, for clearly showing the structure of the three-dimensional memory 100, only four word lines WL are shown in fig. 1A, and the number of word lines WL in the three-dimensional memory 100 may be much more than four.

The three-dimensional memory 100 further includes an array of channel structures 5 extending in a third direction Z through the drain side select gate SGD, the word lines WL, and the source side select gate SGS. As shown in fig. 1B, the channel structure 5 connects the word lines WL in series to form a memory cell string 50. One memory cell string 50 corresponds to the memory capacity of a plurality of planar memory cells. Therefore, the three-dimensional memory can provide a large storage capacity.

As shown in FIG. 1A, the three-dimensional memory 100 includes an array of memory cell strings 50 in the X-Y plane.

With continued reference to fig. 1A, the three-dimensional memory 100 further includes a source layer 13 located below the source select gate SGS. In some examples, the array of memory cell strings 50 shares the source layer 13.

The three-dimensional memory 100 further includes a drain select gate contact SGD CNT, a source select gate contact SGS CNT, a source contact SL CNT, a word line contact WL CNT, and a bit line contact BL CNT. The drain terminal selection gate contact SGD CNT is electrically connected with the drain terminal selection gate SGD; the source end selection gate contact SGS CNT is electrically connected with the source end selection gate SGS; the source end contact SL CNT is electrically connected with a source end SL; each word line contact WL CNT is electrically connected to one word line WL, whereby the word line contacts WL CNT can be addressed separately in each memory cell string 50; each bitline contact BL CNT is electrically connected to the top of one memory cell string 50, whereby each memory cell string 50 can be individually addressed by the bitline contact BL CNT.

The three-dimensional memory 100 further includes a bit line BL electrically connected to the memory cell string 50 through a bit line contact BL CNT.

In some examples, the three-dimensional memory 100 further includes a peripheral device disposed at one side of the array of memory cell strings 50, and an interconnect layer disposed between the array of memory cell strings 50 and the peripheral device, through which the array of memory cell strings 50 and the peripheral device are electrically connected.

As shown in fig. 1A, in order to implement the block storage of the storage regions of the three-dimensional memory 100, the three-dimensional memory 100 further includes gate spacer grooves 8 therein for dividing the stacked structure 4 into a plurality of storage blocks. In some examples, the gate spacer 8 extends through the stacked structure 4 in the third direction Z and at least in the first direction X.

The source layer 13 extends in an X-Y plane, and the first direction X and the second direction Y are, for example, two orthogonal directions in the plane of the source layer 13: the first direction X is, for example, an extending direction of the word line WL, and the second direction Y is, for example, an extending direction of the bit line BL. The third direction Z is perpendicular to the source layer 13, i.e. perpendicular to the X-Y plane.

In the related art, the memory block may be further divided into a plurality of sub-memory blocks by forming a top selection gate tangent line between two adjacent gate isolation trenches, so as to increase the number of effective channel holes and the memory density of the memory.

In order to form a plurality of top selection gate tangents between two adjacent gate isolation grooves and ensure the device yield and reasonable process difficulty, the inventors of the present invention found in research that, in the process of manufacturing a three-dimensional memory, a plurality of gate isolation grooves are formed on a stacked structure, and a plurality of top selection gate tangents are formed on the stacked structure before a sacrificial layer in the stacked structure is removed by the gate isolation grooves. A plurality of top selection gate tangents exist between two adjacent gate isolation grooves, so that the sacrificial layer between the two adjacent top selection gate tangents is isolated by the top selection gate tangents, and the sacrificial layer between the two adjacent top selection gate tangents cannot be removed through the gate isolation grooves and replaced by a gate conductive layer.

And a plurality of grid electrode separation grooves are formed on the stacked structure, after a sacrificial layer in the stacked structure is removed through the grid electrode separation grooves and replaced by a grid conducting layer, a plurality of selective grid grooves and a plurality of top selective grid tangent lines are formed on the stacked structure, an oxidation layer and a grid conducting layer on the stacked structure need to be etched in the process of forming the plurality of selective grid grooves, and due to the fact that materials of the oxidation layer and the grid conducting layer are different, the depth of the selective grid grooves can be accurately controlled only by adjusting the selection ratio of the etched oxidation layer and the grid conducting layer, and the difficulty of the preparation process is increased.

To solve the above problems, some embodiments of the present disclosure provide a method of fabricating a semiconductor structure, for example, for fabricating the semiconductor structure 200 shown in fig. 3A and 3B.

As shown in fig. 2A, the preparation method includes the following S10 to S50:

s10: as shown in fig. 4A, a stacked structure 4 is formed on a substrate 1, the stacked structure 4 including a plurality of film layer pairs 4A arranged in a stack, each film layer pair 4A including an adjacent insulating layer 40 and a first sacrificial layer 41.

It is understood that, in the process of forming the stacked structure 4 on the substrate 1, an insulating layer 40 is formed on the substrate 1, then a first sacrificial layer 41 is formed on the insulating layer 40 at the side away from the substrate 1, and the above preparation steps are repeated to form a plurality of insulating layers 40 and a plurality of first sacrificial layers 41 which are alternately arranged, that is, the stacked structure 4 is formed. The insulating layer 40 in each film layer pair 4a is disposed adjacent to the first sacrificial layer in the other film layer pair.

S20: as shown in fig. 4B and 4D, a plurality of gate spacers 8 and a plurality of select gate trenches 6 are formed. With reference to fig. 3A and 3B, a plurality of selection gate trenches 6 are disposed between two adjacent gate trenches 8, each gate trench 8 penetrates through the stacked structure 4, and each selection gate trench 6 penetrates through at least one insulating layer 40 and at least one first sacrificial layer 41 on a side of the stacked structure 4 away from the substrate 1.

It should be noted that, in conjunction with fig. 3A, 3B and 4F, each gate isolation trench 8 penetrates through the stacked structure 4, and the gate isolation trench 8 may divide the gate conductive layer 43 (the gate conductive layer 43 is formed in a subsequent manufacturing step) into a plurality of gate lines, so as to divide a plurality of memory blocks B on the semiconductor structure 200.

Similarly, each of the selection gate trenches 6 penetrates through the at least one insulating layer 40 and the at least one first sacrificial layer 41 on the side of the stacked structure 4 away from the substrate 1, that is, the selection gate trenches 6 penetrate through the at least one insulating layer 40 and the at least one first sacrificial layer 41 on the top of the stacked structure 4, the selection gate trenches 6 can be used for dividing the at least one gate conductive layer 43 of the stacked structure 4 away from the substrate 1, and the memory block B can be further divided into a plurality of sub-memory blocks B1, so as to increase the number of effective channel holes of the semiconductor structure 200, and thus increase the storage density of the semiconductor structure 200.

Illustratively, as shown in fig. 4B, each select gate trench 6 penetrates through two insulating layers 40 and two first sacrificial layers 41 in the stacked structure 4 away from the substrate 1.

S30: as shown in fig. 4D, 4E and 4F, the first sacrificial layer 41 is removed to form a cavity 42, and a gate conductive material is deposited to form a gate conductive layer 43 within the cavity 42.

It should be noted that the gate trenches 6 and the gate spacers 8 may expose the plurality of first sacrificial layers 41, for example, one side of the plurality of first sacrificial layers 41 is exposed, all the first sacrificial layers 41 may be etched and removed through the gate spacers 8 by using a wet etching process, and the cavities 42 are formed at the positions where the first sacrificial layers 41 are disposed.

A gate conductive material is deposited in the cavity 42 through the select gate trench 6 and the gate spacer 8 using a thin film deposition process to form a gate conductive layer 43 within the cavity 42. In addition, in the process of depositing the gate conductive material, a part of the gate conductive material is deposited in the select gate trench 6 and the gate spacer 8, and the part of the gate conductive material deposited in the select gate trench 6 and the gate spacer 8 is removed through the subsequent preparation steps.

By the above manufacturing method, the purpose of replacing the plurality of first sacrificial layers 41 with the plurality of gate conductive layers 43 is achieved.

S40: as shown in fig. 4I, 4J and 4K, the gate conductive material in the select gate trench 6 is removed.

It can be understood that by removing the gate conductive material in the select gate trench 6, the problem of electrical connection between gate lines resulting from the division of the gate conductive layer 43 by the select gate trench 6 can be avoided.

S50: as shown in fig. 4L, a top select gate cut 60 is formed within the select gate trench 6.

It will be appreciated that the material forming top select gate tangents 60 is a dielectric material, so that insulation between the segments of gate conductive layer 43 adjacent to select gate trenches 6 is achieved by the top select gate tangents 60 blocking the segments of gate conductive layer 43.

In the above manufacturing method of the present disclosure, a plurality of gate spacers 8 and a plurality of selection gate trenches 6 are formed on the stacked structure 4, and a plurality of selection gate trenches 6 are disposed between two adjacent gate spacers 8. Before the top selection gate tangents 60 are formed in the selection gate trench 6, the first sacrificial layer 41 is removed through the gate isolation grooves 8 to form the cavity 42, so that the problem that the first sacrificial layer 41 between two adjacent top selection gate tangents 60 cannot be removed through the gate isolation grooves 8 due to the obstruction of the top selection gate tangents 60 can be solved. Moreover, before depositing the gate conductive material to form the gate conductive layer 43, the plurality of selection gate trenches 6 are formed on the stacked structure 4, so that the insulating layer 40 and the gate conductive layer 43 in the stacked structure 4 need to be etched in the process of forming the plurality of selection gate trenches 6, and the difficulty of the preparation process is reduced.

And, a gate conductive material is deposited in the cavity 42 through the selection gate trench 6 and the gate spacer 8 to form a gate conductive layer 43 within the cavity 42 to replace the plurality of first sacrificial layers 41 with the plurality of gate conductive layers 43. Then, the gate conductive material in the select gate trench 6 is removed, and a top select gate tangent 60 is formed in the select gate trench 6 to form a plurality of top select gate tangents 60 between two adjacent gate spacers 8, so that the memory block B can be further divided into a plurality of sub-memory blocks B1 to increase the number of effective channel holes of the semiconductor structure 200, thereby increasing the memory density of the memory.

In some embodiments, as shown in fig. 2B, S20: forming a plurality of gate spacers 8 and a plurality of select gate trenches 6, including the following S21-S23:

s21: as shown in fig. 4B, a plurality of select gate trenches 6 are formed in the stacked structure 4.

S22: as shown in fig. 4C, a second sacrificial layer 7 is formed, and the second sacrificial layer 7 fills the plurality of select gate trenches 6 and covers the surface of the stacked structure 4 away from the substrate 1.

By forming the second sacrificial layer 7 on the stacked structure 4, the plurality of select gate trenches 6 and the surface of the stacked structure 4 away from the substrate 1 can be filled with the second sacrificial layer 7, so as to improve the surface flatness of the stacked structure 4, thereby facilitating the subsequent manufacturing steps, for example, facilitating the formation of a plurality of gate spacers 8 in the stacked structure 4.

S23: as shown in fig. 4D, a plurality of gate spacers 8 are formed in the stacked structure 4.

The plurality of select gate trenches 6 are filled with the second sacrificial layer 7 and cover the surface of the stacked structure 4 away from the substrate 1, so that the surface flatness of the stacked structure 4 is improved, and therefore, in the process of forming the plurality of gate spacers 8 in the stacked structure 4, for example, an exposure and development process may be adopted to form a patterned photoresist layer on the surface of the stacked structure 4, the stacked structure 4 is etched by using the patterned photoresist layer as a mask, the plurality of gate spacers 8 are formed, and the photoresist layer is removed.

Moreover, since the second sacrificial layer 7 fills the plurality of select gate trenches 6, the photoresist layer can be prevented from falling into the select gate trenches 6 and being difficult to remove.

In some embodiments, the second sacrificial layer 7 is the same material as the first sacrificial layer 41.

Illustratively, as can be seen from fig. 4D and 4E, the same wet etching process and the same etching solution can be used to remove the first sacrificial layer 41 and the second sacrificial layer 7.

Illustratively, the material of the second sacrificial layer 7 and the first sacrificial layer 41 both comprise silicon nitride.

In some embodiments, as shown in fig. 2C, at S40: before removing the gate conductive material in the select gate trench 6, the preparation method further includes the following steps S31 to S32:

s31: as shown in fig. 4F and 4G, the gate conductive material in the gate spacer 8 and on the surface of the stacked structure 4 remote from the substrate 1 is removed.

It should be noted that, as described above, during the deposition of the gate conductive material in the cavity 42, the gate conductive material is deposited in the cavity 42 to form the gate conductive layer 43, and a part of the gate conductive material is deposited in the select gate trench 6 and the gate spacer 8, and a part of the gate conductive material is deposited on the surface of the stacked structure 4 away from the substrate 1.

By the above manufacturing method, the gate conductive material on the inner surface of the gate isolation groove 8 and the surface of the stacked structure 4 away from the substrate 1 is removed, so that the two adjacent gate conductive layers 43 are prevented from being electrically connected with each other along the thickness direction Z of the substrate 1 through the gate conductive material on the inner surface of the gate isolation groove 8.

Illustratively, as shown in fig. 2D, S31: removing the gate conductive material in the gate spacer 8 and on the surface of the stacked structure 4 away from the substrate 1, including the following steps S311 to S312:

s311: as shown in fig. 4F and 4G, the gate conductive material on the sidewalls and bottom of the gate spacer 8 and the surface of the stacked structure 4 remote from the substrate 1 is removed.

For example, a wet etching process may be used, in which an etching liquid is used to etch the gate conductive material on the sidewalls and bottom of the gate spacer 8 and the surface of the stack 4 remote from the substrate 1.

S312: as shown in fig. 4F and 4G, a portion of the gate conductive layer 43 near the gate spacer 8 is removed, and a side surface of the gate conductive layer 43 near the gate spacer 8 is recessed with respect to a side surface of the insulating layer 40 near the gate spacer 8 to form a first recess 430.

For example, a wet etching process is used to etch the gate conductive material on the sidewalls and bottom of the gate spacer 8 and the surface of the stacked structure 4 away from the substrate 1 with an etching solution, and then the duration of the wet etching process is increased, and the etching solution is used to continuously etch the portion of the gate conductive layer 43 close to the gate spacer 8, so that the side of the gate conductive layer 43 close to the gate spacer 8 is recessed relative to the side of the insulating layer 40 close to the gate spacer 8 in the direction U away from the gate spacer 8, so as to form the first recess 430 on the gate conductive layer 43.

Through the above preparation method, the portion of the gate conductive layer 43 close to the gate isolation groove 8 is removed, and the first recess 430 is formed on the gate conductive layer 43, so that the gate conductive material on the inner surface of the gate isolation groove 8 can be more sufficiently removed, thereby avoiding the electrical connection between two adjacent gate conductive layers 43 along the third direction Z through the gate conductive material on the inner surface of the gate isolation groove 8.

S32: as shown in fig. 4H and 4I, a first protection layer 90 is formed to cover the inner surface of the gate spacer 8, and the first protection layer 90 plays a role of protecting the gate spacer 8 during the subsequent removal of the gate conductive material in the select gate trench 6.

Illustratively, as shown in fig. 2E, S32: forming the first protective layer 90 covering the inner surface of the gate spacer 8 includes the following steps S321 to S322:

s321: as shown in fig. 4H, a first protective film 9 is formed, and the first protective film 9 covers the gate spacer 8, the select gate trench 6, and the surface of the stacked structure 4 away from the substrate 1.

For example, a thin film deposition process may be used to form the first protective film 9, and the first protective film 9 covers the gate spacer 8, the select gate trench 6, and the surface of the stacked structure 4 away from the substrate 1.

S322: as shown in fig. 4H and 4I, a portion of the first protective film 9 covering the surface of the select gate trench 6 and the stacked structure 4 away from the substrate 1 is removed to form a first protective layer 90.

It is understood that, referring to fig. 4H, the portion of the first protective film 9 covering the select gate trench 6 and the surface of the stacked structure 4 remote from the substrate 1 are both located on top of the stacked structure 4. Referring to fig. 4I, a dry etching process may be used to etch the portion of the first protective film 9 on top of the stacked structure 4, leaving the portion of the first protective film 9 covering the inner surface of the gate spacer 8, i.e., the first protective layer 90.

In some embodiments, as shown in fig. 4F and 4G, in the process of depositing the gate conductive material, the gate conductive material is deposited on the surfaces of the select gate trench 6, the gate spacer 8 and the stacked structure 4 away from the substrate 1, and the gate conductive material fills the select gate trench 6 to form the sacrificial filling portion 44.

It should be noted that, referring to fig. 4F and 4G, the size of the opening of the select gate trench 6 is smaller than the size of the opening of the gate spacer 8, and the gate conductive material is more easily accumulated in the select gate trench 6, even filled up, to form the sacrificial filling portion 44.

Thus, referring to fig. 4F and 4G, in the process of removing the gate conductive material in the gate spacer 8 and on the surface of the stacked structure 4 remote from the substrate 1, the portion of the sacrificial fill 44 remote from the substrate 1 is removed, forming a second recess 431.

Illustratively, using a wet etching process, an etching solution is contacted with the gate conductive material in the gate spacer 8 and on the surface of the stacked structure 4 away from the substrate 1, and the portion of the sacrificial filling portion 44 away from the substrate 1, so as to etch the gate conductive material in the gate spacer 8 and on the surface of the stacked structure 4 away from the substrate 1, and the portion of the sacrificial filling portion 44 away from the substrate 1, and form the second recess 431 in the select gate trench 6.

Further, as shown in fig. 4H, in the process of forming the first protective film 9, the first protective film 9 covers the second recess 431 in the select gate trench 6. As shown in fig. 4I, in the process of forming the first protective layer 90, a portion of the first protective film 9 covering the second recess 431 is removed.

Illustratively, a thin film deposition process may be employed to form a first protective film 9, the first protective film 9 covering the gate spacer 8 and the surface of the stacked structure 4 remote from the substrate 1, and the second recess 431 within the select gate trench 6.

Illustratively, a dry etching process may be used to etch the portion of the first protective film 9 covering the second recess 431 and the surface of the stacked structure 4 remote from the substrate 1, leaving the portion of the first protective film 9 (the first protective layer 90) covering the inner surface of the gate spacer 8.

In other embodiments, as shown in fig. 5A, the opening size of the select gate trench 6 is larger, during deposition of the gate conductive material, the gate conductive material covers the inner surface of the select gate trench 6, the sacrificial capping layer 62 is formed, and the select gate trench 6 has a gap 63 therein.

It is understood that, due to the large opening size of the select gate trench 6, the select gate trench 6 is not filled with the gate conductive material, but the inner surface of the select gate trench 6 is covered with a layer of the gate conductive material to form the sacrificial capping layer 62, thereby forming the gap 63 in the select gate trench 6.

Based on this, in some embodiments, as shown in fig. 2L, at S31: before removing the gate conductive material in the gate spacer 8 and on the surface of the stacked structure 4 away from the substrate 1, the preparation method further includes the following steps S301 to S302:

s301: as shown in fig. 5B, a second protective film 91 is formed, the second protective film 91 covering the gate spacer 8, the select gate trench 6, and the gate conductive material on the surface of the stacked structure 4 remote from the substrate 1.

Illustratively, the second protective film 91 fills the gap 63 during the formation of the second protective film 91 using a film deposition process. For example, the thin film Deposition process may include an Atomic Layer Deposition (ALD) process.

S302: as shown in fig. 5B and 5C, a portion of the second protective film 91 covering the gate spacer 8 and the gate conductive material on the surface of the stacked structure 4 away from the substrate 1 is removed to form a second protective layer 92.

It is understood that the sacrificial cover layer 62 is a layer of gate conductive material covering the inner surface of the select gate trench 6, and the thickness of the sacrificial cover layer 62 is relatively thin.

The second protection layer 92 fills the gap 63 to protect the sacrificial cover layer 62, so that the situation that the part of the gate conductive layer 43 close to the select gate trench 6 is etched more after the sacrificial cover layer 62 is etched in the subsequent preparation step can be avoided, and the influence on the conductivity of the gate conductive layer 43 can be avoided.

In some embodiments, as shown in fig. 5C and 5D, during the removal of the gate conductive material in the gate spacer 8 and on the surface of the stacked structure 4 remote from the substrate 1, the portion of the sacrificial cover layer 62 remote from the substrate 1 is removed, forming a third recess 620.

Illustratively, using a wet etching process, an etching liquid is brought into contact with the gate conductive material in the gate spacer 8 and on the surface of the stacked structure 4 remote from the substrate 1, and the top of the sacrificial cover layer 62, thereby etching the gate conductive material in the gate spacer 8 and on the surface of the stacked structure 4 remote from the substrate 1, and the portion of the sacrificial cover layer 62 remote from the substrate 1, and forming a third recess 620 in the select gate trench 6.

It can be understood that, by filling the gap 63 with the second protective layer 92, the contact area of the sacrificial cover layer 62 and the etching solution is reduced (only the top of the sacrificial cover layer 62 is in contact with the etching solution), so as to avoid the sacrificial cover layer 62 from being completely etched and avoid the part of the gate conductive layer 43 close to the select gate trench 6 from being excessively etched.

Furthermore, in some embodiments, as shown in fig. 5D and 5E, during the formation of the first protective film 9, the first protective film 9 covers the third recess 620 in the select gate trench 6. As shown in fig. 5E and 5F, in the process of forming the first protective layer 90, a portion of the first protective film 9 covering the third recess 620 is removed.

Illustratively, a thin film deposition process may be used to form the first protective film 9, the first protective film 9 covering the gate spacer 8 and the surface of the stacked structure 4 away from the substrate 1, and the third recess 620 in the select gate trench 6.

Illustratively, the portion of the first protective film 9 covering the third recess 620 and the surface of the stacked structure 4 remote from the substrate 1 is removed, leaving the portion of the first protective film 9 (the first protective layer 90) covering the inner surfaces of the gate spacer 8.

In some embodiments, as shown in fig. 2F, S40: removing the gate conductive material in the select gate trench 6, including the following S41-S42:

s41: as shown in fig. 4I and 4J, the gate conductive material within the select gate trench 6 is removed.

Illustratively, the gate conductive material in the select gate trench 6 may be etched using a dry etch process to remove the gate conductive material within the select gate trench 6. Also, the first protective layer 90 may function to protect the gate spacer 8 during the first etching.

By the above preparation method, the gate conductive material on the inner surface of the select gate trench 6 is removed, and the adjacent two gate conductive layers 43 are prevented from being electrically connected with each other through the gate conductive material on the inner surface of the select gate trench 6 along the third direction Z.

S42: as shown in fig. 4J and 4K, a portion of the gate conductive layer 43 near the select gate trench 6 is removed, and a side of the gate conductive layer 43 near the select gate trench 6 is recessed with respect to a side of the insulating layer 40 near the select gate trench 6 to form a fourth recess 432.

Illustratively, a portion of the gate conductive layer 43 close to the select gate trench 6 is etched using a wet etching process, so that a side surface of the gate conductive layer 43 close to the select gate trench 6 is recessed with respect to a side surface of the insulating layer 40 close to the select gate trench 6 in a direction V away from the select gate trench 6, to form a fourth recess 432 on the gate conductive layer 43.

Through the above preparation method, in the case that the selection gate trench 6 penetrates through two gate conductive layers 43 or more gate conductive layers 43, a portion of the gate conductive layer 43 close to the selection gate trench 6 is removed, and the fourth recess 432 is formed on the gate conductive layer 43, so that the gate conductive material on the inner surface of the selection gate trench 6 can be more sufficiently removed, thereby avoiding the electrical connection between two adjacent gate conductive layers 43 through the gate conductive material on the inner surface of the selection gate trench 6 along the third direction Z.

In some embodiments, as shown in fig. 2G, S50: forming a top select gate cut 60 within the select gate trench 6, including the following S51:

s51: as shown in fig. 4L, a dielectric material is deposited and the dielectric material filling in the select gate trenches 6 forms top select gate tangents 60. Wherein during the deposition of the dielectric material, the dielectric material is also deposited within the gate spacers 8.

It will be appreciated that the smaller opening size of the select gate trench 6 compared to the opening size of the gate spacer 8 makes it easier to fill the select gate trench 6 with dielectric material for a given amount of deposited dielectric material. Thus, as shown in fig. 4L, the select gate trench 6 is filled with a dielectric material, the gate spacer 8 is not filled with a dielectric material, and a layer of dielectric material is deposited in the gate spacer 8 and on the surface of the stacked structure 4 remote from the substrate 1.

Also, the dielectric material deposited in the gate spacer 8 forms an isolation layer 61 for protecting and isolating the structures covered thereby, e.g. the first protection layer 90, the gate spacer 8 and the portion of the gate conductive layer 43 close to the gate spacer 8.

By the above preparation method, a dielectric material is deposited to fill the select gate trench 6, a top select gate tangent 60 is formed in the select gate trench 6, the top select gate tangent 60 can divide the gate conductive layer 6 into two parts, and the top select gate tangent 60 can block the two divided parts of the gate conductive layer 6 to insulate the two divided parts of the gate conductive layer 6.

In some embodiments, as shown in fig. 2H, at S50: after forming the top select gate cut 60 in the select gate trench 6, the method further includes the following step S60:

s60: as shown in fig. 4M, a filling pattern 80 is formed within the gate spacer 8.

It is understood that the filling pattern 80 may also divide the gate conductive layer 6 into two parts, and the filling pattern 80 may block the divided two parts of the gate conductive layer 6 to insulate the divided two parts of the gate conductive layer 6 from each other.

Furthermore, the gate spacer 8 is filled with the filling pattern 80, which can improve the integrity of the semiconductor structure 200 and further improve the structural strength of the semiconductor structure 200.

Illustratively, a thin film deposition process may be employed to deposit a filling material on the stacked structure 4, the filling material filling in the gate spacer 8, and the filling material being deposited on a surface of the stacked structure 4 remote from the substrate 1. Then, the filling material on the surface of the stacked structure 4 away from the substrate 1 is removed, and the filling material in the gate spacer 8 is remained to form a filling pattern 80.

Illustratively, the fill material may comprise polysilicon.

In some embodiments, as shown in fig. 2I, at S10: before forming the stacked structure 4 on the substrate 1, the preparation method further includes S01:

s01: as shown in fig. 4A, at least one stop layer S is formed on the substrate 1.

It is understood that the "stop layer S" is also referred to as an "etch stop layer S", i.e., the etch is terminated at the stop layer S during the etching of the film layer on the side of the stop layer S, and the stop layer S is not etched. The specific functions of the stop layer S according to the embodiments of the present disclosure will be described in the following related steps.

Illustratively, as shown in fig. 4A, S01 includes: a first stop layer 2 and a second stop layer 3 are formed in this order on a substrate 1.

As shown in fig. 2I, between S10 and S20, the preparation method further includes the following S11:

s11: as shown in fig. 4A, a plurality of channel structures 5 are formed, the channel structures 5 penetrating the stacked structure 4 and the at least one stop layer S and extending into the substrate 1.

As shown in fig. 4A, the channel structure 5 includes a memory function layer 51 and a channel layer 52, which are disposed adjacent to each other. Illustratively, both are formed sequentially. Illustratively, the memory function layer 51 may be an Oxide-Nitride-Oxide stack (ONO). For example, the storage function layer 51 includes a blocking layer 5A, a charge storage layer 5B, and a tunneling layer 5C, which are formed by deposition.

As shown in fig. 2I, at S50: after forming the top select gate tangent 60 in the select gate trench 6, the preparation method further includes the following steps S70 to S71:

s70: as shown in fig. 4N to 4Q, the substrate 1 and a portion of the memory function layer 51 of the channel structure 5 extending into the substrate 1 are sequentially removed to expose the channel layer 52 of the channel structure 5.

Illustratively, as shown in fig. 4A, the substrate 1 includes a base 10, a third sacrificial layer 11, and a fourth sacrificial layer 12 formed in this order.

For example, the material of the substrate 10 may include at least one of single crystal silicon, single crystal germanium, a group III-V compound semiconductor material, and a group IIVI compound semiconductor material. The material of the third sacrificial layer 11 may include silicon oxide. The material of the fourth sacrificial layer 12 may comprise polysilicon.

As shown in fig. 4M and 4N, the base 10 of the substrate 1 is removed, for example, the base 10 of the substrate 1 may be removed by a Chemical Mechanical Polishing (CMP) process, a dry etching process or a wet etching process.

As shown in fig. 4N and 4O, the third sacrificial layer 11 of the substrate 1 is removed, for example, the third sacrificial layer 11 of the substrate 1 may be removed by a wet etching process.

The fourth sacrificial layer 12 may serve as a stop layer for the third sacrificial layer 11, and it is understood that the etching solution used in the wet etching process may etch the third sacrificial layer 11 but may not etch the fourth sacrificial layer 12, and the etching is terminated at the fourth sacrificial layer 12.

As shown in fig. 4O and 4P, the fourth sacrificial layer 12 of the substrate 1 is removed, for example, the fourth sacrificial layer 12 of the substrate 1 may be removed by a wet etching process.

The first stop layer 2 can be used as a stop layer of the fourth sacrificial layer 12, and it can be understood that the etching solution used in the above wet etching process can etch the fourth sacrificial layer 12, but can not etch the first stop layer 2, and the etching is terminated at the first stop layer 2. Moreover, the etching solution used in the wet etching process may not etch the barrier layer 5A of the storage function layer 51, i.e., the etching is stopped at the barrier layer 5A, so that the portion of the channel structure 5 extending into the substrate 1 may be exposed.

As shown in fig. 4P and 4Q, a portion of the memory function layer 51 of the channel structure 5 extending into the substrate 1 is removed to expose the channel layer 52 of the channel structure 5. For example, a wet etching process may be used to remove a portion of the memory function layer 51 of the channel structure 5 extending into the substrate 1 to expose the channel layer 52 of the channel structure 5.

It is understood that in the process of removing the portion of the memory function layer 51 of the channel structure 5 extending into the substrate 1, the etching liquid used in the wet etching process also etches the first stop layer 2, but may not etch the second stop layer 3, and may not etch the channel layer 52 of the memory function layer 51, i.e., the etching ends at the second stop layer 3 and the channel layer 52.

S71: as shown in fig. 4R, the source layer 13 is formed, and the source layer 13 covers the exposed portion of the channel layer 52 to be electrically connected to the channel layer 52.

Illustratively, a thin film deposition process may be employed to form a source layer 13 on a side of the second stop layer 3 away from the stack structure 4, the source layer 13 covering the exposed portion of the channel layer 52 to be electrically connected to the channel layer 52.

In some embodiments, as shown in fig. 2J, S71: forming the source layer 13 includes the following S711 to S712:

s711: a doped polysilicon layer is formed.

Illustratively, the polysilicon layer may be doped using an ion implantation process, for example, by implanting P-type or N-type dopants into the polysilicon layer to improve the conductivity of the polysilicon layer.

S712: the polysilicon layer is annealed to form a source layer 13.

Illustratively, a Laser annealing process (Laser annealing, Laser Ann) may be used to anneal the polysilicon layer, repair lattice damage (caused by an ion implantation process) of the polysilicon layer material, and activate dopants implanted into the polysilicon layer.

In some embodiments, as shown in fig. 2K, at S71: after forming the source layer, the method further includes the following steps S80 to S81:

s80: as shown in fig. 4S, an interlayer dielectric layer 14 is formed on the side of the source layer 13 away from the stacked structure 4, and the interlayer dielectric layer 14 has at least one via hole H.

Illustratively, a thin film deposition process may be used to form an interlayer dielectric film on the side of the source layer 13 away from the stacked structure 4. For example, the material of the interlayer dielectric film may include silicon oxide.

The interlayer dielectric film is patterned by a patterning process, and at least one via hole H is opened in the interlayer dielectric layer 14.

S81: as shown in fig. 4S, a metal interconnection layer 15 is formed on a side of the interlayer dielectric layer 14 away from the stacked structure 4, and the metal interconnection layer 15 is electrically connected to the source layer 13 through at least one via H of the interlayer dielectric layer 14.

Illustratively, a thin film deposition process may be used to form a metal interconnection layer 15 on a side of the interlayer dielectric layer 14 away from the stacked structure 4, and the metal interconnection layer 15 is electrically connected to the source layer 13 through at least one via H of the interlayer dielectric layer 14. The portion of the metal interconnect layer 15 located within the via H is referred to as a Pick up Area (Pick up Area).

With the above arrangement, the source layer 13 can be led out from the back surface (bottom) of the semiconductor structure 200 by electrically connecting the source layer 13 and the metal interconnection layer 15, thereby simplifying the structural design of the semiconductor structure 200.

In other embodiments, as shown in fig. 6A and 6B, in the process of removing the portion of the memory function layer 51 of the channel structure 5 extending into the substrate 1, the portion of the first protective layer 90 extending into the substrate 1 and the portion of the isolation layer 61 extending into the substrate 1 are also removed to expose the filling pattern 80.

It is understood that, by using a wet etching process, the portion of the memory function layer 51 of the channel structure 5 extending into the substrate 1 is removed, and the etching solution used by the wet etching process may also etch the portion of the first protection layer 90 extending into the substrate 1 and the portion of the isolation layer 61 extending into the substrate 1, but may not etch the filling pattern 80, i.e., the etching ends at the filling pattern 80.

As shown in fig. 6C, the source layer 13 is formed, and the source layer 13 covers the exposed portion of the channel layer 52 to be electrically connected to the channel layer 52. Also, the source layer 13 covers the exposed portion of the filling pattern 80 to be electrically connected with the filling pattern 80.

In the above embodiments of the present disclosure, the material of the filling pattern 80 includes a conductive material, and the exposed portion of the filling pattern 80 is covered by the source layer 13 to be electrically connected to the filling pattern 80.

With the above arrangement, the source layer 13 can be led out from the front surface (top) of the semiconductor structure 200 by electrically connecting the source layer 13 to the filling pattern 80.

According to the preparation method of the semiconductor structure provided by the present disclosure, a stacked structure 4 is first formed on a substrate 1, and the stacked structure 4 includes a plurality of insulating layers 40 and a plurality of first sacrificial layers 41 which are alternately arranged. Then, a plurality of gate spacers 8 are formed through the stacked structure 4, and a plurality of select gate trenches 6 are formed between two adjacent gate spacers 8, each select gate trench 6 penetrating at least one insulating layer 40 and at least one first sacrificial layer 41 of the stacked structure 4 away from the substrate 1. Thereafter, the first sacrificial layer 41 is removed to form a cavity 42 in the stacked structure 4, and a gate conductive material is deposited in the cavity 42 to form a gate conductive layer 43. Finally, the gate conductive material in the select gate trench 6 is removed, forming a top select gate cut 60 within the select gate trench 6.

According to the preparation method disclosed by the invention, before the top selection gate tangent 60 is formed in the selection gate groove 6, the first sacrificial layer 41 is removed through the gate isolation groove 8 to form the cavity 42, so that the problem that the first sacrificial layer 41 between two adjacent top selection gate tangents 60 cannot be removed through the gate isolation groove 8 due to the obstruction of the top selection gate tangent 60 after the top selection gate tangent 60 is formed in the selection gate groove 6 can be solved.

Moreover, before depositing the gate conductive material to form the gate conductive layer 43, the plurality of selection gate trenches 6 are formed on the stacked structure 4, so that the insulating layer 40 and the gate conductive layer 43 in the stacked structure 4 need to be etched in the process of forming the plurality of selection gate trenches 6 after depositing the gate conductive material to form the gate conductive layer 43, and the difficulty of the preparation process is reduced.

Further, a gate conductive material is deposited in the cavity 42 through the select gate trench 6 and the gate spacer 8 to form a gate conductive layer 43 within the cavity 42 to replace the plurality of first sacrificial layers 41 with the plurality of gate conductive layers 43. Then, the gate conductive material in the select gate trench 6 is removed, and a top select gate tangent 60 is formed in the select gate trench 6 to form a plurality of top select gate tangents 60 between two adjacent gate spacers 8, so that the memory block B can be further divided into a plurality of sub-memory blocks B1 to increase the number of effective channel holes of the semiconductor structure 200, thereby increasing the memory density of the memory.

In addition, some embodiments of the present disclosure also provide a semiconductor structure, as shown in fig. 3A and 3B, the semiconductor structure 200 includes a source layer 13, a stacked structure 4 disposed on the source layer 13, the stacked structure 4 includes a plurality of film pairs 4B stacked one on another, and each film pair 4B includes an adjacent insulating layer 40 and a gate conductive layer 43.

It should be noted that the "stacked structure" in the above paragraph belongs to the structure (product structure) in the semiconductor structure 200, and the "stacked structure" mentioned in the foregoing method for manufacturing a semiconductor structure belongs to the structure in the manufacturing process, and the difference therebetween is that the stacked structure in the manufacturing process includes the plurality of insulating layers 40 and the plurality of first sacrificial layers 41 that are alternately arranged, and the stacked structure in the semiconductor structure 200 includes the plurality of insulating layers 40 and the plurality of gate conductive layers 43 that are alternately arranged.

As shown in fig. 3A, the stacked structure 4 is provided with a plurality of gate spacers 8 and a plurality of select gate trenches 6, and a plurality of select gate trenches 6 are provided between two adjacent gate spacers 8. As shown in fig. 3B, the gate spacer 8 penetrates the stacked structure 4, and the select gate trench 6 penetrates at least one insulating layer 40 and at least one gate conductive layer 43 on a side of the stacked structure 4 away from the source layer 13, i.e., the select gate trench 6 penetrates at least one insulating layer 40 and at least one gate conductive layer 43 on a top of the stacked structure 4. The semiconductor structure 200 also includes a top select gate cut 60 disposed within the select gate trench 6.

In the above semiconductor structure 200 of the present disclosure, the plurality of gate spacers 8 are used to divide the semiconductor structure 200 into a plurality of memory blocks. A plurality of selection gate grooves 6 are arranged between two adjacent gate isolation grooves 8, and top selection gate tangents 60 are arranged in the selection gate grooves 6, namely a plurality of top selection gate tangents 60 are arranged between two adjacent gate isolation grooves 8, and the top selection gate tangents 60 are used for cutting the gate conductive layer 43, so that the memory block can be further divided into a plurality of sub memory blocks, the number of effective channel holes of the semiconductor structure is increased, and the memory density of the memory is increased.

Some embodiments of the present disclosure also provide a storage system 300, as shown in fig. 7 and 8, the storage system 300 includes a controller 301, and the three-dimensional memory 100 as described in any of the above embodiments. The controller 301 may be coupled to the three-dimensional memory 100 and configured to control the three-dimensional memory 100 to store data.

Illustratively, the Storage system 300 described above may be integrated into various types of Storage devices, for example, included in the same package (e.g., Universal Flash Storage (UFS) package or Embedded multimedia Card (eMMC) package). That is, the storage system 300 may be applied to and packaged into different types of electronic products, such as mobile phones, computers (including but not limited to desktop computers, laptop computers, tablet computers, vehicle computers, and the like), televisions, set-top boxes, gaming consoles, printers, positioning devices, in-vehicle devices, wearable electronic devices, smart sensors, Virtual Reality (VR) devices, Augmented Reality (AR) devices, or any other suitable electronic device having storage therein.

Illustratively, as shown in fig. 7, the storage system 300 may include: a controller 301 and a three-dimensional memory 100. The memory system 300 may be integrated into a memory card.

The Memory Card includes any one of a PC Card (PCMCIA), a Compact Flash (CF) Card, a Smart Media (SM) Card, a Memory stick, a Multimedia Card (MMC), a Secure Digital Memory Card (SD), and a UFS.

Illustratively, as shown in fig. 8, the storage system 300 may include: a controller 301 and a plurality of three-dimensional memories 100. The storage system 300 may be integrated into a Solid State Drive (SSD).

In some embodiments, in storage system 300, for example, controller 301 may be configured to operate in a low duty cycle environment, such as an SD card, CF card, Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, mobile phones, and so forth.

As another example, the controller 301 is configured to operate in a high duty cycle environment SSD or eMMC for data storage and enterprise storage arrays of mobile devices such as smart phones, tablets, laptops, and the like.

In some embodiments, the controller 301 may be configured to manage data stored in the three-dimensional memory 100 and communicate with an external device (e.g., a host). In some embodiments, the controller 301 may also be configured to control operations of the three-dimensional memory 100, such as read, erase, and program operations. In some embodiments, the controller 301 may also be configured to manage various functions with respect to data stored or to be stored in the three-dimensional memory 100, including at least one of bad block management, garbage collection, logical-to-physical address translation, wear leveling. In some embodiments, the controller 301 is further configured to process error correction codes with respect to data read from the three-dimensional memory 100 or written to the three-dimensional memory 100.

Of course, the controller 301 may also perform any other suitable function, such as formatting the three-dimensional memory 100. For example, the controller 301 may communicate with an external device (e.g., a host) through at least one of various interface protocols.

It should be noted that the interface protocol includes at least one of a USB protocol, an MMC protocol, a Peripheral Component Interconnect (PCI) protocol, a PCI express (PCI-E) protocol, an Advanced Technology Attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a Small Computer System Interface (SCSI) protocol, an Enhanced Small Disk Interface (ESDI) protocol, an Integrated Drive Electronics (IDE) protocol, and a Firewire protocol.

In the above embodiments of the present disclosure, the memory system 300 includes the semiconductor structure 200 or the three-dimensional memory 100 provided in any of the above embodiments, so that the memory capacity of the memory system 300 is increased.

Some embodiments of the present disclosure also provide an electronic device, as shown in fig. 9, the electronic device 400 including the storage system 300 as described in the above embodiments.

In the above embodiments of the present disclosure, the electronic device 400 includes the storage system 300 provided in the above embodiments, and the storage capacity of the electronic device 400 can be increased.

Illustratively, the electronic device 400 described above includes at least one of: the mobile phone, the desktop computer, the tablet computer, the notebook computer, the server, the vehicle-mounted equipment, the wearable equipment, the portable power source.

The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.

Claims

1. A method for fabricating a semiconductor structure, comprising:

forming a stacked structure on a substrate, the stacked structure comprising a plurality of film layer pairs arranged in a stack, each film layer pair comprising an adjacent insulating layer and a first sacrificial layer;

forming a plurality of grid separating grooves and a plurality of selection grid grooves; a plurality of selection gate grooves are arranged between every two adjacent gate separation grooves, the gate separation grooves penetrate through the stacked structure, and the selection gate grooves penetrate through at least one insulating layer and at least one first sacrificial layer on one side, far away from the substrate, of the stacked structure;

removing the first sacrificial layer to form a cavity, and depositing a gate conductive material to form a gate conductive layer in the cavity;

removing the gate conductive material in the selective gate trench;

and forming a top selection gate tangent in the selection gate groove.

2. The method of claim 1, wherein forming the plurality of gate spacers and the plurality of select gate trenches comprises:

forming the plurality of select gate trenches in the stacked structure;

forming a second sacrificial layer, wherein the second sacrificial layer fills the plurality of selection gate grooves and covers the surface of the stacking structure far away from the substrate;

forming the plurality of gate spacers in the stacked structure.

3. The production method according to claim 2, wherein the second sacrificial layer is the same material as the first sacrificial layer.

4. The method of claim 1, further comprising, prior to said removing the gate conductive material in the select gate trench:

removing the gate conductive material in the gate isolation groove and on the surface of the stacked structure far away from the substrate;

and forming a first protective layer covering the inner surface of the grid isolation groove.

5. The method of claim 4, wherein the removing the gate conductive material in the gate spacer and on the surface of the stacked structure away from the substrate comprises:

removing the gate conductive material on the side wall and the bottom of the gate separation groove and on the surface of the stacking structure far away from the substrate;

and removing the part of the gate conductive layer close to the gate isolation groove to form a first recess.

6. The method of claim 4, wherein the forming a first protective layer covering the inner surface of the gate spacer comprises:

forming a first protective film, wherein the first protective film covers the grid isolation groove, the selection grid groove and the surface of the stacked structure far away from the substrate;

and removing the parts of the first protective film, which cover the surfaces of the selection gate grooves and the stacking structures far away from the substrate, to form the first protective layer.

7. The method according to claim 4, wherein during the deposition of the gate conductive material, the gate conductive material fills the select gate trench to form a sacrificial filling portion;

in the process of removing the gate conductive material in the gate isolation groove and on the surface of the stacked structure far away from the substrate, the part of the sacrificial filling part far away from the substrate is removed to form a second recess.

8. The method of claim 4, further comprising, prior to said removing the gate conductive material in the gate spacer and on the surface of the stacked structure remote from the substrate:

forming a second protective film covering the gate isolation grooves, the selection gate grooves and the gate conductive material on the surface of the stacking structure far away from the substrate;

and removing the part, which covers the grid separating groove and the grid conducting material on the surface of the stacking structure far away from the substrate, of the second protective film to form a second protective layer.

9. The method of claim 8, wherein during the deposition of the gate conductive material, the gate conductive material covers an inner surface of the select gate trench to form a sacrificial cover layer, the select gate trench having a gap therein;

in the process of forming a second protective film, the second protective film fills the gap;

and in the process of removing the gate conductive material in the gate isolation groove and on the surface of the stacked structure far away from the substrate, removing the part of the sacrificial covering layer far away from the substrate to form a third recess.

10. The method for preparing according to any one of claims 1 to 9, wherein the removing the gate conductive material in the select gate trench comprises:

removing the gate conductive material in the selective gate trench;

and removing the part, close to the selection gate groove, of the gate conducting layer, so that the side face, close to the selection gate groove, of the gate conducting layer is retracted inwards relative to the side face, close to the selection gate groove, of the insulating layer, and a fourth recess is formed.

11. The method of any one of claims 1 to 9, wherein forming a top select gate cut within the select gate trench comprises:

depositing a dielectric material, wherein the dielectric material filled in the selection gate groove forms the top selection gate tangent;

wherein, during the deposition of the dielectric material, the dielectric material is also deposited on the inner surfaces of the gate spacers.

12. The method of claim 11, further comprising, after forming a top select gate cut within the select gate trench:

and forming filling patterns in the gate isolation grooves.

13. The method according to any one of claims 1 to 9, further comprising, before forming the stacked structure on the substrate:

forming at least one stop layer on a substrate;

between the step of forming a stacked structure on the substrate and the step of forming the plurality of gate spacers and the plurality of select gate trenches, the method further comprises:

a plurality of channel structures are formed.

14. The method of claim 13, wherein the channel structure extends through the stack structure and the at least one stop layer and into the substrate; the channel structure comprises a storage function layer and a channel layer, and the storage function layer and the channel are adjacently arranged;

after forming a top select gate tangent in the select gate trench, further comprising:

sequentially removing the substrate and the part, extending into the substrate, of the memory function layer of the channel structure to expose the channel layer of the channel structure;

forming a source layer covering the exposed portion of the channel layer to be electrically connected with the channel layer.

15. The method of claim 14, wherein forming a source layer comprises:

forming a doped polysilicon layer;

and annealing the polycrystalline silicon layer to form the source electrode layer.

16. The method of claim 14, wherein after said forming a source layer, the method further comprises:

forming an interlayer dielectric layer on one side of the source layer far away from the stacking structure; the interlayer dielectric layer is provided with at least one through hole;

and forming a metal interconnection layer on one side of the interlayer dielectric layer far away from the stacking structure, wherein the metal interconnection layer is electrically connected with the source layer through at least one through hole of the interlayer dielectric layer.

17. A semiconductor structure, comprising:

a source layer;

a stack structure disposed on the source layer, including a plurality of stacked film pairs, each film pair including an adjacent insulating layer and a gate conductive layer; the stacked structure is provided with a plurality of grid electrode separation grooves and a plurality of selection grid grooves, and a plurality of selection grid grooves are arranged between every two adjacent grid electrode separation grooves; the grid separation groove penetrates through the stacked structure, and the selection grid groove penetrates through at least one insulating layer and at least one grid conducting layer on one side, far away from the source electrode layer, in the stacked structure;

and the top selection gate tangent line is arranged in the selection gate groove.

18. A three-dimensional memory, comprising: a semiconductor structure as in claim 17.

19. A memory system comprising the memory of claim 18 and a controller coupled to the memory and configured to control the memory to store data.

20. An electronic device, comprising: the storage system of claim 19.

21. The electronic device of claim 20, wherein the electronic device comprises at least one of: the mobile phone, the desktop computer, the tablet computer, the notebook computer, the server, the vehicle-mounted equipment, the wearable equipment, the portable power source.