CN114023756A

CN114023756A - Semiconductor structure, preparation method thereof, three-dimensional memory and storage system

Info

Publication number: CN114023756A
Application number: CN202111264319.1A
Authority: CN
Inventors: 陈阳; 王迪; 张中; 周文犀; 夏志良
Original assignee: Yangtze Memory Technologies Co Ltd
Current assignee: Yangtze Memory Technologies Co Ltd
Priority date: 2021-10-28
Filing date: 2021-10-28
Publication date: 2022-02-08

Abstract

The present disclosure relates to the field of semiconductor chip technologies, and in particular, to a semiconductor structure, a method for manufacturing the same, a three-dimensional memory, and a storage system. The problems of device structure performance deterioration, even failure and the like caused by poor filling of subsequent filling materials can be reduced. A semiconductor structure, comprising: a stacked structure including a plurality of insulating layers and a plurality of gate conductive layers alternately stacked in a first direction; the laminated structure is provided with a first core area and a step area; in the bench region, laminated structure divides into wall body and the stair structure who arranges in proper order along the third direction, is provided with the recess that runs through the wall body along the third direction on the upper surface of wall body, and the stair structure includes first bench cluster and the second bench cluster of arranging along the second direction, and the second bench cluster is compared and is kept away from in first bench cluster first nuclear core area, first bench cluster and second bench cluster all contact with the lateral wall of wall body, and the second bench cluster is located the below of recess, and insulating part embedding recess.

Description

Semiconductor structure, preparation method thereof, three-dimensional memory and storage system

Technical Field

The present disclosure relates to the field of semiconductor chip technologies, and in particular, to a semiconductor structure, a method for manufacturing the same, a three-dimensional memory, and a storage system.

Background

As the feature size of the memory cell approaches the lower limit of the process, the manufacturing technology such as the planar process becomes challenging and brings high cost, which causes the storage density of the planar memory such as the 2D NAND flash memory to approach the upper limit, which brings serious challenges to the semiconductor memory industry.

The above limitations are overcome by three-dimensional memories (e.g., 3D NAND flash memories), and in particular, by stacking memory cells three-dimensionally to form a multi-layered structure to increase the storage density, the storage capacity of which is several times higher than that of the same type of flat memory. With the increase of the number of layers of the three-dimensional memory, poor filling is easy to occur in the subsequent oxide filling process, and then the oxide filling material and the step are different materials, under the same heat treatment, larger stress is easy to generate due to the difference of expansion coefficients, and even the performance of the device is deteriorated and even the device is failed.

Disclosure of Invention

Embodiments of the present disclosure provide a semiconductor structure, a method for manufacturing the same, a three-dimensional memory and a storage system, which can reduce the problems of device structure performance deterioration, even failure, and the like caused by poor filling of a subsequent filling material.

In order to achieve the purpose, the embodiment of the disclosure adopts the following technical scheme:

in one aspect, a semiconductor structure is provided, comprising: a stacked structure including a plurality of insulating layers and a plurality of gate conductive layers alternately stacked in a first direction; the laminated structure is provided with a first core area and a step area which are sequentially arranged along a second direction; in the step area, the laminated structure is divided into a wall body and a step structure which are sequentially arranged along a third direction, a groove which at least penetrates through two adjacent wall bodies along the third direction is formed in the upper surface of the wall body, the step structure comprises a first step cluster and a second step cluster which are arranged along the second direction, the second step cluster is far away from the first core area compared with the first step cluster, the first step cluster and the second step cluster are both in contact with the side wall of the wall body, and the second step cluster is located below the groove; the insulating part is embedded into the groove and is in contact with the side wall of the groove; the first step cluster and the second step cluster respectively comprise a plurality of step groups, each step group comprises a plurality of grid conductive patterns which are arranged in a stepped mode, and each grid conductive pattern is located on one of the grid conductive layers; the first direction, the second direction and the third direction are mutually vertical.

In some embodiments, the first step cluster includes a plurality of step groups, and a step group closest to the groove is a first step group, and at least a part of the gate conductive pattern in the first step group is higher than the bottom of the groove.

In some embodiments, the uppermost gate conductive pattern of the first step group is located at an uppermost gate conductive layer of the plurality of gate conductive layers.

In some embodiments, the first step group and the second step cluster have a slope direction opposite to that of a step group adjacent to the first step group.

In some embodiments, a step group farthest from the groove among the plurality of step groups included in the first step cluster is a second step group, and at least a portion of the gate conductive pattern included in the second step group is higher than an uppermost gate conductive pattern included in a step group adjacent to the second step group in the first step cluster.

In some embodiments, in the second step group, each gate conductive pattern of at least some gate conductive patterns is located in the same gate conductive layer as at least one gate conductive pattern of the first step group, and the first step group is a step group closest to the groove among the plurality of step groups included in the first step cluster.

In some embodiments, the semiconductor structure further comprises a plurality of first gate lines in the first core region; the step area comprises a first sub-area and a second sub-area which are sequentially arranged along a second direction, the first sub-area is positioned on one side, close to the first core area, of the groove, and the groove is positioned in the second sub-area; the wall comprises a plurality of conductive wires; the first step cluster is positioned in the first sub-area, one grid conductive pattern contained in the first step cluster is in contact with one first conductive line, the first conductive line is in contact with one first grid line, the second step cluster is positioned in the second sub-area, one grid conductive pattern contained in the second step cluster is in contact with one second conductive line, and the second conductive line is in contact with one first grid line; wherein the first conductive line is a part of the wall where one conductive line is located in the first sub-region, and the second conductive line is a part of the wall where one conductive line is located in the first and second sub-regions.

In some embodiments, the semiconductor structure further comprises: a plurality of first contacts electrically connected to the first step cluster; and one of the two grid conductive patterns is in contact with at least one of the first contacts, and the other grid conductive pattern is not in contact with the first contacts.

In some embodiments, the first step cluster includes a third step group, which is one of the step groups at the lowest position; the second step cluster comprises a plurality of step groups, wherein one step group at the highest position is a fourth step group; the gate conductive pattern on the lowest layer in the third step group and the gate conductive pattern on the uppermost layer in the fourth step group are respectively located on two adjacent gate conductive layers in the plurality of gate conductive layers.

In some embodiments, in the plurality of step groups included in the same step cluster, the inclination directions of two adjacent step groups are opposite.

In some embodiments, the laminate structure further comprises: the second core area is positioned on one side, far away from the first core area, of the stepped area; the step structure further includes: and the third step cluster is positioned on one side of the groove far away from the first step cluster, and the third step cluster is contacted with the side wall of the wall body. The third step cluster comprises a plurality of step groups, each step group comprises a plurality of grid conductive patterns arranged in a ladder mode, and each grid conductive pattern is located on one of the grid conductive layers.

In some embodiments, the semiconductor structure further comprises a plurality of second gate lines in the second core region; the step area further comprises a third sub-area, and the third sub-area is positioned on one side, far away from the first core area, of the groove; the third step cluster is located in the third sub-area, and one gate conductive pattern included in the third step cluster is in contact with one third conductive line, the third conductive line is in contact with one second gate line, one gate conductive pattern included in the second step cluster is in contact with one fourth conductive line, and the fourth conductive line is in contact with one second gate line; wherein the third conductive line is a portion of the wall where one conductive line is located in the third sub-region, and the fourth conductive line is a portion of the wall where one conductive line is located in the second and third sub-regions.

In some embodiments, each of the plurality of gate conductive patterns in the first step cluster and the corresponding at least one gate conductive pattern in the third step cluster are included in the same gate conductive layer.

In another aspect, there is provided a three-dimensional memory including: a semiconductor structure as described above.

In another aspect, a storage system is provided, which includes a three-dimensional memory as described above and a controller coupled to the three-dimensional memory to control the three-dimensional memory to store data.

In another aspect, a method for fabricating a semiconductor structure is provided, including:

an initial stacked structure is formed, the initial stacked structure including a plurality of insulating layers and a plurality of sacrificial layers alternately stacked in a first direction.

The initial stacked structure is divided into a first core region and a terrace region which are sequentially arranged in a second direction.

Forming an initial wall body and an initial step structure which are sequentially arranged along a third direction on the initial laminated structure and are positioned in the step area; the upper surface of the initial wall body is provided with a groove which at least penetrates through two adjacent initial wall bodies along a third direction, the initial step structure comprises a first initial step cluster and a second initial step cluster which are arranged along a second direction, the first initial step cluster and the second initial step cluster are both contacted with the side wall of the initial wall body, and the second initial step cluster is positioned below the groove; the first direction, the second direction and the third direction are mutually vertical. The first initial step cluster and the second initial step cluster each include a plurality of initial step groups, each initial step group including a plurality of sacrificial patterns arranged in a staircase, each sacrificial pattern being located at one of the plurality of sacrificial layers;

and filling an insulating material in the groove to form an insulating part, wherein the insulating part is embedded in the groove and is in contact with the side wall of the groove.

And replacing the sacrificial layer in the initial laminated structure with a gate conductive layer to obtain a laminated structure comprising a plurality of insulating layers and a plurality of gate conductive layers.

In some embodiments, the forming of the initial wall and the initial step structure on the initial laminated structure and in the step area in sequence along the third direction includes: dividing the part of the initial laminated structure, which is positioned in the step area, into a wall area and a step area along a third direction; protecting the part of the initial laminated structure positioned in the wall body area, and etching the part of the initial laminated structure positioned in the step subarea to obtain the initial wall body positioned in the wall body area and the initial step structure positioned in the step subarea; and etching the initial wall body to form the groove on the upper surface of the initial wall body.

In some embodiments, the step partition includes a plurality of third sub-regions and a plurality of fourth sub-regions sequentially distributed along the second direction, each third sub-region including: the first protection area and the first etching area are located on one side, far away from the first core area, of the first protection area, and each fourth sub-area comprises: the second protection area and a second etching area are positioned on one side, close to the first core area, of the second protection area; the etching the part of the initial laminated structure, which is positioned in the step partition, comprises the following steps: protecting the parts of the initial laminated structure, which are positioned in the first protection area and the second protection area, and trimming and etching the parts of the initial laminated structure, which are positioned in the first etching area and the second etching area, to obtain a preliminary step structure, wherein the preliminary step structure comprises a first preliminary step cluster and a second preliminary step cluster which are sequentially arranged along a second direction, the first preliminary step cluster and the second preliminary step cluster both comprise a plurality of preliminary step groups, and the plurality of preliminary step groups are positioned at the same level; and for the plurality of preliminary step groups, the inclination directions of two adjacent preliminary step groups are opposite along the second direction; and at least performing preset etching on all initial step groups contained in the second initial step cluster, so that all initial step groups contained in the second initial step cluster are all decreased by the same level, and the first initial step cluster and the second initial step cluster are obtained.

In some embodiments, the etching of the initial wall and the preset etching of all the original step groups included in the second initial step cluster are performed simultaneously.

In some embodiments, further comprising:

before all initial step groups that the preliminary step cluster of second contained carry out the sculpture, right first preliminary step cluster with preliminary step cluster of second carries out predetermineeing the sculpture many times, makes a plurality of preliminary step groups that first preliminary step cluster contained be located different levels, and a plurality of preliminary step groups that the preliminary step cluster of second contained are located different levels.

In some embodiments, the performing a plurality of preset etches on the first preliminary step cluster and the second preliminary step cluster includes:

and adopting a plurality of groups of mask plates to carry out a plurality of times of preset etching on the first preliminary step cluster and the second preliminary step cluster, wherein in the random twice preset etching, for the first preliminary step cluster and/or the second preliminary step cluster, the edge of an opening of a mask plate adopted by one-time etching and the edge of an opening of a mask plate adopted by another-time etching are not overlapped in the second direction.

The embodiment of the disclosure provides a semiconductor structure, a manufacturing method thereof, a three-dimensional memory and a storage system, wherein a groove is formed in the upper surface of a wall body, and the groove penetrates through the wall body along a third direction, so that the filling depth of an oxide filling material on a second step cluster is reduced, the filling depth-to-width ratio of the oxide filling material on the second step cluster can be reduced, and the risk of poor filling can be reduced.

Drawings

In order to more clearly illustrate the technical solutions in the present disclosure, the drawings needed to be used in some embodiments of the present disclosure will be briefly described below, and it is apparent that the drawings in the following description are only drawings of some embodiments of the present disclosure, and other drawings can be obtained by those skilled in the art according to the drawings. Furthermore, the drawings in the following description may be regarded as schematic diagrams, and do not limit the actual size of products, the actual flow of methods, the actual timing of signals, and the like, involved in the embodiments of the present disclosure.

FIG. 1A is a schematic perspective view of a semiconductor structure according to some embodiments;

FIG. 1B is a cross-sectional view of a memory cell string along line AA in the semiconductor structure shown in FIG. 1A;

fig. 1C is a perspective view of a wall and a step structure in an array device according to the related art;

fig. 1D is a perspective view of a wall and a step structure in another array device provided in the related art;

FIG. 1E is a block diagram of a contact and gate conductive pattern contact according to some embodiments;

FIG. 2A is a perspective view of a wall and step structure in a semiconductor structure, according to some embodiments;

FIG. 2B is an enlarged view of area Q of FIG. 2A;

FIG. 2C is a block diagram of a step area in a semiconductor structure divided into a first sub-area, a second sub-area, and a third sub-area, in accordance with some embodiments;

fig. 2D is a top view of a gate conductive pattern in one step group G2 and step group G8 connected to a first gate line according to some embodiments;

FIG. 2E is a block diagram of embedding an insulation within a groove according to some embodiments;

FIG. 2F is a block diagram of a semiconductor structure in which a first step group and a fifth step group separate a trench structure into 3 trench structures in accordance with some embodiments;

fig. 2G is a top view of a gate conductive pattern in one step group G17 and step group G8 connected to a second gate line according to some embodiments;

FIG. 3A is a block diagram of a memory system according to some embodiments;

FIG. 3B is a block diagram of a memory system according to further embodiments;

FIG. 4A is a perspective view of a method of forming an initial stacked structure according to some embodiments;

FIG. 4B is a block diagram of a step formation zone according to some embodiments;

FIG. 4C is a block diagram of a method of forming an initial wall and an initial step structure according to some embodiments;

FIG. 4D is a block diagram of a step zone divided into a wall zone and a step zone according to some embodiments;

FIG. 4E is a block diagram of a step partition divided into a fourth sub-area and a fifth sub-area in accordance with some embodiments;

FIG. 4F is a block diagram of a preliminary step structure formed in accordance with some embodiments;

FIG. 4G is a top view of a mask pattern for forming a preliminary step structure according to some embodiments;

FIG. 4H is a flow chart of forming a preliminary step structure according to some embodiments;

fig. 4I is a block diagram of a first preliminary step cluster including a plurality of preliminary step groups at different levels and a second preliminary step cluster including a plurality of preliminary step groups at different levels according to some embodiments;

FIG. 4J is a flow diagram of a first pre-etch of a first preliminary step cluster and a second preliminary step cluster, in accordance with certain embodiments;

FIG. 4K is a flow diagram of a second pre-etch of a first preliminary step cluster and a second preliminary step cluster, in accordance with some embodiments;

FIG. 4L is a flow chart of a third pre-etch of the first preliminary step cluster and the second preliminary step cluster, in accordance with some embodiments;

fig. 4M is a flow chart of performing a fourth pre-etch on the first preliminary step cluster and the second preliminary step cluster, in accordance with some embodiments.

Detailed Description

Technical solutions in some embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings, and it is obvious that the described embodiments are only a part of the embodiments of the present disclosure, and not all of the embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments provided by the present disclosure belong to the protection scope of the present disclosure.

In the description of the present disclosure, it is to be understood that the terms "center", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like indicate orientations or positional relationships based on those shown in the drawings, and are only for convenience in describing and simplifying the disclosure, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed in a specific orientation, and be operated, and thus, should not be construed as limiting the disclosure.

Throughout the specification and claims, the term "comprising" is to be interpreted in an open, inclusive sense, i.e., as "including, but not limited to," unless the context requires otherwise. In the description herein, the terms "one embodiment," "some embodiments," "an example embodiment," "exemplary" or "some examples" or the like are intended to mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the disclosure. The schematic representations of the above terms are not necessarily referring to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be included in any suitable manner in any one or more embodiments or examples.

In the following, the terms "first", "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the embodiments of the present disclosure, "a plurality" means two or more unless otherwise specified.

In describing some embodiments, expressions of "coupled" and "connected," along with their derivatives, may be used. For example, the term "connected" may be used in describing some embodiments to indicate that two or more elements are in direct physical or electrical contact with each other. As another example, some embodiments may be described using the term "coupled" to indicate that two or more elements are in direct physical or electrical contact. The term "coupled," however, may also mean that two or more elements are not in direct contact with each other, but yet still co-operate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents herein.

"at least one of A, B and C" has the same meaning as "A, B or at least one of C," each including the following combination of A, B and C: a alone, B alone, C alone, a and B in combination, a and C in combination, B and C in combination, and A, B and C in combination.

"A and/or B" includes the following three combinations: a alone, B alone, and a combination of A and B.

The use of "adapted to" or "configured to" herein is meant to be an open and inclusive language that does not exclude devices adapted to or configured to perform additional tasks or steps.

Additionally, the use of "based on" means open and inclusive, as a process, step, calculation, or other action that is "based on" one or more stated conditions or values may in practice be based on additional conditions or values beyond those stated.

As used herein, "about," "approximately," or "approximately" includes the stated values as well as average values that are within an acceptable range of deviation for the particular value, as determined by one of ordinary skill in the art in view of the measurement in question and the error associated with measurement of the particular quantity (i.e., the limitations of the measurement system).

In the context of this disclosure, the meaning of "on … …," above, "and" over "should be interpreted in the broadest manner such that" on.

Example embodiments are described herein with reference to cross-sectional and/or plan views as idealized example figures. In the drawings, the thickness of layers and regions are exaggerated for clarity. Variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, the exemplary embodiments should not be construed as limited to the shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the exemplary embodiments.

As used herein, the term "substrate" refers to a material onto which subsequent layers of material may be added. The substrate itself may be patterned. The material added on the substrate may be patterned or may remain unpatterned. In addition, the substrate may include a variety of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, and the like. Alternatively, the substrate may be made of a non-conductive material such as glass, plastic, or sapphire wafer.

The term "three-dimensional memory" refers to a semiconductor device formed of memory cell transistor strings (referred to herein as "memory cell strings", e.g., NAND memory cell strings) arranged in an array on a major surface of a substrate and extending in a direction perpendicular to the substrate. As used herein, the term "perpendicular" means nominally perpendicular to a major surface (i.e., a lateral surface) of a substrate.

Some embodiments of the present disclosure provide a three-dimensional memory, comprising: a semiconductor structure and peripheral devices. The semiconductor structure may also be referred to as an array device.

The peripheral device is configured to control and sense the array device. The peripheral devices may be any suitable digital, analog, and/or mixed signal control and sensing for facilitating operation of the array device, including but not limited to page buffers, decoders (e.g., row and column decoders), sense amplifiers, drivers (e.g., word line drivers), charge pumps, current or voltage references, or any active or passive component of a circuit (e.g., a transistor, diode, resistor, or capacitor).

The peripheral devices may include transistors formed on a substrate in which all or a portion of the transistors are formed in the substrate (e.g., below a top surface of the substrate) and/or directly on the substrate. The substrate may be made of a semiconductor material, including, for example, but not limited to, silicon, germanium, silicon-on-insulator (SOI), and the like.

In some embodiments, the array device may be disposed on the peripheral device, or the peripheral device may be disposed on the array device, which may implement simultaneous fabrication of the array device and the peripheral device, and avoid the problem that the peripheral device and the array device are affected during fabrication, which is not beneficial to temperature selection of subsequent layers during fabrication.

In some embodiments, the three-dimensional memory may further include an array interconnect layer, which may be disposed between the array device and the peripheral device, on a side of the array device remote from the peripheral device, or on a side of the peripheral device remote from the array device. The peripheral device and the array device are electrically connected through the array interconnection layer and used for transmitting electric signals between different areas of the array device or transmitting electric signals between the peripheral device and the array device.

In some embodiments, the array interconnect includes a plurality of interconnect layers and contact layers. In some embodiments, the interconnect layer comprises a plurality of metal layers. The metal layer may be made of tungsten, copper, aluminum, or other suitable material. In some embodiments, the contact layer may be made of tungsten, copper, aluminum, or other suitable materials.

Some embodiments of the present disclosure provide a semiconductor structure 100, as shown in fig. 1A-1E, comprising: a substrate 104, a stacked structure 101 disposed on the substrate 104, the stacked structure 101 may include a plurality of insulating layers (as shown by 101a in fig. 1E) and a plurality of gate conductive layers 101b alternately stacked along a first direction Z. In some embodiments, the substrate 104 may be made of a semiconductor material, including, for example, but not limited to, silicon, germanium, silicon-on-insulator thin film (SOI), and the like. In some embodiments, the gate conductive layer 101b is made of a conductive material including, but not limited to, tungsten, cobalt, copper, aluminum, doped silicon, and/or silicide. The insulating layer 101a is made of an insulating material including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof.

In some embodiments, as shown in fig. 1A and 1B, the array device 100 further includes a plurality of memory cell strings 103, the plurality of memory cell strings 103 extending along the first direction Z and penetrating the stacked structure 101. One memory cell string 103 comprises a channel structure 102, the channel structure 102 comprising a semiconductor channel layer and a dielectric layer, the dielectric layer comprising a tunnel layer, a memory cell layer and a barrier layer. Electrons or holes in the semiconductor channel layer may tunnel through the tunnel layer into the memory cell layer, which is used to store charge, the storage or removal of which determines the switching state of the semiconductor channel layer. In some embodiments, the material of the semiconductor channel layer comprises amorphous silicon, polycrystalline silicon, or monocrystalline silicon. The tunnel layer is made of silicon oxide, silicon nitride, or a combination thereof. The material of the barrier layer includes silicon oxide, silicon nitride, a high dielectric constant insulating material, or a combination thereof. The material of the memory cell layer includes silicon nitride, silicon oxynitride, silicon or a combination thereof.

In some embodiments, as shown in fig. 1A and 1B, the gate conductive layer 101B in the stacked structure 101 is used as a select gate or a word line of the plurality of memory cell strings 103, for example, along the first direction Z, the gate conductive layer 101B positioned lowermost in the multi-layered gate conductive layer 101B is configured as a source side select gate SGS, the gate conductive layer 101B positioned uppermost in the multi-layered gate conductive layer 101B is configured as a drain side select gate SGD (which may also be referred to as a top select gate), and the gate conductive layer 101B positioned in the middle layer in the multi-layered gate conductive layer 101B is configured as a plurality of word lines WL (see WL0 to WL4 in fig. 1B). Here, the select gate and the word line are collectively referred to as a gate line WL _ 0. In some embodiments, the select gates and word lines WL are made of a conductive material, including but not limited to tungsten, cobalt, copper, aluminum, doped silicon, and/or silicides.

As shown in fig. 1B, one memory cell string 103 corresponds to the storage capacity of a plurality of planar memory cells. Therefore, the three-dimensional memory can provide a large storage capacity.

In order to transmit a select terminal signal or a word line signal to each gate line, in some embodiments, as shown in fig. 1A, 1C, 1D, and 2A, the stacked structure 101 includes a first core region a1 and a step region B sequentially arranged along the second direction X. The plurality of memory cell strings 103 are disposed in the first core region a1, and at this time, as shown in fig. 2C, the plurality of gate lines WL _0 includes a plurality of first gate lines WL _01 located in the first core region a 1. As shown in fig. 1C, 1D and 2A, in the stepped region B, the laminated structure 101 is divided into a wall body 11 and a stepped structure 21 which are sequentially arranged in the third direction Y. The first direction Z, the second direction X and the third direction Y are mutually vertical. As shown in fig. 1A, the semiconductor structure 100 further includes a plurality of contacts K (a plurality of contacts K may include, for example, a drain side select gate contact SGD CNT, a source side select gate contact SGS CNT, a source side contact SL CNT, and a word line contact WL CNT). As shown in fig. 2A, the stepped structure 21 comprises a first step cluster 211 and a second step cluster 212 arranged along the second direction X, the second step cluster 212 being distant from the first core area a1 compared to the first step cluster 211. First step cluster 211 and second step cluster 212 are both in contact with the sidewall of wall 11. The first step cluster 211 and the second step cluster 212 respectively include a plurality of step groups G, for example, the plurality of step groups G included in the first step cluster 211 are sequentially G1 to G7 along the second direction X, and the plurality of step groups G included in the second step cluster 212 are sequentially G8 to G11 along the second direction X. Referring to fig. 2A and 2C, each step group G includes a plurality of gate conductive patterns GM arranged in a staircase, each gate conductive pattern GM being located at one gate conductive layer 101b of the plurality of gate conductive layers 101 b.

In some embodiments, the semiconductor structure 100 further includes a source terminal SL located below the source select gate SGS. In some examples, multiple strings of memory cells 103 share a source SL.

In some embodiments, semiconductor structure 100 further includes a bitline BL electrically connected to memory cell string 103 through bitline contact BL CNT.

The plurality of memory cell strings 103 form a memory cell array in an X-Y plane, and the second direction X and the third direction Y are, for example, two orthogonal directions in the memory cell array: the second direction X is, for example, an extending direction of the word line WL, and the third direction Y is, for example, an extending direction of the bit line BL. The first direction Z is perpendicular to the X-Y plane.

In order to realize the block storage of the storage region, as shown in fig. 1C, 1D, and 2A, the semiconductor structure 100 further includes an isolation trench St for dividing the stacked structure 101 into a plurality of memory blocks R. The plurality of memory blocks R are arranged in the third direction Y, and adjacent memory blocks R are spaced apart by an isolation trench st. In some examples, the isolation trenches St extend through the stacked structure 101 in the first direction Z and at least in the second direction X.

Here, for example, two adjacent memory blocks R form one memory block group, two memory blocks R in one memory block group may share a separate partition step structure (separated by the isolation trench St), and the two memory blocks R are mirror symmetric. Each of the partitioned step structures may include M steps, each step includes a plurality of sub-partitions in the third direction, a height difference between adjacent steps is a height of N steps, a height difference between adjacent sub-partitions is a height of 1 step, where M is a natural number greater than or equal to 1, thereby forming a two-dimensional composite three-dimensional step structure.

In this case, the height of one step S may be the height of the step of the divisional number, that is, the height difference between adjacent steps is the height of the step of the divisional number, that is, N is equal to the divisional number.

For example, in the case where each rung includes 2 sub-sections, the height of one rung is the height of 2 steps, in the case where each rung includes 3 sub-sections, the height of one rung is the height of 3 steps, and so on, and in the case where each rung includes N sub-sections, the height of one rung is the height of N steps.

As shown in fig. 2B, each step includes two sub-partitioned structures in the third direction Y, and each partitioned step structure may form 2 steps S in the third direction Y. At this time, as shown in fig. 2A, each of the divisional step structures may include two step structures 21 in mirror symmetry, the two step structures 21 being spaced apart by an isolation trench St, each of the step structures 21 being in contact with a sidewall of one of the walls 11.

Here, taking each step group G of each step structure 21 as an example including 30 steps S, the step S close to the wall 11 may be sequentially the 1 st, 3 rd, 5 th, 7 th, 9 th, 11 th, … th, and 29 th layers from bottom to top, and the step structure 21 far from the wall 11 may be the 2 nd, 4 th, 6 th, 8 th, 10 th, 12 th, 14 th, 16 th, …, and 30 th layers from bottom to top. As shown in fig. 2A and 2C, the gate conductive patterns GM of each step S are respectively located at the same layer as one gate line (e.g., the first gate line WL _ 01).

For clearly explaining the step S, the following explanation is made: each step S extends further laterally (e.g., in the Y-axis direction) than any of the respective steps S located at a higher level thereof, and it can be said that each step S is projected laterally than any of the steps S located at a higher level thereof, so that the shape of a horizontal cross section (e.g., a cross section in the XY plane) of the step group changes in the step group according to the vertical distance from the top surface of the substrate or the source layer (i.e., the side surface located at a higher level among the two side surfaces opposite in the Z-axis direction).

The basic structure of the three-dimensional memory is described above, and as the requirement of the three-dimensional memory on the storage capacity is higher, the number of layers of the stacked structure 101 is higher, for example, the number of layers of the stacked structure 101 can reach 96 layers, even 144 layers. However, as the number of layers of the stacked structure 101 is higher and higher, as shown in fig. 1C and 1D, when the oxide filling material is filled subsequently, the filling depth of the oxide filling material on the step structure 21 is larger and larger, and according to the material characteristics of the oxide filling material, the aspect ratio (the ratio of the filling depth to the filling width, which is the dimension of the structure to be filled along the third direction Y, which may refer to the dimension of the above-mentioned partitioned step structure along the third direction Y, i.e. the dimension between the two walls 11) of the oxide filling material during filling has a certain limitation, which causes poor filling when the aspect ratio exceeds the limitation, and if some oxide filling materials are filled relatively deeply, the phenomenon of sealing occurs in advance, which causes filling voids, and the stress is concentrated at the sealing position, and cracks may occur during external force or subsequent annealing, thereby causing the problems of the deterioration and even the failure of the device structure.

Based on this, in some embodiments, as shown in fig. 2A and 2C, the upper surface of the wall 11 is provided with a groove 111 penetrating at least two adjacent walls along the third direction Y, and the second step cluster 212 is located below the groove 111.

The upper surface of the wall 11 is a surface through which a contact passes, that is, the direction of the step S in the step structure 12 is upward, whereas the direction of the step S is downward, and the second step cluster 212 is located below the groove 111, which means that the gate conductive pattern GM of the uppermost layer of the second step cluster 212 is flush with the bottom of the groove 111, or the gate conductive pattern GM of the uppermost layer of the second step cluster 212 is lower than the bottom of the groove 111.

In these embodiments, by providing the groove 111 on the upper surface of the wall 11, since the groove 111 penetrates through the wall 11 along the third direction, compared with fig. 1C and 1D, the filling depth of the oxide filling material on the second step clusters 212 is reduced, the filling aspect ratio of the oxide filling material on the second step clusters 212 can be reduced, and thus the risk of poor filling can be reduced.

In some embodiments, with reference to fig. 2A, 2C and 2D, the step region B includes a first sub-region B1 and a second sub-region B2 sequentially arranged along the second direction, the first sub-region B1 is located at a side of the groove 111 close to the first core region a1, the groove 111 is located at the second sub-region B2, the wall 11 includes a plurality of conductive lines, the first step cluster 211 is located at the first sub-region B1, and one gate conductive pattern GM included in the first step cluster 211 is in contact with one first conductive line DL1, and the first conductive line DL1 is in contact with one first gate line WL _ 01. The second step cluster 212 is located in the second sub-region B2, and one gate conductive pattern GM included in the second step cluster 212 is in contact with one second conductive line DL2, and the second conductive line DL2 is in contact with one first gate line WL _ 01. Wherein the first conductive line WL _01 is the portion of the wall 11 containing one conductive line located in the first sub-region B1, and the second conductive line DL2 is the portion of the wall 11 containing one conductive line located in the first sub-region B1 and the second sub-region B2.

That is, in the embodiments, for the first step cluster 211, one gate conductive pattern GM included therein may be electrically connected to one first gate line WL _01 of the first core region a1 through one first conductive line DL 1. That is, the gate conductive pattern GM, the first conductive line DL1, and the first gate line WL _01 connected to the gate conductive pattern GM included in the first step cluster 211 belong to the same gate conductive layer 101 b. For the second step cluster 212, one gate conductive pattern GM included therein may be electrically connected to one first gate line WL _01 of the first core area a1 through one second conductive line 204. That is, the gate conductive pattern GM, the second conductive line 204, and the first gate line WL _01 connected to the gate conductive pattern GM included in the second step cluster 212 belong to the same gate conductive layer 101 b. By connecting contacts on the gate conductive patterns GM included in each of the first and second step clusters 21 and 22, signals can be transmitted to the first gate lines WL _01 connected to each other.

Taking the example that the gate conductive pattern GM included in the first step cluster 211 belongs to the step group G2, the gate conductive pattern GM included in the second step cluster 212 belongs to the step group G8, the gate conductive pattern GM included in the step group G2 is electrically connected to one first gate line WL _01 of the first core region through one first conductive line DL1 as shown in fig. 2D, and the gate conductive pattern GM included in the step group G2 is electrically connected to one first gate line WL _01 of the first core region a1 through one second conductive line DL2 as shown in fig. 2D.

It should be noted that, while the above description shows the case where the gate conductive patterns GM included in the step group G2 and the step group G8 are located in different gate conductive layers, it can be understood by those skilled in the art that, when the gate conductive patterns GM included in the step group G2 and the step group G8 are located in the same gate conductive layer, the gate conductive pattern GM included in the step group G2 is electrically connected to one first gate line WL _01 of the first core area a1 through the first conductive line DL1, the second conductive line DL2 includes the first conductive line DL1, and the gate conductive patterns GM included in the step group G2 and the step group G8 are both connected to the same first gate line WL _ 01.

In some embodiments, the contact K is made of a conductive material including, but not limited to, tungsten, cobalt, copper, aluminum, and/or silicide.

In some embodiments, as shown in conjunction with fig. 2C and 2E, the semiconductor structure further includes an insulating portion 112, the insulating portion 112 being embedded in the groove 111 and contacting the sidewall of the groove 11.

In these embodiments, the material of the insulating portion 112 may be an oxide material, that is, as shown in fig. 2E, the structure after the groove 111 is filled with an oxide.

Of course, in other embodiments, the insulating portion 112 may also be disposed on the first step cluster 211 and the second step cluster 212, that is, the region where the step group included in the first step cluster 211 and the second step cluster 212 is located is filled, and the final product may be a structure in which the first step cluster 211, the second step cluster 212, and the groove 111 are all filled with an oxide material, and the contact K passes through the oxide material and is electrically connected to the first step cluster 211 and the second step cluster 212.

In some embodiments, as shown in fig. 2A, the first step group 211 includes a plurality of step groups G, and the step group closest to the groove 111 is a first step group, as G7 in fig. 2A, in which at least a portion of the gate conductive pattern GM is higher than the bottom 111a of the groove 111.

The fact that at least a portion of the gate conductive patterns GM in the first step group is higher than the bottom 111a of the groove 111 means that the portion of the gate conductive patterns GM in the first step group is higher than the bottom 111a of the groove 111, or all the gate conductive patterns GM in the first step group are higher than the bottom 111a of the groove 111, where in the case that the portion of the gate conductive patterns GM in the first step group is higher than the bottom 111a of the groove 111, the gate conductive pattern GM of the lowermost layer in the first step group is flush with the bottom 111a of the groove 111, or at least the gate conductive pattern GM of the lowermost layer in the first step group is lower than the bottom 111a of the groove 111. In the case where all the gate conductive patterns GM in the first step group are higher than the bottom 111a of the groove 111, the gate conductive pattern GM of the lowermost layer in the first step group is higher than the bottom 111a of the groove 111.

In these embodiments, by making at least a portion of the gate conductive pattern GM in the first step group higher than the bottom 111a of the groove 111, the first step group may further separate the remaining step groups in the first step clusters 211 from the second step clusters 212, as shown in fig. 2F, the first step group divides the remaining step groups in the first step cluster 211 and the second step cluster 212 into two groove structures W2, as compared to fig. 1D, forming one large groove structure W1 from the first step clusters 211 and the second step clusters 212, when the oxide filling material is filled on the first and

second step clusters

211 and 212, the oxide filling material is respectively filled in the two groove structures W2, therefore, the stress generated by the oxide filling material can be decomposed from one groove structure W1 to two groove structures W2, and the defects caused by stress and expansion can be reduced.

In addition, the first step group can also serve as a support, compared to the case where the first step cluster 211 and the second step cluster 212 form one large groove structure W1.

In some embodiments, the gate conductive pattern GM of the uppermost layer DL in the first step group is positioned at the uppermost gate conductive layer 101b among the plurality of gate conductive layers 101 b.

In these embodiments, the uppermost gate conductive pattern GM in the first step group may be flush with the upper surface of the wall body 11, that is, the first step group may be at a higher level position, and may play a similar role as the support of the wall body 11.

In some embodiments, the first step cluster 211 includes a plurality of step groups, and the step group farthest from the groove 111 is a second step group, such as G1 in fig. 2A, in which at least a portion of the gate conductive pattern GM is higher than the uppermost gate conductive pattern GM included in the step group adjacent to the second step group in the first step cluster 211.

At least a portion of the gate conductive pattern GM in the second step group is higher than the uppermost gate conductive pattern GM included in the step group adjacent to the second step group in the first step cluster 211, meaning that, in the first step cluster 211, the portion of the gate conductive pattern GM in the second step group is higher than the uppermost gate conductive pattern GM included in the step group adjacent thereto, or, all the gate conductive patterns GM in the second step group are higher than the uppermost gate conductive pattern GM included in the step group adjacent thereto, where, in the case where the gate conductive pattern GM of a portion in the second step group is higher than the gate conductive pattern GM of the uppermost layer included in the step group adjacent thereto, the gate conductive pattern GM of the lowermost layer in the second step group is flush with the gate conductive pattern GM of the uppermost layer included in the step group adjacent thereto, or, at least the lowermost gate conductive pattern GM in the second step group is lower than the uppermost gate conductive pattern GM included in the step group adjacent thereto. In the case where all the gate conductive patterns GM in the second step group are higher than the uppermost gate conductive pattern GM included in the step group adjacent thereto, the lowermost gate conductive pattern GM in the second step group is higher than the uppermost gate conductive pattern GM included in the step group adjacent thereto.

In these embodiments, by making at least a part of the gate conductive patterns GM in the second step group higher than the uppermost gate conductive pattern GM included in the step group adjacent to the second step group in the first step cluster 211, the second step group can be at a higher level, so that when the first step group is at a higher level, as shown in fig. 2F, the plurality of step groups in the first step cluster 211 tend to decrease and then increase along the second direction X, and compared with the tendency that the plurality of step groups in the first step cluster 211 gradually increase or decrease along the second direction X, the stress can be resolved onto the plurality of step groups, thereby avoiding poor filling caused by stress concentration.

In some embodiments, as shown in fig. 2A, in the second step group (e.g., G7 in fig. 2A), each of the gate conductive patterns GM of at least part of the gate conductive patterns GM is located in the same gate conductive layer 101b as at least one of the gate conductive patterns GM in the first step group (e.g., G1 in fig. 2A).

In the second step group, each of the gate conductive patterns GM of at least some of the gate conductive patterns GM and at least one of the gate conductive patterns GM of the first step group are located in the same gate conductive layer 101b, which means that, in the second step group, each of the gate conductive patterns GM of some of the gate conductive patterns GM and one of the gate conductive patterns GM of the first step group are located in the same gate conductive layer 101b, or, in the second step group, each of the gate conductive patterns GM of all of the gate conductive patterns GM and one of the gate conductive patterns GM of the first step group are located in the same gate conductive layer 101 b.

As shown in fig. 2A, a case where each of the gate conductive patterns GM of the entire gate conductive patterns GM is located in the same gate conductive layer 101b as one of the gate conductive patterns GM of the first step group in the second step group is shown. It can be understood by those skilled in the art that only the case where the number of layers of the gate conductive patterns GM in the first step group and the second step group is the same and the uppermost gate conductive pattern GM in the second step group is higher than the uppermost gate conductive pattern GM in the first step group (e.g., the uppermost gate conductive pattern GM in the second step group is flush with the uppermost gate conductive pattern GM in the first step group, or the uppermost gate conductive pattern GM in the second step group has a height higher than the uppermost gate conductive pattern GM in the first step group) is illustrated herein, in some embodiments, the number of layers of the gate conductive patterns GM in the first step group and the number of layers of the gate conductive patterns GM in the second step group may be different, in which case, the uppermost gate conductive pattern GM in the second step group is higher than the uppermost gate conductive pattern GM in the first step group, or the uppermost gate conductive pattern GM in the first step group is higher than the uppermost gate conductive pattern GM in the second step group, and is not particularly limited herein.

In some embodiments, the plurality of contacts K may include a plurality of first contacts coupled with the first step cluster 211. And two gate conductive patterns GM which are located on the same gate conductive layer 101b and belong to different step groups, wherein one gate conductive pattern GM is in contact with at least one of the plurality of first contacts, and the other gate conductive pattern GM is not in contact with the plurality of first contacts.

As shown in fig. 2A, for example, two gate conductive patterns GM located on the same gate conductive layer 101b and belonging to different step groups respectively belong to a first step group and a second step group, all gate conductive patterns GM in the second step group and at least one gate conductive pattern GM in the first step group are located on the same gate conductive layer 101b, and all contacts may contact with the second step group, at this time, the first step group serves as a dummy step group to play a role in supporting, or a part of the contacts the first step group and the rest contacts the second step group, and at this time, the second step group serves as a supporting role and a part of the steps in the second step group also play a role in electrical connection.

In other embodiments, two gate conductive patterns GM in the same gate conductive layer 101b and belonging to different step groups are respectively in contact with different first contacts. That is, the first step group plays a supporting role, and simultaneously, all steps in the first step group play an electric connection role.

In some embodiments, the first step cluster 211 includes a plurality of step groups, one step group at the lowest position is a third step group, such as G4 in fig. 2A, the second step cluster 212 includes a plurality of step groups, one step group at the highest position is a fourth step group, such as G8 in fig. 2A, and the gate conductive pattern GM of the lowest layer in the third step group and the gate conductive pattern GM of the uppermost layer in the fourth step group are located at two adjacent gate conductive layers 101b in the plurality of gate conductive layers 101 b.

In these embodiments, by locating the lowermost gate conductive pattern in the third step group and the uppermost gate conductive pattern in the fourth step group at two adjacent gate conductive layers 101b among the plurality of gate conductive layers 101b, it is possible to achieve effective and sufficient utilization of the step structure 21, and to achieve signal transmission to all gate lines.

As shown in fig. 2A, in the first step cluster 211, the 1 st step group (G1) sequentially arranged in the second direction X is inclined in the negative direction of the second direction X, the 2 nd step group (G2) sequentially arranged in the second direction X is inclined in the positive direction of the second direction X, and the 3 rd step group (G3) sequentially arranged in the second direction X is inclined in the negative direction of the second direction X. In the second step cluster 212, the 1 st step group (G8) arranged in the second direction X is inclined in the negative direction of the second direction X, the 2 nd step group (G9) arranged in sequence in the second direction X is inclined in the positive direction of the second direction X, and the 3 rd step group (G10) arranged in sequence in the second direction X is inclined in the negative direction of the second direction X.

In these embodiments, compared with the case that the two adjacent step groups have the same inclination direction, under the condition that the two adjacent step groups have opposite inclination directions, on one hand, when manufacturing, the two adjacent step groups can be obtained by trimming and etching through the same mask pattern, the usage amount of the mask plate and the number of times of trimming and etching can be reduced, and on the other hand, under such a structure, the step groups in the finally formed step structure 21 can be staggered with each other, so that the step group distribution is more dispersed, the step structure 21 can be broken into whole parts, the stress is decomposed to the step groups, and thus the stress concentration can be avoided, and further, the structural stability of the whole semiconductor structure can be improved.

In some embodiments, the first step set and the second step cluster 212 have the adjacent step sets of the first step set inclined in opposite directions.

The step group adjacent to the first step group in the second step cluster 212 means the 1 st step group in the second step cluster 212 sequentially arranged along the second direction X, that is, G8.

In these embodiments, the inclination directions of the step groups adjacent to the first step group in the first step group and the second step group 212 are opposite, so that the technical effects that the inclination directions of the two adjacent step groups in the same group are opposite are the same, and the details are not repeated herein.

In some embodiments, as shown in fig. 2A, the stacked structure 101 further comprises: second core region a2, second core region a2 is located on the side of step region B remote from first core region a 1. The step structure 21 further includes: and a third step cluster 213, wherein the third step cluster 213 is located on one side of the groove 11 far away from the first step cluster 211, and the third step cluster 213 is in contact with the side wall of the wall 1. The third step cluster 213 includes a plurality of step groups, such as G12-G18, sequentially arranged along the second direction as shown in fig. 2A. Each step group includes a plurality of gate conductive patterns GM arranged in a ladder, each of the gate conductive patterns GM being located at one gate conductive layer 101b among the plurality of gate conductive layers 101 b.

In these embodiments, the first step cluster 211 and the third step cluster 213 are respectively disposed on two opposite sides of the groove 111 along the second direction X, and in this case, as shown in fig. 2C and fig. 2G, the plurality of gate lines may further include a plurality of second gate lines WL _02 located in the second core region a2, the step region B may further include a third sub-region B3, the third sub-region B3 is located on one side of the groove 111 close to the second core region a2, and the third step cluster 213 is located in the third sub-region B3. At this time, as shown in fig. 2G, one gate conductive pattern GM included in the third step cluster 213 may be in contact with one third conductive line DL3, one third conductive line DL3 may be in contact with one second gate line WL _02, one gate conductive pattern GM included in the second step cluster 212 may be in contact with one fourth conductive line DL4, and the fourth conductive line DL4 may be in contact with one second gate line WL _ 02. The third conductive line DL3 is the portion of the wall 11 where one conductive line is located in the third sub-region B3, and the fourth conductive line DL4 is the portion of the wall 11 where one conductive line is located in the second sub-region B2 and the third sub-region B3.

In these embodiments, similarly to the above-described case where one gate conductive pattern GM included in the first step cluster 211 is connected to one first gate line WL _01 through one first conductive line DL1, one gate conductive pattern GM included in the second step cluster 212 is electrically connected to one first gate line WL _01 through one second conductive line DL2, one gate conductive pattern GM included in the third step cluster 213 may be electrically connected to one second gate line WL _02 through one third conductive line DL3, and one gate conductive pattern GM included in the second step cluster 212 is electrically connected to one second gate line WL _02 through one fourth conductive line DL4, so that signal transmission to a plurality of second gate lines WL _02 may be achieved, and thus dual-side driving may be achieved.

As shown in fig. 2F, taking as an example that the gate conductive pattern GM included in the third step cluster 213 belongs to the step group G17, and the gate conductive pattern GM included in the second step cluster 212 belongs to the step group G8, the gate conductive pattern GM included in the step group G17 is electrically connected to one second gate line WL _02 of the second core area a2 through one third conductive line DL3, and the gate conductive pattern GM included in the step group G8 is electrically connected to one second gate line WL _02 of the second core area a2 through one fourth conductive line DL 4.

The gate conductive pattern GM, the third conductive line DL3 and the second gate line WL _02 connected to the gate conductive pattern GM included in the third step cluster 213 belong to the same gate conductive layer, and the gate conductive pattern GM, the fourth conductive line DL4 and the second gate line WL _02 connected to the gate conductive pattern GM included in the second step cluster 212 belong to the same gate conductive layer.

That is, in these embodiments, the dual edge driving may be applied, and on the other hand, in this structure, by using the feature of the arrangement of the step structure 21, the groove 111 is disposed in the middle of the wall 11 corresponding to the step structure 21, on the one hand, the dual edge driving is not affected, that is, the first step cluster 211 located at one side of the groove 111 close to the first core area a1 is used to transmit a signal to the first gate line WL _01 located at the upper layer of the first core area a1, the third step cluster 213 located at one side of the groove 111 close to the second core area a2 is used to transmit a signal to the second gate line WL _02 located at the upper layer of the second core area a2, and the second step cluster 212 located below the groove 111 is used to transmit signals to both the first gate line WL _ core 01 and the second gate line WL _02 located at the lower layers of the first core area a1 and the second core area a 2. On the other hand, the stress of the insulating material can be decomposed, and problems such as poor filling can be reduced.

In some embodiments, as shown in fig. 2A, the third step cluster 213 includes a fifth step group, i.e., G12, of the plurality of step groups that is closest to the groove 111. At least a portion of the gate conductive pattern in the fifth step group is higher than the bottom 111a of the groove 111.

The fact that at least a portion of the gate conductive patterns GM in the fifth step group is higher than the bottom 111a of the groove 11 means that the portion of the gate conductive patterns GM in the fifth step group is higher than the bottom 111a of the groove 111, or all the gate conductive patterns GM in the fifth step group are higher than the bottom 111a of the groove 111, where in the case that the portion of the gate conductive patterns GM in the fifth step group is higher than the bottom 111a of the groove 111, the gate conductive pattern GM of the lowermost layer in the fifth step group is flush with the bottom 111a of the groove 111, or at least the gate conductive pattern GM of the lowermost layer in the fifth step group is lower than the bottom 111a of the groove 111. In the case where all the gate conductive patterns GM in the fifth step group are higher than the bottom 111a of the groove 111, the gate conductive pattern GM of the lowermost layer in the fifth step group is higher than the bottom 111a of the groove 111.

In these embodiments, by making at least a portion of the gate conductive pattern GM in the fifth step group higher than the bottom 111a of the groove 111, the fifth step group may separate the remaining step groups in the third step cluster 213 from the second step cluster 212, as shown in fig. 2F, the fifth step group divides the remaining step groups in the third step cluster 213 and the second step cluster 212 into two groove structures W2, as compared to fig. 1C, forming one large groove structure W1 from the first step cluster 211 and the third step cluster 213, when the oxide filling material is filled on the first and

third step clusters

211 and 213, the oxide filling material is respectively filled in the two groove structures W2, therefore, the stress generated by the oxide filling material can be decomposed from one groove structure W1 to two groove structures W2, and the defects caused by stress and expansion can be reduced.

Meanwhile, in comparison with the case where the first, second, and

third step clusters

211, 212, and 213 form one large groove structure W1 as shown in fig. 3A and 3B, in the case where at least part of the gate conductive patterns GM in the first step group and at least part of the gate conductive patterns GM in the fifth step group are higher than the bottom of the groove 111, the first and fifth step groups may divide one large groove structure W1 into three groove structures W2, so that, when the oxide filling material is filled on the first, second, and

third step clusters

211, 212, and 213, the oxide filling material is respectively filled in the three groove structures W2, so that stress generated from the insulating material may be decomposed from one groove structure W1 into the three groove structures W2, and defects caused by the stress and expansion may be reduced.

In some embodiments, the gate conductive pattern GM of the uppermost layer in the fifth step group is positioned in the gate conductive layer 101b of the uppermost layer among the plurality of gate conductive layers 101 b.

In these embodiments, the uppermost gate conductive pattern GM of the fifth step set may be flush with the upper surface of the wall body 11, that is, the fifth step set is at a higher level position, and may play a similar role as the support of the wall body 11.

In some embodiments, the third step cluster 213 includes a plurality of step groups, and the step group farthest from the recess 111 is a sixth step group, in which at least a portion of the gate conductive pattern GM is higher than the uppermost gate conductive pattern GM included in a step group adjacent to the sixth step group in the third step cluster 213.

At least a portion of the gate conductive pattern GM in the sixth step group is higher than the uppermost gate conductive pattern GM included in the step group adjacent to the sixth step group in the third step cluster 213, meaning that, in the third step cluster 213, the partial gate conductive pattern GM in the sixth step group is higher than the uppermost gate conductive pattern GM included in the step group adjacent thereto, alternatively, all the gate conductive patterns GM in the sixth step group are higher than the uppermost gate conductive pattern GM included in the step group adjacent thereto, where, in the case where the partial gate conductive pattern GM is higher in the sixth step group than the uppermost gate conductive pattern GM included in the step group adjacent thereto, the lowermost gate conductive pattern GM in the sixth step group is flush with the uppermost gate conductive pattern GM included in the step group adjacent thereto, alternatively, at least the lowermost gate conductive pattern GM in the sixth step group is lower than the uppermost gate conductive pattern GM included in the step group adjacent thereto. In the case where all the gate conductive patterns GM in the sixth step group are higher than the uppermost gate conductive pattern GM included in the step group adjacent thereto, the lowermost gate conductive pattern GM in the sixth step group is higher than the uppermost gate conductive pattern GM included in the step group adjacent thereto.

In these embodiments, by making at least a portion of the gate conductive pattern GM in the sixth step group higher than the uppermost gate conductive pattern GM included in the step group adjacent to the sixth step group in the third step cluster 213, the sixth step group can be at a higher level, so that when the fifth step group is at a higher level, as shown in fig. 2F, the plurality of step groups in the third step cluster 213 tend to decrease and then increase along the second direction X, and compared with the tendency that the plurality of step groups in the third step cluster 213 gradually increase or decrease along the second direction X, the stress generated by the filled oxide material can be decomposed on each step group, and thus the poor filling caused by the stress concentration can be avoided.

In some embodiments, in the sixth step group, each of the gate conductive patterns GM of at least a portion of the gate conductive patterns GM is located at the same gate conductive layer 101b as at least one of the gate conductive patterns GM in the fifth step group.

In the sixth step group, each of the gate conductive patterns GM of at least some of the gate conductive patterns GM and at least one of the gate conductive patterns GM of the fifth step group are located in the same gate conductive layer 101b, which means that, in the sixth step group, each of the gate conductive patterns GM of some of the gate conductive patterns GM and one of the gate conductive patterns GM of the fifth step group are located in the same gate conductive layer 101b, or, in the sixth step group, each of the gate conductive patterns GM of all of the gate conductive patterns GM and one of the gate conductive patterns GM of the fifth step group are located in the same gate conductive layer 101 b.

As shown in fig. 2A, a case where each gate conductive pattern GM of all the gate conductive patterns GM is located in the same gate conductive layer 101b as one gate conductive pattern GM of the fifth step group in the sixth step group is shown. It can be understood by those skilled in the art that only the case where the number of layers of the gate conductive patterns GM in the fifth step group and the sixth step group is the same and the uppermost gate conductive pattern GM in the sixth step group is higher than the uppermost gate conductive pattern GM in the fifth step group (e.g., the uppermost gate conductive pattern GM in the sixth step group is flush with the uppermost gate conductive pattern GM in the fifth step group, or the uppermost gate conductive pattern GM in the sixth step group is higher than the uppermost gate conductive pattern GM in the fifth step group) is illustrated herein, in some embodiments, the number of layers of the gate conductive patterns GM in the fifth step group and the number of layers of the gate conductive patterns GM in the second step group may be different, in which case, the uppermost gate conductive pattern GM in the sixth step group is higher than the uppermost gate conductive pattern GM in the first step group, or the uppermost gate conductive pattern GM in the fifth step group is higher than the uppermost gate conductive pattern GM in the sixth step group, and is not particularly limited herein.

In some embodiments, the plurality of contacts further comprises: a plurality of second contacts coupled to the third step cluster 213. And in the two gate conductive patterns which are located in the same gate conductive layer 101b and belong to different step groups, one of the gate conductive patterns GM is in contact with at least one of the second contacts, and the other gate conductive pattern GM is not in contact with the second contacts.

As shown in fig. 2A, taking as an example that two gate conductive patterns GM located on the same gate conductive layer 101b and belonging to different step groups respectively belong to a fifth step group and a sixth step group, all gate conductive patterns GM in the sixth step group and at least one gate conductive pattern GM in the fifth step group are located on the same gate conductive layer 101b, and all contacts may contact with the sixth step group, at this time, the fifth step group serves as a dummy step group and plays a role of supporting, or a part of the contacts the fifth step group and the rest contacts the sixth step group, at this time, the sixth step group plays a role of supporting, and at the same time, a part of steps in the sixth step group also play a role of electrically connecting.

In other embodiments, two gate conductive patterns GM in the same gate conductive layer 101b and belonging to different step groups are respectively in contact with different second contacts. That is, the fifth step group plays a supporting role, and simultaneously, all the steps in the fifth step group play an electric connection role.

In some embodiments, as shown in fig. 2A, each of the plurality of gate conductive patterns GM in the first step cluster 211 and at least one gate conductive pattern GM corresponding to the third step cluster 213 are included in the same gate conductive layer 101 b.

That is, each of the gate conductive patterns in the first step cluster 211 can find a gate conductive pattern of a corresponding height in the third step cluster 213. Thereby, the electrical lead-out of the first gate line WL _01 and the second gate line WL _02 at the same level of the first core region a1 and the second core region a2 may be realized.

In some embodiments, in the third step cluster 213, the inclination directions of the adjacent two step groups are opposite.

As shown in fig. 2A, in the third step cluster 213, the 1 st step group (G12) sequentially arranged in the second direction X is inclined in the positive direction of the second direction X, the 2 nd step group (G13) sequentially arranged in the second direction X is inclined in the negative direction of the second direction X, and the 3 rd step group (G14) sequentially arranged in the second direction X is inclined in the positive direction of the second direction X.

In these embodiments, compared with the case that the two adjacent step groups have the same inclination direction, under the condition that the two adjacent step groups have opposite inclination directions, on one hand, during manufacturing, the two adjacent step groups can be obtained by trimming and etching through the same mask pattern, so that the usage amount of the mask pattern and the number of times of trimming and etching can be reduced, and on the other hand, under such a structure, the step groups in the finally formed step structure 21 can be staggered from each other, so that the step group distribution is more dispersed, the step structure 21 can be broken into whole parts, and the stress is decomposed to the step groups, so that stress concentration can be avoided, and the structural stability of the whole semiconductor structure can be improved.

In some embodiments, the fifth step set and the step set adjacent to the fifth step set in second step cluster 212 are inclined in opposite directions.

The step group adjacent to the fifth step group in the second step cluster 212 means the last 1 step groups in the second step cluster 212 arranged in sequence along the second direction X, that is, G11.

In these embodiments, the inclination directions of the step groups adjacent to the fifth step group in the fifth step group and the second step group 212 are opposite, so that the technical effects that the inclination directions of the two adjacent step groups in the same group are opposite are the same, and the details are not repeated herein.

The first step cluster 211 and the third step cluster 213 may be symmetrical or asymmetrical in the second direction X, which is not limited herein. In the embodiments of the present disclosure, only the case where the first step cluster 211 and the third step cluster 213 are asymmetric in the second direction X is illustrated.

Some embodiments of the present disclosure also provide a storage system. FIG. 3A is a block diagram of a memory system according to some embodiments. FIG. 3B is a block diagram of memory systems according to further embodiments. Referring to fig. 3A and 3B, the storage system 1 includes a three-dimensional memory 10 and a controller 20. The three-dimensional memory 10 may be the three-dimensional memory provided in any of the above embodiments. The controller 20 is coupled to the three-dimensional memory 10 to control the three-dimensional memory 10 to store data.

Among them, the Storage system 1 may be integrated into various types of Storage devices, for example, included in the same package (e.g., Universal Flash Storage (UFS) or Embedded multimedia Card (eMMC) package). That is, the storage system 1 may be applied to and packaged into different types of electronic products, such as mobile phones, desktop computers, laptop computers, tablet computers, vehicle computers, game consoles, printers, positioning devices, wearable electronic devices, smart sensors, Virtual Reality (VR) devices, Augmented Reality (AR) devices, or any other suitable electronic device having storage therein.

In some embodiments, referring to fig. 3A, the memory system 1 includes a controller 20 and a three-dimensional memory 10, and the memory system 1 may be integrated into a memory card.

The Memory Card includes any one of a PC Card (PCMCIA), a Compact Flash (CF) Card, a Smart Media (SM) Card, a Memory stick, a Multimedia Card (MMC), a Secure Digital Memory Card (SD), and a UFS.

In other embodiments, referring to fig. 3B, the storage system 1 includes a controller 20 and a plurality of three-dimensional memories 10, and the storage system 1 is integrated into a Solid State Drive (SSD).

In storage system 1, in some embodiments, controller 20 is configured for operation in a low duty cycle environment, such as an SD card, CF card, Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, mobile phones, and the like.

In other embodiments, the controller 20 is configured for operation in a high duty cycle environment SSD or eMMC for data storage and enterprise storage arrays of mobile devices such as smart phones, tablets, laptops, and the like.

In some embodiments, the controller 20 may be configured to manage data stored in the three-dimensional memory 10 and communicate with an external device (e.g., a host). In some embodiments, the controller 20 may also be configured to control operations of the three-dimensional memory 10, such as read, erase, and program operations. In some embodiments, the controller 20 may also be configured to manage various functions with respect to data stored or to be stored in the three-dimensional memory 10, including at least one of bad block management, garbage collection, logical to physical address translation, wear leveling. In some embodiments, the controller 20 is further configured to process error correction codes with respect to data read from the three-dimensional memory 10 or written to the three-dimensional memory 10.

Of course, the controller 20 may also perform any other suitable function, such as formatting the three-dimensional memory 10. For example, the controller 20 may communicate with an external device (e.g., a host) through at least one of various interface protocols.

It should be noted that the interface protocol includes at least one of a USB protocol, an MMC protocol, a Peripheral Component Interconnect (PCI) protocol, a PCI express (PCI-E) protocol, an Advanced Technology Attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a Small Computer System Interface (SCSI) protocol, an Enhanced Small Disk Interface (ESDI) protocol, an Integrated Drive Electronics (IDE) protocol, and a Firewire protocol.

Some embodiments of the present disclosure also provide a method of fabricating a semiconductor structure. The method can be used for manufacturing the semiconductor structure provided by any one of the above embodiments. Based on the above, the semiconductor structure manufactured by the manufacturing method of the semiconductor structure may have the first core region, the step region, and the second core region sequentially arranged. For the description of the first core region, the step region and the second core region of the semiconductor structure, reference may be made to the above description of the semiconductor structure, and details are not repeated here.

The preparation method of the semiconductor structure comprises the following steps:

s1) as shown in fig. 4A, an initial stacked structure 101_1 is formed, the initial stacked structure 101_1 including a plurality of insulating layers and a plurality of sacrificial layers alternately stacked in a first direction.

For example, chemical vapor deposition, physical vapor deposition, atomic layer deposition, etc. may be used to alternately deposit insulating layers and sacrificial layers on the substrate, wherein one insulating layer and one sacrificial layer form one level, and the initial stacked structure 101_1 may be exemplified by 8 levels, 16 levels, 32 levels, 64 levels, 96 levels, 128 levels, 136 levels, 144 levels, even 300 levels, etc.

Wherein, the material of the insulating layer can be silicon oxide, and the material of the sacrificial layer can be silicon nitride.

The position, material, and function of the initial stacked structure 101_1 are the same as those of the corresponding structure in the stacked structure, except that the sacrificial layer is made of a different material from the gate conductive layer described above. Therefore, as for the remaining structures in the initial stacked structure 101_1, reference may be made to the above description of the corresponding structures in the stacked structure 101, and further description will not be repeated. Specifically, unless otherwise specified, each structure named with "original" in the original stacked structure may be referred to the above description of the corresponding structure in the stacked structure, hereinafter.

Since the semiconductor structure to be formed has the first core region a1, the stepped region B, and the second core region a2, accordingly, the initial stacked structure 101_1 also has the first core region a1, the stepped region B, and the second core region a 2.

S2) as shown in fig. 4B, the initial stacked structure 101_1 is divided into a first core region a1 and a step region B arranged in the second direction.

Specifically, a partition step 201 may be formed on the initial stacked structure 101_1, and the partition step 201 may divide the initial stacked structure 101_1 into a first core region a1, a second core region a2, and a step region B. Here, the description is given only by taking the example of the bilateral driving, and the partition step 201 may be used as a connection step of the top selection gate of the memory cell string 102.

The forming of the partition step 201 on the initial stacked structure 101_1 specifically includes: the uppermost several composite layers of the initial stacked structure 101_1 are trimmed and etched along the second direction X to form two partition steps 201a and 201B that are symmetrical to each other, and the initial stacked structure 101_1 is divided into a first core region a1, a step region B, and a second core region a2, which are sequentially arranged, by the two partition steps 201a and 201B.

The number of the corresponding trimming and etching layers can be 2-3, and the formed step area B is located between the first core area A1 and the second core area A2.

S3) as shown in fig. 4C, an initial wall 11_1 and an initial step structure 21_1 are formed on the initial stacked structure 101_1 and at the step area B, which are arranged in sequence along the third direction Y. The upper surface of the initial wall 11_1 is provided with a groove 111 penetrating through at least two adjacent initial walls 11_1 along the third direction Y, the initial step structure 21_1 includes a first initial step cluster 211_1 and a second initial step cluster 212_1 arranged along the second direction X, both the first initial step cluster 211_1 and the second initial step cluster 212_1 are in contact with the side wall of the wall 1, and the second initial step cluster 212 is located below the groove 111. The first direction Z, the second direction X and the third direction Y are mutually vertical. The first and second initial step clusters 211_1 and 212_1 each include a plurality of initial step groups, each of which includes a plurality of sacrificial patterns arranged in a staircase, each of which is located at one of the plurality of sacrificial layers.

As shown in FIG. 4C, the first initial step cluster 211_1 may include 7 step groups, such as G1 'through G7', and the second initial step cluster 212_1 may include 4 step groups, such as G8 'through G11'.

Here, taking one storage block R as an example, the first step cluster 211 and the second step cluster 212 may belong to one step structure 21 included in the partitioned step structure. A step partition Bi is formed between the two walls 1. The partitioned step structure may include M steps, each step includes a plurality of sub-partitions in the third direction, a height difference between adjacent steps is a height of N steps, a height difference between adjacent sub-partitions is a height of 1 step, where M is a natural number greater than or equal to 1, thereby forming a two-dimensional composite three-dimensional step structure.

On the initial stacked structure 101_1 and located in the step area B, an initial wall 11_1 and an initial step structure 21_1 are formed, which are sequentially arranged along the third direction Y, as shown in fig. 4D to 4G, and include:

s31, as shown in fig. 4D, the portion of the initial stacked structure 101_1 located in the step region B is divided into a wall body region Bj and a step partition Bi along the third direction Y, wherein, as shown in fig. 4D, the region indicated by the dashed box is the step partition Bi, and the region between two step partitions Bi is Bj.

S32, protecting the part of the initial laminated structure 101_1, which is located in the wall body area Bj, and etching the part of the initial laminated structure 101_1, which is located in the step partition Bi, to obtain an initial wall body 11_1 located in the wall body area Bj and an initial step structure 21_1 located in the step partition Bi.

In some embodiments, as shown in fig. 4E, the step partition Bi may include a plurality of fourth sub-partitions B4 and a plurality of fifth sub-partitions B5 that are sequentially distributed along the second direction, and each fourth sub-partition B4 includes: a first protective region B4i1 and a first etching region B4i2 located at a side of the first protective region B4i1 remote from the first core region a1, each fifth sub-region B5 comprising: a second guard region B5i1 and a second etch region B5i2 located on a side of the second guard region B5i1 adjacent to the first core region a 1.

Etching the part of the initial laminated structure 101_1 located in the step partition Bi, including:

as shown in fig. 4E and 4F, portions of the initial stacked structure 101_1 located in the first protection region B4i1 and the second protection region B5i1 are protected, and portions of the initial stacked structure 101_1 located in the first etching region B4i2 and the second etching region B5i2 are trim-etched to obtain a preliminary step structure 21_2, where the preliminary step structure 21_2 includes a first preliminary step cluster 211_2 and a second preliminary step cluster 212_2 arranged in sequence along the second direction, and each of the first preliminary step cluster 211_2 and the second preliminary step cluster 212_2 includes a plurality of preliminary step groups, and the plurality of preliminary step groups are located at the same level. And for a plurality of preliminary step groups, the inclination directions of two adjacent preliminary step groups are opposite along the second direction.

It should be noted that, in this document, a and B being located at the same level may mean that a point in the semiconductor structure (e.g., the center of the semiconductor structure) is taken as an origin, a direction in which the substrate points toward the semiconductor structure or the source layer points toward the semiconductor structure is taken as a positive Z-axis direction, and coordinates of the center of a and the center of B in the Z-axis direction are equal to each other with respect to the origin. Similarly, a being at a higher level than B may mean that a point in the semiconductor structure (e.g., the center of the semiconductor structure) is taken as an origin, and a direction in which the substrate points toward the semiconductor structure or the source layer points toward the semiconductor structure is taken as a positive Z-axis direction, relative to which origin the center of a has a greater coordinate in the Z-axis direction than the center of B. A being at a lower level than B may mean that a point in the semiconductor structure (e.g., the center of the semiconductor structure) is taken as an origin, and a direction in which the substrate points toward the semiconductor structure or the source layer points toward the semiconductor structure is taken as a positive Z-axis direction, relative to which origin a has a smaller coordinate of the center of a in the Z-axis direction than a coordinate of the center of B in the Z-axis direction.

For the plurality of preliminary step groups, the two adjacent preliminary step groups are inclined in opposite directions along the second direction, which means that, in any two adjacent preliminary step groups, if the 1 st step group (e.g., G1 ") sequentially arranged along the second direction is inclined in the negative direction of the second direction X, the 2 nd step group (e.g., G2") sequentially arranged along the second direction is inclined in the positive direction of the second direction X, and if the first step group (e.g., G2 ") sequentially arranged along the second direction is inclined in the positive direction of the second direction X, the second step group (e.g., G3") sequentially arranged along the second direction is inclined in the negative direction of the second direction X.

In these embodiments, since the plurality of preliminary step groups are at the same level and the inclination directions of two adjacent preliminary step groups are opposite in the second direction, the first preliminary step cluster 211_2 and the second preliminary step cluster 212_2 satisfy the condition of mirror-symmetrical distribution, that is, as shown in fig. 4F, the number of levels of the plurality of preliminary step groups is the same and the plurality of preliminary step groups are mirror-symmetrical.

Of course, as shown in fig. 4F, the preliminary step structure 21_2 may further include a third preliminary step cluster 213_2, and at this time, a plurality of preliminary step groups may be respectively marked as G1 "to G18", and two of the groups are mirror-symmetrical to each other.

In some embodiments, the mask pattern may be used to protect the portions of the initial stacked structure 101_1 located in the first and second protection regions B4i1 and B5i1, and the portions of the initial stacked structure located in the first and second etching regions B4i2 and B5i2 may be etched under the protection of the mask pattern and the trimming.

Specifically, for example, by using 3 mask patterns to protect the portions of the initial stacked structure 101_1 located in the first protection region B4i1 and the second protection region B5i1, and performing trimming etching on the portions of the initial stacked structure 101_1 located in the first etching region B4i2 and the second etching region B5i2, as shown in fig. 4G, the portions of the initial stacked structure 101_1 located in the first etching region B4i2 and the second etching region B5i2 may be first subjected to trimming etching by using a first mask pattern M1 of the 3 mask patterns, trimmed 4 times, and etched 5 times to obtain a 5-step structure, and then, the portions of the initial stacked structure 101_1 located in the first etching region B4i2 and the second etching region B5i2 may be subjected to trimming etching by using a second mask pattern M2, similarly trimmed 4 times to obtain 5 steps, and finally, the portions of the initial stacked structure 101_1 located in the first etching region B4i2 and the second etching region B5i2 are subjected to trimming etching by using a third mask pattern M2, likewise, 4 etchings are trimmed 5 times to obtain 5 steps, so that each of the first etch region B4i2 and the second etch region B5i2 obtains 15 steps.

The steps are the same as those described above, and are not described in detail herein.

In order to realize a structure in which each step includes a plurality of steps S along the third direction, in some embodiments, a plurality of sub-partitions may be partitioned in the step partition Bi along the third direction, and each two adjacent sub-partitions are different by one composite layer (including one insulating layer and one sacrificial layer) by etching, so as to obtain a partitioned step structure having a plurality of steps along the third direction Y.

Taking the example above where each step includes two sub-sections in the third direction Y, each of the section-step structures may form 2 steps S in the third direction Y. At this time, the height of two composite layers (i.e., including two insulating layers and two sacrificial layers) is lowered every time etching is performed. That is, the height of one step is the height of two composite layers. At this time, taking an example that each of the first etching region B4i2 and the second etching region B5i2 obtains 15 steps, one preliminary step group may include steps of 30 levels.

As shown in fig. 4H, in the trimming etching process, each time the etching is completed, both sides of the portion of each step group where the first, second and third mask patterns M1, M2 and M3 cover the middle are trimmed along the second direction X, and a single side of the portion of the step group G1 ″ and G18 ″ where the first, second and third mask patterns M1, M2 and M3 cover the both sides is trimmed along the second direction X, so that a plurality of preliminary step groups in mirror symmetry are finally obtained.

It should be noted that, in fig. 4G, a situation that the sizes of the first mask pattern M1, the second mask pattern M2, and the third mask pattern M3 along the second direction X are changed from small to large is shown, and those skilled in the art can understand that the sizes of the first mask pattern M1, the second mask pattern M2, and the third mask pattern M3 along the second direction X can also be changed from large to small, and the same plurality of preliminary step groups can be obtained as well.

S33, performing a predetermined etching on at least all the preliminary step groups included in the second preliminary step cluster 212_2, so that all the preliminary step groups included in the second preliminary step cluster 212_2 are all decreased by the same level, thereby obtaining a first preliminary step cluster 211_1 and a second preliminary step cluster 212_ 1.

If all the preliminary step groups included in the second preliminary step cluster 212_2 are lowered by 30 levels, all the preliminary step groups included in the first preliminary step cluster 211_2 are located at the upper 30 levels of the initial stacked structure 101_1, and all the preliminary step groups included in the second preliminary step cluster 212_2 are located at the lower 30 levels of the initial stacked structure 101_1, and form a 60-level step structure, so that signals can be transmitted to the gate lines of 60 levels.

In some embodiments, the method of making further comprises: before etching all the preliminary step groups contained in the second preliminary step cluster 212_2, the first preliminary step cluster 211_2 and the second preliminary step cluster 212_2 are subjected to multiple times of preset etching, so that a plurality of preliminary step groups contained in the first preliminary step cluster 211_2 are located at different levels, and a plurality of preliminary step groups contained in the second preliminary step cluster 212_2 are located at different levels.

Different levels have meanings opposite to the same level, and specific reference may be made to the above description, and no description is given here, and all the levels that do not satisfy the same level meanings belong to different levels, that is, in these embodiments, by making the plurality of preliminary step groups included in the first preliminary step cluster 211_2 all be at different levels, and the plurality of preliminary step groups included in the second preliminary step cluster 212_2 all be at different levels, the steps included in each preliminary step group can be used for electrically leading out the grid lines as much as possible, and the step of one hundred or even several hundred levels can be manufactured.

As shown in fig. 4I, 6 of the 7 preliminary step groups included in the first preliminary step cluster 211_2 are all located at different levels, and 4 of the 4 preliminary step groups included in the second preliminary step cluster 212_2 are all located at different levels.

Taking each preliminary step group including 30 levels of steps as an example, the first preliminary step cluster 211_2 has 180 levels of steps, the second preliminary step cluster 212_2 has 120 levels of steps, after etching all preliminary step groups included in the second preliminary step cluster 212_2 to make all preliminary step groups included in the second preliminary step cluster 212_2 fall by 150 levels, the finally obtained first preliminary step cluster 211_2 is located at the upper 180 levels of the initial stacked structure, all preliminary step groups included in the second preliminary step cluster 212_2 are located at the lower 120 levels of the initial stacked structure, and a 300-level step structure is formed together, so that a signal transmission to 300 levels can be realized.

In some embodiments, the performing the preset etching on the first preliminary step cluster 211_2 and the second preliminary step cluster 212_2 for a plurality of times includes:

and (2) carrying out multiple times of preset etching on the first preliminary step cluster 211_2 and the second preliminary step cluster 212_2 by adopting a plurality of groups of mask plates M, wherein in the random twice preset etching, for the first preliminary step cluster 211_2 and/or the second preliminary step cluster 212_2, the edge of an opening of one mask plate M adopted by one time of etching and the edge of an opening of another mask plate M adopted by the other time of etching are not overlapped in the second direction.

Here, taking the number of the preliminary step groups included in the first preliminary step cluster 211_2 as 7, the number of the preliminary step groups included in the second preliminary step cluster 212_2 as 4, the number of the preliminary step groups included in the second preliminary step cluster 212_2 as G1 ", G2", G3 ", G4", G5 ", G6", and G7 ", the number of the preliminary step groups included in the second preliminary step cluster 212_2 as G8", G9 ", G10", and G11 ", and the preliminary step groups included in the first preliminary step cluster 211_2 except G1" and G7 "are all etched at different levels (i.e., 6 preliminary step groups are located at different levels), and the preliminary step groups included in the second preliminary step cluster 212_2 are all etched at different levels (i.e., 4 preliminary step groups are all located at different levels), for a predetermined plurality of times, the method comprises the following steps:

and 4 groups of masks M are adopted to perform preset etching on the first preliminary step cluster 211_2 and the second preliminary step cluster 212_2 for 4 times.

Here, the preliminary step structure 21_2 including the first preliminary step cluster 211_2, the second preliminary step cluster 212_2, and the second preliminary step cluster 213_2 will be described as an example.

As shown in fig. 4J, in the first preset etching, the openings of the mask M are exposed to G3 "— G4", G8 "— G9", and G15 "— G16", and accordingly, the positions of the edges of the openings of the mask M in the second direction are located on the left side of G3 ", the right side of G4", the left side of G8 ", the right side of G9", the left side of G15 ", and the right side of G16", respectively.

As shown in fig. 4K, in the second preset etching, the openings of the mask M are exposed to G2 "— G5", G8 "— G10", and G14 "— G17", and the positions of the edges of the openings of the mask M in the second direction X are respectively located on the left side of G2 ", the right side of G5", the left side of G8 ", the right side of G9", the left side of G15 ", and the right side of G16".

As shown in fig. 4L, in the third preset etching, the openings of the mask M are exposed to G4 "— G6", G9 "— G11", and G13 "— G15", and the positions of the edges of the openings of the mask M in the second direction X are respectively located on the left side of G4 ", the right side of G5", the left side of G9 ", the right side of G11", the left side of G13 ", and the right side of G15".

As shown in fig. 4M, in the fourth preset etching, G8 "-G11" are exposed from the opening of the mask M, and the positions of the edge of the opening of the mask M in the second direction are located on the left side of G8 "and the right side of G11", respectively.

Therefore, in the process of presetting etching, for the preliminary step group contained in the first preliminary step cluster 211, the opening edges of the mask plate M adopted by the etching are not overlapped in the second direction X for any two times, so that the defect of poor etching is easily caused along with the fact that the depth of the preliminary step group is larger and larger when the opening edges of the mask plate M are etched for multiple times at the same position. On the other hand, different primary step groups can be lowered to different depths, and the subsequent electrical leading-out of all grid lines is realized.

It should be noted that, for the first preliminary step cluster 211_2 and the second preliminary step cluster 212_2, only the case that, in any two times of the preset etching, the edge of the opening of the mask M used in one etching and the edge of the opening of the mask M used in another etching are not overlapped in the second direction is shown here for the first preliminary step cluster 211_2, and those skilled in the art can understand that, for the second preliminary step cluster 212_2, it is also possible to select different positions of the opening of the mask M in each preset etching to realize that, in any two times of the preset etching, the edge of the opening of the mask M used in one etching and the edge of the opening of the mask M used in another etching are not overlapped in the second direction, and it is also possible to avoid that the depth of the decrease along with the preliminary step group is larger and larger, the defect of poor etching is easily caused.

In these embodiments, by performing the predetermined etching on G2 "— G6" included in the first preliminary step cluster, and performing the predetermined etching on G13 "— G17" included in the third preliminary step cluster 213_2, instead of performing the predetermined etching on G7 "and G12", two support pillars may be formed on two sides of the groove 111 for the G7 "and the G12", so as to support the groove, and at the same time, the two support pillars may further separate the first step cluster 211, the second step cluster 212, and the third step cluster 213 into three groove structures, so as to facilitate the stress decomposition during the subsequent filling of the insulating material.

Here, for convenience of describing a comparison between overlapping and non-overlapping of edges of the opening of the mask M during multiple preset etches, in the embodiment of the present disclosure, the initial step structure includes the first initial step cluster 211_1, the second initial step cluster 212_1, and the third initial step cluster 213_1 as an example for description, and it can be understood by those skilled in the art that, if the initial step structure 21_1 only includes the first initial step cluster 211_1 and the second initial step cluster 212_1, during multiple preset etches, the overlapping of the edges of the opening of the mask M may be referred to, and of course, the edge of the opening of the mask M used in each etch may be adjusted according to an actually-to-be-fabricated structure.

S34, etching the initial wall 11_1 to form the groove 111 on the upper surface of the initial wall 11_ 1.

This step may occur after S33, or may be performed simultaneously with performing the preset etching on all the preliminary step groups included in the second preliminary step cluster 212_2, so as to obtain the structure shown in fig. 4M.

Here, for example, in the first preset etching, G3 "-" G4 ", G8" - "G9", and G15 "-" G16 "are all lowered by 30 levels, in the second preset etching, G2" - "G5", G8 "-" G10 ", and G14" - "G17" are all lowered by 30 levels, in the third preset etching, G4 "-" G6 ", G9" - "G11", and G13 "-" G15 "are all lowered by 90 levels, and in the fourth preset etching, G8" - "G11" is lowered by 150 levels, and after S33, when initial wall 11_1 is etched, initial wall 11_1 may be lowered by at least 150 levels. When the predetermined etching is performed simultaneously on all the preliminary step groups included in the S33 and the second preliminary step cluster 212_2, the preliminary walls 11_1 and G8 "-G11" may be lowered by 150 levels simultaneously. That is, in the fourth preset etching, the initial wall 11_1 is synchronously etched, and at this time, the opening of the mask M also exposes the region of the initial wall 11_1 corresponding to G8 "-G11".

S4, filling the groove 111 with an insulating material to form an insulating portion embedded in the groove 111, wherein the insulating portion is embedded in the groove 111 and contacts with the sidewall of the groove 111.

Wherein the insulating material may be an oxide material. During filling, the step structure can be filled with an insulating material, and at this time, due to the arrangement of the groove 111, the aspect ratio during filling the step structure 21 is reduced, so that stress can be reduced, and poor filling of the insulating part at the step structure 21 is avoided.

S5, replacing the sacrificial layer in the initial stacked structure 101_1 with the gate conductive layer 101b, so as to obtain the stacked structure 101 including a plurality of insulating layers and a plurality of gate conductive layers 101 b.

At this time, wall 11 and step structure 21 are obtained, and wall 11 includes a plurality of conductive wires. This stair structure 21 includes first step cluster 211, second step cluster 212 and third step cluster 213 that arrange in proper order along the second direction, and second step cluster 212 is compared first step cluster 211 and is kept away from first core area A1, and first step cluster 211, second step cluster 212 and third step cluster 213 all contact with the lateral wall of wall 11, and second step cluster 212 is located the below of recess 111. The first and

second step clusters

211 and 212 respectively include a plurality of step groups, each of which includes a plurality of gate conductive patterns GM arranged in a staircase, each of which is located at one of the gate conductive layers 101b among the plurality of gate conductive layers 101 b.

Wherein, replacing the sacrificial layer in the initial stacked structure 101 with the gate conductive layer 101b may include: the sacrificial layer in the stack structure 101 is removed, and the gate conductive layer 101b is formed in the original position of the sacrificial layer. The process of removing the sacrificial layer may be, for example, a wet etching process; the material of the sacrificial layer may be, for example, silicon nitride, polysilicon, or the like.

The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.

Claims

1. A semiconductor structure, comprising:

a stacked structure including a plurality of insulating layers and a plurality of gate conductive layers alternately stacked in a first direction;

the laminated structure has a first core region and a step region arranged in a second direction; in the step area, the laminated structure is divided into a wall body and a step structure which are arranged along a third direction; grooves which at least penetrate through two adjacent walls along the third direction are formed in the upper surface of each wall; the step structure comprises a first step cluster and a second step cluster which are arranged along the second direction, the second step cluster is far away from the first core area compared with the first step cluster, the first step cluster and the second step cluster are both contacted with the side wall of the wall body, and the second step cluster is positioned below the groove;

the insulating part is embedded into the groove and is in contact with the side wall of the groove;

the first step cluster and the second step cluster respectively comprise a plurality of step groups, each step group comprises a plurality of grid conductive patterns which are arranged in a stepped mode, and each grid conductive pattern is located on one of the grid conductive layers; the first direction, the second direction and the third direction are mutually vertical.

2. The semiconductor structure of claim 1,

among a plurality of step groups included in the first step cluster, the step group closest to the groove is the first step group, and at least part of the gate conductive patterns in the first step group are higher than the bottom of the groove.

3. The semiconductor structure of claim 2,

the uppermost gate conductive pattern in the first step group is located at an uppermost gate conductive layer among the plurality of gate conductive layers.

4. The semiconductor structure of claim 2,

the first step group and the second step cluster are opposite in inclination direction of the step group adjacent to the first step group.

5. The semiconductor structure of claim 1,

among a plurality of step groups included in the first step cluster, a step group farthest from the groove is a second step group, and at least a part of gate conductive patterns included in the second step group are higher than gate conductive patterns included in step groups adjacent to the second step group in the first step cluster.

6. The semiconductor structure of claim 5,

in the second step group, each gate conductive pattern in at least part of the gate conductive patterns and at least one gate conductive pattern in the first step group are located in the same gate conductive layer, and the first step group is the step group which is closest to the groove in the plurality of step groups included in the first step cluster.

7. The semiconductor structure of claim 1,

the semiconductor structure further includes a plurality of first gate lines in the first core region;

the step area comprises a first sub-area and a second sub-area which are sequentially arranged along a second direction, the first sub-area is positioned on one side, close to the first core area, of the groove, and the groove is positioned in the second sub-area;

the wall comprises a plurality of conductive wires;

the first step cluster is positioned in the first sub-area, one grid conductive pattern contained in the first step cluster is in contact with one first conductive line, the first conductive line is in contact with one first grid line, the second step cluster is positioned in the second sub-area, one grid conductive pattern contained in the second step cluster is in contact with one second conductive line, and the second conductive line is in contact with one first grid line;

wherein the first conductive line is a part of the wall where one conductive line is located in the first sub-region, and the second conductive line is a part of the wall where one conductive line is located in the first and second sub-regions.

8. The semiconductor structure of claim 1,

the semiconductor structure further includes: a plurality of contacts electrically connected to the first step cluster;

and one of the two grid conductive patterns is in contact with at least one of the contacts, and the other grid conductive pattern is not in contact with the contacts.

9. The semiconductor structure of claim 1,

one step group at the lowest position in the plurality of step groups included in the first step cluster is a third step group;

the second step cluster comprises a plurality of step groups, wherein one step group at the highest position is a fourth step group;

the gate conductive pattern on the lowest layer in the third step group and the gate conductive pattern on the uppermost layer in the fourth step group are respectively located on two adjacent gate conductive layers in the plurality of gate conductive layers.

10. The semiconductor structure of claim 1,

in a plurality of step groups included in the same step cluster, the inclination directions of two adjacent step groups are opposite.

11. The semiconductor structure of any one of claims 1 to 10,

the laminated structure further includes: the second core area is positioned on one side, far away from the first core area, of the stepped area;

the step structure further includes: the third step cluster is positioned on one side, away from the first step cluster, of the groove and is in contact with the side wall of the wall;

the third step cluster comprises a plurality of step groups, each step group comprises a plurality of grid conductive patterns arranged in a ladder mode, and each grid conductive pattern is located on one of the grid conductive layers.

12. The semiconductor structure of claim 11,

the semiconductor structure further includes a plurality of second gate lines in the second core region;

the step area further comprises a third sub-area, and the third sub-area is positioned on one side, far away from the first core area, of the groove;

the third step cluster is located in the third sub-area, and one gate conductive pattern included in the third step cluster is in contact with one third conductive line, the third conductive line is in contact with one second gate line, one gate conductive pattern included in the second step cluster is in contact with one fourth conductive line, and the fourth conductive line is in contact with one second gate line;

wherein the third conductive line is a portion of the wall where one conductive line is located in the third sub-region, and the fourth conductive line is a portion of the wall where one conductive line is located in the second and third sub-regions.

13. The semiconductor structure of claim 11,

each of the plurality of gate conductive patterns in the first step cluster and the corresponding at least one gate conductive pattern in the third step cluster are included in the same gate conductive layer.

14. A three-dimensional memory, comprising:

a semiconductor structure as claimed in any one of claims 1 to 13.

15. A storage system comprising a three-dimensional memory as recited in claim 14 and a controller, the controller coupled to the three-dimensional memory to control the three-dimensional memory to store data.

16. A method for fabricating a semiconductor structure, comprising:

forming an initial stacked structure including a plurality of insulating layers and a plurality of sacrificial layers alternately stacked in a first direction;

dividing the initial laminated structure into a first core region and a step region arranged along a second direction;

forming an initial wall body and an initial step structure which are sequentially arranged along a third direction on the initial laminated structure and are positioned in the step area; a groove penetrating through at least two adjacent initial walls along a third direction is formed in the upper surface of each initial wall, each initial step structure comprises a first initial step cluster and a second initial step cluster which are arranged along a second direction, the first initial step cluster and the second initial step cluster are both in contact with the side wall of each initial wall, and each second initial step cluster is located below the corresponding groove; the first direction, the second direction and the third direction are mutually vertical; the first initial step cluster and the second initial step cluster each include a plurality of initial step groups, each initial step group including a plurality of sacrificial patterns arranged in a staircase, each sacrificial pattern being located at one of the plurality of sacrificial layers;

filling an insulating material in the groove to form an insulating part, wherein the insulating part is embedded in the groove and is in contact with the side wall of the groove;

17. The method of claim 16, wherein the step of forming the semiconductor structure comprises the step of forming a semiconductor layer on the substrate,

the initial wall and the initial step structure which are arranged in sequence along the third direction are formed on the initial laminated structure and are positioned in the step area, and the method comprises the following steps:

dividing the part of the initial laminated structure, which is positioned in the step area, into a wall area and a step area along a third direction;

protecting the part of the initial laminated structure positioned in the wall body area, and etching the part of the initial laminated structure positioned in the step subarea to obtain the initial wall body positioned in the wall body area and the initial step structure positioned in the step subarea;

and etching the initial wall body to form the groove on the upper surface of the initial wall body.

18. The method of claim 17, wherein the step of forming the semiconductor structure comprises the step of forming a semiconductor layer on the substrate,

the step partition comprises a plurality of third sub-areas and a plurality of fourth sub-areas which are sequentially distributed along the second direction, and each third sub-area comprises: the first protection area and the first etching area are located on one side, far away from the first core area, of the first protection area, and each fourth sub-area comprises: the second protection area and a second etching area are positioned on one side, close to the first core area, of the second protection area;

the etching the part of the initial laminated structure, which is positioned in the step partition, comprises the following steps:

protecting the parts of the initial laminated structure, which are positioned in the first protection area and the second protection area, and trimming and etching the parts of the initial laminated structure, which are positioned in the first etching area and the second etching area, to obtain a preliminary step structure, wherein the preliminary step structure comprises a first preliminary step cluster and a second preliminary step cluster which are sequentially arranged along a second direction, the first preliminary step cluster and the second preliminary step cluster both comprise a plurality of preliminary step groups, and the plurality of preliminary step groups are positioned at the same level; and for the plurality of preliminary step groups, the inclination directions of two adjacent preliminary step groups are opposite along the second direction;

and at least performing preset etching on all initial step groups contained in the second initial step cluster, so that all initial step groups contained in the second initial step cluster are all decreased by the same level, and the first initial step cluster and the second initial step cluster are obtained.

19. The method of claim 18, wherein the step of forming the semiconductor structure comprises the step of forming the semiconductor structure,

and etching the initial wall body, and performing preset etching on all the original step groups contained in the second initial step cluster synchronously.

20. The method of claim 18, further comprising:

21. The method of claim 20, wherein the step of forming the semiconductor structure comprises the step of forming the semiconductor structure,

the multiple preset etching is carried out on the first preliminary step cluster and the second preliminary step cluster, and the method comprises the following steps: