CN114284286A - Semiconductor device, manufacturing method thereof and storage system - Google Patents

Abstract

The application provides a semiconductor device, a preparation method thereof and a storage system, relates to the technical field of semiconductor chips, and is used for reducing the process difficulty of preparing the semiconductor device, shortening the preparation process flow, improving the preparation efficiency and reducing the preparation cost. The preparation method of the semiconductor device comprises the following steps: providing a three-dimensional array structure; the three-dimensional array structure comprises a substrate, a first stop layer, a second stop layer and a laminated structure. A channel hole is formed through the stacked structure and extending to the substrate. And forming a channel structure in the channel hole. And removing the substrate and the part of the channel structure extending to the substrate to the first stop layer. And etching the first stop layer and the part of the memory function layer extending to the first stop layer to the second stop layer, and exposing the part of the channel layer extending to the first stop layer. A source layer is formed in electrical contact with the exposed portion of the channel layer. The semiconductor device is applied to a three-dimensional memory to realize reading and writing operations of data.

Description

Semiconductor device, manufacturing method thereof and storage system

Technical Field

The present disclosure relates to the field of semiconductor chip technologies, and in particular, to a semiconductor device, a manufacturing method thereof, and a memory system.

Background

As the feature size of memory cells approaches the lower process limit, planar processes and manufacturing techniques become challenging and costly, which causes the storage density of 2D or planar NAND flash memories to approach the upper limit. To overcome the limitations imposed by 2D or planar NAND flash memories, memories having a three-dimensional structure (3D NAND) have been developed to increase the storage density by arranging memory cells three-dimensionally over a substrate.

Disclosure of Invention

Embodiments of the present application provide a semiconductor device, a manufacturing method thereof, and a storage system, which are used for reducing the difficulty of a process for manufacturing the semiconductor device, shortening the manufacturing process flow, improving the manufacturing efficiency, and reducing the manufacturing cost.

In order to achieve the above purpose, the embodiment of the present application adopts the following technical solutions:

in one aspect, a method of fabricating a semiconductor device is provided. The preparation method of the semiconductor device comprises the following steps: providing a three-dimensional array structure; the three-dimensional array structure comprises a substrate, and a first stop layer, a second stop layer and a laminated structure which are sequentially arranged on one side of the substrate in a laminated mode. A plurality of channel holes are formed through the stacked structure and extending to the substrate. And sequentially forming a memory function layer and a channel layer in the channel holes to form a plurality of channel structures. And removing the substrate and the part of the channel structure extending to the substrate to the first stop layer. And etching the first stop layer and the part of the memory function layer extending to the first stop layer to the second stop layer, and exposing the part of the channel layer extending to the first stop layer. Forming a source layer on a side of the second stop layer remote from the stacked layer structure, the source layer forming an electrical contact with the exposed portion of the channel layer.

Therefore, in the method for manufacturing a semiconductor device according to some embodiments of the present application, after forming the trench hole and the trench structure located in the trench hole, the substrate and the portion of the trench structure extending to the substrate are removed (for example, by a grinding process) to expose the trench structure, and then the portion of the memory function layer extending to the first stop layer is etched to expose the portion of the trench layer extending to the first stop layer, so that not only can the control on the trench opening be reduced, the etching window of the trench structure be increased, the difficulty of the manufacturing process and the manufacturing cost be reduced, but also the step of removing (for example, by a grinding process) the portion of the substrate and the portion of the trench structure extending to the substrate can be used to replace the step of forming the first oxide layer in the prior art to the step of etching the bottom polysilicon layer with the etched second oxide layer as a mask to expose the trench structure, the process flow for preparing and forming the semiconductor device is shortened, the preparation efficiency is improved, and the preparation cost is reduced.

In some embodiments, the removing the substrate and the portion of the channel structure extending to the substrate to the first stop layer comprises: and removing the substrate and the part of the channel structure extending to the substrate to the first stop layer by adopting a grinding process.

In some embodiments, the substrate includes a base, a first sacrificial layer, and a second sacrificial layer, which are sequentially stacked. The removing the substrate and the part of the channel structure extending to the substrate to the first stop layer by using a grinding process comprises: removing the substrate and the first sacrificial layer; and removing the second sacrificial layer and the part of the channel structure extending to the substrate by adopting a grinding process.

In some embodiments, a gap is provided within the channel layer. After removing the portion of the channel structure extending to the substrate to the first stop layer, before the etching the first stop layer and the portion of the memory function layer extending to the first stop layer to the second stop layer, and exposing the portion of the channel layer extending to the first stop layer, a gap of the channel layer of at least one of the channel structures is exposed, and the manufacturing method further includes: forming a dielectric layer, wherein the dielectric layer fills the gap and covers the first stop layer; and removing the part of the dielectric layer covering the first stop layer, and reserving the part of the dielectric layer filled in the gap.

In some embodiments, prior to forming the source layer, the method of making further comprises: and carrying out doping treatment on the exposed part of the channel layer.

In some embodiments, the material of the second stop layer and the material of the channel layer are the same. In the process of doping the exposed portion of the channel layer, the second stop layer is also doped.

In some embodiments, before the removing the substrate and the portion of the channel structure extending to the substrate to the first stop layer, the method further comprises: forming a gate line slit penetrating the stacked structure and extending to the substrate; and forming a grid line isolation structure in the grid line gap. And in the process of removing the substrate and the part of the channel structure extending to the substrate to the first stop layer, removing the part of the grid line isolation structure extending to the substrate. The source layer also forms an electrical contact with the exposed portion of the gate line isolation structure.

In some embodiments, before the removing the substrate and the portion of the channel structure extending to the substrate to the first stop layer, the method further comprises: and forming a virtual channel structure penetrating through the laminated structure and extending to the substrate. And in the process of removing the substrate and the part of the channel structure extending to the substrate to the first stop layer, removing the part of the dummy channel structure extending to the substrate. The source layer also covers exposed portions of the dummy channel structure.

In some embodiments, before the removing the substrate and the portion of the channel structure extending to the substrate to the first stop layer, the method further comprises: providing a peripheral circuit structure; and bonding the peripheral circuit structure and the three-dimensional array structure.

In some embodiments, after the forming a source layer on a side of the second stop layer away from the stacked-layer structure, the source layer forming an electrical contact with the exposed portion of the channel layer, the method further comprises: providing a peripheral circuit structure; and bonding the peripheral circuit structure and the processed three-dimensional array structure.

In another aspect, a semiconductor device is provided. The semiconductor device includes: a source layer; a second stop layer disposed on a side of the source layer; a stack structure disposed on a side of the second stop layer away from the source layer; and a plurality of channel structures extending through the stack structure and extending to the source layer. The channel structure comprises a memory function layer and a channel layer which are sequentially arranged, wherein an opening is formed in the part, close to the source layer, of the memory function layer, and the channel layer extends into the source layer through the opening and is in electric contact with the source layer.

In some embodiments, a gap is provided within the channel layer. The semiconductor device further includes: a filling dielectric layer arranged in at least one of the gaps; the fill dielectric layer is in contact with the source layer.

In some embodiments, a side surface of the fill dielectric layer adjacent to the source layer is lower than a side surface of the channel layer extending into the source layer relative to the second stop layer, and portions of the fill dielectric layer and the channel layer extending into the source layer form a recess; the source layer fills the recess.

In some embodiments, a side surface of the second stop layer close to the source layer, a side surface of the storage function layer close to the source layer, and a side surface of the filling medium layer close to the source layer are located on the same plane.

In some embodiments, the semiconductor device further comprises: and a gate line isolation structure penetrating the stacked structure and the second stop layer. The gate line isolation structure is in electrical contact with the source layer. At least one part of the grid line isolation structure is close to one side surface of the source layer, and the second stop layer is close to one side surface of the source layer and is positioned on the same plane.

In some embodiments, the semiconductor device further comprises: a dummy channel structure extending through the stack structure and the second stop layer. The dummy channel structure is in contact with the source layer. The dummy channel structure is located on a side surface of the source layer, and the second stop layer is located on a side surface of the source layer.

In some embodiments, the semiconductor device further comprises: and the peripheral circuit structure is arranged on one side of the laminated structure far away from the source layer and is electrically connected with the channel structure.

In yet another aspect, a storage system is provided. The storage system includes: a controller, and a semiconductor device as described in some embodiments above. Wherein the controller is coupled to the semiconductor device and is used for controlling the semiconductor device to store data.

It can be understood that, in the semiconductor device and the three-dimensional memory provided in the embodiments of the present application, the beneficial effects achieved by the semiconductor device and the three-dimensional memory can refer to the beneficial effects of the above semiconductor device manufacturing method, and are not described herein again.

Drawings

In order to more clearly illustrate the technical solutions in the present application, the drawings required to be used in some embodiments of the present application will be briefly described below, and it is apparent that the drawings in the following description are only drawings of some embodiments of the present application, and other drawings can be obtained by those skilled in the art according to the drawings. Furthermore, the drawings in the following description may be regarded as schematic diagrams, and do not limit the actual size of products, the actual flow of methods, and the like, which are referred to in the embodiments of the present application.

Fig. 1 is a flow chart of a method of fabricating a semiconductor device according to some embodiments;

fig. 2 is a flow chart of another method of fabricating a semiconductor device according to some embodiments;

FIGS. 3 a-1-3 i are diagrams of steps of a method of fabricating a semiconductor device according to some embodiments;

FIGS. 4 a-4 d are diagrams illustrating steps in another method of fabricating a semiconductor device in accordance with some embodiments;

FIGS. 5 a-5 e are diagrams illustrating steps in a method of fabricating a semiconductor device according to yet another embodiment;

FIG. 6a is an enlarged partial view of the step diagram of FIG. 4 a;

FIG. 6b is an enlarged partial view of the step diagram of FIG. 4 b;

FIG. 6c is an enlarged partial view of the step diagram of FIG. 4 c;

FIG. 6d is an enlarged view of a portion of the step diagram of FIG. 4 d;

FIG. 7 is a scanning electron microscope image of a semiconductor device according to some embodiments;

FIG. 8 is a scanning electron microscope view of another semiconductor device in accordance with some embodiments;

FIG. 9 is a scanning electron microscope view of yet another semiconductor device in accordance with some embodiments;

FIG. 10 is a block diagram of a semiconductor device in accordance with some embodiments;

FIG. 11 is a block diagram of another semiconductor device in accordance with some embodiments;

FIG. 12 is a block diagram of yet another semiconductor device in accordance with some embodiments;

fig. 13 is a cross-sectional view of a memory cell string in the direction D-D' in the semiconductor device shown in fig. 11;

FIG. 14 is a block diagram of a storage system in accordance with some embodiments;

FIG. 15 is a block diagram of another memory system in accordance with some embodiments.

Detailed Description

The technical solutions in some embodiments of the present application will be described clearly and completely with reference to the accompanying drawings, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments that can be derived by one of ordinary skill in the art from the examples provided herein fall within the scope of the present application.

In the description of the present application, it is to be understood that the terms "center", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like indicate orientations or positional relationships based on those shown in the drawings, and are only for convenience in describing the present application and simplifying the description, but do not indicate or imply that the referred device or element must have a particular orientation, be constructed in a particular orientation, and be operated, and thus should not be construed as limiting the present application.

Throughout the specification and claims, the term "comprising" is to be interpreted in an open, inclusive sense, i.e., as "including, but not limited to," unless the context requires otherwise. In the description herein, the terms "one embodiment," "some embodiments," "an example embodiment," "exemplarily" or "some examples" or the like are intended to indicate that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present application. The schematic representations of the above terms are not necessarily referring to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be included in any suitable manner in any one or more embodiments or examples.

In the following, the terms "first", "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the embodiments of the present application, "a plurality" means two or more unless otherwise specified.

In describing some embodiments, expressions of "coupled" and "connected," along with their derivatives, may be used. For example, the term "connected" may be used in describing some embodiments to indicate that two or more elements are in direct physical or electrical contact with each other. As another example, some embodiments may be described using the term "coupled" to indicate that two or more elements are in direct physical or electrical contact. The term "coupled," however, may also mean that two or more elements are not in direct contact with each other, but yet still co-operate or interact with each other. The embodiments claimed herein are not necessarily limited to the contents herein.

The use of "adapted to" or "configured to" herein is meant to be an open and inclusive language that does not exclude devices adapted to or configured to perform additional tasks or steps.

Additionally, the use of "based on" means open and inclusive, as a process, step, calculation, or other action that is "based on" one or more stated conditions or values may in practice be based on additional conditions or values beyond those stated.

As used herein, "about," "approximately," or "approximately" includes the stated values as well as average values that are within an acceptable range of deviation for the particular value, as determined by one of ordinary skill in the art in view of the measurement in question and the error associated with measurement of the particular quantity (i.e., the limitations of the measurement system).

In the context of this application, the meaning of "on … …", "above", and "over" should be interpreted in the broadest manner such that "on.

Example embodiments are described herein with reference to cross-sectional and/or plan views as idealized example figures. In the drawings, the thickness of layers and regions are exaggerated for clarity. Variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, the exemplary embodiments should not be construed as limited to the shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the exemplary embodiments.

As used herein, the term "substrate" refers to a material onto which subsequent layers of material may be added. The substrate itself may be patterned. The material added on the substrate may be patterned or may remain unpatterned. In addition, the substrate may include a variety of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, and the like. Alternatively, the substrate may be made of a non-conductive material such as glass, plastic, or sapphire wafer.

The term "three-dimensional memory" refers to a semiconductor device formed of memory cell transistor strings (referred to herein as "memory cell strings", e.g., NAND memory cell strings) arranged in an array on a major surface of a substrate and extending in a direction perpendicular to the substrate. As used herein, the term "perpendicular" means nominally perpendicular to a major surface (i.e., a lateral surface) of a substrate.

At present, in order to control the variation of channel hole slotting (CH gouging), and avoid damaging the channel structure in the subsequent process, the depths of different channel holes need to be basically consistent, so as to ensure that different channel holes can stay in the same film layer (for example, a bottom polysilicon layer) in the process of forming the channel holes, thereby easily increasing the difficulty of the 3D NAND manufacturing process and increasing the manufacturing cost.

In addition, in order to avoid the problem of Leakage (Leakage) caused by short circuit between a Word Line (WL) and an Array Common Source (ACS) in the process of filling a conductive material in a gate Line gap, multiple process steps are required to remove a memory function layer of a channel structure from the bottom of a 3D NAND and expose a channel layer of the channel structure. In one implementation, the bottom substrate of the 3D NAND is removed first; forming a first oxide layer at the bottom of the 3D NAND, and etching the first oxide layer; then forming a second oxide layer at the bottom of the 3D NAND; forming a photoresist layer on one side of the second oxide layer, and arranging a mask plate on one side of the photoresist layer to pattern the photoresist; then, taking the patterned photoresist layer as a mask, etching the second oxide layer, removing the part of the second oxide layer covering the channel structure, and exposing the part of the second oxide layer not covering the channel structure; etching the bottom polycrystalline silicon layer by taking the etched second oxide layer as a mask to expose the channel structure; and then etching the channel structure, removing the storage function layer of the channel structure and exposing the channel layer of the channel structure.

As can be seen from the above, the number of process steps required to remove the memory function layer of the channel structure from the bottom of the 3D NAND and expose the channel layer of the channel structure is large, which not only increases the process flow of forming the 3D NAND, but also greatly increases the manufacturing cost of the 3D NAND. Therefore, in the related art, how to simplify the process step of removing the memory function layer of the channel structure from the bottom of the 3D NAND to expose the channel layer of the channel structure is also a problem to be solved at present.

Fig. 1-2 are flow charts of methods of fabricating semiconductor devices provided by some embodiments of the present application; fig. 3a-1 to 3i and 4a to 4d are cross-sectional structural views corresponding to respective steps in a method of manufacturing a semiconductor device according to some embodiments. It should be understood that the steps shown in fig. 1-2 are not exclusive and that other steps may be performed before, after, or between any of the steps shown. Further, some of the steps may be performed simultaneously, or may be performed in an order different from that shown in fig. 1 to 2. A method for manufacturing a semiconductor device in some embodiments is described below with reference to fig. 1 to 2, 3a to 1 to 3i, and 4a to 4 d.

Some embodiments of the present application provide a method of manufacturing a semiconductor device. As shown in fig. 1, the preparation method comprises: s100 to S600.

S100, as shown in FIGS. 3a-1 and 3a-2, a three-dimensional array structure 1 is provided. The three-dimensional array structure 1 includes a substrate 11, and a first stop layer 12, a second stop layer 13, and a stacked structure 14, which are sequentially stacked on one side of the substrate 11.

Illustratively, the substrate 11 may provide support for subsequent processing steps. For example, the material of the substrate 11 may be single crystal silicon (Si), single crystal germanium (Ge), silicon germanium (GeSi), silicon carbide (SiC), or the like; silicon-on-insulator (SOI), germanium-on-insulator (GOI), or the like; other materials, such as III-V compounds such as gallium arsenide, are also possible.

Illustratively, as shown in FIGS. 3a-1 and 3a-2, the above-described laminated structure 14 includes a plurality of film layers stacked in sequence along the direction Z. The plurality of film layers includes, for example, a plurality of gate dielectric layers 141 and a plurality of gate sacrificial layers 142 that are alternately stacked. In the stacked structure 14, the thicknesses of the gate dielectric layers 141 may be the same or different, and the thicknesses of the gate sacrificial layers 142 may be the same or different, and may be specifically set according to actual needs. In addition, in the manufacturing process of the stacked structure 14, different stacking layers correspond to different stacking heights, for example, the number of stacked layers of the stacked structure 14 may be 32, 64 or 128, and the more the number of stacked layers of the stacked structure 14, the higher the integration level, the more the number of memory cells formed by the stacked structure, and the stacking layers and the stacking heights of the stacked structure 14 may be specifically designed according to actual memory requirements, which is not limited in this application.

For example, gate dielectric layer 141 and gate sacrificial layer 142 may have different etch selectivity ratios. This allows the gate dielectric layer 141 to be retained and the gate sacrificial layer 142 to be removed in a subsequent process, so as to form a sacrificial gap between any two adjacent gate dielectric layers 141, which facilitates the subsequent filling of the sacrificial gap with a conductive material to form the gate layer 143 (i.e., the word line).

Alternatively, the material of the gate dielectric layer 141 includes, for example, silicon oxide, and the material of the gate sacrificial layer 142 includes, for example, silicon nitride.

Illustratively, as shown in FIGS. 3a-1 and 3a-2, the edges of the laminate structure 14 are stepped. The edge structure of the stacked structure 14 may be formed, for example, by performing a plurality of "trim-etch" cycles on the plurality of gate dielectric layers 141 and the plurality of gate sacrificial layers 142 of the stacked structure 14.

For example, the edges of the laminated structure 14 may be provided with an insulating cover layer. The insulating cover layer may cover a stepped edge in the layer stack 14. The material of the insulating cover layer may be a dielectric material. Further, the material of the insulating capping layer may be the same as the material of the gate dielectric layer 141, for example, the material of the insulating capping layer is silicon oxide.

Alternatively, the material of the first stop layer 12 may be silicon oxide.

S200, as shown in FIGS. 3b-1 to 3b-3, a plurality of channel holes 2 are formed to penetrate the stacked structure 14 and extend to the substrate 11.

Illustratively, the plurality of channel holes 2 may be formed using a dry etching process or a wet etching process. The channel hole 2 may extend in the direction Z towards the substrate 11.

S300, as shown in fig. 3c, sequentially forming the memory function layer 31 and the channel layer 32 in the channel hole 2 to form a plurality of channel structures 3.

For example, the charge blocking Layer 311, the charge trapping Layer 312, the tunneling Layer 313 and the channel Layer 32 may be sequentially deposited in the channel hole 2 by a thin film Deposition process of Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD) or any combination thereof. Among them, the charge blocking layer 311, the charge trapping layer 312, and the tunneling layer 313 may constitute the storage function layer 31.

For example, in the process of forming the channel layer 32, one or more gaps G may be formed inside the channel layer 32 by controlling the formation process of the channel layer 32 to relieve structural stress.

Alternatively, the material of the charge blocking layer 311 may be silicon oxide, the material of the charge trapping layer 312 may be silicon nitride, the material of the tunneling layer 313 may be silicon oxide, and the material of the channel layer 32 may be polysilicon. The charge blocking layer 311, the charge trapping layer 312, the tunneling layer 313, and the channel layer 32 may form a "SONO" structure.

S400, as shown in fig. 3g, 4a and 5a, the substrate 11 and the portion of the channel structure 3 extending to the substrate 11 are removed to the first stop layer 12.

It should be noted that, in the process of removing the substrate 11 and the portion of the channel structure 3 extending to the substrate 11, the substrate 11 and the portion of the channel structure 3 extending to the substrate 11 are removed at the same time, instead of removing the substrate 11 first and then removing the portion of the channel structure 3 extending to the substrate 11. Therefore, as shown in fig. 3b-1 to 3b-3, regardless of whether the depths of the channel holes 2 are uniform, if it is ensured that the channel holes 2 can extend into the substrate 11 so that the channel structures 3 in the channel holes 2 also extend into the substrate 11, at least the end portions of the memory function layers 31 in the channel structures 3 are removed, and even the end portions of the memory function layers 31 and the end portions of the channel layers 32 are removed at the same time, exposing the memory function layers 31 and the channel layers 32 in S400.

That is to say, the present application can reduce the control on the grooving variation of the trench holes 2, and the depths of the trench holes 2 may be uniform or non-uniform, and may extend into the substrate 11.

Therefore, the method is beneficial to enlarging the etching process window of the channel structure 3, reducing the preparation process difficulty of the semiconductor device and reducing the preparation cost.

Here, the first stop layer 12 is located between the second stop layer 13 and the substrate 11. The first stop layer 12 may be used to stop the removal action at the first stop layer 12 during the removal of the substrate 11 and the portion of the channel structure 3 extending to the substrate 11.

By providing the first stop layer 12, the uniformity of the process in removing the substrate 11 and the portion of the channel structure 3 extending to the substrate 11 is advantageously controlled, so that the surface of the channel structure 3 on the side away from the stacked structure 14 can be flush with the surface of the first stop layer 12 on the side away from the stacked structure 14.

It will be appreciated that the three-dimensional array structure 1 may be inverted before removing the substrate 11 and the portion of the channel structure 3 extending to the substrate 11, and then removing the substrate 11 and the portion of the channel structure 3 extending to the substrate 11.

In some examples, removing the portion of the substrate 11 and the channel structure 3 extending to the substrate 11 to the first stop layer 12 includes: the substrate 11 and the portion of the channel structure 3 extending to the substrate 11 are removed to the first stop layer 12 by a grinding process.

Illustratively, the Grinding process includes a Chemical Mechanical Polishing (CMP) process or a surface Grinding (Grinding) process. That is, the substrate 11 may be directly polished by a CMP process or a Grinding process while portions of the substrate 11 and the channel structures 3 extending to the substrate 11 are polished.

For example, the present application may also use other processes to remove the substrate 11, and use a grinding process to remove the portion of the channel structure 3 extending to the substrate 11 to the first stop layer 12. The process for removing the substrate 11 may be determined according to the structure of the substrate 11, and specifically refer to the following description, which is not repeated herein.

It is understood that, in the case that the substrate 11 and the portion of the channel structure 3 extending to the substrate 11 to the first stop layer 12 are removed by a Grinding process, the above-mentioned removing action is also referred to as a Grinding process, i.e. a CMP process or a Grinding process.

S500, as shown in fig. 3h, fig. 4c and fig. 5c, the first stop layer 12 and the memory function layer 31 are etched to the second stop layer 13 from the portion extending to the first stop layer 12, and the portion extending to the first stop layer 12 of the channel layer 32 is exposed.

For example, the first stop layer 12 and the portion of the memory function layer 31 extending to the first stop layer 12 may be etched by a dry etching process. Wherein the dry etching may include chemical etching or physical chemical etching.

For example, in the process of etching the portion of the first stop layer 12 and the storage function layer 31 extending to the first stop layer 12, a suitable gas may be selected according to the material of the first stop layer 12 and the material of the storage function layer 31, so that the plasma in the gas reacts with the portion of the first stop layer 12 and the storage function layer 31 extending to the first stop layer 12, and the portion of the first stop layer 12 and the storage function layer 31 extending to the first stop layer 12 is etched away. The plasma in the gas may not react with the channel layer 32, thereby leaving and exposing portions of the channel layer 32 extending to the first stop layer 12.

Alternatively, by controlling the time of etching or the kind of plasma in the above-described gas, it is possible to stop the etching of the first stop layer 12 at the second stop layer 13 and stop the etching of the memory function layer 31 at the second stop layer 13, thereby exposing a portion of the channel layer 32 extending to the first stop layer 12.

For example, as shown in fig. 3h, after the memory function layer 31 is etched, a surface of the memory function layer 31 away from the stacked structure 14 may be flush with a surface of the second stop layer 13 away from the stacked structure 14.

By providing the second stop layer 13, it is beneficial to control the process uniformity in the process of removing the first stop layer 12 and the portion of the storage function layer 31 extending to the first stop layer 12, so that the surface of the side of the storage function layer 31 away from the stacked structure 14 can be flush with the surface of the second stop layer 13 where the dry etching process is stopped.

In the related art, after the bottom substrate is removed, the bottom polysilicon layer can be etched by adopting 6 processes to expose the channel structure, and the process flow is long. Moreover, in the process of etching the bottom polysilicon layer and etching the channel structure, different etching devices are required to be used respectively.

In the present application, after the substrate 11 and the portion of the channel structure 3 extending to the substrate 11 are removed to the first stop layer 12, the portion of the memory function layer 31 extending to the first stop layer 12 can be directly etched without 6 processes in the prior art, and the portion of the channel layer 32 extending to the first stop layer 12 is exposed. Moreover, in the process of etching the memory function layer 31, only one etching apparatus needs to be used. Therefore, the method is not only beneficial to shortening the process flow and improving the preparation efficiency, but also beneficial to reducing the use of etching equipment and greatly reducing the preparation cost.

S600, as shown in fig. 3i, 4d, 5d and 6d, a source layer 4 is formed on the side of the second stop layer 13 away from the stacked-layer structure 14, and the source layer 4 is in electrical contact with the exposed portion of the channel layer 32.

Illustratively, the source layer 4 may be deposited on the side of the second stop layer 13 away from the stacked structure 14 by a thin film deposition process such as CVD, PVD, ALD, or any combination thereof.

The formation of the source layer 4 may be varied according to the material of the source layer 4.

For example, the material of the source layer 4 may be polysilicon. At this time, after the source layer 4 is formed by depositing polysilicon, for example, ion implantation may be performed on the source layer 4 to perform doping treatment, and then, for example, annealing treatment may be performed by using an annealing process (for example, a laser annealing process) to repair lattice damage of the material caused by the ion implantation process and activate the implanted dopants.

As another example, the material of the source layer 4 may be doped polysilicon. At this point, the source layer 4 may be formed directly using doped polysilicon deposition.

Illustratively, as shown in fig. 3i, 4d, 5d and 6d, the source layer 4 covers the exposed portion of the channel layer 32, surrounds the exposed portion of the channel layer 32, and contacts the exposed portion of the channel layer 32 to form an electrical connection. This enables the source layer 4 and the channel layer 32 to have a larger contact area, which is advantageous for increasing the reliability of the contact connection and the performance of the semiconductor device 100.

Therefore, in the method for manufacturing a semiconductor device according to some embodiments of the present application, after forming the channel hole 2 and the channel structure 3 located in the channel hole 2, the substrate 11 and the part of the channel structure 3 extending to the substrate 11 are removed (for example, by a grinding process) to expose the channel structure 3, and then the part of the memory function layer 31 extending to the first stop layer 12 is etched to expose the part of the channel layer 32 extending to the first stop layer 12, so that not only can the control of slotting on the channel hole 2 be reduced, the etching window of the channel structure 3 be increased, the difficulty of the manufacturing process and the manufacturing cost be reduced, but also the step of removing (for example, removing by a grinding process) the part of the substrate 11 and the part of the channel structure 3 extending to the substrate 11 can be used to replace the step of forming the first oxide layer in the related art to the step of etching the bottom polysilicon layer with the etched second oxide layer as a mask, And the step of exposing the channel structure shortens the process flow of preparing and forming the semiconductor device, improves the preparation efficiency and further reduces the preparation cost.

The substrate 11 may be a single-layer substrate or a composite substrate.

In some examples, as shown in fig. 3a-2, in the case that the substrate 11 is a single-layer substrate, for example, a CMP process or a Grinding process may be used to perform Grinding to remove the substrate 11 and the portion of the channel structure 3 extending to the substrate 11.

In other examples, as shown in fig. 3a-1, in the case where the substrate 11 is a composite substrate, the substrate 11 may include a base 111, a first sacrificial layer 112, and a second sacrificial layer 113, which are sequentially stacked. Wherein the first stop layer 12 is located on a side of the second sacrificial layer 113 away from the substrate 111.

For example, the material of the substrate 111 may be single crystal silicon (Si), single crystal germanium (Ge), silicon germanium (GeSi), silicon carbide (SiC), or the like; silicon-on-insulator (SOI), germanium-on-insulator (GOI), or the like; other materials, such as III-V compounds such as gallium arsenide, are also possible. The material of the first sacrificial layer 112 may be silicon oxide, and the material of the second sacrificial layer 113 may be polysilicon.

Based on this, as shown in fig. 7 to 9, removing the substrate 11 and the portion of the channel structure 3 extending to the substrate 11 to the first stop layer 12 by using a grinding process includes: removing the substrate 111 and the first sacrificial layer 112; a grinding process is used to remove the second sacrificial layer 113 and the portion of the channel structure 3 extending to the substrate 11.

For example, the substrate 111 may be removed by a marking process and a wet etching process, and the first sacrificial layer 112 may be removed by a CMP process and a dry etching process.

Illustratively, the second sacrificial layer 113 may be removed by polishing the second sacrificial layer 113 using a CMP process. The second sacrificial layer 113 may be used as a stop layer for removing the first sacrificial layer 112 by a CMP process, for example.

Of course, the substrate 111 may also be removed by Grinding using a Grinding process, and the first sacrificial layer 112 and the second sacrificial layer 113 may also be removed by Grinding using a CMP process. It is sufficient to ensure that the second sacrificial layer 113 is removed by a grinding process.

By providing a composite substrate, it is helpful to control the process uniformity during removal of the substrate 11.

In the case where the substrate 11 is a composite substrate, at least a portion of the channel structure 3 may extend to the second sacrificial layer 113, at least a portion of the channel structure 3 may extend to the first sacrificial layer 112, and at least a portion of the channel structure 3 may extend to the base 111. At this time, after the second sacrificial layer 113 is removed by polishing, the portion of each channel structure 3 extending to the substrate 11 is naturally removed by polishing.

It is to be understood that when the grinding process is used to remove the portion of the substrate 11 and the channel structure 3 extending to the substrate 11 to the first stop layer 12, that is, the present application may simultaneously remove the portion of the substrate 11 and the channel structure 3 extending to the substrate 11 to the first stop layer 12 by using a single semiconductor process. Therefore, the one-time semiconductor process can be used for replacing the steps from the step of forming the first oxide layer to the step of etching the bottom polycrystalline silicon layer by taking the etched second oxide layer as a mask and exposing the channel structure in the related technology, so that the preparation flow of the semiconductor device can be further simplified, the preparation efficiency can be improved, and the difficulty and the preparation cost of the preparation process can be further reduced.

In some embodiments, the channel layer 32 has a gap G therein. Since the present application does not limit the position where the different channel structures 3 extend to the substrate 11, after the substrate 11 is removed by grinding, the portions of the different channel structures 3 that are removed may be different, and the gap G of the channel layer 32 may be exposed (as shown in fig. 4a and 5 a) or may not be exposed (as shown in fig. 3G).

In some examples, as shown in fig. 3G, in S400 above, after removing the portion of the channel structure 3 extending to the substrate 11 to the first stop layer 12, the gap G of the channel layer 32 of the channel structure 3 is not exposed. Accordingly, S500 and S600 may be performed sequentially to fabricate the semiconductor device.

In other examples, as shown in fig. 4a, 5a and 6a, in S400, after removing the portion of the channel structure 3 extending to the substrate 11 to the first stop layer 12, the gap G of the channel layer 32 of at least one channel structure 3 is exposed.

Illustratively, as shown in fig. 2, before the above S500, that is, before etching the first stop layer 12 and the portion of the memory function layer 31 extending to the first stop layer 12 to the second stop layer 13, and exposing the portion of the channel layer 32 extending to the first stop layer 12, the preparation method further includes: s410 to S420.

S410, as shown in fig. 4b, 5b and 6b, a dielectric layer 5 is formed, and the dielectric layer 5 fills the gap G and covers the first stop layer 12.

For example, the dielectric layer 5 covers the end face of the channel structure 3 as well as the first stopper layer 12.

For example, the dielectric layer 5 may be formed by filling the gap G with the material of the dielectric layer 5 by a thin film deposition process such as chemical vapor deposition CVD, PVD, ALD, or any combination thereof. Alternatively, the material of the dielectric layer 5 may be silicon oxide.

For example, in the process of forming the dielectric layer 5, one or more voids may be formed inside the dielectric layer 5 by controlling the formation process of the dielectric layer 5 to relieve the structural stress.

S420, as shown in fig. 4c, 5c and 6c, the portion of the dielectric layer 5 covering the first stop layer 12 is removed, and the portion of the dielectric layer 5 filled in the gap G is remained.

For example, the portion of the dielectric layer 5 covering the first stop layer 12 may be removed by etching using a dry etching process.

Alternatively, a portion of the dielectric layer 5 filled in the gap G is referred to as a filled dielectric layer 5 a. The amount of the filling dielectric layer 5a remaining can be controlled by controlling the etching time or the kind of plasma in the etching gas. That is, the distance between the surface of the side of the filling dielectric layer 5a away from the stacked-layer structure 14 and the surface of the side of the channel layer 32 away from the stacked-layer structure 14 can be controlled.

It is understood that S420 may be performed simultaneously with S500. That is, in the same dry etching process step, not only the portion of the dielectric layer 5 covering the first stop layer 12, but also the portions of the first stop layer 12 and the memory function layer 31 extending to the first stop layer 12 may be removed. At this time, the second stop layer 13 may be used as a stop layer for etching the dielectric layer 5 by a dry etching process, so that the etching of the filling dielectric layer 5a is stopped at the second stop layer 13 (that is, the surface of the side of the filling dielectric layer 5a away from the stacked structure 14 is flush with the surface of the side of the second stop layer 13 away from the stacked structure 14).

By providing the filling medium layer 5a in the gap G of the channel layer 32, the material of the source layer 4 can be prevented from falling into the gap G in the subsequent process of forming the source layer 4 in S600, so that the performance of the prepared and formed semiconductor device 100 can be prevented from being affected.

In some embodiments, before S600, that is, before forming the source layer 4, the method for manufacturing a semiconductor device further includes: the exposed portion of the channel layer 32 is subjected to a doping process.

In some examples, the exposed portion of the channel layer 32 may be ion implanted using an ion implantation process to perform a doping process. The implanted dopant may be a P-type or N-type dopant.

Illustratively, after the exposed portion of the channel layer 32 is doped, an annealing process (e.g., a laser annealing process) may be used to anneal the exposed portion of the channel layer 32 to repair lattice damage to the material and activate the implanted dopants after the ion implantation process.

In some examples, the material of the second stop layer 13 and the material of the channel layer 32 are the same. In this case, in the process of subjecting the exposed portion of the channel layer 32 to the doping treatment, the second stop layer 13 is also subjected to the doping treatment.

Alternatively, the material of the second stop layer 13 and the material of the channel layer 32 may both be polysilicon.

For example, the exposed portion of the channel layer 32 and the second stop layer 13 may be simultaneously ion-implanted in the same ion implantation process to perform the doping process. Thereafter, the exposed portion of the channel layer 32 and the second stop layer 13 may be annealed in the same annealing process to repair the lattice damage of the material and activate the implanted dopants caused by the ion implantation process.

This is advantageous in simplifying the manufacturing process of the semiconductor device.

In some embodiments, before S400, that is, before removing the substrate 11 and the portion of the channel structure 3 extending to the substrate 11 to the first stop layer 12, the method for manufacturing a semiconductor device further includes: s310 to S320.

S310, as shown in fig. 3d, a gate line slit 6 is formed to penetrate the stacked structure 14 and extend to the substrate 11.

Illustratively, the gate line slit 6 may be formed by a dry etching process or a wet etching process. In the case where the substrate 11 is a composite substrate, the second sacrificial layer 113 may serve as an etching stop layer for controlling the groove change of the gate line gap 6. This can stop the etching of the gate line slit 6 by the second sacrificial layer 113, and prevent the gate line slit 6 from extending into the substrate 111.

It is understood that the number of the gate line slits 6 may be plural. Illustratively, the gate line slits 6 may extend along the direction X and be sequentially spaced along the direction Y. Each gate line slit 6 may divide the stacked structure 14 into a plurality of memory block regions, each having a plurality of channel structures 3.

Illustratively, the gate line slit 6 may serve as an etching path. At this time, the gate sacrificial layer 142 may be removed through the gate line slit 6. Here, the gate sacrificial layer 142 in the stacked-layer structure 14 may be removed through the gate line slit 6 to form a plurality of sacrificial gaps, for example, using a wet etching process.

For example, after forming the sacrificial gap, a thin film deposition process such as CVD, PVD, ALD, or any combination thereof may be used to form the gate layer 143 within the sacrificial gap. The material of the gate layer 143 may be at least one of tungsten, cobalt, copper, aluminum, doped crystalline silicon, and silicide.

Alternatively, a gate blocking layer may be formed on the inner walls of the gate line slit 6 and the sacrificial gap using a thin film deposition process before forming the gate electrode layer 143 in the sacrificial gap. The material of the gate blocking layer may include a material with a relatively high dielectric constant, such as aluminum oxide.

Further, a thin film deposition process may be used to form an adhesion layer on a surface of the gate barrier layer facing into the sacrificial gap. The material of the adhesion layer may include tantalum nitride or titanium nitride, for example.

By providing the adhesion layer, adhesion between the gate blocking layer and the gate layer 143 formed during a subsequent process may be increased.

Alternatively, after the gate blocking layer and the adhesion layer are formed, the adhesion layer and the portion of the gate layer 143 located in the gate line slit 6 may be removed, for example, by using a wet etching process.

S320, as shown in fig. 3e, a gate line isolation structure 7 is formed in the gate line gap 6.

For example, the first isolation layer 71, the second isolation layer 72, and the conductive layer 73 may be sequentially deposited in the gate line slit 6 by using a thin film deposition process such as CVD, PVD, ALD, or any combination thereof. Wherein the first isolation layer 71, the second isolation layer 72 and the conductive layer 73 may constitute the gate line isolation structure 7.

Alternatively, the material of the first isolation layer 71 may be silicon oxide, the material of the second isolation layer 72 may be silicon oxide, and the material of the conductive layer 73 may be doped polysilicon.

For example, in the process of forming the conductive layer 73, one or more voids may be formed inside the conductive layer 73 by controlling the formation process of the conductive layer 73 to relieve structural stress. The grid line isolation structure 7 can effectively adjust the warping deformation of the storage block area and provide good support for the storage block area.

Alternatively, the gate line isolation structure 7 may also be referred to as an array common source.

Based on this, in some examples, as shown in fig. 3g, 4a and 5a, in the above S400, in the process of removing the substrate 11 and the portion of the channel structure 3 extending to the substrate 11 to the first stop layer 12, the portion of the gate line isolation structure 7 extending to the substrate 11 is also removed.

That is, in the process of removing (e.g., grinding and removing) the substrate 11 and the portion of the channel structure 3 extending to the substrate 11 to the first stop layer 12, the portion of the gate line isolation structure 7 extending to the substrate 11 is also removed along with the removal of the substrate 11, and the end face of the conductive layer 73 is exposed. Wherein, a surface of the gate line isolation structure 7 away from the stacked structure 14 may be flush with a surface of the first stop layer 12.

Therefore, the control of slotting the grid line gap 6 can be reduced, the depth of the grid line gap 6 can be consistent or inconsistent, and the control can be extended to the substrate 11.

Therefore, the preparation method is beneficial to reducing the difficulty of the preparation process of the semiconductor device and reducing the preparation cost.

Note that, in the case where the gate line isolation structure 7 includes the first isolation layer 71 and the second isolation layer 72, and the material of the first isolation layer 71 and the second isolation layer 72 is silicon oxide, in the above S500, the portion of the first isolation layer 71 and the second isolation layer 72 extending to the first stop layer 12 may be etched to the second stop layer 13 at the same time, and the portion of the conductive layer 73 extending to the first stop layer 12 may be exposed.

In some examples, as shown in fig. 3i, 4d and 5d, in the above S600, the source layer 4 also forms an electrical contact with the exposed portion of the gate line isolation structure 7.

That is, the source layer 4 also covers the exposed portion of the gate line isolation structure 7, and contacts the exposed portion of the gate line isolation structure 7 to form an electrical connection. The source layer 4 surrounds the exposed part of the gate line isolation structure 7, so that a larger contact area is formed between the source layer 4 and the gate line isolation structure 7, and the reliability of contact connection is increased.

Here, the exposed portion of the gate line isolation structure 7 refers to, for example, an exposed portion of the conductive layer 73.

In some embodiments, as shown in fig. 3d and 3e, before the above S400, that is, before removing the substrate 11 and the portion of the channel structure 3 extending to the substrate 11 to the first stop layer 12, the method for manufacturing a semiconductor device further includes: a dummy channel structure 8 is formed through the stack structure 14 and extending to the substrate 11.

In some examples, the dummy channel hole may be formed using a dry etching process or a wet etching process, and then the dummy channel structure 8 may be formed within the dummy channel hole using a thin film deposition process such as CVD, PVD, ALD, or any combination thereof. Alternatively, the material of the dummy channel structure 8 may be silicon oxide.

Illustratively, the dummy channel structure 8 is used to provide a mechanical support function without forming the memory function layer 31 and the channel layer 32 having a memory function.

In some examples, in the above S400, in the process of removing the substrate 11 and the portion of the channel structure 3 extending to the substrate 11 to the first stop layer 12, the portion of the dummy channel structure 8 extending to the substrate 11 is also removed.

That is, in the process of removing (e.g., grinding away) the substrate 11 and the portion of the channel structure 3 extending to the substrate 11 to the first stop layer 12, the portion of the dummy channel structure 8 extending to the substrate 11 is also removed along with the removal of the substrate 11. Wherein, a side surface of the dummy channel structure 8 away from the stacked structure 14 may be flush with a side surface of the first stop layer 12 away from the stacked structure 14.

In some examples, in the step S500, during the etching of the first stop layer 12 and the portion of the memory function layer 31 extending to the first stop layer 12 to the second stop layer 13, and exposing the portion of the channel layer 32 extending to the first stop layer 12, the portion of the dummy channel structure 8 extending to the first stop layer 12 may be removed.

That is, a surface of the dummy channel structure 8 on a side away from the stacked structure 14 may be flush with a surface of the second stopper layer 13 on a side away from the stacked structure 14.

In some examples, as shown in fig. 3i, 4d and 5d, in the above S600, the source layer 4 also covers the exposed portion of the dummy channel structure 8.

Illustratively, the source layer 4 has a planar shape, and shields the exposed portion of the dummy channel structure 8 and makes contact with the exposed portion of the dummy channel structure 8.

In some embodiments, the method for manufacturing a semiconductor device provided by the present application further includes: the three-dimensional array structure 1 is bonded to the peripheral circuit structure 9. The bonding sequence of the three-dimensional array structure 1 and the peripheral circuit structure 9 is related to the structure of the semiconductor device, and may be specifically selected according to actual needs, which is not limited in this application.

In some examples, before S400, that is, before removing the substrate 11 and the portion of the channel structure 3 extending to the substrate 11 to the first stop layer 12, the method for manufacturing a semiconductor device further includes: s330 a-S340 a.

S330a, providing a peripheral circuit structure 9.

Illustratively, the peripheral circuit structure 9 may include a carrier substrate and peripheral devices disposed on the carrier substrate.

S340a, as shown in fig. 3f, bonding the peripheral circuit structure 9 and the three-dimensional array structure 1.

Illustratively, the three-dimensional array structure 1 herein may have a channel structure 3, a gate line isolation structure 7 and a dummy channel structure 8.

It is understood that before the peripheral circuit structure 9 and the three-dimensional array structure 1 are bonded, the three-dimensional array structure 1 may be turned upside down, and then the peripheral circuit structure 9 and the three-dimensional array structure 1 are bonded. In this embodiment, the bonding manner of the three-dimensional array structure 1 and the peripheral circuit structure 9 may be hybrid bonding.

Illustratively, the peripheral devices may be electrically connected to the gate layer 143 and the channel structure 3.

Wherein the peripheral devices are configured as control and three-dimensional array structures 1. The peripheral devices may include active (or passive) components such as page buffers, decoders (e.g., row and column decoders), sense amplifiers, drivers (e.g., word line drivers), or any other circuitry (e.g., transistors, diodes, resistors, capacitors, etc.).

For example, the peripheral devices may include a plurality of transistors, all or a portion of which are formed in the carrier substrate (e.g., below a top surface of the carrier substrate) and/or directly on the carrier substrate. Likewise, shallow trench isolation and doped regions (e.g., source and drain regions of a transistor) may also be formed in the carrier substrate.

It should be noted that the peripheral device may also include any other circuitry compatible with the high-level logic process. Illustratively, the peripheral devices include logic circuitry (e.g., processors and Programmable Logic Devices (PLDs)), and/or storage circuitry (e.g., Static Random Access Memory (SRAM)).

In other examples, after forming the source layer 4 on the side of the second stop layer 13 away from the stacked-layer structure 14, the source layer 4 forming an electrical contact with the exposed portion of the channel layer 32, the method for manufacturing a semiconductor device further includes: s330 b-S340 b.

S330b, providing a peripheral circuit structure 9.

Illustratively, the peripheral circuit structure 9 provided in this example may have the same structure as the peripheral circuit structure 9 provided in some of the above examples.

S340b, bonding the peripheral circuit structure 9 and the processed three-dimensional array structure as shown in fig. 5 e.

Illustratively, the processed three-dimensional array structure herein may refer to a three-dimensional array structure processed through the steps shown as S200 to S600. The semiconductor device formed in the present example is fabricated, for example, with an Xtacking architecture.

Some embodiments of the present application provide a semiconductor device 100. The semiconductor device 100 can be formed by, for example, the above-described method for manufacturing a semiconductor device. As shown in fig. 10 and 11, the semiconductor device 100 may include: a source layer 4, a second stop layer 13, a stacked structure 14a, and a plurality of channel structures 3.

In some examples, as shown in fig. 10 and 11, the second stop layer 13 is disposed on a side of the source layer 4, and the stacked-layer structure 14a is disposed on a side of the second stop layer 13 away from the source layer 4.

It is understood that the stacked structure 14a in this example is a structure obtained by gate replacement. That is, the stacked-layer structure 14a in this example may include a plurality of film layers stacked in sequence along the direction Z, including, for example, a plurality of gate dielectric layers 141 and a plurality of gate layers 143 that are alternately stacked. The gate layer 143 may serve as a word line 143 in the semiconductor device 100.

In some examples, as shown in fig. 10 and 11, the channel structure 3 described above includes a memory function layer 31 and a channel layer 32 that are sequentially disposed.

For the description of the materials of the memory function layer 31 and the channel layer 32, reference may be made to the description in some embodiments above, and further description is omitted here.

Illustratively, as shown in fig. 10 and 11, the channel structure 3 extends through the stacked structure 14a and extends to the source layer 4. The memory function layer 31 has an opening in a portion thereof adjacent to the source layer 4, and the channel layer 32 extends into the source layer 4 through the opening and is in electrical contact with the source layer 4.

Illustratively, the opening is located at the bottom of the storage function layer 31. With respect to the second stop layer 13, the surface of the memory function layer 31 on the side close to the source layer 4 is lower than the surface of the channel layer 32 on the side close to the source layer 4. That is, the channel layer 32 protrudes out of the memory function layer 31 through the opening and protrudes with respect to the memory function layer 31. The protruding portion of the channel layer 32 with respect to the memory function layer 31 is located in the source layer 4 and surrounded by the source layer 4.

The beneficial effects that can be achieved by the semiconductor device 100 provided in some embodiments of the present application are the same as those that can be achieved by the manufacturing method of the semiconductor device provided in some embodiments described above, and are not described herein again.

In some embodiments, as shown in fig. 11, the channel layer 32 has a gap G therein. Wherein the semiconductor device 100 further comprises: and a filling dielectric layer 5a disposed in the at least one gap G. The fill dielectric layer 5a contacts the source layer 4.

It is understood that by providing a gap G within the channel layer 32, structural stress may be mitigated.

Illustratively, the channel layer 32 of the at least one channel structure 3 is open at an end thereof adjacent to the source layer 4. The filling medium layer 5a may be disposed in the gap G of the channel layer 32 disposed in an open manner.

By providing the filling medium layer 5a in the gap G, the filling medium layer 5a can be used to block the source layer 4, so as to prevent the material of the source layer 4 from falling in the gap G and contacting with the top portion (i.e., the end of the channel layer 32 far away from the source layer 4) or the middle portion (i.e., the portion of the channel layer 32 corresponding to the gate layer 143) of the channel layer 32, thereby being beneficial to preventing the performance of the semiconductor device 100 from being affected.

In some examples, as shown in fig. 11, with respect to the second stop layer 13, a side surface of the filling dielectric layer 5a near the source layer 4 is lower than a side surface of the channel layer 32 extending into the source layer 4, and a portion of the filling dielectric layer 5a and the channel layer 32 extending into the source layer 4 forms a recess. Wherein the source layer 4 fills the recess.

Since no other film layer is disposed between the filling medium layer 5a and the source layer 4, in the case where the surface of the filling medium layer 5a on the side close to the source layer 4 is lower than the surface of the channel layer 32 on the side extending into the source layer 4 with respect to the second stop layer 13, a portion of the source layer 4 may be naturally filled in the recess formed by the filling medium layer 5a and the portion of the channel layer 32 extending into the source layer 4.

For the groove, the outer wall of the groove (i.e., the outer surface of the portion of the channel layer 32 extending out of the memory function layer 31) and the inner wall (i.e., the inner surface of the portion of the channel layer 32 not covered by the filling dielectric layer 5 a) are both exposed, and the source layer 4 may be in direct contact with the outer wall of the groove to form an electrical connection, or in direct contact with the inner wall of the groove to form an electrical connection. This can increase the contact area of the channel layer 32 and the source layer 4, which is advantageous for increasing the reliability of the contact connection and the performance of the semiconductor device 100.

In some examples, as shown in fig. 11, a side surface of the second stop layer 13 close to the source layer 4, a side surface of the memory function layer 31 close to the source layer 4, and a side surface of the filling medium layer 5a close to the source layer 4 are located on the same plane.

Therefore, the storage function layer 31 and the filling dielectric layer 5a can be etched simultaneously in the same etching process (for example, a dry etching process), so that the etching of the storage function layer 31 and the filling dielectric layer 5a is stopped at the second stop layer 13, and no other process condition (for example, the etching time is increased) needs to be added additionally. This is advantageous for reducing the difficulty of manufacturing and forming the semiconductor device 100 and improving the efficiency of manufacturing and forming the semiconductor device 100.

In some embodiments, as shown in fig. 10 and 11, the semiconductor device 100 further includes: the gate line isolation structure 7 penetrates the stacked structure 14a and the second stop layer 13. The gate line isolation structure 7 is in electrical contact with the source layer 4.

Illustratively, the source layer 4 covers the gate line isolation structure 7 and is in direct contact with the gate line isolation structure 7 to form an electrical connection.

In some examples, at least a portion of the gate line isolation structure 7 is located on a side surface close to the source layer 4, and the second stopper layer 13 is located on a side surface close to the source layer 4 and located on the same plane.

Illustratively, the gate line isolation structure 7 is entirely located near one side surface of the source layer 4, and the second stop layer 13 is located near one side surface of the source layer 4, and located on the same plane. That is, the gate line isolation structure 7 does not protrude beyond the second stop layer 13.

Illustratively, as shown in fig. 10 and 11, a portion of the gate line isolation structure 7 is located on a side surface close to the source layer 4, and the second stop layer 13 is located on a side surface close to the source layer 4 and located on the same plane. In the case where the gate line isolation structure 7 includes the first isolation layer 71, the second isolation layer 72, and the conductive layer 73, one side surfaces of the first isolation layer 71 and the second isolation layer 72 close to the source layer 4 may be located on the same plane as one side surface of the second stop layer 13 close to the source layer 4; the conductive layer 73 may extend beyond the second stop layer 13 and be located inside the source layer 4, surrounded by the source layer 4.

In some embodiments, as shown in fig. 10 and 11, the semiconductor device 100 further includes: a dummy channel structure 8 extending through the stacked structure 14a and the second stop layer 13. The dummy channel structure 8 is in contact with the source layer 4.

Illustratively, the source layer 4 covers the dummy channel structure 8 and is in direct contact with the dummy channel structure 8.

The number of the dummy channel structures 8 may be plural. The plurality of dummy channel structures 8 may provide support for the stack structure 14 a.

In some examples, as shown in fig. 10 and 10, a side surface of the dummy channel structure 8 close to the source layer 4 and a side surface of the second stopper layer 13 close to the source layer 4 are located on the same plane. That is, the dummy channel structure 8 does not protrude beyond the second stop layer 13.

In some embodiments, as shown in fig. 12, in the semiconductor device 100, the plurality of gate dielectric layers 141 (not shown) and the plurality of gate layers 143 in the stacked-layer structure 14a may extend along the direction X. In the direction Z, the lowermost gate layer 143 of the plurality of gate layers 143 is configured as a source side select gate SGS, the uppermost gate layer 143 of the plurality of gate layers 143 is configured as a drain side select gate SGD, and the intermediate gate layer 143 of the plurality of gate layers 143 is configured as a plurality of word lines WL (see WL1 to WL4 in fig. 13).

In some examples, as shown in fig. 12, the channel structure 3 connects word lines WL in series to form a memory cell string 200.

As shown in fig. 13, one memory cell string 200 corresponds to the storage capacity of a plurality of planar memory cells. Therefore, the semiconductor device 100 can provide a larger storage capacity.

The semiconductor device 100 includes an array of memory cell strings 200 in the X-Y plane.

In some examples, as shown in fig. 12, semiconductor device 100 also includes a drain select gate contact SGD CNT, a source select gate contact SGS CNT, a source contact SL CNT, a wordline contact WL CNT, and a bitline contact BL CNT. The drain terminal selection gate contact SGD CNT is electrically connected with the drain terminal selection gate SGD; the source end selection gate contact SGS CNT is electrically connected with the source end selection gate SGS; the source end contact SL CNT is electrically connected with a source end SL; each word line contact WL CNT is electrically connected to one word line WL, whereby the word line contacts WL CNT can be addressed separately in each memory cell string 200; each bitline contact BL CNT is electrically connected to the top of one memory cell string 200, whereby each memory cell string 200 can be individually addressed by the bitline contact BL CNT.

In some examples, as shown in fig. 12, the semiconductor device 100 further includes a bit line BL electrically connected to the memory cell string 200 through a bit line contact BL CNT.

In some embodiments, as shown in fig. 10 and 11, the semiconductor device 100 further includes: and a peripheral circuit structure 9 disposed on a side of the stacked structure 14a remote from the source layer 4 and electrically connected to the channel structure 3.

Here, the structure of the peripheral circuit structure 9 may be the same as the structure of the peripheral circuit structure 9 mentioned in some embodiments, and is not described herein again.

In some examples, in a case where the semiconductor device 100 further includes a word line, the above-described peripheral circuit structure 9 is also electrically connected to the word line.

Illustratively, the semiconductor device 100 may further include an interconnection layer, and the peripheral circuit structure 9 may be electrically connected to the channel structure 3 or the word line, etc. through the interconnection layer.

Some embodiments of the present application also provide a storage system 1000. As shown in fig. 14 and 15, the storage system 1000 includes: a controller 300, and a semiconductor device 100 as described in any of some of the embodiments above. The controller 300 may be coupled to the semiconductor device 100 and configured to control the semiconductor device 100 to store data.

Illustratively, the Storage system 1000 may be integrated into various types of Storage devices, for example, included in the same package (e.g., Universal Flash Storage (UFS) package or Embedded multimedia Card (eMMC) package). That is, the storage system 1000 may be applied to and packaged into different types of electronic products, such as mobile phones, computers (including but not limited to desktop computers, laptop computers, tablet computers, vehicle computers, and the like), televisions, set-top boxes, gaming consoles, printers, positioning devices, in-vehicle devices, wearable electronic devices, smart sensors, Virtual Reality (VR) devices, Augmented Reality (AR) devices, or any other suitable electronic device having storage therein.

Alternatively, as shown in fig. 14, the storage system 1000 may include: a controller 300 and a semiconductor device 100. The semiconductor device 100 may be integrated into a memory card.

The Memory Card includes any one of a PC Card (PCMCIA), a Compact Flash (CF) Card, a Smart Media (SM) Card, a Memory stick, a Multimedia Card (MMC), a Secure Digital Memory Card (SD), and a UFS.

Alternatively, as shown in fig. 15, the storage system 1000 may include: a controller 300 and a plurality of semiconductor devices 100. The storage system 1000 may be integrated into a Solid State Drive (SSD).

In storage system 1000, for example, controller 300 may be configured to operate in a low duty cycle environment, such as an SD card, CF card, Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, mobile phones, and the like.

As another example, the controller 300 is configured for operation in a high duty cycle environment SSD or eMMC for data storage and enterprise storage arrays of mobile devices such as smart phones, tablets, laptops, and the like.

In some embodiments, the controller 300 may be configured to manage data stored in the semiconductor device 100 and communicate with an external device (e.g., a host). In some embodiments, the controller 300 may also be configured to control operations of the semiconductor device 100, such as read, erase, and program operations. In some embodiments, the controller 300 may be further configured to manage various functions with respect to data stored or to be stored in the semiconductor device 100, including at least one of bad block management, garbage collection, logical to physical address translation, wear leveling. In some embodiments, the controller 300 is further configured to process an error correction code with respect to data read from the semiconductor device 100 or written to the semiconductor device 100.

Of course, the controller 300 may also perform any other suitable function, such as formatting the semiconductor device 100. For example, the controller 300 may communicate with an external device (e.g., a host) through at least one of various interface protocols.

It should be noted that the interface protocol includes at least one of a USB protocol, an MMC protocol, a Peripheral Component Interconnect (PCI) protocol, a PCI express (PCI-E) protocol, an Advanced Technology Attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a Small Computer System Interface (SCSI) protocol, an Enhanced Small Disk Interface (ESDI) protocol, an Integrated Drive Electronics (IDE) protocol, and a Firewire protocol.

The semiconductor device 100 included in the memory system 1000 provided in some embodiments of the present application has the same structure and beneficial effects as the semiconductor device 100 provided in some embodiments described above, and details are not repeated here.

As used herein, whether a component (e.g., a layer, structure, or device) is "on," "over," or "under" another component (e.g., a layer, structure, or device) of a semiconductor device (e.g., a three-dimensional memory) is determined in a third direction Z relative to a substrate of the semiconductor device when the substrate is located in a lowest plane of the semiconductor device in the third direction Z. Throughout this application, the same concepts are applied to describe spatial relationships.

The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present application should be covered within the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims (18)

1. A method of manufacturing a semiconductor device, the method comprising:

providing a three-dimensional array structure; the three-dimensional array structure comprises a substrate, a first stop layer, a second stop layer and a laminated structure, wherein the first stop layer, the second stop layer and the laminated structure are sequentially arranged on one side of the substrate in a laminated mode;

forming a plurality of channel holes extending through the stacked structure and to the substrate;

sequentially forming a storage function layer and a channel layer in the channel holes to form a plurality of channel structures;

removing the substrate and the part of the channel structure extending to the substrate to the first stop layer;

etching the first stop layer and the part of the memory function layer extending to the first stop layer to the second stop layer, and exposing the part of the channel layer extending to the first stop layer;

forming a source layer on a side of the second stop layer remote from the stacked layer structure, the source layer forming an electrical contact with the exposed portion of the channel layer.

2. The method of claim 1, wherein the removing the substrate and the portion of the channel structure extending to the substrate to the first stop layer comprises:

and removing the substrate and the part of the channel structure extending to the substrate to the first stop layer by adopting a grinding process.

3. The production method according to claim 2, wherein the substrate includes a base, a first sacrificial layer, and a second sacrificial layer, which are stacked in this order;

the removing the substrate and the part of the channel structure extending to the substrate to the first stop layer by using a grinding process comprises:

removing the substrate and the first sacrificial layer;

and removing the second sacrificial layer and the part of the channel structure extending to the substrate by adopting a grinding process.

4. The manufacturing method according to claim 1, wherein the channel layer has a gap therein;

after removing a portion of the channel structure extending to the substrate to the first stop layer, a gap of a channel layer of at least one of the channel structures is exposed;

before the etching the first stop layer and the portion of the memory function layer extending to the first stop layer to the second stop layer and exposing the portion of the channel layer extending to the first stop layer, the method further includes:

forming a dielectric layer, wherein the dielectric layer fills the gap and covers the first stop layer;

and removing the part of the dielectric layer covering the first stop layer, and reserving the part of the dielectric layer filled in the gap.

5. The method of claim 1, further comprising, prior to forming the source layer:

and carrying out doping treatment on the exposed part of the channel layer.

6. The manufacturing method according to claim 5, wherein a material of the second stop layer and a material of the channel layer are the same;

in the process of doping the exposed portion of the channel layer, the second stop layer is also doped.

7. The method according to any one of claims 1 to 6, wherein before the removing the substrate and the portion of the channel structure extending to the substrate to the first stop layer, the method further comprises:

forming a gate line slit penetrating the stacked structure and extending to the substrate;

forming a grid line isolation structure in the grid line gap;

in the process of removing the substrate and the part of the channel structure extending to the substrate to the first stop layer, the part of the grid line isolation structure extending to the substrate is also removed;

the source layer also forms an electrical contact with the exposed portion of the gate line isolation structure.

8. The method according to any one of claims 1 to 6, wherein before the removing the substrate and the portion of the channel structure extending to the substrate to the first stop layer, the method further comprises:

forming a dummy channel structure penetrating through the stacked structure and extending to the substrate;

in the process of removing the substrate and the part of the channel structure extending to the substrate to the first stop layer, the part of the dummy channel structure extending to the substrate is also removed;

the source layer also covers exposed portions of the dummy channel structure.

9. The method according to any one of claims 1 to 6, wherein before the removing the substrate and the portion of the channel structure extending to the substrate to the first stop layer, the method further comprises:

providing a peripheral circuit structure;

and bonding the peripheral circuit structure and the three-dimensional array structure.

10. The method of any one of claims 1-6, wherein after forming a source layer on a side of the second stop layer away from the stacked structure, the source layer in electrical contact with an exposed portion of the channel layer, the method further comprises:

providing a peripheral circuit structure;

and bonding the peripheral circuit structure and the processed three-dimensional array structure.

11. A semiconductor device, characterized in that the semiconductor device comprises:

a source layer;

a second stop layer disposed on a side of the source layer;

a stack structure disposed on a side of the second stop layer away from the source layer; and the number of the first and second groups,

a plurality of channel structures extending through the stack structure and to the source layer;

the channel structure comprises a memory function layer and a channel layer which are sequentially arranged, wherein an opening is formed in the part, close to the source layer, of the memory function layer, and the channel layer extends into the source layer through the opening and is in electric contact with the source layer.

12. The semiconductor device according to claim 11, wherein the channel layer has a gap therein;

the semiconductor device further includes: a filling dielectric layer arranged in at least one of the gaps; the fill dielectric layer is in contact with the source layer.

13. The semiconductor device according to claim 12, wherein a side surface of the filling dielectric layer adjacent to the source layer is lower than a side surface of the channel layer extending into the source layer with respect to the second stop layer, and portions of the filling dielectric layer and the channel layer extending into the source layer form a recess; the source layer fills the recess.

14. The semiconductor device of claim 12, wherein a side surface of the second stop layer adjacent to the source layer, a side surface of the storage function layer adjacent to the source layer, and a side surface of the filling dielectric layer adjacent to the source layer are coplanar.

15. The semiconductor device according to claim 11, further comprising: a gate line isolation structure penetrating the stacked structure and the second stop layer;

the grid line isolation structure is electrically contacted with the source electrode layer;

at least one part of the grid line isolation structure is close to one side surface of the source layer, and the second stop layer is close to one side surface of the source layer and is positioned on the same plane.

16. The semiconductor device according to claim 11, further comprising: a dummy channel structure penetrating the stack structure and the second stop layer;

the dummy channel structure is in contact with the source layer;

the dummy channel structure is located on a side surface of the source layer, and the second stop layer is located on a side surface of the source layer.

17. The semiconductor device according to claim 11, further comprising:

and the peripheral circuit structure is arranged on one side of the laminated structure far away from the source layer and is electrically connected with the channel structure.

18. A storage system, comprising: a controller, and the semiconductor device according to any one of claims 11 to 17;

wherein the controller is coupled to the semiconductor device and is used for controlling the semiconductor device to store data.

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