CN114551458A

CN114551458A - Semiconductor structure, preparation method thereof, three-dimensional memory and storage system

Info

Publication number: CN114551458A
Application number: CN202210143436.0A
Authority: CN
Inventors: 黎姗; 杜小龙; 袁伟; 刘小欣; 夏志良
Original assignee: Yangtze Memory Technologies Co Ltd
Current assignee: Yangtze Memory Technologies Co Ltd
Priority date: 2022-02-16
Filing date: 2022-02-16
Publication date: 2022-05-27

Abstract

The disclosure provides a semiconductor structure and a preparation method thereof, a three-dimensional memory and a storage system, relates to the technical field of semiconductor chips, and aims to improve the stability of the three-dimensional memory. The preparation method comprises the following steps: forming an initial laminated structure on one side of the substrate, wherein the initial laminated structure comprises a gate replacement layer and an initial gate dielectric layer which are alternately laminated; forming a channel hole, wherein the channel hole penetrates through the initial laminated structure; forming an initial channel structure in the channel hole, wherein the initial channel structure comprises an initial charge storage layer; forming grid isolation grooves, wherein the grid isolation grooves at least penetrate through the initial laminated structure; removing the initial gate dielectric layer through the gate isolation groove to form a first gap; a target portion of the initial charge storage layer is modified through the first slit to be converted into a partition portion, wherein the partition portion partitions the initial charge storage layer into a plurality of charge storage portions. The prepared semiconductor structure is used for realizing data reading and writing operations.

Description

Semiconductor structure, preparation method thereof, three-dimensional memory and storage system

Technical Field

The present disclosure relates to the field of semiconductor chip technologies, and in particular, to a semiconductor structure, a method for manufacturing the same, a three-dimensional memory, and a storage system.

Background

As the feature size of memory cells approaches the lower process limit, planar processes and manufacturing techniques become challenging and costly, which causes the storage density of 2D or planar NAND flash memories to approach the upper limit.

To overcome the limitations imposed by 2D or planar NAND flash memories, memories having a three-dimensional structure (3D NAND) have been developed to increase the storage density by arranging memory cells three-dimensionally over a substrate.

With the increasing number of stacked layers of the memory cells in the three-dimensional memory and the decreasing distance between the memory cells, the stability of the three-dimensional memory is reduced by the conventional preparation method of the three-dimensional memory.

Disclosure of Invention

The embodiment of the disclosure provides a semiconductor structure, a preparation method thereof, a three-dimensional memory and a storage system, and aims to improve the stability of the three-dimensional memory.

In order to achieve the purpose, the embodiment of the disclosure adopts the following technical scheme:

in one aspect, a method of fabricating a semiconductor structure is provided. The preparation method of the semiconductor structure comprises the following steps: forming an initial laminated structure on one side of a substrate, wherein the initial laminated structure comprises a gate replacement layer and an initial gate dielectric layer which are alternately laminated; forming a channel hole, wherein the channel hole penetrates through the initial laminated structure; forming an initial channel structure within the channel hole, the initial channel structure including an initial charge storage layer; forming gate isolation grooves, wherein the gate isolation grooves at least penetrate through the initial laminated structure; removing the initial gate dielectric layer through the gate isolation groove to form a first gap; modifying a target portion of the initial charge storage layer through the first slit to convert the target portion into a partition portion, wherein the partition portion partitions the initial charge storage layer into a plurality of charge storage portions.

According to the manufacturing method of the semiconductor structure provided by the above embodiment of the disclosure, the target portion in the initial charge storage layer can be modified through the first gap to form the isolation portion, and the two adjacent charge storage portions are electrically insulated by the isolation portion, so that charge migration between the two adjacent charge storage portions is avoided, and thus, the stability of the three-dimensional memory is improved. In addition, one end, close to the channel hole, of the gate replacement layer does not need to be etched, the channel hole cannot be reamed, and the initial channel structure is arranged in the channel hole, so that the storage density of the three-dimensional memory is improved.

In some embodiments, before the step of forming the initial channel structure in the channel hole, the method further includes: removing part of the initial gate dielectric layer through the channel hole to form a first recess; and forming a blocking part in the first recess, wherein the blocking part and the initial gate dielectric layer have different etching rates under the same process condition.

The step of removing the initial gate dielectric layer through the gate isolation groove to form a first gap includes: and sequentially removing the initial gate dielectric layer and the blocking part through the gate isolation groove to form the first gap.

In some embodiments, the initial laminate structure further comprises: barrier layers arranged on two sides of the initial gate dielectric layer along the direction vertical to the substrate; the barrier layer and the initial gate dielectric layer have different etching rates under the same process condition, and the barrier layer and the barrier part have different etching rates under the same process condition; the preparation method further comprises the following steps: and modifying the target part of the initial charge storage layer through the first gap, and simultaneously modifying the barrier layer to convert the barrier layer into an insulating medium layer.

In some embodiments, the step of modifying the barrier layer comprises: and modifying the barrier layer by adopting an oxidation process.

In some embodiments, after the step of performing the insulation modification treatment on the target portion of the initial charge storage layer through the first slit, the method further includes: and filling a dielectric material in the first gap.

In some embodiments, after the first gap is filled with the dielectric material, an air gap is formed in the first gap.

In some embodiments, the initial channel structure further comprises: a barrier film disposed between a sidewall of the channel hole and the initial charge storage layer; before the step of performing modification treatment on the target portion of the initial charge storage layer through the first slit to convert the target portion into a spacer, the manufacturing method further includes: and removing the part of the blocking film exposed to the first gap through the first gap, so that the first gap extends to the surface of the initial charge storage layer, the first gap divides the blocking film into a plurality of blocking parts, and the plurality of blocking parts form a blocking layer.

In some embodiments, the barrier film and the barrier have different etch rates under the same process conditions.

In some embodiments, the modifying the target portion of the initial charge storage layer through the first slit to convert the target portion into a spacer includes: and oxidizing the target part of the initial charge storage layer through the first gap by adopting an oxidation process so as to convert the target part into the isolation part.

In some embodiments, before the step of sequentially removing the initial gate dielectric layer and the blocking portion via the gate isolation trench to form the first gap, the preparation method further includes: removing the gate replacement layer through the gate isolation groove to form a second gap; and sequentially forming a protective layer and a grid line layer in the second gap.

In some embodiments, the material of the barrier portion is the same as the material of the gate replacement layer.

In some embodiments, the material of the barrier comprises a nitride; the material of the initial gate dielectric layer comprises an oxide; the material of the barrier layer comprises silicon carbide nitride or polysilicon.

In another aspect, a semiconductor structure is provided, which is manufactured by the method for manufacturing a semiconductor structure according to any one of the above items.

In yet another aspect, a semiconductor structure is provided, the semiconductor structure comprising: the memory structure comprises a substrate, a memory laminated structure and a channel structure, wherein the memory laminated structure is arranged on one side of the substrate and comprises a gate line layer and a gate dielectric layer which are alternately superposed; the channel structure penetrates through the storage laminated structure and comprises a blocking layer and a charge storage layer, wherein the charge storage layer comprises charge storage parts and isolating parts which are alternately arranged along the height direction of the channel structure; the blocking layer comprises a plurality of sections of blocking parts, and one section of blocking part is positioned between one grid line layer and one charge storage part.

In some embodiments, the gate dielectric layer comprises two insulating dielectric layers, and a dielectric material disposed between the two insulating dielectric layers.

In some embodiments, an air gap is further arranged between two insulating dielectric layers in the gate dielectric layer.

In some embodiments, a projection of one of the spacers in a direction perpendicular to a height direction of the channel structure covers at least one layer of the dielectric material in the gate dielectric layer.

In some embodiments, a dielectric material is filled between two adjacent barrier parts; and/or an air gap is arranged between two adjacent blocking parts.

In some embodiments, the barrier portion is in contact with the isolation portion and the insulating dielectric layer along two sides parallel to the substrate direction, respectively.

In yet another aspect, a three-dimensional memory is provided. The three-dimensional memory includes a semiconductor structure as described in some embodiments above, and a peripheral device electrically connected to the semiconductor structure.

In yet another aspect, a storage system is provided, including: the memory device comprises a three-dimensional memory as described above, and a controller coupled to the three-dimensional memory to control the three-dimensional memory to store data.

It can be understood that, for the manufacturing method of the semiconductor structure, the three-dimensional memory, and the memory system provided in the above embodiments of the disclosure, reference may be made to the above advantageous effects of the semiconductor structure, and details are not described herein again.

Drawings

In order to more clearly illustrate the technical solutions in the present disclosure, the drawings needed to be used in some embodiments of the present disclosure will be briefly described below, and it is apparent that the drawings in the following description are only drawings of some embodiments of the present disclosure, and other drawings can be obtained by those skilled in the art according to the drawings. Furthermore, the drawings in the following description may be regarded as schematic diagrams, and do not limit the actual size of products, the actual flow of methods, the actual timing of signals, and the like, involved in the embodiments of the present disclosure.

FIG. 1A is a flow chart of a method of fabricating a semiconductor structure according to some embodiments;

FIG. 1B is a flow chart of a method of fabricating a semiconductor structure according to other embodiments;

FIG. 1C is a block diagram of a semiconductor structure according to some embodiments;

FIG. 1D is a cross-sectional view of semiconductor structures according to other embodiments;

FIGS. 2A-2M are diagrams illustrating steps in a method of fabricating a semiconductor structure according to some embodiments;

FIG. 3A is a cross-sectional view of a semiconductor structure according to yet further embodiments;

FIGS. 3B and 3C are diagrams of steps in methods of fabricating semiconductor structures according to further embodiments;

FIGS. 4A-4D are diagrams illustrating steps in a method of fabricating a semiconductor structure according to yet further embodiments;

FIGS. 5A-5M are diagrams illustrating steps in a method of fabricating a semiconductor structure according to still further embodiments;

FIGS. 6A-6D are diagrams illustrating steps in methods of fabricating semiconductor structures according to further embodiments;

FIG. 7A is a schematic perspective view of a three-dimensional memory according to some embodiments;

FIG. 7B is a cross-sectional view of a three-dimensional memory according to some embodiments;

FIG. 7C is a cross-sectional view of a memory cell string along section line AA' in the three-dimensional memory of FIG. 7A;

FIG. 7D is an equivalent circuit diagram of a memory cell string;

FIG. 8A is a block diagram of a storage system according to some embodiments;

FIG. 8B is a block diagram of memory systems according to further embodiments.

Detailed Description

Technical solutions in some embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings, and it is obvious that the described embodiments are only a part of the embodiments of the present disclosure, and not all of the embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments provided by the present disclosure belong to the protection scope of the present disclosure.

Throughout the specification and claims, the term "comprising" is to be interpreted in an open, inclusive sense, i.e., as "including, but not limited to," unless the context requires otherwise. In the description herein, the terms "some embodiments," "exemplary," and the like are intended to indicate that a particular feature, structure, material, or characteristic described in connection with the embodiments or examples is included in at least one embodiment or example of the disclosure. The schematic representations of the above terms are not necessarily referring to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be included in any suitable manner in any one or more embodiments or examples.

In the following, the terms "first", "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the embodiments of the present disclosure, "a plurality" means two or more unless otherwise specified.

In describing some embodiments, expressions of "coupled" and "connected," along with their derivatives, may be used. For example, the term "connected" may be used in describing some embodiments to indicate that two or more elements are in direct physical or electrical contact with each other. As another example, some embodiments may be described using the term "coupled" to indicate that two or more elements are in direct physical or electrical contact. The term "coupled," however, may also mean that two or more elements are not in direct contact with each other, but yet still co-operate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents herein.

"A and/or B" includes the following three combinations: a alone, B alone, and a combination of A and B.

The use of "configured to" herein means open and inclusive language that does not exclude devices that are suitable or configured to perform additional tasks or steps.

Example embodiments are described herein with reference to cross-sectional and/or plan views as idealized example figures. In the drawings, the thickness of layers and regions are exaggerated for clarity. Variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, the exemplary embodiments should not be construed as limited to the shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the exemplary embodiments.

As used herein, the term "substrate" refers to a material onto which subsequent layers of material may be added. The substrate itself may be patterned. The material added on the substrate may be patterned or may remain unpatterned. In addition, the substrate may include a variety of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, and the like. Alternatively, the substrate may be made of a non-conductive material such as glass, plastic, or sapphire wafer.

The term "three-dimensional memory" refers to a semiconductor device formed of strings of memory cell transistors (referred to herein as "strings of memory cells," e.g., NAND memory cells) arranged in an array on a major surface of a substrate or a source layer and extending in a direction perpendicular to the substrate or source layer. As used herein, the term "vertically" means nominally perpendicular to a major surface (i.e., a lateral surface) of the substrate or source layer.

Some embodiments of the present disclosure provide a method for fabricating a semiconductor structure, which includes steps S1 to S7, referring to fig. 1A.

S1, forming an initial stacked structure 10 on one side of the substrate 1, wherein the initial stacked structure 10 comprises a gate replacement layer 11 and an initial gate dielectric layer 12 which are alternately stacked.

Referring to fig. 2A and 5A, in step S1, gate replacement layers 11 and initial gate dielectric layers 12, which are alternately stacked, may be formed on a substrate 1 through a thin film deposition process.

"alternately stacked" means that, referring to fig. 5A, after forming an initial gate dielectric layer 12 on a substrate 1, a gate replacement layer 11 is formed on the initial gate dielectric layer 12, then an initial gate dielectric layer 12 is formed on the gate replacement layer 11, and so on … …. In one possible implementation, referring to fig. 2A, the initial laminated structure 10 further includes: and the barrier layers 13 are arranged on two sides of the initial gate dielectric layer 12 along the direction vertical to the substrate 1, when the initial laminated structure 10 is formed, the barrier layer 13, the initial gate dielectric layer 12, the barrier layer 13 and the gate replacement layer 11 are sequentially formed on the substrate 1, and then the steps are repeated.

Illustratively, the thin film Deposition process is, for example, one or more of Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), or Atomic Layer Deposition (ALD) and electroplating. Wherein the gate replacement layer 11 may be replaced with the gate line layer 110 in a subsequent process. In some examples, the gate replacement layer 11 may be formed of nitride, and illustratively, the gate replacement layer 11 may be formed of silicon nitride, and further, the gate replacement layer 11 may be formed of polysilicon.

In some examples, the material of the initial gate dielectric layer 12 includes an oxide, and the material of the initial gate dielectric layer 12 may include silicon oxide, and further, the material of the initial gate dielectric layer 12 may be silicon oxycarbide.

In some examples, the substrate 1 may be a single-layer substrate, and the substrate may be made of a semiconductor material, for example, a compound semiconductor such as silicon (Si), germanium (Ge), SiGe, an alloy semiconductor, or the like. In other examples, a single layer substrate may also be made of a non-conductive material such as glass, plastic, or sapphire wafers. Furthermore, in some other examples, the substrate may also be a composite substrate, specifically, the composite substrate includes a base layer, a sacrificial layer, and a stop layer, and the initial stacked structure 10 may be formed on a side of the stop layer away from the sacrificial layer. Wherein the base layer may comprise amorphous silicon, polycrystalline silicon, single crystal germanium, group III-V compound semiconductor materials, group II-VI compound semiconductor materials, and other suitable semiconductor materials; the base layer may also be made of a non-conductive material such as glass, plastic, or sapphire wafers. The material of the sacrificial layer may be silicon oxide, silicon nitride, or the like. The material of the stop layer may be a semiconductor material, such as amorphous silicon, polycrystalline silicon, or a combination of one or more of single crystal silicon.

S2, forming a Channel Hole (CH) 14, wherein the Channel Hole 14 penetrates the initial stacked structure 10.

Referring to fig. 2B and 5B, in step S2, a channel hole 14 may be formed on the initial stacked structure 10 through a dry etching process or a wet etching process, and the channel hole 14 may penetrate the initial stacked structure 10 in the first direction Z, and the number of the channel holes 14 is plural. In some embodiments, the channel hole 14 may extend into the substrate 1.

S3, forming an initial channel structure 20 within the channel hole 14, the initial channel structure 20 including an initial charge storage layer 21.

Referring to fig. 2E and 5E, the initial channel structure 20 includes a blocking thin film 22, an initial charge storage layer 21, a tunneling layer 23, and a channel layer 24, which are sequentially disposed in the channel hole 14. Wherein the channel layer 24 may enclose a chamber, which may be filled with an oxide to form the support 25, the support 25 may provide support to the initial channel structure 20. The barrier film 22 may be formed of an oxide, and the oxide may be silicon dioxide, for example. While the initial charge storage layer 21 may be formed of nitride, which may be, for example, silicon nitride. The tunneling layer 23 may be formed of an oxide, which may be, for example, silicon dioxide.

S4, forming gate spacer GLS, which penetrate at least the initial stacked structure 10.

Referring to fig. 1C, the gate spacer GLS extends along the second direction X, and in some examples, the gate spacer GLS may divide the semiconductor structure into a plurality of memory blocks BB, and the plurality of initial channel structures 20 may be arranged in an array within the memory blocks BB. Referring to fig. 1D, gate spacers GLS can penetrate the initial stacked structure 10 in a first direction Z. Illustratively, the gate spacer GLS may extend into the substrate 1.

In step S4, the gate spacer GLS may be formed by an etching process. In a subsequent process, the gate replacement layer 11 may be replaced with a gate line layer 110 by a gate spacer GLS, and the gate spacer GLS may separate the gate line layer 110 into a plurality of gate lines G.

S5, the initial gate dielectric layer 12 is removed through the gate spacer GLS to form the first slit 17.

Wherein, an etching process may be used to remove the initial gate dielectric layer 12. After removing the initial gate dielectric layer 12, referring to fig. 2J and 5J, the first slit 17 is formed, and the blocking film 22 in the initial channel structure 20 may be exposed to the first slit 17.

S6, the target portion 211 of the initial charge storage layer 21 is modified through the first slit 17 so that the target portion 211 is converted into a partition 212, wherein the partition 212 partitions the initial charge storage layer 21 into a plurality of charge storage portions 213.

Herein, "modifying" refers to changing the original properties of the material. For example, the modification reduces the conductivity of target portion 211, thereby completely insulating target portion 211.

In step S6, the target portion 211 may be converted into the isolation portion 212 after being modified. Referring to fig. 2K and 5K, the isolation portion 212 separates the initial charge storage layer 21 into a plurality of charge storage portions 213, wherein the electrical conductivity of the isolation portion 212 is lower than that of the charge storage portions 213. Referring to fig. 2K and 5K, in one initial channel structure 20, the number of the isolation portions 212 may be plural, and at this time, the plural isolation portions 212 partition the initial charge storage layer 21 into the plural charge storage portions 213, and the isolation portions 212 and the charge storage portions 213 are alternately arranged in the first direction Z.

One spacer 212 projects in a direction perpendicular to the height direction of the initial channel structure 20 at least over a portion of the first slit 17, one target portion 211 corresponding to one first slit 17. For convenience of description, a direction perpendicular to the height direction of the initial trench structure 20 may be defined as a projection direction. Here, a direction perpendicular to the height direction of the initial channel structure 20 is a direction perpendicular to the depth direction of the channel hole 14, and the depth direction of the channel hole 14 is a first direction Z, so that the projection direction is perpendicular to the first direction Z, see fig. 2J and 5J, and the direction indicated by an arrow a is the projection direction.

The projection of one charge storage section 213 in the projection direction a covers at least a part of the region where one gate replacement layer 11 is located. It should be noted that, the gate replacement layer 11 may be replaced with the gate line layer 110 in the subsequent process, so that the area where the gate replacement layer 11 is located is the area where the gate line layer 110 is located, the plurality of charge storage portions 213 may correspond to the plurality of gate line layers 110 one by one, and one charge storage portion 213 corresponds to one gate line layer 110. In some examples, the projection of one charge storage part 213 in the projection direction a may cover only a portion of the area where one gate replacement layer 11 is located, i.e., the projection of one charge storage part 213 in the projection direction a does not completely cover the area where one gate replacement layer 11 is located. In other examples, the projection of one charge storage 213 in the projection direction may cover the whole of the region where the gate replacement layer 11 is located.

In step S6, the target portion 211 is converted into the isolation portion 212, and further the initial charge storage layer 21 is converted into the charge storage layer 210, and the initial channel structure 20 is converted into the channel structure 200.

In some examples, the gate line layer 110 is separated into a plurality of gate lines G by the gate separating grooves GLS, and the channel structure 200 and one gate line G surrounding the channel structure 200 may form a memory cell, where it is noted that one charge storage part 213 is included in one memory cell. The charge storage 213 in the memory cell is used to store electrons such that the memory cell has a corresponding threshold voltage.

In one implementation, in order to provide more layers in the semiconductor structure 300, the thickness of each layer in the semiconductor structure 300 may be reduced, for example, the thickness of the initial gate dielectric layer 12 and the gate replacement layer 11 is reduced when the semiconductor structure is fabricated. While the gate replacement layer 11 may be replaced with the gate line layer 110 in a subsequent process, at this time, referring to fig. 3A, one gate line G and a part of the channel structure surrounded by the one gate line G may form a memory cell 610, wherein it can be understood that a projection of the part of the channel structure surrounded by the one gate line G along the projection direction a may cover the one gate line G. A portion of one memory cell 610 including the charge storage layer 210, and a portion of the charge storage layer 210 located in the memory cell 610 is the charge storage portion 213. The distance between two adjacent memory cells 610 in the same memory cell string 600 is reduced due to the reduced thickness of the film layer. It should be noted that the charge storage layer 210 is the initial charge storage layer 21 provided in some embodiments. Referring to fig. 3A, the charge storage layer 210 corresponding to the initial gate dielectric layer 12 is made of the same material as the charge storage portion 213, and the charge storage layer 210 corresponding to the initial gate dielectric layer 12 is not modified, so that coupling can occur between the charge storage portions 213 in two adjacent memory cells 610, and charge transfer can occur severely between the charge storage portions 213 in two adjacent memory cells 610, so that the threshold voltage corresponding to the memory cell 610 is changed, and the stability of the three-dimensional memory 400 is reduced.

In some embodiments of the present disclosure, in step S6, the target portion 211 is converted into the isolation portion 212 by modifying the target portion 211, and the isolation portion 212 can isolate two adjacent charge storage portions 213, so that the two adjacent charge storage portions 213 are electrically insulated, thereby preventing charge migration between the charge storage portions 213 in the two adjacent memory cells and improving the stability of the three-dimensional memory 400. In another implementation, referring to fig. 3B, the initial stacked structure 10 includes an initial gate dielectric layer 12 and a gate replacement layer 11 that are alternately stacked, and after the channel hole 14 is formed in the initial stacked structure 10, a portion of the gate replacement layer 11 adjacent to the channel hole 14 is removed to form the second recess 19. Then, referring to fig. 3C, an initial channel structure 20 is formed in the channel hole 14, wherein the initial channel structure 20 includes a blocking thin film 22, a charge storage layer 210, a tunneling layer 23, a channel layer 24, and a support 25, which are sequentially disposed in the channel hole 14, wherein it should be noted that the blocking thin film 22, the charge storage layer 210, and the tunneling layer 23 are formed in the second recess 19, and the channel layer 24 and the support 25 are formed in the channel hole 14. Wherein the charge storage layer 210 is separated into a plurality of charge storage portions 213 by the initial gate dielectric layer 12. In this implementation, the gate replacement layer 11 is etched, and the charge storage part 213 is formed in the second recess 19 formed after etching the portion of the gate replacement layer 11, so that an area covered by an orthographic projection of one channel structure 200 on the substrate 1 is larger than an area covered by an orthographic projection of one channel hole 14 on the substrate 1, thereby causing a hole expansion of the channel hole 14. The larger the area of the orthographic projection of the channel structure 200 on the substrate 1, the smaller the number of channel structures 200 provided in a unit area, thereby resulting in a reduction in the storage density of the three-dimensional memory 400.

Referring to fig. 2L and 5L, in some embodiments of the disclosure, the blocking thin film 22, the charge storage layer 210, the tunneling layer 23, and the channel layer 24 in the initial channel structure 20 are all formed in the channel hole 14, and it is not necessary to etch the gate replacement layer 11, and to dispose a portion of the channel structure 200 in the second recess 19, and then the channel structure 200 is not disposed outside the channel hole 14, and therefore, some embodiments provided by the disclosure may not cause the channel hole 14 to be reamed, and then increase the number of the channel structures 200 in a unit area, which may improve the storage density of the three-dimensional memory 400. In addition, the present disclosure may modify the target portion 211 in the initial charge storage layer 21 through the first slit 17, so as to form the isolation portion 212, and electrically insulate the two adjacent charge storage portions 213 through the isolation portion 212, thereby avoiding charge migration between the two adjacent charge storage portions 213, and improving stability of the three-dimensional memory 400.

In summary, the method for manufacturing the semiconductor structure according to some embodiments of the present disclosure can electrically insulate the two adjacent charge storage portions 213, prevent the two adjacent charge storage portions 213 from charge migration, and improve the stability of the three-dimensional memory 400, and also does not need to etch the gate replacement layer 11, and does not cause the hole expansion of the channel hole 14, thereby improving the storage density of the three-dimensional memory 400.

In some embodiments, referring to fig. 1B, the following steps S21 and S22 are further included prior to forming the initial channel structure 20 in the channel hole 14 at S3.

S21, removing a portion of the initial gate dielectric layer 12 through the channel hole 14 to form a first recess 15.

Referring to fig. 2C and 5C, after the channel hole 14 is formed at step S2, the initial gate dielectric layer 12 may be exposed through the channel hole 14. In step S21, the initial gate dielectric layer 12 is removed from the trench hole 14, so that the end surface of the initial gate dielectric layer 12 close to the trench hole 14 is recessed into the gate replacement layer 11 to form the first recess 15. In some embodiments, a wet etching process may be used to remove the portion of the initial gate dielectric layer 12 near the channel hole 14 using an etching solution.

And S22, forming a barrier part 16 in the first recess 15, wherein the etching rate of the barrier part 16 and the etching rate of the initial gate dielectric layer 12 are different under the same process condition.

Referring to fig. 2D and 5D, the blocking portion 16 is disposed in the first recess 15, and an end surface of the blocking portion 16 facing the channel hole 14 forms a continuous surface with a sidewall of the channel hole 14.

The barriers 16 may comprise a sacrificial material, which may illustratively be polysilicon. In forming the barrier, a sacrificial material may be deposited through the channel hole 14, wherein the sacrificial material is filled in the first recess 15 and covers the sidewall of the channel hole 14. The sacrificial material overlying the sidewalls of the trench hole 14 is then removed while the sacrificial material filling the first recess 15 remains, thereby forming the barrier 16. The barriers 16 formed in step S22 may separate the initial channel structures 20 from the initial gate dielectric layer 12.

In the case where the method for fabricating a semiconductor structure further includes the above steps S21 and S22, the step S5 of removing the initial gate dielectric layer 12 via the gate spacer GLS to form the first slit 17 further includes: s51, the initial gate dielectric layer 12 and the blocking portion 16 are sequentially removed through the gate spacer GLS to form a first slit 17.

In step S51, the initial gate dielectric layer 12 and the blocking portion 16 may be removed in steps. First, referring to fig. 2I and 5I, the initial gate dielectric layer 12 is removed so that the blocking portion 16 is exposed.

Then, referring to fig. 2J and 5J, the dam 16 is removed, the first slit 17 is formed, and a portion of the barrier film 22 is exposed to the first slit 17.

In some examples, the barrier 16 and the initial gate dielectric layer 12 have different etch rates under the same process conditions, and the barrier 16 and the barrier film 22 have different etch rates under the same process conditions.

In some examples, where the material of the initial gate dielectric layer 12 is an oxide and the material of the barrier film 22 in the initial channel structure 20 is also an oxide, the present disclosure spaces the initial gate dielectric layer 12 from the barrier film 22 by the barrier 16, and thus, the barrier film 22 is not damaged when the initial gate dielectric layer 12 is removed, thereby ensuring the stability of the semiconductor structure 300.

In some embodiments, referring to fig. 2A-2H, the initial stacked structure 10 further comprises: barrier layers 13 arranged at two sides of the initial gate dielectric layer 12 along the direction vertical to the substrate 1; the etching rates of the barrier layer 13 and the initial gate dielectric layer 12 are different under the same process condition; referring to fig. 2K and 4B, the preparation method further includes: the target portion 211 of the initial charge storage layer 21 is modified through the first slit 17, and the barrier layer 13 is also modified so that the barrier layer 13 is converted into the insulating medium layer 130.

Referring to fig. 2A, a direction perpendicular to the substrate 1 is a first direction Z, barrier layers 13 are disposed on two sides of each initial gate dielectric layer 12 in the first direction Z, barrier layers 13 are disposed on two opposite sides of each initial gate dielectric layer 12, and a barrier layer 13 is disposed between each adjacent initial gate dielectric layer 12 and the gate replacement layer 11.

Referring to fig. 2J, in step S5, after removing the initial gate dielectric layer 12, a first gap 17 is formed between two adjacent barrier layers 13.

Referring to fig. 2K and 4B, in step S6, when the target portion 211 is modified by the first slit 17, the larger the size of the first slit 17 in the first direction Z, the larger the size of the spacer 212 formed in the first direction Z. In some embodiments, the formation of the barrier layers 13 on both sides of the initial gate dielectric layer 12 may reduce the thickness of the initial gate dielectric layer 12 in the first direction Z, and further reduce the size of the first gap 17 in the first direction Z, and further reduce the size of the isolation portion 212 in the first direction Z. The smaller the dimension of the isolation portion 212 in the first direction Z is, the larger the dimension of the charge storage portion 213 formed in the first direction Z is, thereby securing the amount of electricity stored in the charge storage portion 213.

The barrier layer 13 and the initial gate dielectric layer 12 have different etching rates under the same process condition, so that the barrier layer 13 can be retained when the initial gate dielectric layer 12 is removed.

In some examples, the barrier layer 13 and the barrier 16 have different etch rates under the same process conditions, and thus, when the barrier 16 is removed, referring to fig. 2J, the barrier layer 13 can remain.

In step S21, after removing the portion of the initial gate dielectric layer 12 near the side of the channel hole 14 in the initial stacked structure 10 including the barrier layers 13 on both sides of the initial gate dielectric layer 12, referring to fig. 2C, the end surface of the initial gate dielectric layer 12 near the channel hole 14 is recessed into the end surface of the barrier layer 13, so as to form the first recess 15, and thus the first recess 15 is surrounded by the barrier layer 13 and the initial gate dielectric layer 12.

In some embodiments, the step of subjecting the barrier layer 13 to a modification treatment includes: an oxidation process is used to modify the barrier layer 13.

Here, the barrier layer 13 may be modified by an oxidation process, and similarly, the target portion 211 of the initial charge storage layer 21 may be modified by an oxidation process.

In some embodiments, referring to fig. 1B, the step of performing a modification process on the target portion 211 of the initial charge storage layer 21 through the first slit 17 to convert the target portion 211 into the isolation portion 212, S6, includes: s61, the target portion 211 of the initial charge storage layer 21 is oxidized through the first slit 17 by an oxidation process so that the target portion 211 is converted into the isolation portion 212.

Here, referring to fig. 2J and 5J, the initial charge storage layer 21 includes the predetermined portion 214 therein, and a projection of the predetermined portion 214 in the projection direction just covers the first slit 17, that is, a size of the predetermined portion 214 in the first direction Z is the same as a size of the first slit 17 in the first direction Z.

In some examples, referring to fig. 2K and 5K, the first slit 17 extends to the surface of the barrier film 22, and when the initial charge storage layer 21 is oxidized through the first slit 17, oxygen can penetrate the barrier film 22 into the predetermined portion 214, so that the predetermined portion 214 is oxidized. Furthermore, oxygen can also penetrate along the first direction Z, so that the portion of the initial charge storage layer 21 except the predetermined portion 214 is oxidized, and thus the dimension of the portion of the initial charge storage layer 21 converted into the isolation portion 212 in the first direction Z is larger than the dimension of the predetermined portion 214 in the first direction Z, that is, the dimension of the target portion 211 and the isolation portion 212 in the first direction Z is larger than the dimension of the predetermined portion 214 in the first direction Z, and the dimension of the predetermined portion 214 in the first direction Z is the same as the dimension of the first slit 17 in the first direction Z, so that the dimension of the first slit 17 in the first direction Z is smaller than the dimension of the isolation portion 212 in the first direction Z, that is, the region covered by the projection of the isolation portion 212 in the projection direction a completely covers the first slit 17.

In some embodiments, a barrier layer 13 is disposed in the initial stacked structure 10, and in step 61, referring to fig. 2K, the target portion 211 is oxidized while the barrier layer 13 is oxidized into the insulating dielectric layer 130. At this time, the area covered by the projection of the isolation portion 212 in the projection direction a completely covers the first slit 17 and can also cover a part of the insulating dielectric layer 130. Therefore, the projection of the charge storage part 213 in the projection direction a may cover the region where the gate dielectric layer 11 is located and the rest of the insulating dielectric layer 130, and thus, the size of the charge storage part 213 in the first direction Z may be larger than the size of the region where the gate dielectric layer 11 is located in the first direction Z. In some embodiments, the gate dielectric layer 11 is replaced with the gate line layer 110, so that the area where the gate dielectric layer 11 is located is the area where the gate line layer 110 is located.

In other embodiments, referring to fig. 5J, the initial laminate structure 10 is not provided with a barrier layer 13, when the target portion 211 in the initial charge storage layer 21 is oxidized through the first slit 17, referring to fig. 5K, the projection of the isolation portion 212 in the projection direction a may be formed to completely cover the first slit 17, and cover a portion of the gate dielectric layer 11, therefore, the dimension of the spacer 212 in the first direction Z is larger than the dimension of the first slit 17 in the first direction Z, further, the size of the charge storage part 213 in the first direction Z is smaller than the size of the region where the gate dielectric layer 11 is located, that is, the region where the gate line layer 110 is located, in the first direction Z, and, at this time, a projection of one charge storage section 213 in the projection direction covers a part of the area where one gate replacement layer 11 is located, i.e. the portion of the projection of one charge storage section 213 in the projection direction, which covers the area where one gate line layer 110 is located.

In addition, oxygen needs to permeate the barrier film 22 and then oxidize the target site 211, and thus, the target site 211 may be oxidized using a permeation oxidation process. After the oxygen in the first slit 17 permeates the barrier film 22, the predetermined portion 214 is oxidized, so that the diffusion distance of oxygen in the first direction Z, that is, the size of the oxidized portion in the initial charge storage layer 21 in the first direction Z, that is, the size of the isolation portion 212 in the first direction Z, can be reduced, and the smaller the size of the isolation portion 212 in the first direction Z, the larger the size of the charge storage portion 213 in the first direction Z, thereby increasing the size of the charge storage portion 213 in the first direction Z.

In some embodiments, after the step of modifying the target portion 211 of the initial charge storage layer 21 through the first slit 17 at S6, the method further includes: in step S7, the dielectric material 140 is filled in the first slit 17.

Referring to fig. 2L, 2M, 4C, 4D, 5L, 5M, 6C and 6D, in step S7, a dielectric material 140 is filled in the first gap 17, wherein the dielectric material 140 may be an insulating material.

In some examples, the dielectric material 140 may be an oxide, which may be silicon dioxide, for example, and the dielectric material 140 may be silicon oxycarbonitride, among others.

In other examples, the initial stacked structure 10 includes barrier layers 13 on both sides of the initial gate dielectric layer 12, and in this case, in step S7, referring to fig. 2L, 2M, 4C and 4D, the first gap 17 is filled with a dielectric material 140, and the dielectric material 140 is filled between the two insulating dielectric layers 130.

In other examples, the initial stacked structure 10 includes only the initial gate dielectric layer 12 and the gate replacement layer 11 stacked alternately, and at this time, in step S7, referring to fig. 5L, 5M, 6C and 6D, the dielectric material 140 is filled between two adjacent gate line layers 110.

When the first gap 17 is filled with the dielectric material 140, in some embodiments, the dielectric material 140 may be filled in the entire space of the first gap 15, as shown in fig. 2M, 4D, 5L and 6C, in which case the first gap is filled more tightly, which can achieve better support and electrical insulation effect between the grid lines G.

In other embodiments, referring to fig. 2L, 4C, 5M and 6D, after the dielectric material 140 is filled in the first gap 17, an air gap 150 is formed in the first gap 17.

In some examples, the initial stacked structure 10 further includes a barrier layer 13, and the barrier layer 13 may be converted into an insulating dielectric layer 130 in a subsequent process, so that, referring to fig. 2L and fig. 4C, a dielectric material 140 is filled between two adjacent insulating dielectric layers 130, and an air gap 150 is formed between two adjacent insulating dielectric layers 130 and also between two adjacent gate line layers 110.

In other examples, the barrier layer 13 is not disposed in the initial stacked structure 10, and the gate replacement layer 11 is replaced with the gate line layer 110 after the first gap 17 is formed, at which time the dielectric material 140 is filled between the adjacent gate replacement layers 11, and then the gate replacement layer 11 may be replaced with the gate line layer 110, so that the dielectric material 140 and the air gap 150 are disposed between the two adjacent gate line layers 110. In other examples, the gate replacement layer 11 is replaced with the gate line layer 110 before the first slit 17 is formed, referring to fig. 5M and 6D, the dielectric material 140 is filled between the adjacent two gate line layers 110, and then the air gap 150 may be formed between the adjacent two gate line layers 110.

In summary, in the semiconductor structure 300 formed by the above manufacturing method, the air gap 150 is disposed between two adjacent gate line layers 110.

In one implementation, in order to make the semiconductor structure 300 have more film layers, the gate replacement layer 11 and the initial gate dielectric layer 12 are thinned, and as the initial gate dielectric layer 12 and the gate replacement layer 11 are thinned, the gate replacement layer 11 may be replaced with the gate line layer 110 in a subsequent process, and the gate line layer 110 may be separated into a plurality of gate lines G by the gate separation grooves GLS, so that as the initial gate dielectric layer 12 and the gate replacement layer 11 are thinned, a distance between two adjacent gate lines G is reduced. The two adjacent gate lines G may form a capacitor, and the distance between the two adjacent gate lines G is reduced, which may increase the capacitance of the capacitor formed by the two adjacent gate lines G, so that the RC Delay phenomenon is serious.

In some embodiments of the present disclosure, the air gap 150 is formed between two adjacent gate line layers 110, and the dielectric constant of air is smaller, so that the capacitance of the capacitor formed between two adjacent gate lines G is smaller, and the RC Delay phenomenon can be further alleviated.

In some embodiments, referring to fig. 2J and 5J, the initial channel structure 20 further comprises: a barrier film 22 disposed between the sidewall of the channel hole 14 and the initial charge storage layer 21; referring to fig. 1A, before the step of modifying the target portion 211 of the initial charge storage layer 21 through the first slit 17 to convert the target portion 211 into the isolation portion 212 at S6, the preparation method further includes: s52, removing the portion of the barrier film 22 exposed to the first slit 17 through the first slit 17, so that the first slit 17 extends to the surface of the initial charge storage layer 21, the first slit 17 dividing the barrier film 22 into a plurality of barrier portions 221, the plurality of barrier portions 221 constituting the barrier layer 220.

Referring to fig. 2J and 5J, after the first slit 17 is formed, a portion of the barrier film 22 is exposed.

Referring to fig. 4A and 6A, in step S52, the portion of the barrier film 22 exposed to the first slit 17 is removed, such that the first slit 17 extends to the surface of the initial charge storage layer 21, and at this time, the portion of the initial charge storage layer 21 exposed to the first slit 17 is the predetermined portion 214.

Then, referring to fig. 4B and 6B, the target portion 211 may be oxidized through the predetermined portion 214 to form the isolation portion 212, and since the predetermined portion 214 of the initial charge storage layer 21 may be exposed to the first slit 17, oxygen in the first slit 17 may directly contact the predetermined portion 214 when the target portion 211 is oxidized, and thus the target portion 211 may be oxidized by a direct oxidation process, and since oxygen may directly contact a portion of the initial charge storage layer 21 (i.e., the predetermined portion 214), an oxidation condition may be relatively easy, for example, a temperature required for the direct oxidation may be relatively low and a time may be relatively short. Furthermore, oxygen can also penetrate along the first direction Z, so that the spacer 212 can be formed to completely cover the area where the predetermined portion 214 is located, and therefore, the predetermined portion 214 is completely located within the area where the target portion 211 is located, and the dimension of the spacer 212 in the first direction Z is larger than the dimension of the predetermined portion 214 in the first direction Z.

In some examples, referring to fig. 4A, a barrier layer 13 is disposed in the initial stacked structure 10, and each of the gate replacement layers 11 is disposed with the barrier layer 13 on both sides in the first direction Z. In step S52, after removing the portion of the barrier film 22 exposed to the first slit 17, the barrier film 22 is separated into a plurality of barrier portions 221, wherein one barrier portion 221 corresponds to one gate line G. At this time, a projection of one barrier section 221 in the projection direction a covers a region where a barrier layer 11 is located and regions where barrier layers 13 located on both sides of the barrier layer 11 are located. In some embodiments, the gate replacement layer 11 is replaced with the gate line layer 110 before etching the barrier film 22, and at this time, the area where one gate replacement layer 11 is located is the area where one gate line layer 110 is located.

In other examples, referring to fig. 6A to 6D, the barrier layer 13 is not disposed in the initial stacked structure 10, and in this case, the projection of the barrier portion 221 in the projection direction can just cover the area where the grid replacement layer 11 is located.

In step S52, the first slit 17 extends to the surface of the initial charge storage layer 21, and at this time, a portion of the first slit 17 is located between two adjacent barrier portions 221. In step S7, when the first gap 17 is filled with the dielectric material 140, in some embodiments, referring to fig. 4D and 6C, the dielectric material 140 may fill the first gap 17, and at this time, the dielectric material 140 may be filled between two adjacent barriers 221.

In other embodiments, referring to fig. 4C and 6D, after the dielectric material 140 is filled into the first gap 17, an air gap 150 is formed in the first gap 17. In some examples, the air gap 150 may be formed between two adjacent blocking portions 221. In other examples, the dielectric material 140 may also be filled between two adjacent barrier portions 221. In other examples, the air gap 150 and the dielectric material 140 may be located between two adjacent barriers 221.

In some embodiments, the barrier film 22 and the barrier 16 have different etch rates under the same process conditions.

Since the barrier film 22 and the barrier portion 16 have different etching rates under the same process condition, the barrier film 22 is not damaged when the barrier portion 16 is removed.

In some embodiments, referring to fig. 1A, before the step of removing the initial gate dielectric layer 12 via the gate spacer GLS to form the first slit 17 at S5, the preparation method further includes: steps S41 to S42.

S41, the gate replacement layer 11 is removed through the gate spacer GLS to form the second slit 18.

In step S41, the gate replacement layer 11 in the initial stacked structure 10 may be removed by isotropic etching through the gate spacer GLS, thereby forming the second slit 18, see fig. 2F and 5F. Wherein, the isotropic etching can adopt selective wet etching or gas phase etching.

S42, forming the protective layer 111 and the gate line layer 110 in the second slit 18 in sequence.

In step S42, referring to fig. 2G and 5G, first, the protective layer 111 is formed in the second slit 18 by a deposition process, and the protective layer 111 may be a high-K dielectric layer, and in some examples, the high-K dielectric layer may include any one or more of aluminum oxide, hafnium oxide, zirconium oxide, or titanium oxide.

Thereafter, referring to fig. 2H and 5H, the gate line layer 110 is formed within the second slits 18. Here, the gate line layer 110 may be made of a metal material, and the metal material may be, for example, tungsten (W), etc.

In some examples, referring to fig. 2H, the barrier layer 13 is further included in the initial stacked structure 10, and the protective layer 111 may be formed between the barrier layer 13 and the gate line layer 110, and between the gate line layer 110 and the barrier film 22. When the target portion 211 is oxidized, the barrier layer 13 can protect the gate line layer 110 from being oxidized, and the protective layer 111 can also protect the gate line layer 110 from being oxidized, so that the conductivity of the gate line layer 110 is prevented from being affected by the oxidation of the gate line layer 110.

In addition, after the gate replacement layer 11 is replaced with the gate line layer 110, the target portion 211 is oxidized, so that the oxidation of the portion of the gate replacement layer 11 close to the barrier layer 13 can be avoided. If the gate replacement layer 11 is oxidized, when the gate replacement layer 11 is removed, the oxidized portion of the gate replacement layer 11 cannot be removed, so that the size of the second slit 18 in the first direction Z is reduced, and further, the size of the gate line layer 110 formed in the second slit 18 in the first direction Z is reduced. Therefore, forming the protective layer 111 and the gate line layer 110 before step S6 can ensure the dimension of the second slit 18 in the first direction Z, and thus the dimension of the gate line layer 110 in the first direction Z.

In some embodiments, the material of the barrier 16 is the same as the material of the gate replacement layer 11.

Among them, in some examples, referring to fig. 2D, the barrier layer 13 is included in the initial stacked structure 10, the barrier portion 16 is located between two adjacent barrier layers 13, and the barrier portion 16 is not in contact with the gate replacement layer 11, and therefore, the material of the barrier portion 16 and the gate replacement layer 11 may be made the same.

In some embodiments, the gate replacement layer 11 and the barrier 16 may be formed of nitride, which may be silicon nitride for example.

In some embodiments, the material of the barrier layer 13 may include either or both of silicon carbide nitride and polysilicon. And the material of the initial gate dielectric layer 12 may be either or both of silicon oxide and silicon oxycarbide. Under the same process condition, the etching rate of the materials such as silicon oxide, silicon oxycarbonitride, and the like is different from the etching rate of silicon oxycarbonitride, and polysilicon, so that when the initial gate dielectric layer 12 is etched in step S51, the barrier layer 13 is not etched together, and the barrier layer 13 can be retained. In addition, since the gate replacement layer 11 and the barrier portion 16 are made of silicon nitride, the barrier layer 13 is not damaged when the barrier portion 16 is removed in step S51 and the gate replacement layer 11 is removed in step S41, thereby ensuring the stability of the semiconductor structure 300.

In other examples, referring to fig. 5E, the barrier layer 13 is not disposed in the initial stacked structure 10, the barrier 16 is located between two adjacent gate replacement layers 11, and the material of the barrier 16 is different from that of the gate replacement layers 11. Illustratively, the material of the gate replacement layer 11 may be nitride, the nitride may be silicon nitride, and the material of the barrier 16 may be polysilicon.

In some embodiments, referring to fig. 7B, the initial channel structure 20 extends into the substrate 1. After step S7, the substrate 1 may be removed to expose the portion of the initial channel structure 20 extending into the substrate 1; then removing the blocking thin film 22, the initial charge storage layer 21 and the tunneling layer 23 in sequence in the portion of the initial channel structure 20 in the substrate 1 to expose the channel layer 24; then, a source layer SL is formed at a position where the substrate 1 is originally formed, the source layer SL can cover the channel layer 24, the source layer SL can be in contact with the channel layer 24, and electrical connection between the source layer SL and the channel layer 24 is possible.

The source layer SL may include a semiconductor material such as single crystal silicon, single crystal germanium, III-V compound semiconductor material, II-VI compound semiconductor material, and other suitable semiconductor materials. The source layer SL may be partially or fully doped. Illustratively, the source layer SL may include a doped region doped with a p-type dopant. The source layer SL may further include an undoped region.

In some embodiments, referring to fig. 7B, a gate isolation structure 160 may be formed within the gate spacer GLS, the gate isolation structure 160 including an insulating isolation portion 161 and a conductive portion 162 sequentially disposed in the gate spacer GLS, the insulating isolation portion 161 and the conductive portion 162 both extending into the substrate 1. The insulating spacer 161 may be made of one or a combination of silicon oxide, silicon nitride, metal oxide, and organosilicate glass. And conductive portion 162 is formed of a conductive material, which may be, for example, one or more of tungsten, cobalt, copper, aluminum, doped silicon, and silicide.

In some embodiments, after removing the substrate 1, the portion of the insulating isolation portion 161 of the gate isolation structure 160 extending into the substrate 1 may be exposed, and then the portion of the insulating isolation portion 161 of the gate isolation structure 160 extending into the substrate 1 may be removed, and after forming the source layer SL, as shown in fig. 7B, the source layer SL may be in contact with the conductive portion 162, so that the conductive portion 162 is electrically connected to the source layer SL.

Some embodiments of the present disclosure provide a semiconductor structure 300 made by the method for fabricating the semiconductor structure provided in the above embodiments. Therefore, the semiconductor structure 300 provided in some embodiments of the present disclosure has all the advantages of the method for manufacturing the semiconductor structure provided in some embodiments above, and details are not repeated herein.

Some embodiments of the present disclosure provide a semiconductor structure 300, referring to fig. 6C and 6D, the semiconductor structure 300 including: a substrate, a memory stack structure 100 and a channel structure 200. The memory stack structure 100 is disposed on one side of the substrate, and the memory stack structure 100 includes a gate line layer 110 and a gate dielectric layer 120 that are alternately stacked. The channel structure 200 penetrates the memory stack structure 100, and the channel structure 200 includes a blocking layer 220 and a charge storage layer 210, wherein the charge storage layer 210 includes charge storage portions 213 and isolation portions 212 alternately arranged in a height direction of the channel structure 200. The blocking layer 220 includes a plurality of blocking portions 221, and one blocking portion 221 is located between one gate line layer 110 and one charge storage portion 213.

In the preparation of the semiconductor structure 300, the initial stacked structure 10 may be disposed on the substrate 1, and in the subsequent process, the substrate 1 may be removed, as shown in fig. 7B, and a source layer SL is formed at the position where the substrate 1 is originally disposed, in this case, the source layer SL is the base. In other embodiments, the substrate 1 is not removed, and the substrate 1 is the base.

In some embodiments, referring to fig. 5A, the initial stacked structure 10 includes a gate replacement layer 11 and an initial gate dielectric layer 12 that are alternately stacked. Wherein the initial gate dielectric layer 12 may be removed in a subsequent process to form the first slit 17, as can be seen in fig. 5K. Then, referring to fig. 5L and 5M, a dielectric material 140 may be filled in the first gap 17, so as to form the gate dielectric layer 120. And the gate replacement layer 11 may be replaced with the gate line layer 110. The gate line layer 110 may be formed of a conductive material, which may be tungsten, for example.

Referring to fig. 6C and 6D, the charge storage layer 210 includes charge storage portions 213 and isolation portions 212 alternately arranged in a height direction of the channel structure 200. It should be noted that, since the height direction of the channel structure is the first direction Z, the charge storage portions 213 and the isolation portions 213 alternately arranged along the first direction Z can be electrically insulated from each other by the isolation portions 212, so that charge transfer between the charge storage portions 213 in two adjacent memory cells can be avoided, and the reliability of the three-dimensional memory 400 can be improved.

Referring to fig. 6C and 6D, the barrier layer 220 includes a multi-segment barrier 221, and the barrier 221 may be formed in step S52. A barrier section 221 is located between a gate line layer 110 and a charge storage section 213.

In other embodiments, referring to fig. 5L and 5M, the blocking film 22 is not etched, and at this time, the channel structure 200 in the semiconductor structure 300 includes the blocking film 22 and the charge storage layer 210.

In addition, referring to fig. 5M, fig. 5L, fig. 6C and fig. 6D, the channel structure 200 further includes a tunneling layer 23 and a channel layer 24 sequentially disposed on a side of the charge storage layer 210 away from the blocking layer 220 or the blocking thin film 22, wherein a chamber surrounded by the channel layer 24 may be filled with an oxide to form a support portion 25 for supporting the channel structure 200.

In some embodiments, referring to fig. 2L, 2M, 4C, and 4D, gate dielectric layer 120 includes two insulating dielectric layers 130, and a dielectric material 140 disposed between the two insulating dielectric layers 130.

In some examples, the initial stacked structure 10 further includes barrier layers 13, the barrier layers 13 are disposed on two sides of the initial gate dielectric layer 12, and the target portion 211 is modified and the barrier layers 13 are also modified, so that the barrier layers 13 are converted into the insulating dielectric layer 130. And the initial gate dielectric layer 12 is removed in subsequent processes and replaced with dielectric material 140. After the semiconductor structure 300 is formed, referring to fig. 2L, fig. 2M, fig. 4C and fig. 4D, two insulating dielectric layers 130 and a dielectric material 140 located between the two insulating dielectric layers 130 are disposed between two adjacent gate line layers 110.

Based on the embodiment that the gate dielectric layer 120 includes two insulating dielectric layers 130 and a dielectric material 140 disposed between the two insulating dielectric layers 130, referring to fig. 2L and 2M, the blocking film 22 may be included in the channel structure 200. In other examples, referring to fig. 4C and 4D, a barrier layer 220 may be included in the channel structure 200, the barrier layer 220 including a plurality of barriers 221.

In the manufacturing process of the semiconductor structure 300, referring to fig. 2K and 4B, after the initial gate dielectric layer 12 is removed, the first gap 17 may be formed, and the target portion 211 may be modified through the first gap 17 to form the isolation portion 212. The smaller the size of the first slit 17 in the first direction Z, the smaller the size of the isolation portion 212 formed in the first direction Z, and correspondingly, the larger the size of the charge storage portion 213 formed in the first direction Z. The first slit 17 can be formed after the initial gate dielectric layer 12 is removed, and therefore, the size of the initial gate dielectric layer 12 in the first direction Z determines the size of the first slit 17 in the first direction Z. In some embodiments, referring to fig. 2J and 4A, the size of the isolation portion 212 in the first direction Z can be reduced and the size of the charge storage portion 213 in the first direction Z can be increased by forming the barrier layer 13 in the initial stacked structure 10 to reduce the size of the initial gate dielectric layer 12 in the first direction Z and further reduce the size of the first gap 17 in the first direction Z.

In some embodiments, a projection of one charge storage part 213 in a direction perpendicular to a height direction of the channel structure 200 covers at least a portion of one gate line layer 110, wherein the direction perpendicular to the height direction of the channel structure 200 is a projection direction a. The projection of one charge storage section 213 in the projection direction a covers at least a portion of one gate line layer 110, and specifically, the following examples may be included.

In some examples, referring to fig. 2L, 2M, 4C, and 4D, gate dielectric layer 120 includes two insulating dielectric layers 130, and a dielectric material 140 disposed between the two insulating dielectric layers 130. At this time, the projection of one charge storage section 213 in the projection direction may completely cover one gate line layer 110, and the size of the charge storage section 213 in the first direction Z is larger than the size of one gate line layer 110 in the first direction Z.

In other examples, referring to fig. 5L, 5M, 6C, and 6D, gate dielectric layer 120 does not include insulating dielectric layer 130 and only includes dielectric material 140. At this time, the projection of one charge storage section 213 in the projection direction a covers a portion of one gate line layer 110, that is, the size of one charge storage section 213 in the first direction Z is smaller than the size of one gate line layer 110 in the first direction Z.

In other examples, the projection of one charge storage section 213 in the projection direction a covers just a part of one gate line layer 110, that is, the size of one charge storage section 213 in the first direction Z is equal to the size of one gate line layer 110 in the first direction Z.

In some embodiments, referring to fig. 2L and 4C, an air gap 150 is further disposed between two insulating dielectric layers 130 in the gate dielectric layer 120. A gate dielectric layer 120 is formed between two adjacent gate line layers 110, and thus, the air gap 150 in the gate dielectric layer 120 is also located between two adjacent gate line layers 110.

In other embodiments, referring to fig. 5M and 6D, the gate dielectric layer 120 does not include the insulating dielectric layer 130, and only includes the dielectric material 140, in this case, the dielectric material 140 is disposed between two adjacent gate line layers 110, an air gap 150 is disposed between two gate line layers 110,

the memory stack structure 100 further includes a gate isolation structure 160, the gate isolation structure 160 penetrates through the memory stack structure 100, the gate line layer 110 may be divided into a plurality of gate lines G by the gate isolation structure 160, and two adjacent gate lines G may form a capacitor. In one implementation, in order to make the semiconductor structure 300 have more film layers, the gate line layer 110 and the gate dielectric layer are thinned, and as the gate line layer 110 and the gate dielectric layer are thinned, the distance between two adjacent gate lines G is reduced, so that the capacitance of the capacitor formed by the two adjacent gate lines G is increased, and the RC Delay (capacitance-resistance Delay) phenomenon is serious.

In some embodiments, referring to fig. 2L, 2M, 4C, 4D, 5L, 5M, 6C, and 6D, a projection of one spacer 212 in a direction perpendicular to a height direction of the channel structure 200 covers at least one dielectric material 140 in the gate dielectric layer 120. The direction perpendicular to the height direction of the channel structure 200 is the projection direction a.

In some examples, the projection of one partition 212 in the projection direction a exactly covers the dielectric material 140. At this time, the dimension of the isolation portion 212 in the first direction Z is equal to the dimension of the layer of dielectric material 140 in the first direction Z.

In other examples, the projection of one spacer 212 in the projection direction a can completely cover the dielectric material 140, and the dimension of one spacer 212 in the first direction Z is larger than the dimension of one layer of the dielectric material 140 in the first direction Z. Illustratively, in fig. 2L, 2M, 4C and 4D, the gate dielectric layer 120 includes an insulating dielectric layer 130 and a dielectric material 140, and a projection of one of the spacers 212 in the projection direction a can cover the dielectric material 140 and at least a portion of the insulating dielectric layer 130. Illustratively, referring to fig. 5L, 5M, 6C and 6D, the gate dielectric layer 120 does not include the insulating dielectric layer 130, and only includes the dielectric material 140, and a projection of one of the spacers 212 in the projection direction a can cover the dielectric material 140 and at least a portion of the gate line layer 110.

In some examples, the isolation portion 212 may be formed in the step 61, referring to fig. 2J, 4A, 5G and 6A, the initial charge storage layer 21 further includes a predetermined portion 214 therein, and a projection of the predetermined portion 214 in the projection direction a just covers a region where the first slit 17 is located, and when the initial charge storage layer 21 is oxidized through the first slit 17, the predetermined portion 214 can be oxidized by oxygen. Furthermore, oxygen can also permeate along the first direction Z, so that the portion of the initial charge storage layer 21 other than the preset portion 214 is oxidized, and therefore, referring to fig. 2L, fig. 2M, fig. 4C, fig. 4D, fig. 5L, fig. 5M, fig. 6C, and fig. 6D, the size of the isolation portion 212 in the first direction Z is formed to be larger than the preset portion 214, and therefore, the projection of the isolation portion 212 in the projection direction in the first direction Z can completely cover the dielectric material 140, and the size of the isolation portion 212 in the first direction Z is larger than the size of the dielectric material 140 in the first direction Z.

In some embodiments, the dielectric material 140 is filled between two adjacent barriers 221; and/or, an air gap 150 is arranged between two adjacent blocking parts 221.

Various examples may be included, and in some examples, only the dielectric material 140 is filled between two adjacent barrier portions 221. In some examples, only the air gap 150 is formed between adjacent two blocking portions 221. In some examples, two adjacent barriers 221 have both dielectric material 140 disposed therebetween and also have air gaps 150 formed therebetween.

Based on the above-described embodiment in which gate dielectric layer 120 includes insulating dielectric layer 130 and dielectric material 140, in some examples, referring to fig. 4C and 4D, barrier 221 contacts isolation 212 and insulating dielectric layer 130 along both sides parallel to the substrate direction, respectively.

Here, in step S52, when the portion of the barrier film 22 exposed in the first slit 17 is removed through the first slit 17, the portion of the barrier film 22 contacting the insulating dielectric layer 130 remains, and thus, in step S52, the side of the barrier 221 away from the spacer 212 contacts the insulating dielectric layer 130.

In some embodiments, a protective layer 111 is further formed between the gate line layer 110 and the insulating dielectric layer 130, and between the gate line layer 110 and the barrier portion 221, and thus, a side of the barrier portion 221 contacting the insulating dielectric layer 130 also contacts the protective layer 111. Illustratively, the protective layer 111 may be a high-K dielectric layer.

In another example, the gate dielectric layer 120 does not include the insulating dielectric layer 130, and only includes the dielectric material 140, and referring to fig. 6C and 6D, the projection of the barrier portion 221 in the projection direction a may completely cover the area where the gate line layer 110 is located. In other examples, a protective layer 111 is also formed between the gate line layer 110 and the barrier, and between the gate line layer 110 and the dielectric material 140.

In some embodiments, referring to fig. 7B, the semiconductor structure further includes a gate isolation structure 160, and the gate isolation structure 160 includes an insulating isolation portion 161 and a conductive portion 162 sequentially disposed, wherein the conductive portion 162 is in contact with the source layer SL. In some other embodiments, the conductive portion 162 and the source layer SL are isolated from each other by the insulating isolation portion 161.

Fig. 7A is a schematic perspective view of a three-dimensional memory 400 according to some embodiments of the present disclosure, fig. 7B is a cross-sectional view of the three-dimensional memory 400, fig. 7C is a cross-sectional view of a memory cell string 600 of the three-dimensional memory 400 of fig. 7A along a section line AA', and fig. 7D is an equivalent circuit diagram of the memory cell string 600 of fig. 7C.

Referring to fig. 7A and 7B, some embodiments of the present disclosure provide a three-dimensional memory 400. The three-dimensional memory 400 may include a semiconductor structure 300, and a peripheral device 500 coupled to the semiconductor structure 300. The semiconductor structure 300 includes the memory stack structure 100 and a substrate disposed on one side of the memory stack structure 100, and the peripheral device 500 may be disposed on one side of the memory stack structure 100 away from the substrate.

The semiconductor structure 300 may include memory cell transistor strings (referred to herein as "memory cell strings," e.g., NAND memory cell strings) 600 arranged in an array. In some embodiments, the substrate may be a source layer SL, which may be coupled to the source terminals of the plurality of memory cell strings 600.

Specifically, referring to fig. 7C and 7D, the memory cell string 600 may include a plurality of transistors T, for example, the transistors T1 to T6 in fig. 7D may form one memory cell string 600, wherein one transistor T may be provided as one memory cell, and the transistors T are connected together to form the memory cell string 600. A transistor T (e.g., each transistor T) may be formed of the channel structure 200 and one gate line G surrounding the channel structure 200. Wherein the gate line G is configured to control a turn-on state of the transistor.

It should be noted that the numbers of transistors in fig. 7A to 7D are merely schematic, and the memory cell string 600 of the three-dimensional memory 400 provided in the embodiment of the present disclosure may further include other numbers of transistors, such as 4, 16, 32, 64, 128 and more, which are not listed here.

Further, along the first direction Z, a lowermost gate line of the gate lines G (e.g., a gate line closest to the source layer SL of the gate lines G) is configured as a source select gate SGS, and the source select gate SGS is configured to control a conduction state of the transistor T6, and thus a conduction state of a source channel in the memory cell string 600. The uppermost gate line among the plurality of gate lines G (e.g., the gate line farthest from the source layer SL among the plurality of gate lines G) is configured as a drain select gate SGD configured to control the on-state of the transistor T1, thereby controlling the on-state of the drain channel in the memory cell string 600. The gate line in the middle of the plurality of gate lines G may be configured as a plurality of word lines WL, including, for example, word line WL0, word line WL1, word line WL2, and word line WL 3. Writing, reading, and erasing of data of the respective memory cells (e.g., transistors T) in the memory cell string 600 may be accomplished by writing different voltages on the word lines WL.

The three-dimensional memory 400 extends in an X-Y plane, and the second direction X and the third direction Y are, for example, two orthogonal directions in a plane (e.g., a plane in which the source layer SL is located) in which the semiconductor structure 300 is located: the second direction X is, for example, an extending direction of the word line WL, and the third direction Y is, for example, an extending direction of the bit line BL. The first direction Z is perpendicular to the plane of the semiconductor structure 300, i.e., perpendicular to the X-Y plane.

As used in this disclosure, whether a component (e.g., a layer, structure, or device) is "on," "above," or "below" another component (e.g., a layer, structure, or device) of a semiconductor device (e.g., a three-dimensional memory) is determined in a first direction Z relative to a substrate 1 or a source layer SL of the semiconductor device when the substrate 1 or the source layer SL is located in a lowest plane of the semiconductor device in the first direction Z. Throughout this disclosure, the same concepts are applied to describe spatial relationships.

In fig. 7B, a view of the array area CA and a view of the step area SS are shown, the view of the array area CA is based on a left-side coordinate system, the view of the step area SS is based on a right-side coordinate system, that is, the view of the array area CA shows a cross-sectional structure along the Y direction, and the view of the step area SS shows a cross-sectional structure along the X direction.

With continued reference to fig. 7A and 7B, in some embodiments, the semiconductor structure 300 may further include an array interconnect layer 390. The array interconnect layer 390 may be coupled with the memory cell string 600. The array interconnect layer 390 may include a drain terminal (i.e., a bit line BL) of the memory cell string 600, which may be coupled to a semiconductor channel of each transistor T in at least one memory cell string 600.

The array interconnect layer 390 may include one or more first interlayer insulating layers 392, and may further include a plurality of contacts insulated from each other by the first interlayer insulating layers 392, the contacts including, for example, bit line contacts BL-CNT coupled to the bit lines BL; a drain select gate contact SGD-CNT coupled to drain select gate SGD. The array interconnect layer 390 may also include one or more first interconnect conductor layers 391. The first interconnect conductor layer 391 may include a plurality of connection lines, such as bit lines BL, and word line connection lines WL-CL coupled to word lines WL. The material of the first interconnect conductor layer 391 and the contacts may be a conductive material such as a combination of one or more of tungsten, cobalt, copper, aluminum, and metal silicide, and may be other suitable materials. The material of the first interlayer insulating layer 392 is one or a combination of silicon oxide, silicon nitride, and a high-k insulating material, and may be other suitable materials.

The peripheral device 500 may include peripheral circuitry. The peripheral circuitry is configured to control and sense the array devices. The peripheral circuitry may be any suitable digital, analog, and/or mixed signal control and sensing circuitry for supporting array device operation (or working), including but not limited to page buffers, decoders (e.g., row and column decoders), sense amplifiers, drivers (e.g., word line drivers), charge pumps, current or voltage references, or any active or passive component of circuitry (e.g., transistors, diodes, resistors, or capacitors). The peripheral circuits may also include any other circuits compatible with advanced Logic processes, including Logic circuits (e.g., processors and Programmable Logic Devices (PLDs) or Memory circuits (e.g., Static Random-Access memories (SRAMs)).

Specifically, in some embodiments, the peripheral device 500 may include a substrate 510, a transistor 520 disposed on the substrate 510, and a peripheral interconnect layer 530 disposed on the substrate 510. The peripheral circuitry may include a transistor 520.

The material of the substrate 510 may be monocrystalline silicon, or may be other suitable materials, such as silicon germanium, or a silicon-on-insulator thin film.

Peripheral interconnect layer 530 is coupled to transistors 520 to enable the transmission of electrical signals between transistors 520 and peripheral interconnect layer 530. The peripheral interconnect layer 530 may include one or more second interlayer insulating layers 531 and may further include one or more second interconnect conductor layers 532. Different second interconnect conductor layers 532 may be coupled to each other by contacts. The material of the second interconnect conductor layer 532 and the contacts may be a conductive material such as a combination of one or more of tungsten, cobalt, copper, aluminum, and metal silicide, and may be other suitable materials. The material of the second interlayer insulating layer 531 is one or a combination of silicon oxide, silicon nitride, and a high-k insulating material, and may be other suitable materials.

The peripheral interconnect layer 530 may be coupled with the array interconnect layer 390 such that the semiconductor structure 300 and the peripheral device 500 may be coupled. Specifically, since the peripheral interconnect layer 530 is coupled to the array interconnect layer 390, peripheral circuits in the peripheral device 500 may be coupled to the memory cell strings 600 in the semiconductor structure 300 to enable transmission of electrical signals between the peripheral circuits and the memory cell strings 600. In some possible implementations, a bonding interface 900 may be disposed between the peripheral interconnection layer 530 and the array interconnection layer 390, and the peripheral interconnection layer 530 and the array interconnection layer 390 may be bonded and coupled to each other through the bonding interface 900.

Fig. 8A is a block diagram of a storage system 700 according to some embodiments. FIG. 8B is a block diagram of a memory system 700 according to further embodiments.

Referring to fig. 8A and 8B, some embodiments of the present disclosure also provide a storage system 700. The storage system 700 includes a controller 800, and the three-dimensional memory 400 of some embodiments as above, the controller 800 being coupled to the three-dimensional memory 400 to control the three-dimensional memory 400 to store data.

Among other things, the Storage system 700 may be integrated into various types of Storage devices, for example, included in the same package (e.g., a Universal Flash Storage (UFS) package or an Embedded multimedia Card (eMMC) package). That is, the storage system 700 may be applied to and packaged into different types of electronic products, such as a mobile phone (e.g., a cell phone), a desktop computer, a tablet computer, a laptop computer, a server, an in-vehicle device, a game console, a printer, a positioning device, a wearable device, a smart sensor, a mobile power supply, a Virtual Reality (VR) device, an Augmented Reality (AR) device, or any other suitable electronic device having storage therein.

In some embodiments, referring to fig. 8A, the memory system 700 includes a controller 800 and a three-dimensional memory 400, and the memory system 700 may be integrated into a memory card.

The Memory Card includes any one of a PC Card (PCMCIA), a Compact Flash (CF) Card, a Smart Media (SM) Card, a Memory stick, a Multimedia Card (MMC), a Secure Digital Memory Card (SD), and a UFS.

In other embodiments, referring to fig. 8B, the storage system 700 includes a controller 800 and a plurality of three-dimensional memories 400, and the storage system 700 is integrated into a Solid State Drive (SSD).

In storage system 700, in some embodiments, controller 800 is configured for operation in a low duty cycle environment, such as an SD card, CF card, Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, mobile phones, and the like.

In other embodiments, the controller 800 is configured for operation in a high duty cycle environment SSD or eMMC for data storage and enterprise storage arrays of mobile devices such as smart phones, tablets, laptops, and the like.

In some embodiments, the controller 800 may be configured to manage data stored in the three-dimensional memory 400 and communicate with an external device (e.g., a host). In some embodiments, the controller 800 may also be configured to control operations of the three-dimensional memory 400, such as read, erase, and program operations. In some embodiments, the controller 800 may also be configured to manage various functions with respect to data stored or to be stored in the three-dimensional memory 400, including at least one of bad block management, garbage collection, logical-to-physical address translation, wear leveling. In some embodiments, the controller 800 is further configured to process error correction codes with respect to data read from the three-dimensional memory 400 or written to the three-dimensional memory 400.

Of course, the controller 800 may also perform any other suitable functions, such as formatting the three-dimensional memory 400; for example, the controller 800 may communicate with an external device (e.g., a host) via at least one of various interface protocols.

It should be noted that the interface protocol includes at least one of a USB protocol, an MMC protocol, a Peripheral Component Interconnect (PCI) protocol, a PCI express (PCI-E) protocol, an Advanced Technology Attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a Small Computer System Interface (SCSI) protocol, an Enhanced Small Disk Interface (ESDI) protocol, an Integrated Drive Electronics (IDE) protocol, and a Firewire protocol.

Some embodiments of the present disclosure also provide an electronic device. The electronic device may be any one of a mobile phone, a desktop computer, a tablet computer, a notebook computer, a server, an in-vehicle device, a wearable device (e.g., a smart watch, a smart bracelet, smart glasses, etc.), a mobile power source, a game console, a digital multimedia player, and the like.

The electronic device may include the storage system 700 described above, and may further include at least one of a Central Processing Unit (CPU), a cache (cache), and the like.

The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.

Claims

1. A method for fabricating a semiconductor structure, comprising:

forming an initial laminated structure on one side of a substrate, wherein the initial laminated structure comprises a gate replacement layer and an initial gate dielectric layer which are alternately laminated;

forming a channel hole, wherein the channel hole penetrates through the initial laminated structure;

forming an initial channel structure within the channel hole, the initial channel structure including an initial charge storage layer;

forming gate isolation grooves, wherein the gate isolation grooves at least penetrate through the initial laminated structure;

removing the initial gate dielectric layer through the gate isolation groove to form a first gap;

modifying a target portion of the initial charge storage layer through the first slit to convert the target portion into a partition portion, wherein the partition portion partitions the initial charge storage layer into a plurality of charge storage portions.

2. The method of claim 1, wherein the step of forming the semiconductor structure comprises the step of forming a semiconductor layer on the substrate,

before the step of forming the initial channel structure in the channel hole, the method further comprises:

removing part of the initial gate dielectric layer through the channel hole to form a first recess;

forming a blocking part in the first recess, wherein the blocking part and the initial gate dielectric layer have different etching rates under the same process condition;

the step of removing the initial gate dielectric layer through the gate isolation groove to form a first gap includes:

and sequentially removing the initial gate dielectric layer and the blocking part through the gate isolation groove to form the first gap.

3. The method of manufacturing a semiconductor structure according to claim 2,

the initial laminate structure further comprises: barrier layers arranged on two sides of the initial gate dielectric layer along the direction vertical to the substrate; the barrier layer and the initial gate dielectric layer have different etching rates under the same process condition, and the barrier layer and the barrier part have different etching rates under the same process condition;

the preparation method further comprises the following steps:

and modifying the target part of the initial charge storage layer through the first gap, and simultaneously modifying the barrier layer to convert the barrier layer into an insulating medium layer.

4. The method of claim 3, wherein the step of modifying the barrier layer comprises:

and modifying the barrier layer by adopting an oxidation process.

5. The method for fabricating a semiconductor structure according to any one of claims 1 to 4,

after the step of performing modification treatment on the target portion of the initial charge storage layer through the first slit, the method further includes:

and filling a dielectric material in the first gap.

6. The method of claim 5, wherein the step of forming the semiconductor structure comprises the step of forming the semiconductor structure,

and after the dielectric material is filled in the first gap, an air gap is formed in the first gap.

7. The method for fabricating a semiconductor structure according to any one of claims 1 to 4,

the initial channel structure further comprises: a barrier film disposed between a sidewall of the channel hole and the initial charge storage layer;

before the step of performing modification treatment on the target portion of the initial charge storage layer through the first slit to convert the target portion into a spacer, the manufacturing method further includes:

and removing the part of the blocking film exposed to the first gap through the first gap, so that the first gap extends to the surface of the initial charge storage layer, the first gap divides the blocking film into a plurality of blocking parts, and the plurality of blocking parts form a blocking layer.

8. The method of claim 7, wherein the step of forming the semiconductor structure comprises the step of forming the semiconductor structure,

the barrier film and the barrier part have different etching rates under the same process condition.

9. The method for fabricating a semiconductor structure according to any one of claims 1 to 4,

the step of performing modification processing on a target portion of the initial charge storage layer through the first slit to convert the target portion into a spacer includes:

and oxidizing the target part of the initial charge storage layer through the first gap by adopting an oxidation process so as to convert the target part into the isolation part.

10. The method for fabricating a semiconductor structure according to any one of claims 1 to 4,

before the step of sequentially removing the initial gate dielectric layer and the blocking part through the gate isolation groove to form a first gap, the preparation method further comprises:

removing the gate replacement layer through the gate isolation groove to form a second gap;

and sequentially forming a protective layer and a grid line layer in the second gap.

11. The method for fabricating a semiconductor structure according to claim 3 or 4,

the material of the barrier portion is the same as that of the gate replacement layer.

12. The method for fabricating a semiconductor structure according to claim 3 or 4,

the material of the barrier comprises a nitride;

the material of the initial gate dielectric layer comprises an oxide;

the material of the barrier layer comprises silicon carbide nitride or polysilicon.

13. A semiconductor structure, comprising:

the semiconductor structure is manufactured by the method for manufacturing the semiconductor structure according to any one of claims 1 to 12.

14. A semiconductor structure, comprising:

a substrate;

the storage laminated structure is arranged on one side of the substrate and comprises a gate line layer and a gate dielectric layer which are alternately superposed;

a channel structure penetrating the memory stack structure, the channel structure including a blocking layer and a charge storage layer, wherein the charge storage layer includes charge storage portions and isolation portions alternately arranged in a height direction of the channel structure; the blocking layer comprises a plurality of sections of blocking parts, and one section of blocking part is positioned between one grid line layer and one charge storage part.

15. The semiconductor structure of claim 14,

the gate dielectric layer comprises two insulating dielectric layers and a dielectric material arranged between the two insulating dielectric layers.

16. The semiconductor structure of claim 15,

and an air gap is also arranged between two insulating medium layers in the gate medium layers.

17. The semiconductor structure of claim 15,

and the projection of one isolation part in the direction vertical to the height direction of the channel structure at least covers one layer of dielectric material in the gate dielectric layer.

18. The semiconductor structure of claim 16,

a dielectric material is filled between every two adjacent barrier parts; and/or an air gap is arranged between two adjacent blocking parts.

19. A three-dimensional memory, comprising:

a semiconductor structure as claimed in any one of claims 13 to 18;

a peripheral device electrically connected to the semiconductor structure.

20. A storage system, comprising:

a three-dimensional memory, the three-dimensional memory of claim 19;

a controller coupled to the three-dimensional memory to control the three-dimensional memory to store data.