CN115440741A

CN115440741A - Semiconductor structure, preparation method thereof and three-dimensional memory

Info

Publication number: CN115440741A
Application number: CN202211079935.4A
Authority: CN
Inventors: 张坤; 吴林春; 周文犀
Original assignee: Yangtze Memory Technologies Co Ltd
Current assignee: Yangtze Memory Technologies Co Ltd
Priority date: 2022-09-05
Filing date: 2022-09-05
Publication date: 2022-12-06

Abstract

The disclosure provides a semiconductor structure, a preparation method thereof and a three-dimensional memory, relates to the technical field of semiconductor chips, and aims to solve the problem that the memory capacity of the three-dimensional memory in the related art is small. The semiconductor structure includes: the grid line gap structure extends from the first area to the second area and comprises an isolation structure, a first separation structure and a second separation structure, wherein the isolation structure is located in the first area and located between the first separation structure and the second separation structure. In the process of removing part of the sacrificial layer twice, the isolation structure is favorable for blocking etching liquid from flowing into the region where the other side is located, so that the extension length of the transition region in the first region is favorable for being shortened, and the storage capacity is improved. The semiconductor structure is applied to a three-dimensional memory to realize reading and writing operations of data.

Description

Semiconductor structure, preparation method thereof and three-dimensional memory

Technical Field

The present disclosure relates to the field of semiconductor chip technologies, and in particular, to a semiconductor structure, a method for manufacturing the same, a three-dimensional memory, a storage system, and an electronic device.

Background

As the feature size of memory cells approaches the lower process limit, planar processes and manufacturing techniques become challenging and costly, which causes the storage density of 2D or planar NAND flash memories to approach the upper limit.

To overcome the limitations imposed by 2D or planar NAND flash memories, memories having a three-dimensional structure (3D NAND) have been developed to increase the storage density by arranging memory cells three-dimensionally over a substrate.

However, the memory of the three-dimensional structure in the related art has a problem of small storage capacity.

Disclosure of Invention

Embodiments of the present disclosure provide a semiconductor structure, a method for manufacturing the same, a three-dimensional memory, a storage system, and an electronic device, and aim to solve the problem in the related art that a storage capacity of a three-dimensional memory is small.

In order to achieve the above purpose, the embodiments of the present disclosure adopt the following technical solutions:

in one aspect, a semiconductor structure is provided. The semiconductor structure comprises a stacked structure and a grid line gap structure, wherein the stacked structure comprises grid layers and dielectric layers which are alternately stacked; the stacked structure includes a first region and a second region adjacent to the first region. The grid line gap structure extends from the first region to the second region and penetrates through the stacked structure; the gate line gap structure includes an isolation structure, a first isolation structure, and a second isolation structure, the isolation structure being located in the first region and between the first isolation structure and the second isolation structure.

The above embodiments of the present disclosure provide a semiconductor structure, comprising: the stacked structure comprises gate layers and dielectric layers which are alternately stacked, and the stacked structure comprises a first area and a second area adjacent to the first area; a gate line gap structure extending from the first region to the second region, the gate line gap structure penetrating the stack structure; the grid line gap structure comprises an isolation structure, a first isolation structure and a second isolation structure, wherein the isolation structure is located in the first area and located between the first isolation structure and the second isolation structure. This disclosed embodiment is through setting up isolation structure, when getting rid of the sacrificial layer around the first partition structure, isolation structure is favorable to blockking in the regional at etching liquid inflow second partition structure place, and simultaneously, when getting rid of the sacrificial layer around the second partition structure, isolation structure is favorable to blockking in the regional at etching liquid inflow first partition structure place, and then is favorable to shortening the extension length of transition zone in the first district, the extension length of the effective storage area of extension first district, the storage capacity of three-dimensional memory is improved. Here, the "transition region" may refer to a region between the isolation structure and the second region.

In some embodiments, the isolation structure comprises an isolation pillar and a plurality of isolation layers disposed around the isolation pillar; the isolation columns penetrate through the stacked structure along a direction perpendicular to the dielectric layers, the isolation layers and the dielectric layers are alternately stacked, and one isolation layer and one gate layer are arranged on the same layer.

In some embodiments, the first separation structure extends into the isolation layer near an end of the second separation structure, and/or the second separation structure extends into the isolation layer near an end of the first separation structure.

In some embodiments, a width of the isolation pillar in a first direction is less than or equal to a multiple of 1.5 of a width of the first partition structure in the first direction; the first direction is perpendicular to the extending direction of the gate line gap structure and parallel to the gate layer.

In some embodiments, a width of the isolation layer in a first direction is greater than or equal to a width of the first separation structure in the first direction; the first direction is perpendicular to the extending direction of the grid line gap structure and parallel to the grid layer.

In some embodiments, half of a width of the isolation layer in the first direction is less than half of a center distance between two adjacent first separation structures; the first direction is perpendicular to the extending direction of the gate line gap structure and parallel to the gate layer.

In some embodiments, the number of the gate line slit structures is plural, and the plural gate line slit structures are arranged in parallel with each other.

In some embodiments, at least two of the isolation structures are staggered along the first direction, and the distance between the staggered two isolation structures along the second direction ranges from 50nm to 250nm;

the first direction is perpendicular to the extending direction of the grid line gap structure and is parallel to the grid layer; the second direction is parallel to the extending direction of the grid line gap structure;

in some embodiments, a distance between any of the isolation structures and the second region ranges from 50nm to 750nm.

In some embodiments, the gate layer is disposed around the isolation structure, and the gate layer extends from the first region to the second region.

In some embodiments, further comprising: the first region comprises a plurality of channel structures, and the channel structures penetrate through the stacked structure; the second region comprises a plurality of contact structures, and the contact structures penetrate through part of the stacked structure; one of the contact structures is electrically connected to one of the gate layers.

In another aspect, a method for fabricating a semiconductor structure is provided, including: forming a stacked structure, wherein the stacked structure comprises gate layers and dielectric layers which are alternately stacked; the stacking structure comprises a first area and a second area adjacent to the first area; forming an isolation structure, wherein the isolation structure is positioned in the first region; forming a first separation structure and a second separation structure, the separation structure being located between the first separation structure and the second separation structure; the first separation structure, the second separation structure and the isolation structure jointly form a grid line gap structure, and the grid line gap structure extends from the first region to the second region and penetrates through the stacked structure.

In some embodiments, the forming a stacked structure comprises: forming a laminated structure, wherein the laminated structure comprises sacrificial layers and dielectric layers which are alternately laminated; the forming of the isolation structure comprises: forming a sacrificial hole, wherein the sacrificial hole penetrates through the laminated structure; removing a portion of the sacrificial layer through the sacrificial hole to form a sacrificial gap; and filling an isolation material in the sacrificial gap to form an isolation layer, and filling an isolation material in the sacrificial hole to form an isolation column, wherein the isolation column and the isolation layer jointly form the isolation structure.

In some embodiments, the forming a stacked structure comprises: forming a second isolation groove on one side of the isolation structure, wherein the second isolation groove penetrates through the laminated structure and extends from the first area to the second area; replacing a portion of the sacrificial layer with a second portion of the gate layer via the second separation trench; forming a first separation groove on the other side of the isolation structure, wherein the first separation groove penetrates through the laminated structure and is positioned in the first area; replacing a portion of the sacrificial layer with a first portion of the gate layer via the first spacer trench; the first part of the gate layer and the second part of the gate layer jointly form the gate layer, and the gate layer and the dielectric layer jointly form the stack structure.

In some embodiments, the forming the first and second partition structures comprises: forming a first separation structure in the first separation groove; forming a second separation structure in the second separation groove; the first separation structure, the second separation structure and the isolation structure jointly form a grid line gap structure.

In some embodiments, the forming a stacked structure further comprises: forming a plurality of channel holes in the first region and penetrating through the laminated structure; after the forming of the isolation structure and before the forming of the first isolation trench and the second isolation trench, the method further includes: and filling a channel material in the channel hole to form a channel structure.

In some embodiments, further comprising: forming a plurality of contact holes in the second region and penetrating through a part of the stacked structure; and forming contact structures in the contact holes, wherein one contact structure of the stacked structures is electrically connected with one grid layer.

In yet another aspect, a three-dimensional memory is provided. The three-dimensional memory includes the semiconductor structure as described in some embodiments above, and a peripheral device electrically connected to the semiconductor structure.

In yet another aspect, a storage system is provided, including: the memory device comprises a three-dimensional memory as described above, and a controller coupled to the three-dimensional memory to control the three-dimensional memory to store data.

In yet another aspect, an electronic device is provided, comprising the storage system as described above.

It can be understood that the beneficial effects of the manufacturing method of the semiconductor structure, the three-dimensional memory, the storage system and the electronic device provided by the embodiments of the disclosure can refer to the beneficial effects of the semiconductor structure mentioned above, and are not described herein again.

Drawings

In order to more clearly illustrate the technical solutions in the present disclosure, the drawings needed to be used in some embodiments of the present disclosure will be briefly described below, and it is apparent that the drawings in the following description are only drawings of some embodiments of the present disclosure, and other drawings can be obtained by those skilled in the art according to the drawings. Furthermore, the drawings in the following description may be considered as schematic diagrams, and do not limit the actual size of products, the actual flow of methods, the actual timing of signals, and the like, involved in the embodiments of the present disclosure.

FIG. 1 is a schematic structural diagram of a three-dimensional memory according to an embodiment of the related art;

fig. 2 is a schematic perspective view of a three-dimensional memory according to an embodiment of the disclosure;

fig. 3 is a first schematic structural diagram of a semiconductor structure according to an embodiment of the present disclosure;

FIG. 4 is an enlarged view of a portion of FIG. 3 at A;

FIG. 5 is a cross-sectional view of the structure of FIG. 4 along section line C-C;

fig. 6 is a second schematic structural diagram of a semiconductor structure according to an embodiment of the present disclosure;

fig. 7 is a flowchart illustrating steps in a method of fabricating a semiconductor structure according to an embodiment of the present disclosure;

fig. 8 is a schematic structural diagram of a stacked structure formed in a method for manufacturing a semiconductor structure according to an embodiment of the present disclosure;

fig. 9 is a schematic structural diagram of a mask layer formed in a method for manufacturing a semiconductor structure according to an embodiment of the present disclosure;

fig. 10 is a schematic structural view of a sacrificial gap formed in a method for fabricating a semiconductor structure according to an embodiment of the present disclosure;

fig. 11 is a schematic structural diagram of an isolation structure formed in a method for manufacturing a semiconductor structure according to an embodiment of the present disclosure;

fig. 12 is a schematic structural diagram of a channel structure formed in a method for manufacturing a semiconductor structure according to an embodiment of the present disclosure;

fig. 13 is a schematic structural diagram of a first sacrificial sidewall and a second sacrificial sidewall formed in a method for manufacturing a semiconductor structure according to an embodiment of the present disclosure;

fig. 14 is a schematic structural diagram of a second isolation trench formed in a method for manufacturing a semiconductor structure according to an embodiment of the present disclosure;

fig. 15 is a schematic structural diagram of a second space formed in a method for manufacturing a semiconductor structure according to an embodiment of the present disclosure;

fig. 16 is a schematic structural diagram of a second sacrificial pattern formed in a method for manufacturing a semiconductor structure according to an embodiment of the present disclosure;

fig. 17 is a schematic structural diagram of a third sacrificial pattern formed in a method for manufacturing a semiconductor structure according to an embodiment of the present disclosure;

fig. 18 is a schematic structural view of a first isolation trench formed in a method for fabricating a semiconductor structure according to an embodiment of the present disclosure;

fig. 19 is a schematic structural diagram of a first space formed in a method for manufacturing a semiconductor structure according to an embodiment of the present disclosure;

fig. 20 is a schematic structural view of a first isolation trench and a second isolation trench formed in a method for manufacturing a semiconductor structure according to an embodiment of the present disclosure;

fig. 21 is a schematic structural diagram of a first isolation structure and a second isolation structure formed in a method for manufacturing a semiconductor structure according to an embodiment of the present disclosure;

fig. 22 is a first block diagram of a storage system according to an embodiment of the present disclosure;

fig. 23 is a second block diagram of a storage system according to an embodiment of the present disclosure.

Detailed Description

Technical solutions in some embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings, and it is obvious that the described embodiments are only a part of the embodiments of the present disclosure, and not all of the embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments provided by the present disclosure belong to the protection scope of the present disclosure.

In the description of the present disclosure, it is to be understood that the terms "center", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like indicate orientations or positional relationships based on those shown in the drawings, merely for convenience in describing the present disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed in a particular orientation, and be operated, and therefore, should not be construed as limiting the present disclosure.

Throughout the specification and claims, the term "comprising" is to be interpreted in an open, inclusive sense, i.e., as "including, but not limited to," unless the context requires otherwise. In the description herein, the terms "one embodiment," "some embodiments," "an example embodiment," "exemplary" or "some examples" or the like are intended to mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the disclosure. The schematic representations of the above terms are not necessarily referring to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics may be included in any suitable manner in any one or more embodiments or examples.

In the following, the terms "first", "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the embodiments of the present disclosure, "a plurality" means two or more unless otherwise specified.

In describing some embodiments, the expressions "coupled" and "connected," along with their derivatives, may be used. For example, the term "connected" may be used in describing some embodiments to indicate that two or more elements are in direct physical or electrical contact with each other. As another example, some embodiments may be described using the term "coupled" to indicate that two or more elements are in direct physical or electrical contact. The term "coupled," however, may also mean that two or more elements are not in direct contact with each other, but yet still co-operate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents herein.

"at least one of A, B and C" has the same meaning as "at least one of A, B or C" and includes the following combinations of A, B and C: a alone, B alone, C alone, a combination of A and B, A and C in combination, B and C in combination, and A, B and C in combination.

"A and/or B" includes the following three combinations: a alone, B alone, and a combination of A and B.

The use of "adapted to" or "configured to" herein means open and inclusive language that does not exclude devices adapted to or configured to perform additional tasks or steps.

Additionally, the use of "based on" means open and inclusive, as a process, step, calculation, or other action that is "based on" one or more stated conditions or values may in practice be based on additional conditions or values beyond those stated.

As used herein, "about," "approximately," or "approximately" includes the stated values as well as average values that are within an acceptable range of deviation for the particular value, as determined by one of ordinary skill in the art in view of the measurement in question and the error associated with measurement of the particular quantity (i.e., the limitations of the measurement system).

In the context of this disclosure, the meaning of "over 8230 \8230; over", "above", and "over" should be interpreted in the broadest manner such that "over" means not only "directly over something", but also includes the meaning of "over something" with intervening features or layers therebetween, and "over" or "over" means not only "over" or "above" something, but also includes the meaning of "over" or "above" something (i.e., directly over something) without intervening features or layers therebetween.

Example embodiments are described herein with reference to cross-sectional and/or plan views as idealized example figures. In the drawings, the thickness of layers and regions are exaggerated for clarity. Variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, example embodiments should not be construed as limited to the shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the exemplary embodiments.

As used herein, the term "substrate" refers to a material onto which subsequent layers of material may be added. The substrate itself may be patterned. The material added on the substrate may be patterned or may remain unpatterned. In addition, the substrate may include a variety of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, and the like. Alternatively, the substrate may be made of a non-conductive material such as glass, plastic, or sapphire wafer.

The term "three-dimensional memory" refers to a semiconductor device formed of strings of memory cell transistors (referred to herein as "strings of memory cells," e.g., NAND strings of memory cells) arranged in an array on a major surface of a substrate or a source layer and extending in a direction perpendicular to the substrate or source layer. As used herein, the term "vertically" means nominally perpendicular to a major surface (i.e., a lateral surface) of the substrate or source layer.

In a three-dimensional memory such as a 3D NAND flash memory, referring to fig. 1, a memory array may include a core area CA in which a plurality of channel structures 11 are disposed and a connection area SS in which a plurality of connection structures 12 are disposed. The memory array further includes a gate line structure 203, and the gate line structure 203 includes a first gate line structure located at the connection region SS and a second gate line structure located at the core region CA.

In the related art, with continued reference to fig. 1, the formation of the gate line structure 203 includes the following steps: forming a stacked structure 10, wherein the stacked structure 10 comprises dielectric layers and sacrificial layers which are alternately stacked; forming grid isolation grooves, wherein the grid isolation grooves comprise first isolation grooves located in the connection area SS and second isolation grooves located in the core area CA; forming a first isolation part in the first isolation groove; removing a part of the sacrificial layer in the core area CA through the second isolation groove to form a second gap; removing the first isolation part; removing a portion of the sacrificial layer located at the connection region SS through the first isolation groove to form a first gap; forming a gate layer 50 in the first gap and the second gap, wherein the gate layer 50 is used for leading out control gates in layers in the channel structure 11 to the connection structure 12 of the connection region SS, so that functions of reading, erasing, programming and the like are realized; a gate line structure 203 is formed in the first and second trenches. The core area CA comprises a transition area CA1 adjacent to the link area SS, so that etching of the contact structure 12 in the link area SS during removal of a part of the sacrificial layer via the second spacer trench is avoided, while etching of the channel structure 11 in the core area CA during removal of a part of the sacrificial layer via the first spacer trench is avoided. However, the extended length of the transition area CA1 in the related art is long, so that the extended length of the effective memory area CA2 of the core area CA is short, resulting in a small memory capacity of the memory.

Embodiments of the present disclosure provide a semiconductor structure, a method for fabricating the same, and a three-dimensional memory. The semiconductor structure includes: a gate line gap structure extending from the first region to the second region, the gate line gap structure penetrating the stack structure; the grid line gap structure comprises an isolation structure, a first isolation structure and a second isolation structure, wherein the isolation structure is located in the first area and located between the first isolation structure and the second isolation structure. By arranging the isolation structure, when the sacrificial layer around the first isolation structure is removed, the isolation structure is favorable for preventing the etching liquid from flowing into the area where the second isolation structure is located, and meanwhile, when the sacrificial layer around the second isolation structure is removed, the isolation structure is favorable for preventing the etching liquid from flowing into the area where the first isolation structure is located. Compare in the correlation technique, through setting up the longer transition zone consumption etching liquid of extension length, this disclosed embodiment stops the flow of etching liquid through setting up isolation structure, is favorable to shortening the extension length of transition zone in the first district, prolongs the extension length of the effective memory area of first district, and then improves the storage capacity of three-dimensional memory. Here, the "transition region" refers to a region in the first region which is adjacent to the second region; by "active storage area" is meant the area within the first area, on the side of the transition area remote from the second area.

Fig. 2 is a schematic perspective view of a three-dimensional memory according to an embodiment of the disclosure. Note that, in fig. 2, the three-dimensional memory 601 extends in an X-Y plane, and the first direction X and the second direction Y are, for example, two orthogonal directions in a plane (e.g., a plane in which the source layer SL is located) in which the semiconductor structure 200 is located: the first direction X is, for example, an extending direction of a word line, and the second direction Y is, for example, an extending direction of a bit line. The third direction Z is perpendicular to the plane of the semiconductor structure 200, i.e., perpendicular to the X-Y plane.

As used in this disclosure, whether a component (e.g., a layer, structure, or device) is "on," "above," or "below" another component (e.g., a layer, structure, or device) of a semiconductor device (e.g., a three-dimensional memory) is determined in a third direction Z relative to a substrate or a source layer of the semiconductor device when the substrate or the source layer is located in a lowest plane of the semiconductor device in the third direction Z. Throughout this disclosure, the same concepts are applied to describe spatial relationships.

In order to show the structure of the device more clearly, in fig. 2, a view of the core area CA and a view of the connection area SS are shown, the view of the core area CA is based on a left coordinate system, the view of the connection area SS is based on the left coordinate system, that is, the view of the core area CA shows a cross-sectional structure along the Y direction, and the view of the connection area SS shows a cross-sectional structure along the X direction.

The embodiment of the present disclosure provides a three-dimensional memory 601, and the three-dimensional memory 601 may include a semiconductor structure 200. The three-dimensional memory 601 may further include a source layer SL coupled to the semiconductor structure 200, and a peripheral device 600 coupled to the semiconductor structure 200. The peripheral device 600 may be disposed on a side of the semiconductor structure 200 away from the source layer SL.

The source layer SL may include a semiconductor material such as single crystal silicon, single crystal germanium, a III-V compound semiconductor material, a II-VI compound semiconductor material, and other suitable semiconductor materials. The source layer SL may be partially or fully doped. Illustratively, the source layer SL may include a doped region doped with a p-type dopant. The source layer SL may further include an undoped region.

The semiconductor structure 200 may include memory cell transistor strings (referred to herein as "memory cell strings 640," e.g., NAND memory cell strings 640) arranged in an array. The source layer SL may be coupled to sources of the plurality of memory cell strings 640. With continued reference to fig. 2, in some embodiments, the semiconductor structure 200 may further include an array interconnect layer 290. Array interconnect layer 290 may be coupled with memory cell string 640. The array interconnect layer 290 may include drain terminals (i.e., bit lines) of the memory cell strings 640, which may be coupled to semiconductor channels of respective transistors in at least one of the memory cell strings 640.

The array interconnect layer 290 may include one or more first interlayer insulating layers 292, and may further include a plurality of contacts insulated from each other by the first interlayer insulating layers 292, the contacts including, for example, bitline contacts BL-CNT coupled to bitlines; a drain select gate contact coupled to the drain select gate; the gate line contact 293 is coupled to the gate layer 50. The array interconnect layer 290 may also include one or more first interconnect conductor layers 291. The first interconnect conductor layer 291 may include a plurality of connection lines, such as bit lines, and word line connection lines coupled to word lines. The material of the first interconnect conductor layer 291 and the contacts may be a conductive material such as a combination of one or more of tungsten, cobalt, copper, aluminum, and metal silicide, and may be other suitable materials. The material of the first interlayer insulating layer 292 is an insulating material, such as silicon oxide, silicon nitride, and a combination of one or more of high-k insulating materials, or other suitable materials.

The peripheral device 600 may include peripheral circuitry. The peripheral circuitry is configured to control and sense the array device. The peripheral circuitry may be any suitable digital, analog, and/or mixed signal control and sensing circuitry for supporting array device operation (or working), including but not limited to page buffers, decoders (e.g., row and column decoders), sense amplifiers, drivers (e.g., word line drivers), charge pumps, current or voltage references, or any active or passive component of circuitry (e.g., transistors, diodes, resistors, or capacitors). The peripheral circuitry may also include any other circuitry compatible with advanced Logic processes, including Logic circuitry (e.g., processors and Programmable Logic Devices (PLDs) or Memory circuitry (e.g., static RanDom Access Memory (SRAM)).

Specifically, in some embodiments, the peripheral device 600 may include a substrate 610, a transistor 620 disposed on the substrate 610, and a peripheral interconnect layer 630 disposed on the substrate 610. The peripheral circuitry may include a transistor 620.

The substrate 610 may be a single crystal silicon, or may be other suitable materials, such as silicon germanium, or a silicon-on-insulator film.

The peripheral interconnect layer 630 is coupled to the transistor 620 to enable the transmission of electrical signals between the transistor 620 and the peripheral interconnect layer 630. The peripheral interconnect layer 630 may include one or more second interlayer insulating layers 631 and may further include one or more second interconnect conductor layers 632. Different second interconnect conductor layers 632 may be coupled to each other by contacts. The material of the second interconnect conductor layer 632 and the contacts may be a conductive material, such as a combination of one or more of tungsten, cobalt, copper, aluminum, and metal silicide, and may be other suitable materials. The material of the second interlayer insulating layer 631 is an insulating material, such as one or a combination of silicon oxide, silicon nitride, and a high-k insulating material, and may be other suitable materials.

The peripheral interconnect layer 630 may be coupled with the array interconnect layer 290 such that the semiconductor structure 200 and the peripheral device 600 may be coupled. Specifically, since the peripheral interconnect layer 630 is coupled with the array interconnect layer 290, peripheral circuits in the peripheral device 600 may be coupled with the memory cell strings 640 in the semiconductor structure 200 to enable transmission of electrical signals between the peripheral circuits and the memory cell strings 640. In some possible implementations, a bonding interface 700 may be disposed between the peripheral interconnection layer 630 and the array interconnection layer 290, and the peripheral interconnection layer 630 and the array interconnection layer 290 may be bonded and coupled to each other through the bonding interface 700.

Fig. 3 is a first schematic structural diagram of a semiconductor structure according to an embodiment of the present disclosure; FIG. 4 is an enlarged view of a portion of FIG. 3 at A; FIG. 5 is a cross-sectional view of the structure of FIG. 4 taken along section line C-C; fig. 6 is a second schematic structural diagram of a semiconductor structure according to an embodiment of the present disclosure. Based on this, the embodiment of the present disclosure also provides a semiconductor structure 200. The semiconductor structure 200 includes a stack structure 10 and a gate line slit structure 20. The stacked structure 10 may be disposed on a substrate (not shown). It should be noted that, in fig. 3, 4, 5 and 6, the first direction X is perpendicular to the extending direction of the gate line slit structure 20 and parallel to the gate layer 50; the second direction Y is parallel to the extending direction of the gate line slit structure 20; the third direction Z is perpendicular to the X-Y plane.

Referring to fig. 2 and 3, the stacked structure 10 includes gate layers 50 and dielectric layers 80 alternately stacked. It is understood that the alternating stacked arrangement means that the gate layer 50 and the dielectric layer 80 are stacked and arranged in an alternating manner; for example, in a direction from the bottom layer to the top layer of the stacked structure 10, a gate layer 50 is disposed first, a dielectric layer 80 is disposed on the gate layer 50, and then a gate layer 50 is disposed on the dielectric layer 80, which are alternated cyclically to form the stacked structure 10. The specific number of stacked layers of the gate layer 50/dielectric layer 80 can be set according to practical situations. The gate layer 50 may be made of a conductive material, and may include, for example, one or a combination of tungsten, cobalt, copper, aluminum, doped silicon, and/or silicide. Dielectric layer 80 may be made of an insulating material and may include, for example, one or a combination of silicon oxide, silicon nitride, and silicon oxynitride.

The stacked structure 10 includes a first area AA and a second area BB adjacent to the first area AA. Illustratively, the first region AA comprises a core region CA and the second region BB comprises a joining region SS.

For convenience of description, the following description will take the first region AA as the core region CA and the second region BB as the connecting region SS as an example. The first area AA includes a transition area AA1 and an effective storage area AA2, the transition area AA1 is adjacent to the second area BB, the transition area AA1 may be located between the isolation structure 23 and the second area BB, and the transition area AA1 may have a storage function or may partially have a storage function. The effective storage area AA2 may be located on the side of the transition area AA1 remote from the second area BB. Among them, the effective storage area AA2 has a storage function.

A plurality of channel structures 11 may be included in the first area AA, and the channel structures 11 penetrate through the stacked structure 10. The channel structure 11 may be a substantially columnar structure, and a blocking layer, a storage layer, a tunneling layer, a channel layer, and a filling layer are sequentially disposed along a direction perpendicular to an extending direction thereof. Wherein the barrier layer may comprise a layer, for example, the barrier layer comprises silicon dioxide (SiO) ₂ ) A layer; the barrier layer may also comprise multiple layers, for example, a barrier layer comprising silicon dioxide and aluminum oxide (Al) ₂ O ₃ ) And (5) laminating. The memory layer may include a layer, for example, a memory layer including a silicon nitride (SiN) layer; the memory layer may also comprise multiple layers, for example, the memory layer comprises a stack of silicon nitride, silicon oxynitride (SiON), silicon nitride. The tunneling layer can include multiple layers, e.g., the tunneling layer includes silicon monoxide (SiO), oxynitrideSilicon oxide, silicon oxide stack. The material of the channel layer may include a semiconductor material, for example, polycrystalline silicon and/or monocrystalline silicon. The material of the fill layer may include an insulating material, such as silicon dioxide.

It should be noted that, in some embodiments, a plurality of semiconductor plugs may be disposed in the first area AA. In some examples, the semiconductor plug is formed at the bottom of the channel structure 11, i.e., a bottom SEG (Selective epitaxial Growth); in other examples, the semiconductor plug surrounds a sidewall of the channel structure 11 near one end of the substrate, i.e., the sidewall SEG. In some examples, the semiconductor plug comprises N-type polysilicon, and the sidewall SEG forms a SWNN (Side Wall N-poly/N-Sub) structure. In some embodiments, the SWNN (Side Wall N-poly/N-Sub) structure may generate a gate-induced-drain-leakage (GIDL) assisted body bias voltage when performing an erase operation on the 3D memory device, and is therefore also referred to as a "GIDL erase". The above inventive concepts provided by the disclosed embodiments are applicable to both of the above structures.

A plurality of contact structures 12 may be disposed in the second region BB, and the contact structures 12 penetrate through a portion of the stacked structure 10. Referring to fig. 2, the contact structure 12 includes a body portion 121 and an extension portion 122. An extension portion 122 is electrically connected to a gate layer 50 and disposed at the same layer as the gate layer 50. The body portion 121 is joined to the extension portion 122 and extends through the gate layer 50 at a side of the stacked structure 10 away from the source layer. Through the above arrangement, one contact structure 12 is electrically connected to one gate layer 50, so that the contact structure 12 can control the channel structure 11 through the gate layer 50, thereby implementing functions of reading, erasing, programming, and the like.

The second region BB may further comprise a plurality of dummy channel structures (not shown in the figure). A plurality of dummy channel structures extend through the stacked structure 10. The dummy channel structure may be the same as or different from the channel structure 11, and the embodiment of the disclosure is not limited thereto. It should be noted that the dummy channel structure may not actually serve as a memory cell, but rather serves to provide mechanical support and/or load balancing for the three-dimensional memory.

The semiconductor structure 200 further includes a gate line slit structure 20 extending from the first region AA to the second region BB, the gate line slit structure 20 penetrating the stacked structure 10. The gate line slit structure 20 includes an isolation structure 23, a first isolation structure 21, and a second isolation structure 22, and the isolation structure 23 is located in the first region AA and between the first isolation structure 21 and the second isolation structure 22. The gate line slit structure 20 is used to divide the stacked structure 10 into a plurality of block structures (blocks). Illustratively, the first partition structure 21 is located in the first region AA, and the second partition structure 22 extends from the first region AA to the second region BB. The isolation structure 23 may be made of silicon nitride, silicon oxide, or silicon oxynitride.

It should be noted that, during the manufacturing process of the stacked structure 10, it is necessary to provide the sacrificial layers and the dielectric layers 80 alternately stacked, and remove a portion of the sacrificial layers through the grooves where the gate line slit structures 20 are located, and replace the sacrificial layers with the gate electrode layers 50, thereby forming the stacked structure 10. That is, the stacked structure 10 further includes the remaining sacrificial layer, and the sacrificial layer is disposed at the same layer as the gate layer 50. Referring to fig. 3, the sacrificial layer on the side of the isolation structure 23 away from the second region BB may be entirely replaced with the gate layer 50, and the sacrificial layer on the side of the isolation layer 232 close to the second region BB may be partially replaced with the gate layer 50. For example, the gate layer 50 may be disposed around the isolation structure 23, and the gate layer 50 may extend from the first region AA to the second region BB, so as to improve the electrical connection effect between the channel structure 11 in the first region AA and the contact structure 12 in the second region BB, and further improve the performance of the semiconductor structure 200.

As described in the foregoing embodiment, the provision of the transition area AA1 is beneficial to preventing the excessive etching liquid from directly flowing into the channel structure 11 of the first area AA when the peripheral sacrificial layer is removed through the groove where the first separation structure 21 is located, so as to avoid etching to the channel structure 11; meanwhile, when the surrounding sacrificial layer is removed through the groove where the second isolation structure 22 is located, the excessive etching liquid is prevented from directly flowing into the contact structure 12 of the second area BB, so that the etching to the contact structure 12 is avoided, and the performance of the semiconductor structure 200 is further improved.

In some embodiments, the transition area AA1 may include a plurality of dummy channel structures 11, and as described in the above embodiments, the dummy channel structures may not be actually used as memory cells, so that the transition area AA1 does not have a memory function. In some other embodiments, the transition area AA1 may include a plurality of channel structures 11 and a plurality of dummy channel structures, and the channel structures 11 are disposed around the second partition structure 22, so that a part of the transition area AA1 may have a memory function.

To sum up, by providing the isolation structure 23, when removing the sacrificial layer around the first isolation structure 21, the isolation structure 23 is favorable for blocking the etching liquid from flowing into the region where the second isolation structure 22 is located, and meanwhile, when removing the sacrificial layer around the second isolation structure 22, the isolation structure 23 is favorable for blocking the etching liquid from flowing into the region where the first isolation structure 21 is located. Compared with the related art, the etching liquid is consumed by arranging the transition area AA1 with a longer extension length, the isolation structure 23 is arranged to block the flowing of the etching liquid, so that the extension length of the transition area AA1 in the first area AA is favorably shortened, the extension length of the effective storage area AA2 of the first area AA is prolonged, and the storage capacity of the three-dimensional memory 601 is further improved.

Referring to fig. 3, 4 and 5, the isolation structure 23 may include an isolation pillar 231 and a plurality of isolation layers 232 disposed around the isolation pillar 231. The isolation pillars 231 penetrate the stacked structure 10 in a direction perpendicular to the dielectric layer 80. Illustratively, the cross-sectional shape of the isolation pillars 231 may be rectangular, trapezoidal, or other polygonal shapes in a plane parallel to the gate layer 50, which is not limited by the embodiment. The isolation layers 232 and the dielectric layers 80 are alternately stacked in a direction perpendicular to the dielectric layers 80, and one isolation layer 232 and one gate layer 50 are disposed on the same layer. Illustratively, the cross-sectional shape of the isolation layer 232 may include an arc shape in a plane parallel to the gate layer 50, which is not limited by the embodiment. Through the arrangement, the contact area between the isolation structure 23 and the stack structure 10 is increased, the isolation structure 23 plays a role in adhesion, stripping between film layer structures is avoided when a sacrificial layer is removed, and therefore the performance of the semiconductor structure 200 is improved.

It is worth to be noted that, along the direction perpendicular to the dielectric layer 80, the isolation layers 232 and the dielectric layers 80 are alternately stacked between the isolation pillar 231 and the second isolation groove 221, the structure is a second sub-isolation portion B2, and the second sub-isolation portion B2 and the isolation pillar 231 can both play an isolation role; the isolation layer 232 and the dielectric layer 80 are alternately stacked between the isolation pillar 231 and the first isolation groove 211, the structure is a first sub-isolation part B1, and the first sub-isolation part B1 and the isolation pillar 231 can both play an isolation role.

An end of the first partition structure 21 near the second partition structure 22 may extend into the isolation layer 232, and/or an end of the second partition structure 22 near the first partition structure 21 may extend into the isolation layer 232. Referring to fig. 4, the isolation layer 232 of the isolation structure 23 is provided with a first groove 233, an extending direction of the first groove 233 is parallel to an extending direction of the isolation pillar 231, an opening direction of the first groove 233 deviates from the second area BB, and one end of the first isolation structure 21 close to the second isolation structure 22 extends into the first groove 233, so that a contact area between one end of the first isolation structure 21 close to the second isolation structure 22 and the isolation layer 232 is increased, which is beneficial to improving a bonding effect between the first isolation structure 21 and the isolation structure 23.

Similarly, a second groove 234 opposite to the first groove 233 may be further disposed in the isolation layer 232 of the isolation structure 23, an extending direction of the second groove 234 is parallel to an extending direction of the isolation pillar 231, an opening direction of the second groove 234 is close to the second area BB, and one end of the second isolation structure 22 close to the first isolation structure 21 extends into the second groove 234, so that a contact area between one end of the second isolation structure 22 close to the first isolation structure 21 and the isolation layer 232 is increased, which is beneficial to improving a bonding effect between the second isolation structure 22 and the isolation structure 23.

In some other embodiments, an end of the first partition structure 21 near the second partition structure 22 may be directly joined with the isolation layer 232, and/or an end of the second partition structure 22 near the first partition structure 21 may be directly joined with the isolation layer 232.

Referring to fig. 4, the width H1 of the isolation pillars 231 in the first direction X may be less than or equal to a multiple value of 1.5 of the width H2 of the first partition structure 21 in the first direction X. For example, the width H2 of the first partition structure 21 in the first direction X may be equal to the width of the second partition structure 22 in the second direction Y, the width H2 may be 200nm, and the width H1 of the isolation pillar 231 in the first direction X may be less than or equal to 300nm. Because the channel structure 11 is disposed at the edges of the first isolation structure 21 and the second isolation structure 22, by defining the width of the isolation pillar 231 along the first direction X, it is beneficial to avoid the isolation pillar 231 from being oversized to cause damage to the channel structure 11, thereby avoiding the occurrence of electric leakage in the channel structure 11.

Referring to fig. 4, a width H3 of the isolation layer 232 in the first direction X may be greater than or equal to a width H2 of the first partition structure 21 in the first direction X. Through the above arrangement, the isolation layer 232 can isolate the first separation structure 21 from the second separation structure 22, when the sacrificial layer around the first separation structure 21 is removed, the isolation structure 23 is favorable for blocking the etching liquid from flowing into the region where the second separation structure 22 is located, and simultaneously, when the sacrificial layer around the second separation structure 22 is removed, the isolation structure 23 is favorable for blocking the etching liquid from flowing into the region where the first separation structure 21 is located. By setting the width H3 of the isolation layer 232 along the first direction X, the flow of the etching solution can be blocked, which is beneficial to shortening the extension length of the transition area AA1 in the first area AA and prolonging the extension length of the effective storage area AA2 of the first area AA, so that the storage capacity of the three-dimensional memory 601 is further improved.

Referring to fig. 3 and 4, half of the width H3 of the isolation layer 232 in the first direction X may be less than half of the center distance H4 between adjacent two first separation structures 21. Illustratively, by the above arrangement, it is beneficial to avoid the contact between the isolation layers 232 in two adjacent isolation structures 23. It is worth noting that since the isolation layer 232 is disposed on the same layer as the gate layer 50, when the isolation layer 232 in two adjacent isolation structures 23 is in contact, the two adjacent isolation structures 23 together form an isolation member, which disconnects the gate layer 50 in the effective storage area AA2 from the gate layer 50 in the transition area AA 1. It can be seen that half of the width H3 of the isolation layer 232 along the first direction X may be smaller than half of the center distance H4 between two adjacent first isolation structures 21, which is beneficial to ensuring the electrical connection effect between the channel structure 11 in the first area AA and the contact structure 12 in the second area BB, and further improving the performance of the semiconductor structure 200.

Meanwhile, by the arrangement, the isolation layer 232 in the isolation structure 23 is prevented from occupying too much space, and the storage capacity in the effective storage area AA2 is improved.

The number of the gate line slit structures 20 may be plural, and the plurality of gate line slit structures 20 are disposed at intervals along the first direction X. With continued reference to fig. 3, in fig. 3, for example, three gate line slit structures 20 may be provided, and the three gate line slit structures 20 may separate the stacked structure 10 into four block structures. In some embodiments, a plurality of sub-separation structures may be further disposed in the block structure, the sub-separation structures may be located in the second area BB, and the sub-separation structures extend along the second direction Y and are arranged at intervals along the second direction Y, so as to play a role of fixing and supporting the second area BB, which is beneficial to improving the stability of the semiconductor structure 200.

In some embodiments, referring to fig. 6, at least two isolation structures 23 may be disposed in a staggered manner along the first direction X. Through staggering the setting with at least two isolation structures 23, be favorable to avoiding staggering the environmental stress concentration that the isolation structure 23 that sets up belonged to, and then avoid the isolation structure 23 that forms to take place the skew, be difficult to damage channel structure 11 promptly.

Further, the range of the distance D1 between the two staggered isolation structures 23 along the second direction Y is 50nm to 250nm. For example, the distance D1 along the second direction Y of the two staggered isolation structures 23 may be 50nm, 150nm, or 250nm. The distance D1 between the two staggered isolation structures 23 along the second direction Y is greater than or equal to 50nm, which is beneficial to dispersing the stress in the environment where the isolation structures 23 are located; the distance D1 between the two staggered isolation structures 23 along the second direction Y is less than or equal to 250nm, which is beneficial to improving the structural compactness of the semiconductor structure 200 and reducing the extension length of the transition region AA 1.

In this embodiment, referring to fig. 3, a value of the distance D2 between any isolation structure 23 and the second area BB is in a range of 50nm to 750nm. In the related art, referring to fig. 1, in the process of removing a part of the sacrificial layer, the etching effect of the self-stop region P is poor, residues are easily left, the subsequent filling effect is poor, and the word line are easily broken down, so that the risk of electric leakage is increased. Here, the "self-stop region P" refers to the farthest boundary to which the etching liquid can flow. In this embodiment, by controlling the position of any isolation structure 23, a plurality of isolation structures 23 arranged along the first direction X can form a boundary structure, and then the distance between the self-stop region P in the etching process and the second direction Y is controlled, which is beneficial to solving the problem that the etching effect is too large, and further the electric leakage occurs between the word line and the word line.

Further, the distance D2 between any isolation structure 23 and the second region BB may be 50nm, 400nm, or 750nm. The distance D2 between any isolation structure 23 and the second area BB is greater than or equal to 50mm, so that a certain interval is favorably ensured between the self-stopping area P and the second area BB, and the etching liquid is prevented from flowing to the second area BB; the distance D2 between any isolation structure 23 and the second area BB is less than or equal to 750mm, which is beneficial to reducing the extension length of the transition area AA1, extending the extension length of the effective storage area AA2 of the first area AA, and improving the storage capacity.

In some other embodiments, the isolation structures 23 may be further sequentially arranged along the first direction X, which is beneficial to further improving the regularity of the semiconductor structure 200, and is also beneficial to simplifying the process and improving the manufacturing efficiency of the semiconductor structure 200.

Fig. 7 is a flowchart illustrating steps of a method for fabricating a semiconductor structure according to an embodiment of the present disclosure, and fig. 8 to 21 are schematic structural diagrams of the semiconductor structure according to the embodiment of the present disclosure at different fabrication stages. Please refer to fig. 7 in conjunction with fig. 8 to 21; some embodiments of the present disclosure provide a method of fabricating a semiconductor structure 200, the method comprising S1 to S3.

S1, forming a stacking structure, wherein the stacking structure comprises grid layers and dielectric layers which are alternately stacked; the stacked structure includes a first region and a second region adjacent to the first region.

It is worth mentioning that, before forming the stacked structure 10, the following steps may be further included: a substrate (not shown) is provided. The substrate may comprise, among other things, silicon (e.g., single crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), and/or any other suitable material. In some examples, the substrate comprises silicon, for example: monocrystalline silicon and polycrystalline silicon.

Fig. 8 is a schematic structural diagram of a stacked structure 102 formed in a method for manufacturing a semiconductor structure according to an embodiment of the present disclosure. Referring to fig. 8, the step of forming the stacked structure 10 includes: a stacked structure 102 is formed, the stacked structure 102 including the sacrificial layer and the dielectric layer 80 alternately stacked. The sacrificial layer and the dielectric layer 80 are made of two different materials, and the etching speed of the sacrificial layer is different from that of the dielectric layer 80 under the same process condition. In some examples, the sacrificial layer comprises a nitride (e.g., silicon nitride) and the dielectric layer 80 comprises an oxide (e.g., silicon oxide).

As in the previous embodiments, the stacked structure 102 also includes a first region AA and a second region BB, where the first region AA includes a core region and the second region BB includes a connecting region. It is understood that the drawings are illustrated with a first area AA and a second area BB, but the stacked structure 102 in the embodiment of the disclosure is not limited thereto, that is, the stacked structure 102 may be provided with the second area BB at the periphery of the first area AA, or provided with the second area BB in the middle of two first areas AA.

The step of forming the stacked structure 102 further comprises: a plurality of channel holes 101 are formed, wherein the channel holes 101 are located in the first region AA and penetrate through the stacked structure 102. It is noted that the stacked structure 102 includes a plurality of block structures extending along the second direction Y, and each block structure is provided with a plurality of channel holes 101, and the channel holes 101 are used for forming the channel structures 11. At the same time as the channel hole 101 is formed, a plurality of contact holes may be formed, which are located in the second region BB and penetrate through a portion of the stacked structure 10. The contact holes are used for the subsequent formation of the contact structures 12.

In some embodiments, a plurality of virtual channel holes may be simultaneously formed at the same time as the plurality of channel holes 101, the plurality of virtual channel holes all penetrate through the stacked structure 10, and the plurality of virtual channel holes are located in the second region BB. Of course, in other embodiments, a plurality of dummy trench holes may also be located in the first area AA, which is not limited by this embodiment. The dummy channel hole 101 is used to subsequently form a dummy channel structure.

In this embodiment, after the laminated structure 102 is formed, the method further includes:

and S2, forming an isolation structure, wherein the isolation structure is positioned in the first area.

Referring to fig. 9 to 11, the step of forming the isolation structure 23 includes: a sacrificial hole 201 is formed, the sacrificial hole 201 penetrating the stacked-layer structure 102. Illustratively, a plurality of sacrificial holes 201 may be formed, the sacrificial holes 201 may be located between the block structures, and at least two sacrificial holes 201 are arranged in a staggered manner along the first direction X. Of course, in some other embodiments, the sacrificial holes 201 may also be arranged in sequence along the first direction X.

Fig. 9 is a schematic structural diagram of a mask layer 30 formed in a method for manufacturing a semiconductor structure according to an embodiment of the present disclosure. Referring to fig. 9, after forming the sacrificial hole 201, the step of forming the isolation structure 23 further includes: a mask layer 30 is formed covering the top surface of the stacked structure 102, and the mask layer 30 has a mask opening 301, and the mask opening 301 coincides with the sacrificial hole 201.

Fig. 10 is a schematic structural diagram of a sacrificial gap 202 formed in a method for manufacturing a semiconductor structure according to an embodiment of the present disclosure. Referring to fig. 10, after forming mask layer 30, the step of forming isolation structure 23 further includes: a portion of the sacrificial layer is removed through the sacrificial hole 201 to form a sacrificial gap 202. For example, a wet etch process may be used to remove portions of the sacrificial layer. In some examples, the etching rate of the sacrificial layer is greater than the etching rate of the dielectric layer 80 under the etching conditions created by the etching liquid by selecting the etching liquid corresponding to the material of the sacrificial layer.

Fig. 11 is a schematic structural diagram of an isolation structure 23 formed in a method for manufacturing a semiconductor structure according to an embodiment of the present disclosure. Referring to fig. 11, after forming the sacrificial gap 202, the step of forming the isolation structure 23 further includes: the isolation material is filled in the sacrificial gap 202 to form an isolation layer 232, and the isolation material is filled in the sacrificial hole 201 to form an isolation pillar 231, and the isolation pillar 231 and the isolation layer 232 together constitute the isolation structure 23. Illustratively, the isolation layer 232 and the isolation pillar 231 are made of the same material, which is beneficial to simplifying the process and improving the manufacturing efficiency of the semiconductor structure 200. Meanwhile, the isolation structure 23 is formed at one time by filling the isolation material, which is beneficial to improving the bonding effect of the isolation column 231 and the isolation layer 232, and further improving the adhesion effect of the isolation structure 23. For example, the isolation material may include, for example, one or a combination of silicon nitride, silicon oxide, and silicon oxynitride.

The isolation structure 23 formed by the above process is beneficial to increasing the contact area between the isolation structure 23 and the stack structure 10, and the isolation structure 23 plays a role in adhesion, so that peeling between film layer structures is avoided when a sacrificial layer is removed, and the performance of the semiconductor structure 200 is improved.

Fig. 12 is a schematic structural diagram of a channel structure 11 formed in a method for manufacturing a semiconductor structure according to an embodiment of the present disclosure. Referring to fig. 12, in the present embodiment, after forming the isolation structure 23, the method further includes: a channel material is filled in the channel hole 101 to form a channel structure 11.

An OxiDe-NitriDe-OxiDe-polysilicon (OxiDe-nitred-OxiDe-Poly, ONOP) structure may be sequentially stacked in the channel hole 101. In this case, the material of the channel blocking layer may include, for example, silicon oxide, the material of the memory layer may include, for example, silicon nitride, the material of the tunneling layer may include, for example, silicon oxide, and the material of the channel layer may include, for example, polysilicon. In the above steps, a filling layer, such as silicon oxide, may be further formed in the trench hole where the memory layer and the channel layer are formed by using a thin film deposition process, such as CVD, PVD, or ALD.

It should be noted that, while the channel structure 11 is formed, filling may be performed in the dummy channel hole to synchronously form a dummy channel structure, that is, the dummy channel structure is completely the same as the channel structure 11. Of course, in some other embodiments, the dummy trench hole may be filled with an insulating material, that is, the dummy trench structure is different from the trench structure 11.

Referring to fig. 12, the partition structure 23 may partition the first area AA into a transition area AA1 and an effective storage area AA2. The transition area AA1 is adjacent to the second area BB, and the effective storage area AA2 is located on the side of the transition area AA1 away from the second area BB. Wherein, the effective storage area AA2 includes a plurality of channel structures 11 so that the effective storage area AA2 has a storage function.

In some embodiments, the transition area AA1 may include a plurality of dummy channel structures 11, and as described in the above embodiments, the dummy channel structures may not be actually used as memory cells, so that the transition area AA1 does not have a memory function. In some other embodiments, the transition area AA1 may include a plurality of channel structures 11 and a plurality of dummy channel structures, and the channel structures 11 are disposed around the second partition structure 22, so that a portion of the transition area AA1 may have a memory function.

In this embodiment, referring to fig. 13 to 18, after forming the isolation structure 23, the forming of the stacked structure 10 further includes: a second isolation trench 221 is formed at one side of the isolation structure 23, the second isolation trench 221 penetrates through the stacked structure 102, and the second isolation trench 221 extends from the first region AA to the second region BB.

Fig. 13 is a schematic structural diagram of a first sacrificial side wall 41 and a second sacrificial side wall 42 formed in a method for manufacturing a semiconductor structure according to an embodiment of the present disclosure. Referring to fig. 13, the step of forming the second separation groove 221 includes: forming a first sacrificial side wall 41 and a second sacrificial side wall 42, wherein the first sacrificial side wall 41 is located in the first area AA, the second sacrificial side wall 42 is located in the first area AA and the second area BB, one end of the first sacrificial side wall 41 close to the second sacrificial side wall 42 and the isolation layer 232 are alternately stacked, and one end of the second sacrificial side wall 42 close to the first sacrificial side wall 41 and the isolation layer 232 are alternately stacked.

Fig. 14 is a schematic structural diagram of a second isolation trench 221 formed in a method for manufacturing a semiconductor structure according to an embodiment of the present disclosure. Referring to fig. 14, while forming the first sacrificial sidewall 41 and the second sacrificial sidewall 42, a first sacrificial pattern 402 having a first sacrificial opening is formed, and the first sacrificial opening exposes the second sacrificial sidewall 42 and a portion of the isolation layer 232.

In some examples, the forming of the first sacrificial sidewall 41, the second sacrificial sidewall 42 and the first sacrificial pattern 402 may include: removing part of the stacked structure 102 on both sides of the isolation structure 23 to form a groove, filling the groove with a sacrificial material 401 to form a first sacrificial sidewall 41 and a second sacrificial sidewall 42, wherein the sacrificial material 401 further covers the stacked structure 102, the first sacrificial sidewall 41, the isolation structure 23, and the second sacrificial sidewall 42. A portion of the sacrificial material 401 is removed to form a first sacrificial pattern 402 having a first sacrificial opening exposing a portion of the isolation layer 232 and the second sacrificial sidewall spacers 42. Wherein, the partial isolation layers 232 and the second sacrificial sidewall spacers 42 are alternately stacked.

Referring to fig. 14, after forming the first sacrificial pattern 402, the step of forming the second separation groove 221 further includes: the second sacrificial sidewall 42 and a portion of the isolation layer 232 are removed to form a second isolation trench 221. That is, the second sacrificial sidewall spacers 42 and the portion of the isolation layer 232 exposed by the first sacrificial opening are removed. In some examples, the second sacrificial sidewall 42 and a portion of the isolation layer 232 may be removed using a dry etching process, wherein, for example, the etching time may be controlled so as to etch to the substrate.

Fig. 15 is a schematic structural diagram of a second partial gate layer 52 formed in a method for manufacturing a semiconductor structure according to an embodiment of the present disclosure. Referring to fig. 15, after forming the second separation groove 221, the step of forming the stacked structure 10 further includes: a portion of the sacrificial layer is removed through the second partition groove 221 to form a second space 502.

Since the second isolation trench 221 penetrates through the stacked structure 102, the sacrificial layer and the dielectric layer 80 in the stacked structure 102 are exposed through the second isolation trench 221, and a portion of the sacrificial layer in the stacked structure 102 can be removed through the second isolation trench 221. For example, a wet etch process may be used to remove portions of the sacrificial layer. In some examples, the etching rate of the sacrificial layer is greater than the etching rate of the dielectric layer 80 under the etching conditions created by the etching solution by selecting the etching solution corresponding to the material of the sacrificial layer.

It should be noted that the isolation layer 232 and the dielectric layer 80 are alternately stacked between the isolation pillar 231 and the second isolation trench 221, and the structure is a second sub-isolation portion B2, and the second sub-isolation portion B2 can also play an isolation role. That is, by providing the isolation structure 23, it is beneficial to block the etching liquid from flowing into the other side area of the isolation structure 23, and further beneficial to prevent the channel structure 11 in the other side of the isolation structure 23 from being etched, so as to prevent the leakage phenomenon of the channel structure 11. Meanwhile, the extension length of the transition area AA1 in the first area AA is shortened, the extension length of the effective storage area AA2 of the first area AA is prolonged, and the storage capacity is improved.

Furthermore, by arranging the isolation structure 23, the etching liquid can be prevented from flowing into the other side area of the isolation structure 23, and the etching liquid can be diffused along the first direction X, so that the etching efficiency is improved, and the manufacturing efficiency of the semiconductor structure 200 is improved.

In this embodiment, after forming the second space 502, the step of forming the stacked structure 10 further includes: a first isolation trench 211 is formed on the other side of the isolation structure 23, and the first isolation trench 211 penetrates through the stacked structure 102 and is located in the first area AA.

Fig. 16 is a schematic structural diagram of the second sacrificial pattern 403 formed in the method for manufacturing a semiconductor structure according to the embodiment of the present disclosure, fig. 17 is a schematic structural diagram of the third sacrificial pattern 223 formed in the method for manufacturing a semiconductor structure according to the embodiment of the present disclosure, and fig. 18 is a schematic structural diagram of the first separating groove 211 formed in the method for manufacturing a semiconductor structure according to the embodiment of the present disclosure.

Referring to fig. 16, the step of forming the first partition groove 211 includes: a portion of the first sacrificial pattern 402 is removed to form a second sacrificial pattern 403 having a second sacrificial opening, which exposes the first sacrificial sidewall 41 and a portion of the isolation layer 232. Wherein, the partial isolation layers 232 and the second sacrificial sidewall spacers 42 are alternately stacked. Referring to fig. 17, after the second sacrificial pattern 403 is formed, a third sacrificial pattern 223 is formed in the second isolation trench 221 and the second space 502, and the third sacrificial pattern 223 plays a role in isolation, so as to prevent an etching solution from entering the second isolation trench 221 when the sacrificial layer is subsequently removed through the first isolation trench 211.

Referring to fig. 18, after forming the second sacrificial pattern 403, the first sacrificial sidewall spacers 41 and a portion of the isolation layer 232 are removed to form first separation grooves 211. That is, the first sacrificial sidewall spacers 41 and the portion of the isolation layer 232 exposed by the second sacrificial opening are removed. In some examples, the first sacrificial sidewall 41 and a portion of the isolation layer 232 may be removed by using a dry etching process, wherein, for example, the etching time may be controlled so as to etch to the substrate.

Fig. 19 is a schematic structural diagram of a first space 501 formed in a method for manufacturing a semiconductor structure according to an embodiment of the present disclosure. Referring to fig. 19, after forming the first partition groove 211, the step of forming the stacked structure 10 further includes: a portion of the sacrificial layer is removed through the first partition groove 211 to form a first space 501. For example, a wet etch process may be used to remove portions of the sacrificial layer. In some examples, the etching rate of the sacrificial layer is greater than the etching rate of the dielectric layer 80 under the etching conditions created by the etching liquid by selecting the etching liquid corresponding to the material of the sacrificial layer.

It should be noted that, the isolation layer 232 and the dielectric layer 80 are alternately stacked between the isolation pillar 231 and the first isolation trench 211, and the structure is a first sub-isolation portion B1, and the first sub-isolation portion B1 can also play an isolation role. That is, by providing the isolation structure 23, it is beneficial to block the etching liquid from flowing into the other side area of the isolation structure 23, and further beneficial to prevent the channel structure 11 in the other side of the isolation structure 23 from being etched, and prevent the contact structure 12 from leaking electricity. Meanwhile, the extension length of the transition area AA1 in the first area AA is shortened, the extension length of the effective storage area AA2 of the first area AA is prolonged, and the storage capacity is improved.

Fig. 20 is a schematic structural diagram of a first separation trench 211 and a second separation trench 221 formed in a method for manufacturing a semiconductor structure according to an embodiment of the present disclosure. Referring to fig. 20, after the stacked structure 10 is formed, the third sacrificial pattern 223 may be removed to avoid affecting subsequent processes while forming the first and

second partition trenches

211 and 221.

Fig. 21 is a schematic structural diagram of a first isolation structure 21 and a second isolation structure 22 formed in a method for manufacturing a semiconductor structure according to an embodiment of the present disclosure. Referring to fig. 21, after forming the first and

second partition grooves

211 and 221, the step of forming the stack structure 10 further includes: forming a first partial gate layer 51 and a second partial gate layer 52 in the first space 501 and the second space 502, respectively; the first partial gate layer 51 and the second partial gate layer 52 together form a gate layer 50, and the gate layer 50 and the dielectric layer 80 together form the stacked structure 10.

In some embodiments, an adhesion layer and a gate conductive layer may be sequentially deposited within the first space 501 to form the first partial gate layer 51. Among other things, the adhesion layer serves to improve adhesion between the gate conductive layer and other structures in contact to improve reliability of the semiconductor structure 200. The adhesion layer may be a conductive material including one or a combination of metals (e.g., titanium (Ti), tantalum (Ta), chromium (Cr), tungsten (W), etc.), metal compounds (e.g., titanium nitride (TiNx), tantalum nitride (TaNx), chromium nitride (CrNx), tungsten nitride (WNx), etc.), and metal alloys (e.g., tiSixNy, taSixNy, crSixNy, WSixNy, etc.). The gate conductive layer comprises a conductive material, for example, a combination comprising one or more of tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or other suitable material.

It should be noted that the structure of the first portion of the gate layer 51 may be formed simultaneously with the formation of the second portion of the gate layer 52, and the structure and material of the second portion of the gate layer 52 are not described herein again.

In this embodiment, after forming the stacked structure 10 and the isolation structure 23, the method further includes:

s3, forming a first separation structure and a second separation structure, wherein the separation structure is located between the first separation structure and the second separation structure; the first separation structure, the second separation structure and the isolation structure jointly form a gate line gap structure, and the gate line gap structure extends from the first area AA to the second area BB and penetrates through the stacking structure.

Referring to fig. 21, the step of forming the first and

second partition structures

21 and 22 includes: forming a first partition structure 21 in the first partition groove 211; forming a second partition structure 22 in the second partition groove 221; in some embodiments, the filling may be simultaneously performed in the first and

second partition grooves

211 and 221 to simultaneously form the first and

second partition structures

21 and 22. The first and

second partition structures

21 and 22 may be formed, for example, by filling an insulating material, or by filling an insulating material and a conductive material in sequence.

In this embodiment, the first isolation structure 21, the second isolation structure 22, and the isolation structure 23 together form the gate line slit structure 20. For example, the number of the gate line slit structures 20 may be plural, and the plural gate line slit structures 20 are arranged in parallel with each other. The gate line slit structure 20 is used to separate the stacked structure 10 into a plurality of block structures, thereby forming a plurality of memory blocks.

It should be noted that the contact structure 12 may be formed simultaneously with the formation of the first and

second partition structures

21 and 22. In the present embodiment, the contact structure 12 is formed in the contact hole, and one contact structure 12 of the stacked structure 10 is electrically connected to one gate layer 50. The connecting structure may form the contact structure 12 by depositing a conductive material within the contact hole using one or more thin film deposition processes including, but not limited to, PVD, CVD, ALD. The conductive material includes, but is not limited to, a combination of one or more of tungsten, cobalt, copper, aluminum, and metal silicide, and may be other suitable materials. Through the process steps, the process is further simplified, and the manufacturing efficiency is improved.

To sum up, according to the manufacturing method of the semiconductor structure 200 provided by the embodiment of the disclosure, by forming the isolation structure 23 first, when the sacrificial layer around the first isolation structure 21 is removed, the isolation structure 23 is favorable for blocking the etching liquid from flowing into the area where the second isolation structure 22 is located, and meanwhile, when the sacrificial layer around the second isolation structure 22 is removed, the isolation structure 23 is favorable for blocking the etching liquid from flowing into the area where the first isolation structure 21 is located, so as to be favorable for shortening the extension length of the transition area AA1 in the first area AA, further prolong the extension length of the effective storage area AA2 in the first area AA, and improve the storage capacity of the three-dimensional memory 601.

Referring to fig. 22 and 23, some embodiments of the present disclosure also provide a storage system 60. The storage system 60 includes a controller 602, and a three-dimensional memory 601 as in some embodiments above, the controller 602 being coupled to the three-dimensional memory 601 to control the three-dimensional memory 601 to store data.

The Storage system 60 may be integrated into various types of Storage devices, for example, included in the same package (e.g., universal Flash Storage (UFS) package or EmbeDDeD multimedia CarD (eMMC) package). That is, the storage system 60 may be applied to and packaged into different types of electronic products, such as a mobile phone (e.g., a cell phone), a desktop computer, a tablet computer, a laptop computer, a server, an in-vehicle device, a game console, a printer, a positioning device, a wearable device, a smart sensor, a mobile power supply, a Virtual Reality (VR) device, an AugmenteD Reality (AR) device, or any other suitable electronic device having storage therein.

In some embodiments, referring to FIG. 22, the memory system 60 includes a controller 602 and a three-dimensional memory 601, and the memory system 60 may be integrated into a memory card.

The Memory CarD includes any one of a PC CarD (PCMCIA, personal computer Memory CarD international association), a Compact Flash (CF) CarD, a Smart MeDia (SM) CarD, a Memory stick, a MultimeDia CarD (MMC), a Secure Digital Memory CarD (SD), and a UFS.

In other embodiments, referring to fig. 23, the storage system 60 includes a controller 602 and a plurality of three-dimensional memories 601, and the storage system 60 is integrated into a SoliD State Drive (SSD).

In storage system 60, in some embodiments, controller 602 is configured for operation in a low duty cycle environment, such as an SD card, CF card, universal Serial Bus (USB) flash drive, or other media for use in electronic devices such as personal computers, digital cameras, mobile phones, and the like.

In other embodiments, the controller 602 is configured for operation in a high duty cycle environment SSD or eMMC for data storage and enterprise storage arrays of mobile devices such as smart phones, tablets, laptops, and the like.

In some embodiments, the controller 602 may be configured to manage data stored in the three-dimensional memory 601 and communicate with an external device (e.g., a host). In some embodiments, the controller 602 may also be configured to control operations of the three-dimensional memory 601, such as read, erase, and program operations. In some embodiments, the controller 602 may also be configured to manage various functions with respect to data stored or to be stored in the three-dimensional memory 601, including at least one of bad block management, garbage collection, logical to physical address translation, wear leveling. In some embodiments, the controller 602 is further configured to process error correction codes with respect to data read from the three-dimensional memory 601 or written to the three-dimensional memory 601.

Of course, the controller 602 may also perform any other suitable functions, such as formatting the three-dimensional memory 601; for example, the controller 602 may communicate with an external device (e.g., a host) via at least one of various interface protocols.

It should be noted that the interface protocol includes at least one of a USB protocol, an MMC protocol, a Peripheral Component Interconnect (PCI) protocol, a PCI express (PCI-E) protocol, an Advanced Technology Attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a Small Computer System Interface (SCSI) protocol, an Enhanced Small Disk Interface (ESDI) protocol, an Integrated Drive Electronics (IDE) protocol, and a Firewire protocol.

Some embodiments of the present disclosure also provide an electronic device. The electronic device may be any one of a mobile phone, a desktop computer, a tablet computer, a notebook computer, a server, an in-vehicle device, a wearable device (e.g., a smart watch, a smart bracelet, smart glasses, etc.), a mobile power source, a game console, a digital multimedia player, and the like.

The electronic device may include the storage system 60 described above, and may further include at least one of a Central Processing Unit (CPU), a cache (cache), and the like.

The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.

Claims

1. A semiconductor structure, comprising:

the stacked structure comprises gate layers and dielectric layers which are alternately stacked; the stacking structure comprises a first area and a second area adjacent to the first area;

a gate line slit structure extending from the first region to the second region and penetrating the stacked structure; the gate line gap structure includes an isolation structure, a first isolation structure, and a second isolation structure, the isolation structure being located in the first region and between the first isolation structure and the second isolation structure.

2. The semiconductor structure of claim 1, wherein the isolation structure comprises an isolation pillar and a plurality of isolation layers disposed around the isolation pillar; the isolation columns penetrate through the stacked structure along a direction perpendicular to the dielectric layers, the isolation layers and the dielectric layers are alternately stacked, and one isolation layer and one gate layer are arranged on the same layer.

3. The semiconductor structure of claim 2, wherein an end of the first spacer structure proximate to the second spacer structure extends into the isolation layer, and/or wherein an end of the second spacer structure proximate to the first spacer structure extends into the isolation layer.

4. The semiconductor structure of claim 2, wherein a width of the isolation pillar along a first direction is less than or equal to a multiple of 1.5 of a width of the first isolation structure along the first direction;

the first direction is perpendicular to the extending direction of the gate line gap structure and parallel to the gate layer.

5. The semiconductor structure of claim 2,

the width of the isolation layer along a first direction is greater than or equal to the width of the first isolation structure along the first direction;

6. The semiconductor structure of claim 2,

half of the width of the isolation layer along the first direction is smaller than half of the center distance between two adjacent first separation structures;

7. The semiconductor structure of any one of claims 1 to 6, wherein the gate line slit structures are provided in a plurality, and a plurality of the gate line slit structures are spaced apart in a first direction; the first direction is perpendicular to the extending direction of the gate line gap structure and parallel to the gate layer.

8. The semiconductor structure of claim 7, wherein at least two of the isolation structures are staggered along the first direction, and a distance between the staggered two of the isolation structures along the second direction ranges from 50nm to 250nm;

the first direction is perpendicular to the extending direction of the grid line gap structure and is parallel to the grid layer; the second direction is parallel to the extending direction of the gate line slit structure.

9. The semiconductor structure of any of claims 1-6,

the distance between any of the isolation structures and the second region ranges from 50nm to 750nm.

10. The semiconductor structure of any of claims 1-6, wherein the gate layer is disposed around the isolation structure and extends from the first region to the second region.

11. The semiconductor structure of any of claims 1-6, further comprising:

the first region comprises a plurality of channel structures, and the channel structures penetrate through the stacked structure;

the second region comprises a plurality of contact structures, and the contact structures penetrate through part of the stacked structure; one of the contact structures is electrically connected to one of the gate layers.

12. A method for fabricating a semiconductor structure, comprising,

forming a stacked structure, wherein the stacked structure comprises gate layers and dielectric layers which are alternately stacked; the stacking structure comprises a first area and a second area adjacent to the first area;

forming an isolation structure, wherein the isolation structure is positioned in the first area;

forming a first separation structure and a second separation structure, the separation structure being located between the first separation structure and the second separation structure; the first separation structure, the second separation structure and the separation structure jointly form a gate line gap structure, and the gate line gap structure extends from the first region to the second region and penetrates through the stacked structure.

13. The production method according to claim 12,

the forming a stacked structure includes:

forming a laminated structure, wherein the laminated structure comprises sacrificial layers and dielectric layers which are alternately laminated;

the forming of the isolation structure comprises:

forming a sacrificial hole, wherein the sacrificial hole penetrates through the laminated structure;

removing a portion of the sacrificial layer through the sacrificial hole to form a sacrificial gap;

and filling an isolation material in the sacrificial gap to form an isolation layer, and filling an isolation material in the sacrificial hole to form an isolation column, wherein the isolation column and the isolation layer jointly form the isolation structure.

14. The method of claim 13,

the forming a stacked structure includes:

forming a second isolation groove on one side of the isolation structure, wherein the second isolation groove penetrates through the laminated structure and extends from the first area to the second area;

removing a portion of the sacrificial layer through the second separation groove to form a second space;

forming a first separation groove on the other side of the isolation structure, wherein the first separation groove penetrates through the laminated structure and is positioned in the first area;

removing a portion of the sacrificial layer through the first separation groove to form a first space;

forming a second partial gate layer and a first partial gate layer in the second space and the first space, respectively; the first part of the gate layer and the second part of the gate layer jointly form the gate layer, and the gate layer and the dielectric layer jointly form the stack structure.

15. The method of claim 14,

the forming of the first and second partition structures includes:

forming a first separation structure in the first separation groove;

forming a second separation structure in the second separation groove;

the first separation structure, the second separation structure and the isolation structure jointly form a grid line gap structure.

16. The method of manufacturing according to any one of claims 13 to 15, wherein the forming a stacked structure further comprises:

forming a plurality of channel holes in the first region and penetrating through the laminated structure;

after the forming of the isolation structure and before the forming of the first isolation trench and the second isolation trench, the method further includes:

and filling a channel material in the channel hole to form a channel structure.

17. The method for preparing a porous material according to any one of claims 13 to 15, further comprising:

forming a plurality of contact holes in the second region and penetrating through a part of the stacked structure;

and forming contact structures in the contact holes, wherein one contact structure of the stacked structures is electrically connected with one gate layer.

18. A three-dimensional memory, comprising:

a semiconductor structure, the semiconductor structure being as claimed in any one of claims 1-11;

a peripheral device electrically connected to the semiconductor structure.

19. A storage system, comprising:

a three-dimensional memory as claimed in claim 18;

a controller coupled to the three-dimensional memory to control the three-dimensional memory to store data.

20. An electronic device comprising the storage system of claim 19.