CN115440740A - Semiconductor structure, preparation method thereof and three-dimensional memory - Google Patents

Abstract

The disclosure provides a semiconductor structure, a preparation method thereof and a three-dimensional memory, relates to the technical field of semiconductor chips, and aims to solve the problem that the storage capacity of the three-dimensional memory is small in the related technology. The semiconductor structure comprises a stacking structure and a grid line gap structure, wherein the grid line gap structure comprises a first separation structure and a second separation structure; the first partition structure comprises a first part which is connected with the second partition structure; the second partition structure has a width in the first direction greater than a width of the first portion in the first direction. When the sacrificial layer around the second separation structure is removed, the etching liquid flowing from the second area to the first area is reduced, the channel structure in the first area is prevented from being etched, the extension length of the transition area is reduced, and the storage capacity of the semiconductor structure is improved. The semiconductor structure is applied to a three-dimensional memory to realize reading and writing operations of data.

Description

Semiconductor structure, preparation method thereof and three-dimensional memory

Technical Field

The present disclosure relates to the field of semiconductor chip technologies, and in particular, to a semiconductor structure, a method for manufacturing the same, and a three-dimensional memory.

Background

As the feature size of memory cells approaches the lower process limit, planar processes and manufacturing techniques become challenging and costly, which causes the storage density of 2D or planar NAND flash memories to approach the upper limit.

To overcome the limitations imposed by 2D or planar NAND flash memories, memories having a three-dimensional structure (3D NAND) have been developed to increase the storage density by arranging memory cells three-dimensionally over a substrate.

However, the memory with the three-dimensional structure in the related art has a technical problem of small storage capacity.

Disclosure of Invention

The embodiment of the disclosure provides a semiconductor structure, a preparation method thereof and a three-dimensional memory, and aims to solve the problem that the storage capacity of the three-dimensional memory is small in the related art.

In order to achieve the above purpose, the embodiments of the present disclosure adopt the following technical solutions:

in one aspect, a semiconductor structure is provided. The semiconductor structure comprises a stacking structure and a grid line gap structure, wherein the stacking structure comprises grid layers and dielectric layers which are alternately stacked; the stacked structure includes a first region and a second region adjacent to the first region. The grid line gap structure extends from the first region to the second region and penetrates through the stacked structure; the grid line gap structure comprises a first separation structure and a second separation structure; the first partition structure is located in the first zone and the second partition structure is located in the second zone. The first partition structure includes a first portion connected to the second partition structure; a width of the second partition structure in a first direction is greater than a width of the first portion in the first direction; the first direction is perpendicular to the extending direction of the gate line gap structure and parallel to the gate layer.

The semiconductor structure provided by the above embodiment of the present disclosure includes a stacked structure and a gate line gap structure, where the stacked structure includes gate layers and dielectric layers that are alternately stacked; the stacked structure includes a first region and a second region adjacent to the first region. The grid line gap structure extends from the first area to the second area and penetrates through the stacked structure; the grid line gap structure comprises a first separation structure and a second separation structure; the first separation structure is located in the first zone and the second separation structure is located in the second zone. The first partition structure includes a first portion, and the second partition structure has a width in the first direction greater than a width of the first portion in the first direction. When the sacrificial layer around getting rid of the second partition structure, through the aforesaid setting, be favorable to reducing by the etching liquid of second district flow direction first district, and then avoid the sculpture to the channel structure department that is located the first district, be favorable to reducing the extension length of the transition district in the first district, and then the extension length of the effective storage area of extension first district, improve semiconductor structure's storage capacity. Here, the "transition region in the first region" refers to a region in the first region which is adjacent to the second region; by "active storage area" is meant the area within the first area, on the side of the transition area remote from the second area.

In some embodiments, the second partition structure comprises a second portion; the second portion comprises a first end proximate to the first portion and a second end distal from the first portion, the second end having a width in a first direction that is greater than a width of the first end in the first direction, the first end having a width in the first direction that is greater than or equal to the width of the first portion in the first direction; the first direction is perpendicular to the extending direction of the grid line gap structure and parallel to the grid layer.

In some embodiments, the direction pointing from the first end to the second end is a second direction; the width of the second portion in the first direction gradually increases in the second direction.

In some embodiments, the direction pointing from the first end to the second end is a second direction; a length of the second portion along the second direction is less than or equal to 25nm; and/or the maximum width of the second part along the first direction has a value range of: 250nm-700nm.

In some embodiments, the second partition structure further comprises a third portion; the third portion is connected to the second portion; the widths of the third portions in the first direction are each greater than or equal to the width of the second end in the first direction.

In some embodiments, the first partition structure further comprises a fourth portion and a fifth portion; the fourth portion is connected to the first portion; a width of the fourth portion in the first direction is greater than a width of the first portion in the first direction; the fifth part is connected with one end of the fourth part far away from the first part; a width of the fifth portion in the first direction is smaller than a width of the fourth portion in the first direction.

In some embodiments, further comprising: a plurality of channel structures extending through the stacked structure; the plurality of channel structures comprise a first channel structure arranged along the edge of the grid line gap structure, and the distance between the first channel structure and the grid line gap structure ranges from 50nm to 200nm.

In another aspect, a method for manufacturing a semiconductor structure is provided, in which a stacked structure is formed, the stacked structure including sacrificial layers and dielectric layers that are alternately stacked; the laminated structure comprises a first area and a second area adjacent to the first area. And forming a grid line separation groove, extending from the first region to the second region and penetrating through the laminated structure. And replacing the sacrificial layer with a gate layer through the gate line isolation groove to form a stack structure. Filling the grid line separation grooves to form a grid line gap structure, wherein the grid line gap structure comprises a first separation structure and a second separation structure; the first separation structure is located in the first zone and the second separation structure is located in the second zone; the first partition structure includes a first portion and the second partition structure includes a second portion; the first portion is connected to the second portion; the second portion includes a first end proximate to the first portion and a second end distal from the first portion, the second end of the second portion having a width greater than a width of the first end of the second portion, the first end of the second portion having a width greater than or equal to the width of the first portion.

In some embodiments, the grid line spacer trench comprises a first spacer trench and a second spacer trench; the forming a stacked structure includes: forming a sacrificial structure, wherein the sacrificial structure is positioned in the first separation groove; removing a portion of the sacrificial layer located in the second region through the second separation groove to form a second gap; forming a blocking structure located in the second separation groove and the second gap; removing the sacrificial structure; removing the sacrificial layer located in the first region through the first separation groove to form a first gap; removing the barrier structure; and forming a gate layer, wherein the gate layer is positioned in the first gap and the second gap, and the gate layer and the dielectric layer jointly form the stack structure.

In some embodiments, the first dividing channel comprises a first channel portion and a second channel portion, the second channel portion being distal from the channel bottom relative to the first channel portion; the forming of the sacrificial structure includes: forming a first sacrificial part, wherein the first sacrificial part is filled in the first groove part; forming a barrier layer, wherein the barrier layer comprises a first barrier layer and a second barrier layer; the first barrier layer covers the first sacrificial part and the side wall of the second groove part; the second barrier layer covers the side face, close to the second separation groove, of the first sacrificial part; forming a second sacrificial part, wherein the second sacrificial part is filled in the second groove part; wherein the first sacrificial portion, the first barrier layer, and the second sacrificial portion collectively constitute the sacrificial structure.

In some embodiments, the barrier layer further comprises a third barrier layer covering sidewalls of the second separation trench.

In some embodiments, the forming the first sacrificial portion comprises: filling a first dielectric material in the first separation groove and the second separation groove; the first separator tank includes a first tank section, a second tank section, and a third tank section, the second tank section being located between the first tank section and the third tank section, the first tank section being closer to the second separator tank than the third tank section; in the first groove section and the third groove section, at least the first medium material in the first groove section is filled into a solid structure; and removing the first dielectric material on the inner wall of the second separation groove and part of the first dielectric material in the first separation groove, and remaining the first dielectric material in the first groove part to form the first sacrificial part.

In some embodiments, the removing, via the second separation groove, the portion of the sacrificial layer located in the second region further includes: and removing the third barrier layer.

In some embodiments, further comprising: forming a contact hole, wherein the contact hole is positioned in the second area; when the gate layer is formed, the method further comprises the following steps: and forming a gate conductive layer in the contact hole.

In yet another aspect, a three-dimensional memory is provided. The three-dimensional memory includes a semiconductor structure as described in some embodiments above, and a peripheral device electrically connected to the semiconductor structure.

In yet another aspect, a storage system is provided, including: the memory device comprises a three-dimensional memory as described above, and a controller coupled to the three-dimensional memory to control the three-dimensional memory to store data.

In yet another aspect, an electronic device is provided, comprising the storage system as described above.

It can be understood that, in the manufacturing method of the semiconductor structure, the three-dimensional memory, the storage system and the electronic device provided in the embodiments of the disclosure, reference may be made to the above beneficial effects of the semiconductor structure, and details are not described herein again.

Drawings

In order to more clearly illustrate the technical solutions in the present disclosure, the drawings needed to be used in some embodiments of the present disclosure will be briefly described below, and it is apparent that the drawings in the following description are only drawings of some embodiments of the present disclosure, and other drawings can be obtained by those skilled in the art according to the drawings. Furthermore, the drawings in the following description may be regarded as schematic diagrams, and do not limit the actual size of products, the actual flow of methods, the actual timing of signals, and the like, involved in the embodiments of the present disclosure.

FIG. 1 is a cross-sectional view of a three-dimensional memory according to some embodiments;

FIG. 2 is a first top view of a semiconductor structure, according to some embodiments;

FIG. 3 is a second top view of a semiconductor structure according to some embodiments;

figure 4 is a third top view of a semiconductor structure, in accordance with some embodiments;

FIG. 5 is a fourth top view of a semiconductor structure according to some embodiments;

FIG. 6 is a flow chart of steps in a method of fabricating a semiconductor structure according to some embodiments;

fig. 7 is a top view of a first channel structure formed in a method of fabricating a semiconductor structure according to some embodiments;

fig. 8 is a top view of a gate line spacer trench formed in a method of fabricating a semiconductor structure according to some embodiments;

fig. 9 is a cross-sectional view of a gate line spacer trench formed in a method of fabricating a semiconductor structure according to some embodiments;

FIG. 10 is a partial cross-sectional view of a structure after a first dielectric material is formed in a method of fabricating a semiconductor structure in accordance with some embodiments taken along a plane in which the dielectric layer is located;

FIG. 11 is a cross-sectional view of a first dielectric material formed in a method of fabricating a semiconductor structure according to some embodiments;

FIG. 12 is a top view of a first sacrificial portion formed in a method of fabricating a semiconductor structure according to some embodiments;

FIG. 13 is a top view of a barrier layer formed in a method of fabricating a semiconductor structure according to some embodiments;

FIG. 14 is a cross-sectional view of a barrier layer formed in a method of fabricating a semiconductor structure according to some embodiments;

FIG. 15 is a top view of a second dielectric material formed in a method of fabricating a semiconductor structure according to some embodiments;

FIG. 16 is a cross-sectional view of a second dielectric material formed in a method of fabricating a semiconductor structure according to some embodiments;

FIG. 17 is a top view of a mask layer formed in a method of fabricating a semiconductor structure according to some embodiments;

FIG. 18 is a top view of a sacrificial structure formed in a method of fabricating a semiconductor structure according to some embodiments;

FIG. 19 is a cross-sectional view of a sacrificial structure formed in a method of fabricating a semiconductor structure according to some embodiments;

FIG. 20 is a top view of a second gap formed in a method of fabricating a semiconductor structure according to some embodiments;

FIG. 21 is a cross-sectional view of a second gap formed in a method of fabricating a semiconductor structure according to some embodiments;

figure 22 is a top view of a barrier structure formed in a method of fabricating a semiconductor structure according to some embodiments;

figure 23 is a top view of a barrier structure formed in a method of fabricating a semiconductor structure according to some embodiments;

FIG. 24 is a top view of a sacrificial structure removed in a method of fabricating a semiconductor structure according to some embodiments;

FIG. 25 is a cross-sectional view of a semiconductor structure after removal of a sacrificial structure in a method of fabricating the semiconductor structure, in accordance with some embodiments;

figure 26 is a cross-sectional view of a first gap formed in a method of fabricating a semiconductor structure according to some embodiments;

figure 27 is a top view of a gate layer formed in a method of fabricating a semiconductor structure according to some embodiments;

figure 28 is a cross-sectional view of a gate layer formed in a method of fabricating a semiconductor structure according to some embodiments;

FIG. 29 is a cross-sectional view of a spacer structure formed in a method of fabricating a semiconductor structure according to some embodiments;

FIG. 30 is a block diagram of a storage system according to some embodiments;

FIG. 31 is a block diagram of memory systems according to further embodiments.

Detailed Description

The technical solutions in some embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings, and it is to be understood that the described embodiments are only a part of the embodiments of the present disclosure, and not all of the embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments provided by the present disclosure belong to the protection scope of the present disclosure.

In the description of the present disclosure, it is to be understood that the terms "upper", "lower", "front", "rear", "left", "right", "top", "bottom", "inner", "outer", and the like, indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, are merely for convenience in describing the present disclosure and simplifying the description, and do not indicate or imply that the referred devices or elements must have a specific orientation, be constructed in a specific orientation, and be operated, and thus, should not be construed as limiting the present disclosure.

Throughout the specification and claims, the term "comprising" is to be interpreted in an open, inclusive sense, i.e., as "including, but not limited to," unless the context requires otherwise. In the description of the specification, the terms "one embodiment," "some embodiments," "example embodiments," "exemplary" or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the disclosure. The schematic representations of the above terms are not necessarily referring to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be included in any suitable manner in any one or more embodiments or examples.

In the following, the terms "first", "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the embodiments of the present disclosure, "a plurality" means two or more unless otherwise specified.

In describing some embodiments, the expressions "coupled" and "connected," along with their derivatives, may be used. For example, the term "connected" may be used in describing some embodiments to indicate that two or more elements are in direct physical or electrical contact with each other. As another example, some embodiments may be described using the term "coupled" to indicate that two or more elements are in direct physical or electrical contact. The term "coupled," however, may also mean that two or more elements are not in direct contact with each other, but yet still co-operate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents herein.

"at least one of A, B and C" has the same meaning as "at least one of A, B or C" and includes combinations of the following A, B and C: a alone, B alone, C alone, a combination of A and B, A and C in combination, B and C in combination, and A, B and C in combination.

"A and/or B" includes the following three combinations: a alone, B alone, and a combination of A and B.

Additionally, the use of "based on" means open and inclusive, as a process, step, calculation, or other action that is "based on" one or more stated conditions or values may in practice be based on additional conditions or values beyond those stated.

As used herein, "about," "approximately" or "approximately" includes the stated value as well as average values within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art in view of the measurement in question and the error associated with measuring the particular quantity (i.e., the limitations of the measurement system). "equal" includes absolute equal and approximately equal, where the difference between the two, which may be equal within an acceptable deviation of approximately equal, is less than or equal to 5% of either.

In the context of the embodiments of the present disclosure, the meaning of "on" \8230; \8230on "," above ", and" over "should be interpreted in the broadest manner such that" on "not only means" directly on something ", but also includes the meaning of" on something "with intervening features or layers therebetween, and" above "or" over "not only means" above "or" over "something, but also includes the meaning of" above "or" over "something without intervening features or layers therebetween (i.e., directly on something).

In the context of the embodiments of the present disclosure, the meaning of "in one direction, a is disposed opposite to B" should be interpreted in the broadest way, as can be understood: the orthographic projection of A on C caused by the light rays parallel to the direction and the orthographic projection of B on C caused by the light rays in the direction are overlapped. The overlap may be, for example, a complete overlap or a partial overlap.

Example embodiments are described herein with reference to cross-sectional and/or plan views as idealized example figures. In the drawings, the thickness of layers and regions are exaggerated for clarity. Variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, the exemplary embodiments should not be construed as limited to the shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of exemplary embodiments.

As used herein, the term "substrate" refers to a material onto which subsequent layers of material may be added. The substrate itself may be patterned. The material added to the substrate may be patterned or may remain unpatterned. In addition, the substrate may include a variety of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, and the like. Alternatively, the substrate may be made of a non-conductive material such as glass, plastic, or sapphire wafer.

The term "three-dimensional memory" refers to a semiconductor device formed of strings of memory cell transistors (referred to herein as "strings of memory cells," e.g., NAND strings of memory cells) arranged in an array on a major surface of a substrate or a source layer and extending in a direction perpendicular to the substrate or source layer. As used herein, the term "vertically" means nominally perpendicular to a major surface (i.e., a lateral surface) of the substrate or source layer.

Fig. 1 is a cross-sectional view of a three-dimensional memory according to some embodiments. Note that, in fig. 1, the three-dimensional memory 10 extends in an X-Y plane, and the second direction Y and the first direction X are, for example, two orthogonal directions in a plane in which the semiconductor structure 200 is located (e.g., a plane in which the source layer SL is located): the second direction Y is, for example, an extending direction of word lines, and the first direction X is, for example, an extending direction of bit lines. The third direction Z is perpendicular to the plane of the semiconductor structure 200, i.e., perpendicular to the X-Y plane.

As used in embodiments of the present disclosure, whether a component (e.g., a layer, structure, or device) is "on," "above," or "below" another component (e.g., a layer, structure, or device) of a semiconductor device (e.g., a three-dimensional memory) is determined relative to a substrate or a source layer of the semiconductor device in a third direction Z when the substrate or source layer SL is located in a lowest plane of the semiconductor device in the third direction Z. Throughout the context of the disclosed embodiments, the same concepts are applied to describe spatial relationships.

In order to show the structure of the device more clearly, in fig. 1, a view of the memory area CA and a view of the connection area SS are shown, the view of the memory area CA is based on a left-hand coordinate system, the view of the connection area SS is based on a right-hand coordinate system, i.e., the view of the memory area CA shows a cross-sectional structure in the Y direction, and the view of the connection area SS shows a cross-sectional structure in the X direction.

Referring to fig. 1, some embodiments of the present disclosure provide a three-dimensional memory 10. The three-dimensional memory 10 may include a semiconductor structure 200. The semiconductor structure 200 may include a source layer SL and an array interconnect layer 290. The three-dimensional memory 10 may also include a peripheral device 100 coupled to the semiconductor structure 200. The peripheral device 100 may be disposed on a side of the array interconnect layer 290 away from the source layer SL.

The source layer SL may comprise a semiconductor material including, for example, monocrystalline silicon, monocrystalline germanium, a III-V compound semiconductor material, a II-VI compound semiconductor material, and other suitable semiconductor materials. The source layer SL may be partially or fully doped. Illustratively, the source layer SL may include a doped region doped with a p-type dopant. The source layer SL may also include an undoped region.

The semiconductor structure 200 may include memory cell transistor strings (referred to herein as "memory cell strings 400," e.g., NAND memory cell strings) arranged in an array. The source layer SL may be coupled to sources of the plurality of memory cell strings 400.

With continued reference to fig. 1, in some embodiments, array interconnect layer 290 may be coupled with a string of memory cells 400. The array interconnect layer 290 may include drain terminals (i.e., bit lines) of the memory cell strings 400, which may be coupled to semiconductor channels of respective transistors in at least one of the memory cell strings 400.

The array interconnect layer 290 may include one or more first interlayer insulating layers 292, and may further include a plurality of contacts insulated from each other by the first interlayer insulating layers 292, the contacts including, for example, bitline contacts BL-CNT coupled to bitlines; a drain select gate contact coupled to the drain select gate; the gate line contact 293 is coupled to the gate layer 203. The array interconnect layer 290 may also include one or more first interconnect conductor layers 291. The first interconnect conductor layer 291 may include a plurality of connection lines, such as bit lines, and word line connection lines coupled to word lines. The material of the first interconnect conductor layer 291 and the contact may comprise a conductive material including, for example, a combination of one or more of tungsten, cobalt, copper, aluminum, and metal silicide, and may also comprise other suitable materials. The material of the first interlayer insulating layer 292 is an insulating material including, for example, a combination of one or more of silicon oxide, silicon nitride, and a high-k insulating material, or may include other suitable materials.

The peripheral device 100 may include peripheral circuitry. The peripheral circuitry is configured to control and sense the array device. The peripheral circuitry may be any suitable digital, analog, and/or mixed-signal control and sensing circuitry for supporting the operation (or working) of the array device (e.g., semiconductor structure 200), including but not limited to page buffers, decoders (e.g., row and column decoders), sense amplifiers, drivers (e.g., word line drivers), charge pumps, current or voltage references, or any active or passive component of circuitry (e.g., transistors, diodes, resistors, or capacitors). The peripheral circuitry may also include any other circuitry compatible with advanced Logic processes, including Logic circuitry (e.g., processors and Programmable Logic Devices (PLDs) or Memory circuitry (e.g., static Random-Access Memory (SRAM)).

For example, in some embodiments, the peripheral device 100 may include a substrate 110, a transistor 120 disposed on the substrate 110, and a peripheral interconnect layer 130 disposed on the substrate 110. The peripheral circuitry may include a transistor 120.

The material of the substrate 110 may include single crystal silicon, but may also include other suitable materials, such as silicon germanium, or silicon-on-insulator thin film.

Peripheral interconnect layer 130 is coupled to transistor 120 to enable the transmission of electrical signals between transistor 120 and peripheral interconnect layer 130. The peripheral interconnection layer 130 may include one or more second interlayer insulating layers 131, and may further include one or more second interconnection conductor layers 132. Different second interconnect conductor layers 132 may be coupled to each other by contacts. The material of the second interconnect conductor layer 132 and the contacts may comprise a conductive material including, for example, a combination of one or more of tungsten, cobalt, copper, aluminum, and metal silicides, and may also comprise other suitable materials. The material of the second interlayer insulating layer 131 includes an insulating material including, for example, a combination of one or more of silicon oxide, silicon nitride, and a high-dielectric-constant insulating material, or may be another suitable material.

The peripheral interconnect layer 130 may be coupled with the array interconnect layer 290 such that the semiconductor structure 200 and the peripheral device 100 may be coupled. In some examples, since the peripheral interconnect layer 130 is coupled with the array interconnect layer 290, peripheral circuitry in the peripheral device 100 may be coupled with strings of memory cells in the semiconductor structure 200 to enable transmission of electrical signals between the peripheral circuitry and the strings of memory cells. In some possible implementations, a bonding interface 500 may be disposed between the peripheral interconnection layer 130 and the array interconnection layer 290, and the peripheral interconnection layer 130 and the array interconnection layer 290 may be bonded and coupled to each other through the bonding interface 500.

Fig. 2 is a top view one of a semiconductor structure 200 according to some embodiments. With continued reference to fig. 1 in conjunction with fig. 2, the semiconductor structure 200 further includes a stacked structure 232 and a gate line slit structure 30, wherein the stacked structure 232 includes gate layers 203 and dielectric layers 201 alternately stacked. The gate layer 203 is also a word line. The stacked structure 232 includes a first area AA and a second area BB adjacent to the first area AA; the gate line slit structure 30 extends from the first region AA to the second region BB and penetrates through the stacked structure 232; the gate line slit structure 30 includes a first partition structure 31 and a second partition structure 32; the first partition structure 31 is located in the first region AA, and the second partition structure 32 is located in the second region BB.

In the related art, the step of forming the gate line slit structure 30 includes: forming a stack structure 232, wherein the stack structure 232 comprises dielectric layers 201 and sacrificial layers which are alternately stacked; forming grid isolation grooves, wherein the grid isolation grooves comprise first isolation grooves located in the connection region SS and second isolation grooves located in the core region CA; forming a first isolation part in the first isolation groove; removing the part, located in the core area CA, of the sacrificial layer through the second separation groove to form a second gap; removing the first isolation part; removing a portion of the sacrificial layer located at the connection region SS through the first isolation groove to form a first gap; forming a gate layer 203 in the first gap and the second gap, wherein the gate layer 203 is used for leading out control gates in all layers in the channel structure to a connection structure of a connection region SS, so that functions of reading, erasing, programming and the like are realized; a gate line slit structure 30 is formed in the first and second barrier grooves. A transition region is included in the core region CA adjacent to the connection region SS to avoid etching into the contact structure 12 in the connection region SS during the removal of part of the sacrificial layer via the second spacer trench. However, in the related art, the extended length of the transition area in the core area CA is longer, and the extended length of the effective storage area of the core area CA is shorter, resulting in a smaller storage capacity of the three-dimensional memory. Here, the "transition region in the core region CA" refers to a region adjacent to the connection region SS in the core region CA; the "effective memory area" refers to an area within the core area CA on the side of the transition area remote from the connection area SS.

In view of the above, some embodiments of the present disclosure provide a three-dimensional memory. Referring to fig. 1 to 5, fig. 3 is a second top view of a semiconductor structure 200 according to some embodiments; fig. 4 is a third top view of the semiconductor structure 200, according to some embodiments; fig. 5 is a top view four of the semiconductor structure 200, according to some embodiments. The semiconductor structure 200 in the three-dimensional memory includes a source layer SL, a stack structure 232, a gate line slit structure 30, and a first channel structure 220. The stack structure 232 and the first channel structure 220 are both located above the source layer SL. It should be noted that, in fig. 2 to 5, the second direction Y is parallel to the extending direction of the gate line slit structure 30, and the second direction Y is parallel to the gate layer 203; the first direction X is perpendicular to the extending direction of the gate line slit structure 30, and the first direction X is parallel to the gate layer 203; the third direction Z is perpendicular to the plane of the semiconductor structure 200, i.e., perpendicular to the X-Y plane.

The material of the source layer SL has been described in detail previously, and is not described herein again.

The stacked structure 232 includes gate layers 203 and dielectric layers 201 alternately stacked. It is understood that the alternating stacking arrangement means that the gate layer 203 and the dielectric layer 201 are stacked and arranged in an alternating manner; for example, in a direction from the bottom layer to the top layer of the stacked structure 232, a gate layer 203 is disposed first, a dielectric layer 201 is disposed on the gate layer 203, and then a gate layer 203 is disposed on the dielectric layer 201, which are cyclically alternated to form the stacked structure 232. The specific number of stacked layers of the gate layer 203/the dielectric layer 201 can be set according to practical situations. The gate layer 203 may be made of a conductive material, which may be as described in the above embodiments and will not be described herein. The dielectric layer 201 may be made of an insulating material, which may be as described in the above embodiments and will not be described herein.

The stacked structure 232 includes a first area AA and a second area BB adjacent to the first area AA. Illustratively, the first region AA comprises a core region CA and the second region BB comprises a joining region SS.

For convenience of description, the following description will take the first region AA as the core region CA and the second region BB as the connecting region SS as an example. The first area AA includes a first partial transition area AA1 and an effective storage area AA2, where the first partial transition area AA1 is adjacent to the second area, and the first partial transition area AA1 may not have a storage function, or may partially have a storage function; the effective storage area AA2 is located on the side of the first partial transition area AA1 away from the second area, and the effective storage area AA2 has a storage function.

A plurality of channel structures extend through the stacked structure 232, and the channel structure further includes a first channel structure 220 disposed along an edge of the gate line slit structure 30. Wherein the first channel structure 220 may be located in the first region AA and the second region BB. In some embodiments, the first channel structure 220 located at the first area AA may be used for data storage. For example, the first channel structure 220 may have a substantially columnar structure, such as an OxiDe-NitriDe-OxiDe-polysilicon (OxiDe-nitriede-OxiDe-Poly, ONOP) structure, which may be sequentially stacked. In this case, the material of the channel blocking layer may include, for example, silicon oxide, the material of the memory layer may include, for example, silicon nitride, the material of the tunneling layer may include, for example, silicon oxide, and the material of the channel layer may include, for example, polysilicon. In the above steps, a filling layer, for example, silicon oxide, may be further formed in the channel hole in which the memory layer and the channel layer are formed by using a thin film deposition process, such as CVD, PVD, or ALD, and the above channel structure having the channel blocking layer, the memory layer, the tunneling layer, the channel layer, and the filling layer may be referred to as an "ONOPO" structure.

In some other embodiments, the first channel structure 220 located in the second region BB may further include a dummy channel structure. Of course, in other embodiments, a plurality of dummy channel structures may also be located in the first area AA, which is not limited in this embodiment. The dummy channel structure may be the same as or different from the channel structure, which is not limited in this embodiment. It should be noted that the dummy channel structure may not actually be used as a memory cell, but rather may serve to provide mechanical support and/or load balancing for the three-dimensional memory.

In some embodiments, a plurality of semiconductor plugs may be further disposed in the first area AA, and the semiconductor plugs are formed at the bottom of the channel structure, that is, at the bottom SEG (Selective epitaxial Growth); in other examples, the semiconductor plug surrounds a sidewall of the channel structure near one end of the substrate, i.e., sidewall SEG. In some examples, the semiconductor plug comprises N-type polysilicon and the sidewall SEG forms an SWNN (Side Wall N-poly/N-Sub) structure. In some embodiments, the SWNN (Side Wall N-poly/N-Sub) structure may generate a gate-induced-drain-leakage (GIDL) auxiliary body bias voltage when performing an erase operation on the 3D memory device, and is therefore also referred to as a "GIDL erase". The above inventive concepts provided by the disclosed embodiments are applicable to both of the above structures.

It is noted that the semiconductor structure 200 further includes a contact structure 12, the contact structure 12 may be located in the connection region SS (i.e. may be located in the second region BB), and the contact structure 12 penetrates through the stacked structure 232. Referring to fig. 1, the contact structure 12 may include a body portion 121 and an extension portion 122. An extension portion 122 is electrically connected to a gate layer 203 and disposed on the same layer as the gate layer 203. The body portion 121 is joined to the extension portion 122 and penetrates through the stacked structure 232 at a side of the gate layer 203 away from the source layer. Through the above arrangement, one contact structure 12 is electrically connected to one gate layer 203, so that the contact structure 12 can control the channel structure through the gate layer 203, and thus the three-dimensional memory can achieve the functions of reading, erasing, programming, and the like.

The first partition structure 31 includes a first portion 311, the first portion 311 being connected to the second partition structure 32; the width of the second partition structure 32 in the first direction X is greater than the width of the first portion 311 in the first direction X. For example, the widths of the second partition structures 32 in the second direction Y may be all equal, and the widths of the first portions 311 in the second direction Y may also be all equal. Referring to fig. 2, the first portion 311 is located in the first portion transition area AA1.

In summary, the width of the second isolation structure 32 along the first direction X is greater than the width of the first portion 311 along the first direction X, and when the sacrificial layer 202 around the second isolation structure 32 is removed, through the above arrangement, the etching liquid flowing from the second area BB to the first area AA is favorably reduced, so as to avoid etching to the channel structure located in the first area AA, which is favorable for reducing the extension length of the first portion transition area AA1 in the first area AA, extending the extension length of the effective storage area of the first area AA, and being favorable for increasing the storage capacity of the semiconductor structure 200.

As shown in fig. 3-5, the second partition structure 32 may include a second portion 322; the first portion 311 may be connected to the second portion 322; the second portion 322 may include a first end close to the first portion 311 and a second end far from the first portion 311, and a width of the second end M2 in the first direction X is greater than a width of the first end M1 in the first direction X.

It is worth mentioning that the second region BB may comprise a second partial transition region BB1, the second partial transition region BB1 being located on a side of the first partial transition region AA1 facing away from the first region AA. The second part transition area BB1 may not have a memory function, or may partially have a memory function. The second portion 322 is located in the second portion transition zone BB1.

As shown in fig. 3-5, a first end M1 of second portion 322 is a left end of second portion 322 in the position shown, and a second end M2 of second portion 322 is a right end of second portion 322 in the position shown. The width of the second end M2 along the first direction X is greater than the width of the first end M1 along the first direction X. Through the above arrangement, the width of the second portion 322 adjacent to the first area AA along the first direction X can be widened, so that when the sacrificial layer 202 around the second isolation structure 32 is removed, the etching liquid in the second area BB can be favorably diffused toward the first direction X, the etching liquid flowing from the second area BB to the first area AA is reduced, etching to the channel structure located in the first area AA is further avoided, the extension length of the first portion transition area AA1 is favorably reduced, the extension length of the effective storage area AA2 of the first area AA is prolonged, and the storage capacity of the semiconductor structure 200 is favorably improved.

Further, the extension length D1 of the first portion 311 may range from 100nm to 2000nm. Here, the "extension length D1" is a length of the first portion 311 in the second direction Y. In some embodiments, a solid structure may be disposed in the first portion 311, and by adjusting the extension length D1 of the first portion 311, the extension length of the first portion 311 may be further reduced while ensuring the blocking effect of the first portion 311, so as to extend the extension length of the effective storage area AA2 of the first area AA, which is beneficial to increasing the storage capacity of the semiconductor structure 200. For example, the extension length D1 of the first portion 311 may be 100nm, 1000nm, or 2000nm. The extension length D1 of the first portion 311 is greater than 100nm, which is beneficial to ensuring the blocking effect of the first portion 311, and the extension length D1 of the first portion 311 is less than 2000nm, which is beneficial to reducing the extension length of the first portion 311 and improving the storage capacity of the semiconductor structure 200.

With continued reference to fig. 3, the width of the first end M1 in the first direction X may be greater than or equal to the width of the first portion 311 in the first direction X. For example, in fig. 3, the first end M1 of the second portion 322 is connected to the first portion 311, the width of the first portion 311 along the first direction X is equal in the second direction Y, and the width of the first end M1 along the first direction X may be equal to the width of the first portion 311 along the first direction X. Of course, in some examples, the width of the first end M1 in the first direction X may also be greater than the width of the first portion 311 in the first direction X. Through the above arrangement, when the sacrificial layer 202 around the second partition structure 32 is removed, the etching liquid flowing from the second area BB to the first area AA is favorably reduced, and then the channel structure located in the first area AA is prevented from being etched, which is favorable for reducing the extension length of the first part transition area AA1, extending the extension length of the effective storage area AA2 of the first area AA, and contributing to improving the storage capacity of the semiconductor structure 200.

The width of the second portion 322 along the first direction X may gradually increase along the second direction Y, which is to be noted that the second direction Y is an extending direction of the gate line slit structure 30, that is, the second direction Y is a direction pointing from the first end M1 to the second end M2. With continued reference to fig. 3 to fig. 5, the width of the second portion 322 along the first direction X gradually increases from the left end to the right end in the illustrated position, and with the above arrangement, when the sacrificial layer 202 around the second partition structure 32 is removed, the etching liquid flowing from the second region BB to the first region AA can be gradually reduced, which is beneficial to further avoiding etching to the channel structure, further reducing the extension length of the first portion transition region AA1, extending the extension length of the effective storage region AA2 of the first region AA, and being beneficial to improving the storage capacity of the semiconductor structure 200.

In some other embodiments, the width of the second portion 322 along the first direction X may decrease from the first end M1 to the second end M2 and then increase, or the width of the second portion 322 along the first direction X may increase from the first end M1 to the second end M2 and then decrease, which is not limited in this embodiment.

With continued reference to fig. 3-5, the length L of the second portion 322 along the second direction Y is less than or equal to 25nm; and/or the maximum width W of the second portion 322 along the first direction X may range from: 250nm-700nm. For example, the joint surface of the second portion 322 and the first portion 311 may be a plane, and a projection distance of the plane in the first direction X is a length L of the second portion 322 in the second direction Y. The projection distance of the plane in the second direction Y is the maximum width W of the second portion 322 along the first direction X. Through the above arrangement, when the sacrificial layer 202 around the second isolation structure 32 is removed, the etching liquid flowing from the second region BB to the first region AA can be gradually reduced, which is beneficial to further avoiding etching to the channel structure, further reducing the extension length of the first transition region AA1, extending the extension length of the effective storage region AA2 of the first region AA, and being beneficial to improving the storage capacity of the semiconductor structure 200. It should be noted that, in some other embodiments, the joint surface between the second portion 322 and the first portion 311 may also be an arc surface, which is not limited by the disclosure.

For example, the length L of the second portion 322 may be 13nm or 25nm. The length L of the second portion 322 is less than 25nm, which is beneficial for improving the compactness of the semiconductor structure 200. For example, the maximum width W of the second portion 322 along the first direction X may be 250nm, 470nm, or 700nm. The maximum width W of the second portion 322 along the first direction X may be greater than 250nm, which is beneficial for the etching liquid to diffuse to the first direction X through the second portion 322, thereby avoiding etching to the channel structure; the maximum width W of the second portion 322 along the first direction X may be less than 700nm, which is beneficial for improving the structural compactness of the semiconductor structure 200.

With continued reference to fig. 3-5, the second partition structure 32 may further include a third portion 323; the third portion 323 is connected to the second portion 322; the width of the third portion 323 in the first direction X is greater than or equal to the width of the second end M2 in the first direction X. In this embodiment, the widths of the third portion 323 along the first direction X are all equal along the second direction Y, and the width of the second end M2 along the first direction X may be equal to the width of the third portion 323 along the first direction X, so that the etching solution is favorably diffused toward the first direction X through the third portion 323, thereby avoiding etching to the channel structure, reducing the extension length of the first portion transition area AA1, extending the extension length of the effective storage area AA2 of the first area AA, and being favorable for increasing the storage capacity of the semiconductor structure 200. Meanwhile, the regularity of the second isolation structure 32 is improved, the process is simplified, and the manufacturing efficiency of the semiconductor structure 200 is improved.

Of course, in some other embodiments, the widths of the third portions 323 along the first direction X may also be greater than the width of the second end M2 along the first direction X, so as to facilitate the etching solution in the second area BB to further diffuse toward the first direction X, further reduce the extension length of the first portion transition area AA1, and extend the extension length of the effective storage area AA2 of the first area AA, which is beneficial to improve the storage capacity of the semiconductor structure 200.

With continued reference to fig. 3, in some embodiments, the first partition structure 31 may further include a fourth portion 314 and a fifth portion 315; the fourth portion 314 is connected to the first portion 311; the width of the fourth portion 314 in the first direction X is greater than the width of the first portion 311 in the first direction X; the fifth portion 315 is connected to an end of the fourth portion 314 remote from the first portion 311; the width of the fifth portion 315 in the first direction X is smaller than the width of the fourth portion 314 in the first direction X. For example, the width of the fifth portion 315 in the first direction X may be equal to the width of the first portion 311 in the first direction X. By arranging the fourth portion 314 in the first partition structure 31, when the sacrificial layer 202 around the first partition structure 31 is removed, the etching liquid is favorably diffused to the first direction X through the fourth portion 314, the etching liquid flowing from the first area AA to the second area BB is reduced, etching to the contact structure 12 located in the second area BB is avoided, the extension length of the first transition area AA1 is favorably reduced, the extension length of the effective storage area AA2 of the first area AA is prolonged, and the storage capacity of the semiconductor structure 200 is favorably improved.

With continued reference to fig. 4, in some other embodiments, the widths of the first separating structures 31 along the first direction X are equal to each other along the second direction Y, which is beneficial to improving the regularity of the first separating structures 31, simplifying the process, and improving the manufacturing efficiency of the semiconductor structure 200.

It is worth noting that in some embodiments, as shown in fig. 3 to 5, the stacked structure 231 may be provided with one second area BB in the middle of two first areas AA. In the above embodiments, the two first areas AA may have the same structure, for example, the fourth portion 314 is disposed on both of the first areas AA (as shown in fig. 3), or the fourth portion 314 is not disposed on both of the first areas AA (as shown in fig. 4). Of course, the two first areas AA may have different structures, for example, the first area AA at the left end of the illustrated position is provided with the fourth portion 314, and the first area AA at the right end of the illustrated position is not provided with the fourth portion 314 (as shown in fig. 5). Further, in the above-described embodiment, the second partition structure 32 includes at least one second portion 322, for example, the second portion 322 is disposed on the left side or the right side of the third portion 323 in the illustrated position, or the second portions 322 are disposed on both sides of the third portion 323 in the illustrated position.

However, the stacked structure 231 in the embodiment of the disclosure is not limited thereto, and the stacked structure 231 may also include a first area AA and a second area BB, that is, the stacked structure 231 may be provided with the second area BB at the periphery of the first area AA.

As shown in fig. 3, a distance D2 between the first channel structure 220 and the gate line slit structure 30 ranges from 50nm to 200nm. A distance D2 between the first channel structure 220 and the gate line gap structure 30 is a shortest distance between a sidewall of the first channel structure 220 and a sidewall of the gate line gap structure 30. Here, the "shortest distance" may be, for example, a distance between a sidewall of the first channel structure 220 and a sidewall of the second portion 322, and the distance D2 may be 25nm, 38nm, or 50nm. It can be understood that when the distance between the first channel structure 220 and the gate line slit structure 30 is small, the dielectric layer 201 in the stacked structure 232 is easily deformed when the sacrificial layer 202 is removed, resulting in the first channel structure 220 being inclined or even collapsed. The embodiment of the present disclosure is favorable for avoiding the collapse of the first channel structure 220 and improving the performance of the semiconductor structure 200 by controlling the distance between the first channel structure 220 and the gate line gap.

Fig. 6 is a flow chart of steps of a method of fabricating the semiconductor structure 200 according to some embodiments, and fig. 7-29 are schematic structural views of the semiconductor structure 200 at different stages of fabrication according to embodiments of the present disclosure. It should be noted that, in fig. 7 and fig. 29, the second direction Y is parallel to the extending direction of the gate line slit structure 30, and the second direction Y is parallel to the gate layer 203; the first direction X is perpendicular to the extending direction of the gate line slit structure 30, and the first direction X is parallel to the gate layer 203; the third direction Z is perpendicular to the plane of the semiconductor structure 200, i.e., perpendicular to the X-Y plane. Some embodiments of the present disclosure provide a method of fabricating a semiconductor structure 200. Referring to fig. 6 in conjunction with fig. 7 to 29, the method includes S1-S4.

S1, forming a laminated structure, wherein the laminated structure comprises sacrificial layers and dielectric layers which are alternately laminated; the laminated structure includes a first region and a second region adjacent to the first region.

Fig. 7 is a top view of a first channel structure 220 formed in a method of fabricating a semiconductor structure 200 according to some embodiments; fig. 8 is a top view of a gate line spacer trench 34 formed in a method of making a semiconductor structure 200 according to some embodiments; fig. 9 is a cross-sectional view of a gate line spacer 34 formed in a method of fabricating a semiconductor structure 200 according to some embodiments.

It is worth mentioning that, before forming the stacked structure 232, the following steps may be further included: a substrate 210 is provided. Referring to fig. 9, substrate 210 may comprise, for example, a composite substrate 210, the material of which may comprise a combination of multiple of silicon (e.g., single crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), and any other suitable material. Of course, in some embodiments, the substrate 210 may also include a single-layer structure, which is not limited by the embodiments of the present disclosure. An etch stop layer 240 is further disposed on the substrate 210, and the etch stop layer 240 is used to protect the stack structure 232 from being etched when the substrate 210 is subsequently removed. The step of forming the stacked structure 231 further includes: a drain select gate 280 is further disposed on the stack structure 231 in the first region AA, and the drain select gate 280 may be used to open and close a drain of the channel structure.

Referring to fig. 9, the step of forming the stacked structure 232 includes: a stacked structure 231 is formed, and the stacked structure 231 includes a sacrificial layer 202 and a dielectric layer 201 which are alternately stacked. The sacrificial layer 202 and the dielectric layer 201 are made of two different materials, and the etching speed of the sacrificial layer 202 is different from that of the dielectric layer 201 under the same process condition. In some examples, sacrificial layer 202 comprises a nitride (e.g., silicon nitride) and dielectric layer 201 comprises an oxide (e.g., silicon oxide).

As in the previous embodiments, the stacked structure 231 also includes a first region AA and a second region BB, and the first region AA includes a core region and the second region BB includes a connecting region. It is understood that the drawings are illustrated with a first area AA and a second area BB, but the stacked structure 231 in the embodiment of the disclosure is not limited thereto, that is, the stacked structure 231 may have a second area BB disposed at the periphery of a first area AA, or a second area BB disposed in the middle of two first areas AA.

Referring to fig. 7, the step of forming the stack structure 231 further includes: a plurality of channel structures are formed, which further include a first channel structure 220. Wherein the first channel structure 220 is located in the first region AA and the second region BB. As described in the foregoing embodiment, the first channel structure 220 located in the first area AA may be used for data storage, and the first channel structure 220 located in the second area BB may further include a virtual channel structure, which is not described herein again.

It should be noted that, referring to fig. 7, the first channel structure 220 is used to form the gate line slit structure 30 in the region surrounded by the first channel structure 220, so that the first channel structure 220 is disposed along the edge of the gate line slit structure 30. It can be understood that by adjusting the position of the first channel structure 220, the shape of the formed gate line slit structure 30 can be further adjusted, and the number and the position of the first channel structures 220 can be set according to actual needs, which is not specifically limited in the embodiment of the present disclosure.

In this embodiment, after the stacked structure 231 is formed, the method further includes:

and S2, forming a grid line separation groove, extending from the first area to the second area, and penetrating through the laminated structure.

Referring to fig. 8 and 9, the gate line spacer 34 includes a first spacer groove 341 and a second spacer groove 342, the gate line spacer 34 further penetrates the etch stop layer 240, and a portion of the gate line spacer 34 further protrudes into the substrate 210. The first separation groove 341 is located in the first area AA, the second separation groove 342 is located in the second area BB, and the first separation groove 341 communicates with the second separation groove 342. The first partition groove 341 is used for forming the first partition structure 31 therein, and the second partition groove 342 is used for forming the second partition structure 32 therein. It is noted that the empty area in fig. 8 indicates that the inside of the first partition groove 341 or the second partition groove 342 is not filled.

Referring to fig. 9, the first separation groove 341 includes a first groove portion 301 and a second groove portion 302, and the first groove portion 301 and the second groove portion 302 communicate with each other. Illustratively, the first trench 301 may penetrate through the stacked structure 231 and the etch stop layer 240, and a part of the first trench 301 further extends into the substrate 210; the second groove 302 is distant from the groove bottom with respect to the first groove 301. It should be noted that the separation surfaces of the first groove 301 and the second groove 302 may be located on a side of the stacked structure 231 away from the substrate 210, and the embodiment of the disclosure is not limited herein.

Referring to fig. 8, the first partition groove 341 may include a first groove segment 305, a second groove segment 304, and a third groove segment 303, the second groove segment 304 may be located between the first groove segment 305 and the third groove segment 303, and the first groove segment 305 is closer to the second partition groove 342 than the third groove segment 303. As described in the above embodiments, the first area AA includes a first partial transition area AA1 and an effective storage area AA2, and the specific location and function thereof are not described herein again. The first groove segment 305 is located in the first partial transition area AA1, and the effective storage area AA2 includes the second groove segment 304 and the third groove segment 303.

It is noted that the first slot segment 305, the second slot segment 304 and the third slot segment 303 respectively include a portion of the first slot 301 and a portion of the second slot 302.

With continued reference to fig. 8, the second partition may include a fourth slot segment 311 and a fifth slot segment 312, wherein the fourth slot segment 311 may be connected with the first slot segment 305 of the first partition. The width of the end of the fourth slot segment 311 remote from the first slot segment 305 is greater than the width of the end of the fourth slot segment 311 near the first slot segment 305, and the width of the end of the fourth slot segment 311 near the first slot segment 305 is greater than or equal to the width of the first slot segment 305. As described in the above embodiments, the second area BB includes the second partial transition area BB1, and the specific location and function thereof are not described herein again. The area where the fourth slot segment 311 is located is the second partial transition zone BB1.

Through the above arrangement, when the sacrificial layer 202 around the second isolation groove 342 is removed, the etching liquid flowing from the second area BB to the first area AA is reduced, and then the channel structure located in the first area AA is prevented from being etched, so that the extension length of the first transition area AA1 is reduced, the extension length of the effective storage area AA2 of the first area AA is extended, and the storage capacity of the semiconductor structure 200 is improved.

Furthermore, the width of the end of the fourth groove segment 311 away from the first groove segment 305 may be smaller than or equal to the width of the fifth groove segment 312, and through the above arrangement, when the sacrificial layer 202 around the second separating groove 342 is removed, the etching solution is favorably diffused toward the first direction X through the fifth groove segment 312, so as to avoid etching to the channel structure located in the first area AA, reduce the extension length of the first partial transition area AA1, prolong the extension length of the effective storage area AA2 of the first area AA, and favorably improve the storage capacity of the semiconductor structure 200.

With continued reference to fig. 8, the width of the second groove segment 304 is greater than the width of the first groove segment 305, and the width of the third groove segment 303 is less than the width of the second groove segment 304. By arranging the second groove section 304 in the first separating groove 341, when the sacrificial layer 202 around the first separating groove 341 is removed, the etching liquid is favorably diffused toward the first direction X through the second groove section 304, the etching liquid flowing from the first area AA to the second area BB is reduced, and then the etching is avoided to reach the contact structure 12 located in the second area BB, which is favorable for shortening the extension length of the first transition area AA1, extending the extension length of the effective storage area AA2 of the first area AA, and improving the storage capacity of the semiconductor structure 200.

As described in the foregoing embodiments, in some examples, the widths of the first isolation trenches 341 may also be equal along the second direction Y, which is beneficial to improving the regularity of the first isolation trenches 341, simplifying the process, and improving the manufacturing efficiency of the semiconductor structure 200.

Accordingly, fig. 8 illustrates a first separation structure 31 and a second separation structure 32, but the gate line separation groove 34 in the embodiment of the present disclosure is not limited thereto, that is, the gate line separation groove 34 may be provided with a second separation structure 32 at the periphery of a first separation structure 31, or provided with a second separation structure 32 in the middle of two first separation structures 31.

In this embodiment, after the gate line spacing groove 34 is formed, the method further includes:

and S3, replacing the sacrificial layer with a grid layer through the grid line separation groove to form a stack structure.

Referring next to fig. 10 to 16, the step of forming the stacked structure 232 may include: a sacrificial structure 375 is formed, the sacrificial structure 375 being located within the first partition groove 341.

FIG. 10 is a partial cross-sectional view of the structure after formation of a first dielectric material along a plane of the dielectric layer in a method of fabricating a semiconductor structure; FIG. 11 is a cross-sectional view of a first dielectric material 351 formed in a method of fabricating a semiconductor structure 200 according to some embodiments; fig. 12 is a top view of a first sacrificial portion 352 formed in a method of fabricating a semiconductor structure 200 according to some embodiments. With continued reference to fig. 10-12, the steps of forming the sacrificial structure 375 include: a first sacrifice part 352 is formed, and the first sacrifice part 352 fills the first groove part 301.

Referring to fig. 10 and 11, the step of forming the first sacrificial part 352 includes: the first isolation trenches 341 and the second isolation trenches 342 are filled with a first dielectric material 351.

It is worth mentioning that the first dielectric material 351 may be deposited within the first and second isolation trenches 341 and 342 by using one or more thin film deposition processes including, but not limited to, PVD, CVD, ALD, wherein the first dielectric material 351 may comprise, for example, polysilicon, silicon oxynitride, etc.

As shown in fig. 10 and 11, in the first and third slot segments 305 and 303, at least the first dielectric material 351 within the first slot segment 305 is filled with a solid structure. It will be appreciated that, since the width of the first trench segment 305 in the first direction X is smaller than the width of the second trench segment 304 in the first direction X, it is advantageous for the first dielectric material 351 to be filled in the first trench segment 305 during the deposition of the first dielectric material 351. In some embodiments, since the width of third slot segment 303 along first direction X is less than the width of second slot segment 304 along first direction X, packing of first dielectric material 351 within third slot segment 303 is also facilitated. Meanwhile, since the width of the second separation groove 342 in the first direction X is greater than the width of the first separation groove 341 in the first direction X, the first dielectric material 351 is deposited on the sidewall of the second separation groove 342 while forming a solid structure within the first groove segment 305. It should be noted that the empty area in fig. 10 indicates that the inside of the second isolation trench 342 is not filled, and as shown in fig. 11, the first dielectric material 351 is actually deposited on the bottom wall of the second isolation trench 342.

Referring to fig. 12, after filling the first dielectric material 351, the step of forming the first sacrificial portion 352 further includes: the first dielectric material 351 on the inner wall of the second separation groove 342 and a part of the first dielectric material 351 in the first separation groove 341 are removed, and the first dielectric material 351 in the first groove portion 301 remains to form the first sacrificial portion 352.

It is noted that, removing a portion of first dielectric material 351 in first isolation trench 341, that is, removing first dielectric material 351 located in second trench portion 302, so as to leave first dielectric material 351 located in first trench portion 301, forms first sacrificial portion 352. That is, the first groove 301 is a space where the first sacrificial portion 352 is located. It will be appreciated that at least the first sacrificial portion 352 at the first channel section 305 is a solid structure.

Fig. 13 is a top view of a barrier layer 360 formed in a method of fabricating a semiconductor structure 200 according to some embodiments; figure 14 is a cross-sectional view of a barrier layer 360 formed in a method of fabricating the semiconductor structure 200 according to some embodiments. Referring to fig. 13-14, after forming the first sacrificial portion 352, the step of forming the sacrificial structure 375 further includes: forming a barrier layer 360, the barrier layer 360 including a first barrier layer 361 and a second barrier layer 362; first barrier layer 361 covers sidewalls of first sacrificial portion 352 and second trench portion 302; the second barrier layer 362 covers the side of the first sacrificial portion 352 near the second partition groove 342.

With continued reference to fig. 13 and 14, the barrier layer 360 may further include a third barrier layer 363, the third barrier layer 363 covering sidewalls of the second partition trench 342. In some examples, the barrier layer 360 may be formed within the first and second isolation trenches 341 and 342 by using one or more thin film deposition processes including, but not limited to, PVD, CVD, ALD, wherein the material of the barrier layer 360 may include, for example, one or more combinations of silicon nitride, silicon oxide, and silicon oxynitride. It should be noted that the empty area in fig. 13 indicates that the inside of the second isolation trench 342 is not filled, and as shown in fig. 14, a third barrier layer 363 is actually deposited on the bottom wall of the second isolation trench 342.

FIG. 15 is a top view of a second dielectric material 372 formed in a method of fabricating a semiconductor structure 200 according to some embodiments; FIG. 16 is a cross-sectional view of a second dielectric material 372 formed in a method of fabricating semiconductor structure 200 according to some embodiments; fig. 17 is a top view of a mask layer 102 formed in a method of fabricating a semiconductor structure 200 according to some embodiments; fig. 18 is a cross-sectional view of a sacrificial structure 375 formed in a method of fabricating a semiconductor structure 200 according to some embodiments. Referring to fig. 15 and 16, after forming the barrier layer 360, the step of forming the sacrificial structure 375 further includes: forming second sacrificial portions 371, wherein the second groove portions 302 are filled with the second sacrificial portions 371; the first sacrificial portion 352, the first barrier layer 361 and the second sacrificial portion 371 together form a sacrificial structure 375.

Referring to fig. 16, a second dielectric material 372 may be deposited within the first and second isolation trenches 341 and 342 by employing one or more thin film deposition processes including, but not limited to, PVD, CVD, ALD, wherein the second dielectric material 372 may comprise, for example, polysilicon, silicon oxynitride, or the like. A portion of the second dielectric material 372 overlies the first barrier layer 361 and a portion of the second dielectric material 372 also overlies the third barrier layer 363 and is located within the second isolation trench 342. It is understood that in some examples, the width of the second isolation trench 342 is greater than the width of the first isolation trench 341, and after the second dielectric material 372 is deposited in the second isolation trench 342, a gap is present in the second isolation trench 342 to facilitate subsequent removal of the second dielectric material 372 located in the second isolation trench 342.

Referring to fig. 16, after depositing a second dielectric material 372, a masking material 101 may be formed over the stack 231. Referring to fig. 17, after forming the masking material 101, a masking layer 102 may be formed on the stacked-layer structure 231 located in the first area AA, and the masking layer 102 exposes the second dielectric material 372 located in the second area BB and the third barrier layer 363. Referring to fig. 18 and 19, after forming the mask layer 102, the second dielectric material 372 in the second area BB is removed using the mask layer 102 as a mask to form a second sacrificial portion 371. Because the second barrier layer 362 covers the side surface of the first sacrificial part 352 close to the second isolation trench 342, when the second dielectric material 372 is removed, the second barrier layer 362 can play a role in blocking, so as to avoid etching the first sacrificial part 352, which is beneficial to ensuring that at least the first sacrificial part 352 located in the first trench segment 305 is a solid structure.

Through the above steps, the first sacrificial portion 352, the first barrier layer 361, and the second sacrificial portion 371 are sequentially stacked in the first isolation trench 341, and the first sacrificial portion 352, the first barrier layer 361, and the second sacrificial portion 371 together form a sacrificial structure 375.

In some embodiments, referring to fig. 19, the step of forming the semiconductor structure 200 further comprises: a plurality of contact holes 343 are formed, and the contact holes 343 are located in the second region BB and penetrate through the stacked structure 231. In some embodiments, the contact structure 12 may be formed in the contact hole 343, and the contact structure 12 may be as described in the above embodiments, which are not described herein again.

Further, the step of forming the semiconductor structure 200 further includes: a plurality of connection holes 344 are formed, the connection holes 344 being located in the second region BB and penetrating the stacked structure 231. In some embodiments, a connection structure may be formed within the connection hole 344, the connection structure leading out the gate of the semiconductor structure 200 so that the gate may be electrically connected to peripheral devices.

Fig. 20 is a top view of a second gap G2 formed in a method of fabricating a semiconductor structure 200 according to some embodiments; FIG. 21 is a cross-sectional view of a second gap G2 formed in a method of fabricating a semiconductor structure 200 according to some embodiments. Referring to fig. 20 and 21, in the present embodiment, after forming the sacrificial structure 375, the step of forming the stacked structure 232 further includes: a portion of the sacrificial layer 202 located in the second region BB is removed through the second isolation groove 342 to form a second gap G2. It is noted that the mask layer 102 is omitted in fig. 21.

As shown in fig. 21, the second gap G2 is a space where the sacrificial layer 202 located in the second area BB is originally located before being removed, that is, the second gap G2 is located between two adjacent sacrificial layers 202 in the second area BB.

Referring to fig. 19 and 20, the removing of the portion of the sacrificial layer 202 located in the second region BB through the second separation groove 342 further includes: the third barrier layer 363 is removed. In some embodiments, the material of the barrier layer 360 may be the same as the material of the sacrificial layer 202 in the stacked structure 231, which is beneficial to simultaneously removing the third barrier layer 363 and a portion of the sacrificial layer 202 located in the second region BB, simplifying the process, and improving the manufacturing efficiency of the semiconductor structure 200. In some embodiments, the second barrier layer 362 is removed at the same time as the third barrier layer 363 and the portion of the sacrificial layer 202 located in the second region BB are removed.

Further, since at least the first sacrificial portion 352 located in the first groove section 305 is a solid structure, when the second separating groove 342 is used to remove a part of the sacrificial layer 202 located in the second area BB, the solid structure can play a role of blocking, thereby avoiding etching to the channel structure located in the first area AA, which is beneficial to reducing the extension length of the first transition area AA1, extending the extension length of the effective storage area AA2 of the first area AA, and improving the storage capacity of the semiconductor structure 200.

It is understood that, in the above-mentioned process steps, by filling the first dielectric material 351 in at least the first trench segment 305 with a solid structure, and disposing the second barrier layer 362 covering the side surface of the first sacrificial portion 352 close to the second isolation trench 342, the barrier effect of the structure located in the first trench segment 305 is improved, and when the sacrificial layer 202 is removed through the second isolation trench 342, etching to the trench structure located in the first region AA is avoided, which is beneficial to reduce the extension length of the first partial transition region AA1, extend the extension length of the effective storage region AA2 of the first region AA, and improve the storage capacity of the semiconductor structure 200.

Fig. 22 is a top view of a barrier structure 381 formed in a method of fabricating a semiconductor structure 200 according to some embodiments; fig. 23 is a cross-sectional view of a barrier structure 381 formed in a method of fabricating a semiconductor structure 200 according to some embodiments. Referring to fig. 22 and 23, in the present embodiment, after forming the second gap G2, the step of forming the stacked structure 232 further includes: a barrier structure 381 is formed in the second partition groove 342 and the second gap G2.

In some embodiments, barrier structure 381 may be formed by depositing barrier material within second separation trenches 342 and second gap G2 using one or more thin film deposition processes including, but not limited to, PVD, CVD, ALD. Wherein the barrier material may for example comprise carbon.

Figure 24 is a top view of a sacrificial structure 375 removed in a method of fabricating a semiconductor structure 200 according to some embodiments; figure 25 is a cross-sectional view of a semiconductor structure 200 after removal of a sacrificial structure 375 in a method of fabricating the structure, according to some embodiments. Referring to fig. 24 and 25, in the present embodiment, after forming the barrier structure 381, the step of forming the stack structure 232 further includes: sacrificial structure 375 is removed.

In some embodiments, the etch rate of the sacrificial structure 375 is greater than the etch rate of the barrier material under the same process conditions. By providing the barrier structures 381, it is beneficial to prevent the etching liquid from flowing to the second region BB and from etching to the contact structure 12 of the second region BB during the process of removing the sacrificial structure 375, thereby improving the performance of the semiconductor structure 200.

Fig. 26 is a cross-sectional view of a first gap G1 formed in a method of fabricating a semiconductor structure 200 according to some embodiments. Referring to fig. 26, in the present embodiment, after removing the sacrificial structure 375, the step of forming the stacked structure 232 further includes: the sacrificial layer 202 located in the first area AA is removed through the first isolation groove 341 to form a first gap G1.

Illustratively, the first gap G1 is a space where the sacrificial layer 202 located in the first area AA is originally located before being removed, that is, the first gap G1 is located between two adjacent sacrificial layers 202 in the first area AA.

Through the above structure arrangement, by providing the barrier structure 381, when the sacrificial layer 202 is removed through the first isolation groove 341, etching to the contact structure 12 located in the second area BB is avoided, which is beneficial to reducing the extension length of the first partial transition area AA1, extending the extension length of the effective storage area AA2 of the first area AA, and improving the storage capacity of the semiconductor structure 200.

In this embodiment, after forming the first gap G1, the step of forming the stacked structure 232 further includes: the barrier structure 381 is removed. In some embodiments, under the same process conditions, the etching rate of the barrier material is greater than that of the dielectric layer 201 in the stacked structure 232, which is beneficial to reduce the influence on the dielectric layer 201 during the process of removing the barrier structure 381.

Fig. 27 is a top view of a gate layer 203 formed in a method of fabricating a semiconductor structure 200 according to some embodiments; fig. 28 is a cross-sectional view of a gate layer 203 formed in a method of fabricating a semiconductor structure 200 according to some embodiments. Referring to fig. 27 and 28, in the present embodiment, after removing the barrier structure 381, the step of forming the stack structure 232 further includes: and forming a gate layer 203, wherein the gate layer 203 is positioned in the first gap G1 and the second gap G2, and the gate layer 203 and the dielectric layer 201 jointly form a stack structure 232.

Referring to fig. 28, for example, an adhesion layer 391 and a gate conductive layer 392 may be sequentially deposited within the first gap G1 and the second gap G2 to form the gate layer 203. Among other things, the adhesive layer 391 serves to improve adhesion between the gate conductive layer 392 and other structures in contact, thereby improving reliability of the semiconductor structure 200. The adhesion layer 391 may be a conductive material including one or a combination of metals (e.g., titanium (Ti), tantalum (Ta), chromium (Cr), tungsten (W), etc.), metal compounds (e.g., titanium nitride (TiNx), tantalum nitride (TaNx), chromium nitride (CrNx), tungsten nitride (WNx), etc.), and metal alloys (e.g., tiSixNy, taSixNy, crSixNy, WSixNy, etc.). Gate conductive layer 392 comprises a conductive material including, for example, a combination of one or more of tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or other suitable materials.

In some embodiments, depositing the adhesion layer 391 and the gate conductive layer 392 sequentially within the first gap G1 and the second gap G2 further includes: the adhesive layer 391 and the gate conductive layer 392 also cover the sidewalls of the first partition groove 341; the gate conductive layer 392 covering the sidewalls of the first partition grooves 341 is removed.

In some embodiments, the gate layer 203 is formed while further including: forming a gate conductive layer 392 in the contact hole 343; the gate conductive layer 392 covering the surface of the stack structure 232 is removed to form a first conductive layer 393 covering the sidewalls of the contact hole 343. By forming the first gap G1, the second gap G2, and the gate conductive layer 392 in the contact hole 343 simultaneously, the process is simplified, and the manufacturing efficiency of the semiconductor structure 200 is improved. Further, before the gate conductive layer 392 is formed in the contact hole 343, the first gap G1, the second gap G2, and the adhesive layer in the contact hole 343 may be simultaneously formed, thereby further simplifying the process and further improving the manufacturing efficiency of the semiconductor structure 200.

In some examples, after the first conductive layer 393 is formed in the contact hole 343, the contact hole 343 may be filled with an insulating material, and the insulating material, the first conductive layer 393, and the adhesive layer together constitute the contact structure 12.

In some embodiments, the method further includes, while forming the gate layer 203: a gate conductive layer 392 is formed in the connection hole 344; the gate conductive layer 392 covering the surface of the stacked structure 232 is removed to form a second conductive layer 394 covering the sidewalls of the connection hole 344. By forming the first gap G1, the second gap G2, the contact hole 343, and the gate conductive layer 392 in the connection hole 344 simultaneously, the process can be further simplified, and the manufacturing efficiency of the semiconductor structure 200 can be improved.

Figure 29 is a cross-sectional view of a separation structure formed in a method of fabricating a semiconductor structure according to some embodiments. Referring to fig. 29, after forming the stacked structure 232, further includes:

s4, filling the grid line separation grooves to form a grid line gap structure, wherein the grid line gap structure comprises a first separation structure and a second separation structure; the first separation structure is positioned in the first zone, and the second separation structure is positioned in the second zone; the first partition structure includes a first portion; the width of the second partition structure in the first direction is greater than the width of the first portion in the first direction; the first direction is perpendicular to the extending direction of the gate line gap structure and parallel to the gate layer.

In some embodiments, the gate line slit structure 30 may be formed, for example, by filling an insulating material, or by sequentially filling an insulating material and a conductive material. For example, the number of the gate line slit structures 30 may be plural, and the plural gate line slit structures 30 are disposed at intervals along the first direction X.

In some examples, the first partition structure 31 is formed with the first portion 311 positioned within the first channel section 305, and the second partition structure 32 is formed with the second portion 322 positioned within the fourth channel section 311. Through the above arrangement, the width of the second portion 322 adjacent to the first area AA can be widened, when the sacrificial layer 202 around the second isolation structure 32 is removed, the etching liquid in the second area BB can be favorably diffused toward the first direction X, the etching liquid flowing from the second area BB to the first area AA is reduced, and then the etching to the channel structure located in the first area AA is avoided, which is favorable for reducing the extension length of the transition area AA1 of the first portion, extending the extension length of the effective storage area AA2 of the first area AA, and improving the storage capacity of the semiconductor structure 200. Here, the "transition area" refers to an area where the first portion 311 is located in the first area AA.

In summary, the method for manufacturing the semiconductor structure 200 according to the embodiment of the present disclosure includes: forming a stacked structure 231; forming a gate line spacer groove 34; replacing the sacrificial layer 202 with a gate layer 203 via the gate line spacer 34 to form a stacked structure 232; the gate line spacer trenches 34 are filled to form the gate line gap structure 30. The width of the second partition structure 32 in the first direction X is greater than the width of the first portion 311. When the sacrificial layer 202 around the second isolation structure 32 is removed, the etching liquid in the second area BB is favorably diffused toward the first direction X, the etching liquid flowing from the second area BB to the first area AA is reduced, etching to the channel structure located in the first area AA is avoided, the extension length of the first transition area AA1 is favorably reduced, the extension length of the effective storage area AA2 of the first area AA is prolonged, and the storage capacity of the semiconductor structure 200 is favorably improved.

FIG. 30 is a block diagram of a memory system according to some embodiments. FIG. 31 is a block diagram of memory systems according to further embodiments.

Referring to fig. 30 and 31, some embodiments of the present disclosure also provide a memory system 1000. The memory system 1000 includes a controller 20, and the three-dimensional memory 10 of some embodiments as above, the controller 20 is coupled to the three-dimensional memory 10 to control the three-dimensional memory 10 to store data.

The Storage system 1000 may be integrated into various types of Storage devices, for example, included in the same package (e.g., universal Flash Storage (UFS) package or Embedded multimedia Card (eMMC) package). That is, the storage system 1000 may be applied to and packaged into different types of electronic products, such as a mobile phone (e.g., a cell phone), a desktop computer, a tablet computer, a laptop computer, a server, an in-vehicle device, a game console, a printer, a positioning device, a wearable device, a smart sensor, a mobile power supply, a Virtual Reality (VR) device, an Augmented Reality (AR) device, or any other suitable electronic device having storage therein.

In some embodiments, referring to fig. 30, the memory system 1000 includes a controller 20 and a three-dimensional memory 10, and the memory system 1000 may be integrated into a memory card.

The Memory Card includes any one of a PC Card (PCMCIA), a Compact Flash (CF) Card, a Smart Media (SM) Card, a Memory stick, a Multimedia Card (MMC), a Secure Digital Memory Card (SD), and a UFS.

In other embodiments, referring to fig. 31, the storage system 1000 includes a controller 20 and a plurality of three-dimensional memories 10, and the storage system 1000 is integrated into a Solid State Drive (SSD).

In storage system 1000, in some embodiments, controller 20 is configured for operation in a low duty cycle environment, such as an SD card, CF card, universal Serial Bus (USB) flash drive, or other media for use in electronic devices such as personal computers, digital cameras, mobile phones, and the like.

In other embodiments, the controller 20 is configured for operation in a high duty cycle environment SSD or eMMC for data storage and enterprise storage arrays of mobile devices such as smart phones, tablets, laptops, and the like.

In some embodiments, the controller 20 may be configured to manage data stored in the three-dimensional memory 10 and communicate with an external device (e.g., a host). In some embodiments, the controller 20 may also be configured to control operations of the three-dimensional memory 10, such as read, erase, and program operations. In some embodiments, the controller 20 may be further configured to manage various functions with respect to data stored or to be stored in the three-dimensional memory 10, including at least one of bad block management, garbage collection, logical to physical address translation, wear leveling. In some embodiments, the controller, 20 is further configured to process error correction codes for data read from the three-dimensional memory 10 or written to the three-dimensional memory 10.

Of course, the controller 20 may also perform any other suitable functions, such as formatting the three-dimensional memory 10; for example, the controller 20 may communicate with an external device (e.g., a host) via at least one of a variety of interface protocols.

It should be noted that the interface protocol includes at least one of a USB protocol, an MMC protocol, a Peripheral Component Interconnect (PCI) protocol, a PCI express (PCI-E) protocol, an Advanced Technology Attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a Small Computer System Interface (SCSI) protocol, an Enhanced Small Disk Interface (ESDI) protocol, an Integrated Drive Electronics (IDE) protocol, and a Firewire protocol.

Some embodiments of the present disclosure also provide an electronic device. The electronic device may be any one of a mobile phone, a desktop computer, a tablet computer, a notebook computer, a server, an in-vehicle device, a wearable device (e.g., a smart watch, a smart bracelet, smart glasses, etc.), a mobile power source, a game console, a digital multimedia player, and the like.

The electronic device may include the storage system 1000 described above, and may further include at least one of a Central Processing Unit (CPU), a cache (cache), and the like.

The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.

Claims (17)

1. A semiconductor structure, comprising:

the stacked structure comprises gate layers and dielectric layers which are alternately stacked; the stacking structure comprises a first area and a second area adjacent to the first area;

a gate line slit structure extending from the first region to the second region and penetrating the stacked structure; the grid line gap structure comprises a first separation structure and a second separation structure; the first separation structure is located in the first zone and the second separation structure is located in the second zone;

the first partition structure includes a first portion connected to the second partition structure; a width of the second partition structure in a first direction is greater than a width of the first portion in the first direction;

the first direction is perpendicular to the extending direction of the grid line gap structure and parallel to the grid layer.

2. The semiconductor structure of claim 1, wherein the second spacer structure comprises a second portion; the second portion includes a first end proximate to the first portion and a second end distal from the first portion, the second end having a width in a first direction that is greater than a width of the first end in the first direction, the first end having a width in the first direction that is greater than or equal to the width of the first portion in the first direction.

3. The semiconductor structure of claim 2, wherein the direction from the first end to the second end is a second direction;

the width of the second portion in the first direction gradually increases in the second direction.

4. The semiconductor structure of claim 2, wherein the direction from the first end to the second end is a second direction;

a length of the second portion along the second direction is less than or equal to 25nm; and/or the presence of a gas in the gas,

the maximum width of the second portion along the first direction has a range of values: 250nm-700nm.

5. The semiconductor structure of claim 2, wherein the second spacer structure further comprises a third portion;

the third portion is connected to the second portion; the widths of the third portions in the first direction are each greater than or equal to the width of the second end in the first direction.

6. The semiconductor structure of any one of claims 2-4, wherein the first separation structure further comprises a fourth portion and a fifth portion;

the fourth portion is connected to the first portion; a width of the fourth portion in the first direction is greater than a width of the first portion in the first direction;

the fifth part is connected with one end of the fourth part far away from the first part; a width of the fifth portion in the first direction is smaller than a width of the fourth portion in the first direction.

7. The semiconductor structure of any of claims 2-4, further comprising:

a plurality of channel structures extending through the stacked structure; the plurality of channel structures comprise a first channel structure arranged along the edge of the grid line gap structure, and the distance between the first channel structure and the grid line gap structure ranges from 50nm to 200nm.

8. A method for fabricating a semiconductor structure, comprising,

forming a laminated structure, wherein the laminated structure comprises sacrificial layers and dielectric layers which are alternately laminated; the laminated structure comprises a first area and a second area adjacent to the first area;

forming a grid line separation groove, extending from the first region to the second region and penetrating through the laminated structure;

replacing the sacrificial layer with a gate layer through the gate line isolation groove to form a stacked structure;

filling the grid line separation grooves to form a grid line gap structure, wherein the grid line gap structure comprises a first separation structure and a second separation structure; the first separation structure is located in the first zone, the first separation structure comprising a first portion; a width of the second partition structure in a first direction is greater than a width of the first portion in the first direction;

the first direction is perpendicular to the extending direction of the gate line gap structure and parallel to the gate layer.

9. The method of manufacturing of claim 8, wherein the grid spacer grooves include a first spacer groove in the first region and a second spacer groove in the second region;

the forming a stacked structure includes:

forming a sacrificial structure, wherein the sacrificial structure is positioned in the first separation groove;

removing a portion of the sacrificial layer located in the second region through the second separation groove to form a second gap;

forming a blocking structure located in the second separation groove and the second gap;

removing the sacrificial structure;

removing the sacrificial layer located in the first region through the first separation groove to form a first gap;

removing the barrier structure;

and forming a gate layer, wherein the gate layer is positioned in the first gap and the second gap, and the gate layer and the dielectric layer jointly form the stack structure.

10. The production method according to claim 9, wherein the first partition groove includes a first groove portion and a second groove portion, the second groove portion being distant from a groove bottom with respect to the first groove portion;

the forming of the sacrificial structure comprises:

forming a first sacrificial part, wherein the first sacrificial part is filled in the first groove part;

forming a barrier layer, wherein the barrier layer comprises a first barrier layer and a second barrier layer; the first barrier layer covers the first sacrificial part and the side wall of the second groove part; the second barrier layer covers the side face, close to the second separation groove, of the first sacrificial part;

forming a second sacrificial part, wherein the second sacrificial part is filled in the second groove part;

wherein the first sacrificial portion, the first barrier layer, and the second sacrificial portion collectively comprise the sacrificial structure.

11. The method of manufacturing according to claim 10, wherein the barrier layer further includes a third barrier layer covering a side wall of the second separation groove.

12. The method of manufacturing of claim 10, wherein the forming a first sacrificial portion comprises:

filling a first dielectric material in the first separation groove and the second separation groove; the first separator tank includes a first tank section, a second tank section, and a third tank section, the second tank section being located between the first tank section and the third tank section, the first tank section being closer to the second separator tank than the third tank section; in the first groove section and the third groove section, at least the first medium material in the first groove section is filled into a solid structure;

and removing the first dielectric material on the inner wall of the second separation groove and part of the first dielectric material in the first separation groove, and reserving the first dielectric material in the first groove part to form the first sacrificial part.

13. The method according to claim 11, wherein the removing, via the second separation groove, the portion of the sacrificial layer located in the second region further includes: and removing the third barrier layer.

14. The method of any one of claims 9-13, further comprising:

forming a contact hole, wherein the contact hole is positioned in the second area;

when the gate layer is formed, the method further comprises the following steps: and forming a gate conductive layer in the contact hole.

15. A three-dimensional memory, comprising:

a semiconductor structure as claimed in any one of claims 1 to 7;

a peripheral device electrically connected to the semiconductor structure.

16. A storage system, comprising:

a three-dimensional memory as claimed in claim 15;

a controller coupled to the three-dimensional memory to control the three-dimensional memory to store data.

17. An electronic device comprising the storage system of claim 16.

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