CN114664842A

CN114664842A - Semiconductor structure and preparation method thereof, memory, storage system and electronic equipment

Info

Publication number: CN114664842A
Application number: CN202210264478.XA
Authority: CN
Inventors: 乔思; 高晶
Original assignee: Yangtze Memory Technologies Co Ltd
Current assignee: Yangtze Memory Technologies Co Ltd
Priority date: 2022-03-17
Filing date: 2022-03-17
Publication date: 2022-06-24

Abstract

The application provides a semiconductor structure, a preparation method of the semiconductor structure, a memory, a storage system and electronic equipment, relates to the technical field of semiconductor chips, and aims to improve the storage performance of the memory. The preparation method of the semiconductor structure comprises the following steps: forming a laminated structure on a substrate, wherein the laminated structure comprises a gate dielectric layer and a gate sacrificial layer which are sequentially and alternately laminated; forming a first capping layer on the stacked structure; etching the first covering layer and the laminated structure to form a channel hole; corroding the side wall of the channel hole by using corrosive liquid so as to flatten the side wall of the channel hole; the acid corrosion resistance of the first covering layer to the corrosive liquid is less than that of the laminated structure to the corrosive liquid, and the diameter of the corroded channel hole in the first covering layer is greater than or equal to that of the channel hole in the laminated structure; a functional layer and a dielectric core are sequentially formed in the channel hole to form a channel structure. The prepared semiconductor structure is used for realizing reading and writing operations of data.

Description

Semiconductor structure and preparation method thereof, memory, storage system and electronic equipment

Technical Field

The present disclosure relates to the field of semiconductor technologies, and in particular, to a semiconductor structure, a method for manufacturing the semiconductor structure, a memory, a storage system, and an electronic device.

Background

As the feature size of the memory cell approaches the lower limit of the process, the manufacturing technology such as the planar process becomes challenging and brings high cost, which causes the storage density of the planar memory such as the 2D (2-dimensional) NAND flash memory to approach the upper limit, and brings serious challenges to the semiconductor memory industry.

The above limitations can be overcome by a three-dimensional memory (e.g., a 3D NAND flash memory), and in particular, by stacking memory cells three-dimensionally to form a multi-layered structure, the memory density is increased, and the memory capacity is several times higher than that of a similar planar memory. In the preparation process of the three-dimensional memory, a laminated structure needs to be formed on a substrate, and the laminated structure needs to be etched to form a channel hole penetrating through the laminated structure. However, as the number of layers of the stacked structure increases, the aspect ratio of the trench hole becomes larger and larger, and the formation process of the trench hole also presents challenges.

Disclosure of Invention

Embodiments of the present application provide a semiconductor structure, a manufacturing method thereof, a memory, a storage system, and an electronic device, and aim to improve the storage performance of the memory.

In order to achieve the above purpose, the embodiment of the present application adopts the following technical solutions:

in one aspect, a method for fabricating a semiconductor structure is provided, the method comprising: forming a laminated structure on a substrate, wherein the laminated structure comprises a gate dielectric layer and a gate sacrificial layer which are sequentially laminated and alternately arranged; forming a first capping layer on the stacked structure; etching the first covering layer and the laminated structure to form a channel hole; the channel hole penetrates through the first covering layer and the laminated structure in sequence; corroding the side wall of the channel hole by using corrosive liquid so as to flatten the side wall of the channel hole; the acid corrosion resistance of the first covering layer to the corrosive liquid is smaller than that of the laminated structure to the corrosive liquid, and the diameter of the corroded channel hole in the first covering layer is larger than or equal to that of the channel hole in the laminated structure; a functional layer and a dielectric core are sequentially formed in the channel hole to form a channel structure, the functional layer being disposed on an outer wall of the dielectric core.

In some embodiments, forming a stacked structure on a substrate includes: forming a gate dielectric layer and a gate sacrificial layer which are alternately arranged in a stacked mode on a substrate; forming a second covering layer on one side, far away from the substrate, of the gate dielectric layer and the gate sacrificial layer which are alternately stacked; the laminated structure further includes a second cover layer; .

In some embodiments, the material of the first cover layer and the material of the second cover layer are the same; the density of the material of the first cover layer is less than the density of the material of the second cover layer.

In some embodiments, the material of the first cover layer and the material of the second cover layer are not the same.

In some embodiments, after the functional layer and the dielectric core are sequentially formed in the channel hole to form the channel structure, the above manufacturing method further includes: removing the gate sacrificial layer to form a sacrificial gap; and forming a gate electrode layer in the sacrificial gap to form a stacked structure, wherein the stacked structure comprises a gate dielectric layer and a gate electrode layer which are stacked and arranged alternately.

In some embodiments, before forming the stacked structure on the substrate, the above preparation method further includes: an etch stop layer is formed on the substrate.

In yet another aspect, a semiconductor structure is provided. The semiconductor structure includes a stack structure, a first capping layer, a channel hole, and a channel structure. The stacked structure comprises gate dielectric layers and gate electrode layers which are alternately stacked. The first covering layer is arranged on one side of the stacking structure. The channel hole penetrates through the first capping layer and the stacked structure. The diameter of the channel hole at the first covering layer is larger than or equal to that of the channel hole at the stacking structure, and the acid corrosion resistance of the first covering layer is smaller than that of the gate dielectric layer. A channel structure is disposed within the channel hole, the channel structure including a dielectric core and a functional layer. The functional layer is disposed on an outer wall of the dielectric core.

In some embodiments, the diameter of the dielectric core at the first capping layer is greater than or equal to the diameter of the dielectric core at the stacked structure.

In some embodiments, the semiconductor structure further comprises a second capping layer disposed on a side of the first capping layer facing the substrate and on a side of the stacked alternating gate dielectric layers and gate layers facing away from the substrate. The acid corrosion resistance of the first cover layer is less than the acid corrosion resistance of the second cover layer.

In some embodiments, the thickness of the first cover layer is greater than or equal to the thickness of the second cover layer.

In some embodiments, the first capping layer has a thickness in the range of

In some embodiments, the semiconductor structure further includes a source layer disposed on a side of the stacked structure remote from the first cladding layer and coupled to the functional layer in the channel structure.

In another aspect, a three-dimensional memory is provided. The three-dimensional memory includes a semiconductor structure as described in some embodiments above and peripheral circuitry electrically coupled to the semiconductor structure.

In yet another aspect, a storage system is provided. The storage system comprises a controller and a three-dimensional memory as described in some embodiments above, the controller being electrically coupled to the three-dimensional memory for controlling the three-dimensional memory to store data.

In yet another aspect, an electronic device is provided. The electronic device includes a printed circuit board and a memory system as described in some embodiments above, the printed circuit board being coupled to the memory system.

The embodiment of this application is at the in-process of preparation semiconductor construction, because form first overburden in one side of stromatolite, and the acid corrosion resistance of first overburden is less than the acid corrosion resistance of stromatolite, thereby when adopting corrosive liquid to carry out the planarization to the trench hole, the corrosive liquid is greater than the corrosive liquid to the corrosion rate of stromatolite to first overburden, consequently, can guarantee to adopt corrosive liquid to carry out the planarization to the trench hole back, the trench hole is greater than or equal to the trench hole at the diameter of stromatolite at first overburden, so, can carry out reaming processing to the top of trench hole, when having solved and having formed the trench hole at the sculpture, the throat problem appears in the top of trench hole. The diameter of the top end of the channel hole can be increased while the channel hole is flattened by using the corrosive liquid, so that the diameter of the top end of the channel hole is larger than or equal to the diameter of other positions of the channel hole, and thus, when the functional layer and the dielectric core are sequentially formed in the channel hole to form a channel structure, pores are prevented from being easily formed in the dielectric core, and therefore, when a conductive structure is formed above the channel hole in the subsequent process, conductive materials easily enter the pores in the channel hole, so that the storage of electric charges is influenced, the storage performance of the memory is influenced, the yield of products is increased, and the storage performance of the three-dimensional memory is ensured. On the basis, the flattening treatment of the channel hole by using the corrosive liquid is an existing process step in the preparation of the semiconductor structure, and the existing process step is used for carrying out reaming treatment on the necking at the top end of the channel hole, namely, the reaming treatment is carried out on the top end of the channel hole while the flattening treatment is carried out on the channel hole by using the corrosive liquid, so that the operation step does not need to be increased, and the preparation cost does not need to be increased.

It can be understood that the semiconductor structure, the three-dimensional memory, the storage system and the electronic device provided in the embodiments of the present application may refer to the above-mentioned advantages of the semiconductor structure preparation method, and no further description is provided herein.

Drawings

In order to more clearly illustrate the technical solutions in the present application, the drawings required to be used in some embodiments of the present application will be briefly described below, and it is apparent that the drawings in the following description are only drawings of some embodiments of the present application, and other drawings can be obtained by those skilled in the art according to the drawings. Furthermore, the drawings in the following description may be regarded as schematic diagrams, and do not limit actual sizes of products, actual flows of methods, actual timings of signals, and the like, which are related to the embodiments of the present application.

Fig. 1 is a block diagram of an electronic device provided in an embodiment of the present application;

FIG. 2a is a block diagram of a storage system provided by an embodiment of the present application;

FIG. 2b is a block diagram of a memory system according to another embodiment of the present application;

FIG. 3 is a block diagram of a three-dimensional memory according to an embodiment of the present application;

fig. 4a is a perspective view of a semiconductor structure according to an embodiment of the present application;

FIG. 4b is a cross-sectional view of a memory cell string along line AA' in the semiconductor structure shown in FIG. 4 a;

FIG. 4c is an equivalent circuit diagram of a memory cell string of the semiconductor structure of FIG. 4 a;

fig. 5 is a flow chart of a method of fabricating a semiconductor structure according to an embodiment of the present application;

FIG. 6 is a cross-sectional view of a first embodiment of a semiconductor structure during fabrication;

fig. 7 is a cross-sectional structural diagram of a second process for fabricating a semiconductor structure according to an embodiment of the present application;

fig. 8 is a cross-sectional structural diagram three of a process of fabricating a semiconductor structure according to an embodiment of the present application;

fig. 9 is a cross-sectional structural diagram of a process of fabricating a semiconductor structure according to an embodiment of the present application;

FIG. 10a is a cross-sectional view of a fifth example of a cross-sectional structure during fabrication of a semiconductor structure according to an embodiment of the present disclosure;

FIG. 10b is a block diagram of a stacked structure provided by the prior art;

FIG. 10c is a diagram illustrating a prior art method for forming a trench structure in a trench hole;

FIG. 10d is a block diagram of a semiconductor structure provided in the prior art;

FIG. 10e is a prior art block diagram of a conductive structure and a dielectric core in a semiconductor structure;

FIG. 10f is a cross-sectional view of a sixth example of a semiconductor structure in the fabrication of the semiconductor structure according to the present disclosure;

fig. 11 is a cross-sectional structural diagram seven illustrating a process of fabricating a semiconductor structure according to an embodiment of the present application;

fig. 12 is a cross-sectional structural view eight illustrating a process of manufacturing a semiconductor structure according to an embodiment of the present disclosure;

fig. 13 is a cross-sectional structural diagram nine in a process of manufacturing a semiconductor structure according to an embodiment of the present application;

fig. 14 is a cross-sectional structural view ten of a process for fabricating a semiconductor structure according to an embodiment of the present application;

fig. 15a is a cross-sectional structural diagram eleven illustrating a process of manufacturing a semiconductor structure according to an embodiment of the present application;

FIG. 15b is a topographical view of a semiconductor structure provided in accordance with an embodiment of the present application;

fig. 16 is a cross-sectional structural diagram twelve during a process of manufacturing a semiconductor structure according to an embodiment of the present application;

fig. 17 is a cross-sectional structural diagram thirteen in a process of manufacturing a semiconductor structure according to an embodiment of the present application;

fig. 18 is a cross-sectional structural view fourteen in a process of manufacturing a semiconductor structure according to an embodiment of the present application;

fig. 19 is a cross-sectional structural diagram fifteen illustrating a process of fabricating a semiconductor structure according to an embodiment of the present application;

fig. 20 is a cross-sectional structural diagram sixteen of a process of fabricating a semiconductor structure according to an embodiment of the present application;

fig. 21 is a seventeenth cross-sectional view of a semiconductor structure during fabrication thereof according to an embodiment of the present disclosure;

fig. 22 is a sectional structural view eighteen of a process of manufacturing a semiconductor structure according to an embodiment of the present application;

fig. 23 is a nineteen sectional structural view in a process of manufacturing a semiconductor structure according to an embodiment of the present application;

FIG. 24 is a cross-sectional structural view of a semiconductor structure provided in an embodiment of the present application;

FIG. 25 is a cross-sectional view of a semiconductor structure according to another embodiment of the present application;

FIG. 26 is a first cross-sectional view illustrating a process of fabricating a semiconductor structure according to the related art;

FIG. 27 is a sectional view of a second embodiment of a semiconductor structure fabrication process in accordance with the related art;

fig. 28 is a sectional view showing a third structure in a process of manufacturing a semiconductor structure according to the related art;

fig. 29 is a cross-sectional structural view of a semiconductor structure manufacturing process according to the related art;

fig. 30 is a cross-sectional structural view showing a fifth process of fabricating a semiconductor structure according to the related art;

fig. 31 is a cross-sectional structural diagram six of a process of manufacturing a semiconductor structure according to the related art.

Reference numerals: 1-an electronic device; 01-a storage system; 02-printed circuit board; 10-a three-dimensional memory; 11-a controller; 100-a semiconductor structure; 101-a stacked structure; 102-a first cover layer; 103-channel holes; 104-a channel structure; 105-a string of memory cells; 106-a stacked structure; 107-a second cover layer; 110-a functional layer; 110 a-a barrier layer; 110 b-a charge storage layer; 110 c-a tunneling layer; 110 d-channel layer; 111-a dielectric core; 120-gate dielectric layer; 121-gate layer; 1211-conductor layer; 1212-a gate barrier layer; 122-a gate sacrificial layer; 123-sacrificial gap; 160-first cover layer, 200-substrate; 201-a substrate; 201' -a substrate; 201 a-a bottom plate; 201b — a first sacrificial layer; 201c — a second sacrificial layer; 202-peripheral circuitry; 203-etching the barrier layer; 204-array interconnect layer; 205-a first interlayer insulating layer; 206-a first interconnect conductor layer; 207-bonding interface; 209-transistor; 210-peripheral interconnect layer; 211 — a second interlayer insulating layer; 212-second interconnect conductor layer.

Detailed Description

The technical solutions in some embodiments of the present application will be described clearly and completely with reference to the accompanying drawings, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments that can be derived by one of ordinary skill in the art from the examples provided herein fall within the scope of the present application.

In the description of the present application, it is to be understood that the terms "center", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like indicate orientations or positional relationships based on those shown in the drawings, and are only for convenience in describing the present application and simplifying the description, but do not indicate or imply that the referred device or element must have a particular orientation, be constructed in a particular orientation, and be operated, and thus should not be construed as limiting the present application.

Throughout the specification and claims, the term "comprising" is to be interpreted in an open, inclusive sense, i.e., as "including, but not limited to," unless the context requires otherwise. In the description herein, the terms "one embodiment," "some embodiments," "an example embodiment," "exemplarily" or "some examples" or the like are intended to indicate that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present application. The schematic representations of the above terms are not necessarily referring to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be included in any suitable manner in any one or more embodiments or examples.

In the following, the terms "first", "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the embodiments of the present application, "a plurality" means two or more unless otherwise specified.

In describing some embodiments, the expression "coupled" and its derivatives may be used. For example, the term "coupled" may be used in describing some embodiments to indicate that two or more elements are in direct physical or electrical contact. The term "coupled," however, may also mean that two or more elements are not in direct contact with each other, but yet still co-operate or interact with each other. For example, the term "electrically coupled" may be used in describing some embodiments to indicate that two or more elements are in direct physical and electrical contact or are in physical and electrical contact through other elements. The embodiments disclosed herein are not necessarily limited to the contents herein.

The use of "configured to" herein means open and inclusive language that does not exclude devices that are suitable or configured to perform additional tasks or steps.

In the context of this application, the meaning of "on … …", "above", and "over" should be interpreted in the broadest manner such that "on.

Example embodiments are described herein with reference to cross-sectional and/or plan views as idealized example figures. In the drawings, the thickness of layers and regions are exaggerated for clarity. Variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, the exemplary embodiments should not be construed as limited to the shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the exemplary embodiments.

As used herein, the term "substrate" refers to a material onto which subsequent layers of material may be added. The substrate itself may be patterned. The material added to the substrate may be patterned or may remain unpatterned. In addition, the substrate may include a variety of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, and the like. Alternatively, the substrate may be made of a non-conductive material such as glass, plastic, or sapphire wafer.

The term "three-dimensional memory" refers to a semiconductor device formed of memory cell transistor strings (referred to herein as "memory cell strings", e.g., NAND memory cell strings) arranged in an array on a main surface of a substrate and extending in a direction perpendicular to the substrate. As used herein, the term "perpendicular" means nominally perpendicular to a major surface (i.e., a lateral surface) of a substrate.

Embodiments of the present application provide an electronic device, which may include, for example, any one of a mobile phone (mobile phone), a tablet computer (pad), a notebook computer, a television, a Personal Digital Assistant (PDA), an ultra-mobile personal computer (UMPC), a netbook, a wearable device (e.g., a smart watch, a smart bracelet, and smart glasses), and the like.

Fig. 1 exemplarily provides a block diagram of an electronic device, and as shown in fig. 1, the electronic device 1 includes a memory system 01 and a printed circuit board 02, and the printed circuit board 02 is coupled to the memory system 01.

As shown in fig. 2a, the storage system 01 includes a three-dimensional memory 10 and a controller 11, wherein the controller 11 is electrically coupled to the three-dimensional memory 10 for controlling the three-dimensional memory 10 to store data.

In some examples, as shown in fig. 2a, the storage system 01 may include a three-dimensional memory 10, in which case the storage system 10 may be integrated into a memory card, wherein the memory card includes any one of a PC card (PCMCIA), a Compact Flash (CF) card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC), a Secure Digital (SD) card, and a UFS.

In other examples, as shown in fig. 2b, the storage system 01 includes a plurality of three-dimensional memories 10, in which case the storage system 01 may be integrated into a Solid State Drive (SSD).

Referring to fig. 3, the three-dimensional memory 10 described above includes: the semiconductor device includes a base 200 and a semiconductor structure 100 disposed on one side of the base 200, wherein the base 200 includes a substrate 201 'and a peripheral circuit 202 disposed on the substrate 201', and the peripheral circuit 202 is electrically coupled to the semiconductor structure 100. The coupling means may be, for example, a bond or the like.

The substrate 201' may be, for example, monocrystalline silicon, or may be other suitable materials, such as silicon germanium, or a silicon-on-insulator thin film.

The peripheral circuit may include a transistor. The peripheral circuitry 202 is configured to control and sense the semiconductor structure 100. Peripheral circuitry 202 may be any suitable digital, analog, and/or mixed-signal control and sensing circuitry for supporting the operation (or working) of semiconductor structure 100, including, but not limited to, page buffers, decoders (e.g., row and column decoders), sense amplifiers, drivers (e.g., word line drivers), charge pumps, current or voltage references, or any active or passive component of circuitry (e.g., a transistor, diode, resistor, or capacitor). The peripheral circuitry 202 may also include any other circuitry compatible with high-level logic processes, including logic circuitry (e.g., processors and Programmable Logic Devices (PLDs)), or storage circuitry (e.g., Static Random Access Memory (SRAM)).

Referring to fig. 4a, fig. 4b, and fig. 4c, fig. 4a is a perspective view of a semiconductor structure 100 according to some embodiments of the present disclosure. FIG. 4b is a cross-sectional view of a memory cell string of the semiconductor structure 100 of FIG. 4a along section line AA'. Fig. 4c is an equivalent circuit diagram of a memory cell string of the semiconductor structure 100 in fig. 4 a. As shown in fig. 4a, the semiconductor structure 100 may include memory cell transistor strings (referred to herein as "memory cell strings," e.g., NAND memory cell strings) 105 arranged in an array. As shown in fig. 4c, the memory cell string 105 may include a plurality of transistors T, and one transistor T may be provided as one memory cell, and the transistors T are connected together to form the memory cell string. It should be noted that the number of transistors in fig. 4c is only an exemplary one, and the memory cell string 105 of the three-dimensional memory provided in the embodiment of the present disclosure may further include other numbers of transistors, for example, 4, 16, 32, 64, etc., which are not specifically limited herein.

Embodiments of the present disclosure also provide a semiconductor structure 100 and a method for fabricating the same, and the semiconductor structure 100 can be applied to the three-dimensional memory 10.

As shown in fig. 4b, the semiconductor structure 100 according to the embodiment of the present disclosure includes a stacked structure 101 and a source layer SL, which may be disposed on one side of the stacked structure 101 and electrically coupled to source terminals of the plurality of memory cell strings 105.

Here, the material of the source layer SL may include, for example, one or more of single crystal silicon, single crystal germanium, a III-V compound semiconductor material, or a II-VI compound semiconductor material.

In the case where the semiconductor structure 100 is applied to the three-dimensional memory 10 described above, in some examples, the peripheral circuit 202 may be disposed on a side of the semiconductor structure 100 away from the source layer SL.

The stack structure 101 includes stacked gate dielectric layers 120 and gate layers 121 alternately disposed.

In some embodiments, the stacked structure 101 includes a plurality of gate dielectric layers 120 and a plurality of gate layers 121 stacked alternately, and among the gate dielectric layers 120 and the gate layers 121 of the stacked structure 101, a layer closest to the source layer SL is the gate dielectric layer 120.

Here, the number of layers of the gate dielectric layer 120 and the gate layer 121 are not limited, and may be set accordingly as needed. It is understood that the greater the number of layers of the gate dielectric layer 120 and the gate layer 121 in the stacked structure 101, the higher the integration level, and the greater the number of memory cells (e.g., transistors) in the memory cell string 105 formed therefrom.

In some examples, the gate layer 121 may include at least one (e.g., a plurality of) gate lines G for controlling the turn-on state of transistors in the memory cell string 105. Illustratively, at least one (e.g., one; as another example, a plurality of) of the plurality of gate layers 121 (e.g., including the gate layer 121 of the plurality of gate layers 121 closest to the source layer SL) below in the first direction is configured as at least one (e.g., one; as another example, a plurality of) source select gates SGS configured to control a conduction state of a lowermost transistor, and thus a conduction state of a source channel in the string of memory cells 105; at least one (e.g., one; as another example, a plurality of) gate layers 121 (e.g., the gate layer 121 including the gate layer 121 farthest from the source layer SL among the plurality of gate layers 121) positioned above the plurality of gate layers 121 are configured as at least one (e.g., one; as another example, a plurality of) drain select gates SGD configured to control a conduction state of the uppermost transistor, and thus a conduction state of a drain channel in the memory cell string 105; at least one (e.g., one; and as another example, a plurality of) gate layers 121 in the middle among the plurality of gate layers 121 are configured as a plurality of word lines WL, and data writing, reading, and erasing of respective memory cells (e.g., transistors T) in the memory cell string can be accomplished by writing different voltages on the word lines WL.

As shown in fig. 4b, the semiconductor structure 100 may further include a first capping layer 102, a channel hole 103, and a channel structure 104; the first capping layer 102 is disposed on one side of the stack structure 101, and the trench hole 103 penetrates the first capping layer 102 and the stack structure 101. The channel structure 104 is disposed in the channel hole 103, the channel structure 104 includes a dielectric core portion 111 and a functional layer 110, and the functional layer 110 is disposed on an outer wall of the dielectric core portion 111. Wherein, the diameter of the channel hole 103 at the first capping layer 102 is greater than or equal to the diameter of the channel hole 103 at the stacked structure 101, and the acid corrosion resistance of the first capping layer 102 is less than that of the gate dielectric layer 120.

In some examples, as shown in fig. 4b, the stacked structure 101 further includes a second capping layer 107, where the second capping layer 107 is disposed on a side of the first capping layer 102 facing the substrate 201, and is located on a side of the stacked and alternately disposed gate dielectric layers 120 and gate electrode layers 121 away from the substrate 201; the acid corrosion resistance of the first cover layer 102 is smaller than that of the second cover layer 107.

As shown in fig. 4b, the source layer SL may be disposed on a side of the stacked structure 101 away from the first cladding layer 102, and the source layer SL is electrically coupled to the functional layer 110 in the channel structure 104.

As shown in fig. 4a and 4c, the one memory cell, i.e., one transistor T (e.g., each transistor T), may be formed by the channel structure 104 and one gate line G surrounding the channel structure 104. Wherein the gate line G is configured to control a turn-on state of the transistor.

As shown in FIG. 5, preparing the semiconductor structure 100 shown in FIG. 4b may include steps S10-S23:

s10, as shown in fig. 6, an etch stopper 203 is formed on the substrate 201.

Illustratively, the etch stop layer 203 may be formed on the substrate 201 by a thin film deposition process, such as one or more of Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), or Atomic Layer Deposition (ALD) and electroplating.

In some examples, the substrate 201 may be a single layer substrate or may be a composite substrate having a multilayer structure.

In the case where the substrate 201 is a single-layer structure, the substrate 201 may include one or more of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, and the like; the substrate 201 may also be made of a non-conductive material such as glass, plastic, or sapphire wafer.

In the case where the substrate 201 has a multilayer structure, the substrate 201 may include, for example, a base plate 201a and a first sacrificial layer 201b and a second sacrificial layer 201c which are sequentially stacked over the base plate 201 a.

The material of the bottom plate 201a may include, for example, one or more of amorphous silicon, polycrystalline silicon, single crystal germanium, a group III-V compound semiconductor material, a group II-VI compound semiconductor material, and other suitable semiconductor materials; the bottom plate 201a may also be made of a non-conductive material such as glass, plastic, or sapphire wafer. The material of the first sacrificial layer 201b may include silicon oxide and/or silicon nitride, for example. The material of the second sacrificial layer 201c may include, for example, one or more of amorphous silicon, polycrystalline silicon, single crystal germanium, a group III-V compound semiconductor material, a group II-VI compound semiconductor material, and other suitable semiconductor materials.

On the basis, a layer of etch stop layer 203 may be formed on the substrate 201, or a plurality of layers of etch stop layers 203 may be formed. Fig. 6 illustrates an example in which two etching stopper layers 203 are formed on a substrate 201, and the two etching stopper layers 203 are an etching stopper layer 203a and an etching stopper layer 203b, respectively.

It should be noted that step S10 is an optional step, for example, in some examples, step S10 may be omitted.

S11, as shown in fig. 7, forming a stacked structure 106 on the side of the etch stop layer 203 away from the substrate 201, where the stacked structure 106 includes gate dielectric layers 120 and gate sacrificial layers 122 stacked alternately in sequence, that is, forming stacked gate dielectric layers 120 and gate sacrificial layers 122 stacked alternately on the side of the etch stop layer 203 away from the substrate 201. It is understood that, in the case of step S10 being omitted, step S11 is: a stacked structure 106 is formed on a substrate 201.

In step S11, a thin film deposition process may be used to form a stack of alternating gate dielectric layers 120 and gate sacrificial layers 122 on the side of the etch stop layer 203 away from the substrate 201. The thin film deposition process may include, for example, a chemical vapor deposition process, a physical vapor deposition process, an atomic layer deposition process, or an electroplating process.

The number of layers of the gate dielectric layer 120 and the gate sacrificial layer 122 formed in step S11 is not limited, and may be set accordingly as needed. For example, the number of layers of gate dielectric layer 120 or gate sacrificial layer 122 may be 6, 8, 12, 64, etc. Fig. 7 illustrates an example in which the number of layers of the gate dielectric layer 120 and the gate sacrificial layer 122 formed on the etch stop layer 203 is six.

In addition, the thicknesses of the gate dielectric layers 120 may be the same or different, and similarly, the thicknesses of the gate sacrificial layers 122 may be the same or different, and may be set according to specific process requirements.

The stacked structure 106 may also be referred to as an initial stacked structure, and the gate sacrificial layer 122 is formed to form a sacrificial gap between adjacent gate dielectric layers 121 after removing the gate sacrificial layer 122 in a subsequent process, and then the gate layer 121 may be formed in the sacrificial gap.

Here, when the stacked structure 106 is formed, the gate dielectric layer 120 may be formed first, or the gate sacrificial layer 122 may be formed first. In addition, when the stack structure 106 is formed, the gate dielectric layer 120 may be formed last, and the gate sacrificial layer 122 may also be formed last.

The gate dielectric layer 120 is made of an insulating material, which may be, for example, one or more of silicon oxide, silicon nitride, silicon oxynitride, doped silicon oxide, organosilicate glass, dielectric metal oxide (e.g., aluminum oxide, hafnium oxide, etc.) and silicate thereof, and organic insulating material. In addition, the material of each gate dielectric layer 120 may be the same or different. In the case where the materials of the plurality of gate dielectric layers 120 of the stacked structure 101 are the same, the manufacturing process of the stacked structure 101 can be simplified when the plurality of gate dielectric layers 120 are formed.

The material of the gate sacrificial layer 122 may include one or a combination of silicon nitride, silicon oxide, and silicon oxynitride, for example.

S12, as shown in fig. 8, forming a second capping layer 107 on the side of the stacked alternating gate dielectric layers 120 and gate sacrificial layers 122 away from the substrate 201, where the stacked structure 106 further includes the second capping layer 107.

It should be noted that step S12 is an optional step, for example, in some examples, step S12 may be omitted.

It is understood that, through step S11 and step S12, the stacked structure 106 may be formed on the etch stop layer 203, where the stacked structure 106 includes sequentially stacking the gate dielectric layer 120 and the gate sacrificial layer 122 which are alternately disposed, and the second capping layer 107 disposed on the stacked gate dielectric layer 120 and the gate sacrificial layer 122 which are alternately disposed. In the case where step S12 is omitted, stacked structure 106 includes gate dielectric layer 120 and gate sacrificial layer 122 stacked alternately in sequence, excluding second capping layer 107.

Illustratively, the second capping layer 107 may be formed using a thin film deposition process. The thin film deposition process can be referred to above, and is not described herein in detail.

Here, the material of the second capping layer 107 may include, for example, silicon oxide and/or silicon nitride.

On this basis, the material of the second capping layer 107 and the material of the gate dielectric layer 120 may be the same or different.

S13, as shown in fig. 9, the first clad layer 102 is formed on the side of the second clad layer 107 away from the substrate 201. It is understood that, in the case of omitting step S12, step S13 is: first capping layer 102 is formed on the stack of alternating gate dielectric layers 120 and gate sacrificial layers 122.

Illustratively, the first capping layer 102 may be formed using a thin film deposition process. The thin film deposition process can be referred to above, and is not described herein in detail.

Here, the material of the first capping layer 102 may include silicon oxide and/or silicon nitride, for example.

The material of the first cover layer 102 and the material of the second cover layer 107 may be the same or different.

S14, as shown in fig. 10a, the first capping layer 102 and the stacked structure 106 (the stacked structure 106 includes the second capping layer 107 and the gate dielectric layer 120 and the gate sacrificial layer 122 which are stacked and arranged alternately) are etched to form the channel hole 103, and the channel hole 103 sequentially penetrates through the first capping layer 102 and the stacked structure 106, that is, the channel hole 103 sequentially penetrates through the first capping layer 102, the second capping layer 107, and the gate dielectric layer 120 and the gate sacrificial layer 122 which are stacked and arranged alternately.

It is understood that as the number of layers of the gate dielectric layer 120 and the gate sacrificial layer 122 in the stacked structure 106 increases, the aspect ratio of the channel hole 103 becomes larger, which may cause problems in forming the channel hole 103. For example, as shown in fig. 10b, the top end of the channel hole 103 prepared by the prior art has a necking (as shown by a dotted circle in fig. 10 b), i.e., the diameter R at the top end of the channel hole 103 is smaller than the diameter R' at other positions of the channel hole 103. Since the top end of the channel hole 103 is tapered, as shown in fig. 10c, when the functional layer 110 and the dielectric core 111 are sequentially formed in the channel hole to form a channel structure, pores are easily formed inside the dielectric core 111 (as shown in position a in fig. 10c and position a in fig. 10 d), so that when a conductive structure is formed above the channel hole in a subsequent process, a conductive material is easily introduced into the pores of the dielectric core 111, fig. 10e shows a topography of the semiconductor structure, and as can be seen from fig. 10e, a part of the conductive material flows into the pores of the dielectric core 111, which affects the storage performance of the memory.

In summary, as the aspect ratio of the channel hole 103 is increased, when the channel hole 103 is formed by etching, as shown in fig. 10a, a top of the channel hole 103 may have a shrinkage, which may affect the memory performance of the memory. Here, the first capping layer 102 and the stack structure 106 may be etched using a dry etching process or a wet etching process.

It is understood that in the case of forming the etch stop layer 203 on the substrate 201, the etch stop layer 203 may be used to stop etching during the etching process for forming the channel hole 103, so as to prevent the channel hole 103 formed by etching from further extending to the substrate 201, resulting in damage to the substrate 201, so as to protect the substrate 201.

In addition, when the first capping layer 102 and the stacked structure 106 are etched to form the channel hole 103, in order to ensure that the first capping layer 102 and the stacked structure 106 are completely etched, as shown in fig. 10a, an over-etching manner may be adopted during etching, that is, a part or all of the etch stop layer 203 is also etched, and at this time, the etch stop layer 203 may stop etching.

S15, as shown in fig. 10f, etching the sidewall of the trench hole 103 with an etching solution to planarize the sidewall of the trench hole 103; the acid corrosion resistance of the first cover layer 102 to the etching solution is less than the acid corrosion resistance of the stacked structure 106 to the etching solution, so that the diameter of the etched trench hole 103 in the first cover layer 102 is greater than or equal to the diameter of the trench hole 103 in the stacked structure 106.

In the case where the stacked structure 106 includes the second capping layer 107 and the gate dielectric layers 120 and the gate sacrificial layers 122 that are alternately disposed are stacked, that is, the acid corrosion resistance of the first capping layer 102 to the etching solution is smaller than the acid corrosion resistance of the gate dielectric layer 120, the gate sacrificial layers 122, and the second capping layer 107 to the etching solution. In the case where stacked structure 106 includes stacked gate dielectric layers 120 and gate sacrificial layers 122 alternately arranged, and does not include second capping layer 107, that is, first capping layer 102 has less acid corrosion resistance to the etching solution than gate dielectric layers 120 and gate sacrificial layers 122.

Here, the etching liquid may be hydrofluoric acid, for example.

It can be understood that the less the acid corrosion resistance of the film layer to the corrosive liquid, the more easily the film layer is corroded by the corrosive liquid, and conversely, the more acid corrosion resistance of the film layer to the corrosive liquid, the more difficult the film layer is corroded by the corrosive liquid. Because the first cover layer 102 has less acid corrosion resistance against the etching solution than the stacked-layer structure 106, the etching speed of the first cover layer 102 is higher than the etching speed of the stacked-layer structure 106 when the side wall of the trench hole 103 is etched by the etching solution, and the diameter of the trench hole 103 in the first cover layer 102 is larger than or equal to the diameter of the trench hole 103 in the stacked-layer structure 106. In the case where the stacked-layer structure 106 includes the second capping layer 107 and the gate dielectric layer 120 and the gate sacrificial layer 122 alternately stacked, the diameter of the channel hole 103 in the first capping layer 102 is greater than or equal to the diameter of the channel hole 103 in the gate dielectric layer 120, the gate sacrificial layer 122, and the second capping layer 107. In the case where the stacked structure 106 includes the stacked gate dielectric layers 120 and the gate sacrificial layers 122 alternately arranged without the second capping layer 107, the diameter of the channel hole 103 in the first capping layer 102 is greater than or equal to the diameter of the channel hole 103 in the gate dielectric layers 120 and the gate sacrificial layers 122.

In general, as the number of layers of the gate dielectric layer 120 and the gate sacrificial layer 122 in the stacked structure 106 increases, the aspect ratio of the trench hole is increased, and therefore, when the trench hole is etched, a necking exists at the top end of the trench hole, however, in this embodiment of the application, while the trench hole 103 is planarized by using the etching solution, since the acid corrosion resistance of the first capping layer 102 to the etching solution is less than the acid corrosion resistance of the stacked structure 106 to the etching solution, as shown in fig. 10f, the diameter of the etched trench hole 103 at the first capping layer 102 is greater than or equal to the diameter of the trench hole 103 at the stacked structure 106, so that the purpose of performing a hole-expanding process on the top end of the trench hole 103 can be achieved, and the problem of necking at the top end of the trench hole 103 when the trench hole 103 is formed by etching is avoided.

It is considered that if the thickness of the first cover layer 102 is too small, the diameter of the etched channel hole 103 in the first cover layer 102 is larger than or equal to the diameter of the channel hole 103 in the stacked structure 106 after the channel hole 103 is planarized by the etching solution, but if the thickness of the first cover layer 102 is too small, the stacked structure 106 still has a problem of sink-back. Based on this, in some examples, the thickness of the first cover layer 102 may range from

For example, the thickness of the first cover layer 102 may range from

Here, the thickness of the first cover layer 102 may be, for example, the thickness

Or

And the like.

In the case where the stacked-layer structure 106 includes the second capping layer 107, if the thickness of the second capping layer 107 is greater than the thickness of the first capping layer 102, when the trench hole 103 is planarized by the etching solution, since the etching rate of the etching solution to the second capping layer 107 is smaller than that to the first capping layer 102, the second capping layer 107 may also be subject to the occurrence of the crater, and therefore, in some examples, the thickness of the first capping layer 102 is greater than or equal to the thickness of the second capping layer 107, so that the crater at the position of the second capping layer 107 can be avoided.

In the case where the stacked-layer structure 106 includes the second cover layer 107, in order to make the acid corrosion resistance of the first cover layer 102 to the etching liquid smaller than the acid corrosion resistance of the second cover layer 107 to the etching liquid, the following two ways may be implemented:

the first method comprises the following steps: the material of the first cover layer 102 is the same as the material of the second cover layer 107, and the density of the material of the first cover layer 102 is smaller than that of the material of the second cover layer 107.

Under the condition that the material of the first cover layer 102 is the same as that of the second cover layer 107, the density of the material of the first cover layer 102 is smaller than that of the material of the second cover layer 107, so that when the channel hole is subjected to planarization treatment by using the etching solution, the etching rate of the etching solution on the first cover layer 102 is greater than that of the etching solution on the second cover layer 107, the diameter of the processed channel hole 103 in the first cover layer 102 is greater than or equal to that of the channel hole 103 in the second cover layer 107, and the necking at the top end of the channel hole 103 is subjected to reaming treatment.

And the second method comprises the following steps: the material of the first cover layer 102 and the material of the second cover layer 107 may not be the same. In this case, the material of the first cover layer 102 and the material of the second cover layer 107 are not limited to the material, and the acid corrosion resistance of the first cover layer 102 to the etching liquid may be smaller than the acid corrosion resistance of the second cover layer 107 to the etching liquid.

Further, in the case where the material of the first cover layer 102 and the material of the second cover layer 107 are not the same, this can increase the variety of the material selection of the first cover layer 102 and the second cover layer 107.

Under the condition that the laminated structure 106 comprises the second covering layer 107, when the channel hole 103 is subjected to planarization treatment by using an etching solution, the etching solution can etch the first covering layer 102, the second covering layer 107, the stacked and alternated gate dielectric layer 120 and the gate sacrificial layer 122, and the diameters of the channel hole 103 at the first covering layer 102 and the channel hole 103 at the second covering layer 107 form gradient changes, so that the profile change of longitudinal cutting during etching of the channel hole 103 can be reduced, and the structural stability of the prepared semiconductor structure is improved.

S16, sequentially forming a functional layer 110 and a dielectric core portion 111 in the channel hole 103 to form the channel structure 104, the functional layer 110 being disposed on an outer wall of the dielectric core portion 111.

Illustratively, the functional layer 110 may include a barrier layer 110a, a charge storage layer 110b, a tunneling layer 110c, and a channel layer 110d, the barrier layer 110a, the charge storage layer 110b, the tunneling layer 110c, and the channel layer 110d being sequentially disposed on an outer wall of the dielectric core 111.

In some examples, step S16 may include steps S161-S165 as follows:

s161, as shown in fig. 11, a barrier layer 110a is formed in the trench hole 103.

Illustratively, a thin film deposition process may be employed to form the barrier layer 110a within the trench hole 103.

Here, the material of the barrier layer 110a may include one or a combination of silicon oxide, silicon nitride, or silicon oxynitride, for example.

S162, as shown in fig. 12, the charge storage layer 110b is formed on the barrier layer 110 a.

For example, the charge storage layer 110b may be formed on the barrier layer 110a using a thin film deposition process.

Here, the material of the charge storage layer 110b may include, for example, silicon nitride, silicon oxynitride, or a combination of one or more of silicon. The charge storage layer 110b may be configured to perform a storage operation on memory cells in the memory cell string. When a certain voltage is applied to the channel structure 104 through the gate layer 121, the storage or removal of charge in the charge storage layer 110b may affect the on-state of the channel structure 104.

S163, as shown in fig. 13, a tunneling layer 110c is formed on the charge storage layer 110 b.

For example, the tunneling layer 110c may be formed on the charge storage layer 110b using a thin film deposition process.

In some examples, the material of the tunneling layer 110c may include, for example, one or a combination of silicon oxide, silicon nitride, or silicon oxynitride. Electrons or holes in the channel hole 103 may tunnel through the tunneling layer 110c into the charge storage layer 110 b.

S164, as shown in fig. 14, a channel layer 110d is formed on the tunneling layer 110 c.

For example, the channel layer 110d may be formed on the tunneling layer 110c using a thin film deposition process.

Here, the material of the channel layer 110d may include, for example, poly silicon (p-Si).

In a case where the functional layer 110 includes a barrier layer 110a, a charge storage layer 110b, a tunneling layer 110c and a channel layer 110d, and the material of the barrier layer 110a is silicon oxide, the material of the charge storage layer 110b is silicon nitride, the material of the tunneling layer 110c is silicon oxide, and the material of the channel layer 110d is polysilicon, the functional layer 110 may also be referred to as an (oxide-polysilicon) structure layer.

S165, as shown in fig. 15a, the dielectric core 111 is formed in the channel hole 103.

Illustratively, a thin film deposition process may be employed to form the dielectric core 111 within the trench hole 103.

Here, the material of the dielectric core 111 may include, for example, one or a combination of silicon oxide, silicon nitride, or silicon oxynitride.

Fig. 15b is a topographical view of the semiconductor structure after step S165, and it can be seen from fig. 15b that the diameter R1 of the channel hole 103 at the first cladding layer 102 is greater than or equal to the diameter R2 of the channel hole 103 at the layered structure 106.

In some embodiments, the diameter of the dielectric core 111 at the first capping layer 102 is greater than or equal to the diameter of the dielectric core 111 at the stack 106.

Illustratively, after the channel layer 110d is formed in step S164, the channel layer 110d encloses a receiving cavity, and it is understood that an end of the receiving cavity away from the substrate 201 is provided with an opening. Wherein the diameter of the receiving cavity at the first cover layer 102 is greater than or equal to the diameter of the receiving cavity at the laminated structure 106. This prevents the inside of the dielectric core 111 from forming pores when the dielectric core 111 is formed in the receiving cavity, thereby preventing conductive material from easily entering the pores inside the channel hole 103 when a conductive structure is formed above the channel hole 103 by a subsequent process.

Wherein the diameter of the dielectric core 111 formed in the receiving cavity at the first cover layer 102 is greater than or equal to the diameter of the dielectric core 111 at the stacked structure 106.

S17, as shown in fig. 16, the functional layer 110 and the dielectric core 111 are subjected to a rubbing process to expose the surface of the first cover layer 102.

Illustratively, the functional layer 110 and the dielectric core 111 may be subjected to a Chemical Mechanical Polishing (CMP) process to expose the surface of the first cover layer 102, and the surface of the flattened functional layer 110 and the dielectric core 111 away from the substrate 201 is flush with the surface of the first cover layer 102 away from the substrate 201.

S18, as shown in fig. 17, the gate sacrificial layer 122 is removed to form a sacrificial gap 123.

Before removing the gate sacrificial layer 122, a gate line slit may be formed sequentially through the first capping layer 102 and the stacked structure 106, so that the gate sacrificial layer 122 between the gate dielectric layers 120 may be exposed through the gate line slit; next, the gate sacrificial layer 122 may be removed through the gate line slit, and a sacrificial gap 123 may be formed at a position where the gate sacrificial layer 122 is originally disposed in the stacked-layer structure 106.

It should be understood that, in order to remove the gate sacrificial layer 122 without affecting the gate dielectric layer 120, the first capping layer 102 and the second capping layer 107, when selecting the material of the gate sacrificial layer 122 and the material of the gate dielectric layer 120, the first capping layer 102 and the second capping layer 107, it is ensured that the gate sacrificial layer 122, and the gate dielectric layer 120, the first capping layer 102 and the second capping layer 107 have different corrosion resistances, and thus in the etching process, the gate sacrificial layer 122 may be removed while the gate dielectric layer 120, the first capping layer 102 and the second capping layer remain.

S19, forming a gate layer 121 in the sacrificial gap 123 to form a stacked structure 101, wherein the stacked structure 101 includes the second capping layer 107 and the gate dielectric layer 120 and the gate layer 121 alternately stacked.

It is noted that, in some examples, before step S19, the method for manufacturing a semiconductor structure may further include: as shown in fig. 18, a gate barrier 1211 is formed in the sacrificial gap 123. Illustratively, the gate barrier 1211 may be formed within the sacrificial gap 123 using a thin film deposition process.

Here, the material of the gate barrier 1211 may include, for example, one or a combination of titanium nitride, tantalum nitride, and tungsten carbide, and may be other suitable materials.

After the gate barrier layer 1211 is formed, step S19 may be performed, i.e., as shown in fig. 19, the gate layer 121 is formed within the sacrificial gap 123.

Illustratively, the gate layer 121 may be formed within the sacrificial gap 123 using a thin film deposition process.

Here, the material of the gate layer 121 may include, for example, a combination of one or more of tungsten, cobalt, copper, aluminum, doped silicon, and silicide. In addition, the material of each gate layer 121 may be the same or different. In some embodiments, the material of each gate layer 121 is the same, such as tungsten.

It is understood that in the case of forming the gate barrier 1211, the gate layer 121 may be spaced apart from the channel structure 104 by the gate barrier 1211. The gate barrier 1211 is configured as a material barrier layer that may serve as a barrier layer to reduce diffusion of impurity atoms or gases into the gate dielectric layer 120 and the channel structure 104; the gate barrier layer 1211 may also be configured as an adhesion layer for enhancing adhesion between the gate layer 121 and the gate dielectric layer 120.

In some embodiments, the diameter of the dielectric core 111 at the first capping layer 102 is greater than or equal to the diameter of the dielectric core 111 at the stacked structure 101.

In the case that the semiconductor structure 100 further includes the source layer SL, in some examples, after the step S19, the method for manufacturing the semiconductor structure 100 further includes:

s20, as shown in fig. 20, an array interconnection layer 204 is formed on the first capping layer 102.

Here, the array interconnect layer 204 may be electrically coupled with the memory cell string. The array interconnect layer 204 may include drain terminals (i.e., bit lines BL) of the memory cell strings 105, which may be electrically coupled to the channel layer 110d of each transistor T in at least one of the memory cell strings 105, such that the semiconductor structure 100 may be electrically coupled to peripheral circuits through the array interconnect layer 204.

For example, as shown in fig. 20, the array interconnection layer 204 may include one or more first interlayer insulating layers 205, and may further include a plurality of contacts insulated from each other by the first interlayer insulating layers 205, as shown in fig. 4a, the contacts including, for example, bitline contacts BL-CNT electrically coupled to the bitline BL; a drain select gate contact SGD-CNT electrically coupled to drain select gate SGD. The array interconnect layer 204 may also include one or more first interconnect conductor layers 206. The first interconnect conductor layer 206 may include a plurality of connection lines, such as bit lines BL, and word line connection lines WL-CL electrically coupled to word lines WL.

Here, the material of the first interconnect conductor layer 206 and the contact may include, for example, one or a combination of tungsten, cobalt, copper, aluminum, and metal silicide, and may be other suitable materials.

In addition, the material of the first interlayer insulating layer 205 may include one or a combination of silicon oxide, silicon nitride, and a high-k insulating material, or other suitable materials.

In some examples, the array interconnect layer 204 is to electrically couple with peripheral circuitry such that the memory cell strings 105 of the semiconductor structure 100 and the peripheral circuitry can be electrically coupled to enable transmission of electrical signals between the memory cell strings 105 and the peripheral circuitry. Based on this, in some examples, after step S20, the method for manufacturing a semiconductor structure may further include: as shown in fig. 21, a peripheral interconnection layer 210 is formed on a side of the array interconnection layer 204 away from the stacked structure 101, and the peripheral interconnection layer 210 is electrically coupled to the array interconnection layer 204.

As shown in fig. 21, the peripheral interconnect layer 210 may be used to electrically couple the array interconnect layer 204 and the peripheral circuitry 202 in the substrate 200, such that the semiconductor structure 100 and the peripheral circuitry 202 may be electrically coupled. Peripheral circuitry 202 may include transistors 209 and, in particular, peripheral interconnect layer 210 may be electrically coupled to transistors 209 of peripheral circuitry 202 to enable the transmission of electrical signals between transistors 209 and peripheral interconnect layer 210.

The peripheral interconnect layer 210 may include one or more second interlayer insulating layers 211 and may further include one or more second interconnect conductor layers 212. Different second interconnect conductor layers 212 may be electrically coupled to each other through contacts.

The material of the second interconnect conductor layer 212 and the contacts may be, for example, one or a combination of tungsten, cobalt, copper, aluminum, and metal silicide, and may be other suitable materials. The material of the second interlayer insulating layer 211 is an insulating material, such as one or a combination of silicon oxide, silicon nitride, and a high-k insulating material, and may be other suitable materials.

In some possible implementations, a bonding interface 207 as shown in fig. 21 may be further disposed between the peripheral interconnection layer 210 and the array interconnection layer 204, and the peripheral interconnection layer 210 and the array interconnection layer 204 may be bonded and electrically coupled to each other through the bonding interface 207.

S21, as shown in fig. 22, the substrate 201 is removed.

Here, the bottom plate 201a in the substrate 201 may be removed using a CMP process, and the first sacrificial layer 201b and the second sacrificial layer 201c in the substrate 201 may be removed using an etching process.

S22, as shown in fig. 23, the etching stop layer 203a is etched, and the barrier layer 110a, the charge storage layer 110b and the tunneling layer 110c exposed in the stacked structure 101 in the functional layer 110 are etched to expose the channel layer 110 d.

S23, as shown in fig. 24, a source layer SL is formed on a side of the stacked structure 101 away from the first cladding layer 102, and the source layer SL is electrically coupled to the channel layer 110 d.

It should be noted that, in some examples, in the process of manufacturing the semiconductor structure 100, when the stacked structure 106 is formed on the substrate 201, the step S11 and the step S12 are included, in this case, the semiconductor structure 100 is manufactured as shown in fig. 24, and the stacked structure 101 includes the second capping layer 107, and the second capping layer 107 is disposed on the side of the first capping layer 102 facing the substrate 201 and is located on the side of the stacked and alternated gate dielectric layers 120 and gate electrode layers 121 away from the substrate 201. In other examples, step S11 is included and step S12 is not included in forming the stacked-layer structure 106 on the substrate 201, in which case the resulting semiconductor structure 100 is shown in fig. 25.

It can be understood that as the number of layers of the gate dielectric layer 120 and the gate sacrificial layer 122 in the stacked structure 106 increases, the difficulty of the process for etching the stacked structure 106 to form the channel hole 103 increases due to the increase of the aspect ratio of the channel hole 103. Specifically, when the channel hole 103 is formed by a dry etching process and/or a wet etching process, limited by the limitation of the etching process, the diameter of the top end of the channel hole 103 formed by etching is smaller than the diameter of the channel hole 103 at other positions, that is, a necking is formed at the top end of the channel hole 103, and when the functional layer 110 and the dielectric core 111 are sequentially formed in the channel hole 103 in the subsequent process, a void is easily formed inside the dielectric core 111, so that when a conductive structure is formed above the channel hole 103 in the subsequent process, a conductive material is easily introduced into the void inside the dielectric core 111, which may affect the storage of charges in the charge storage layer 110b in the functional layer 100, and may affect the storage performance of the three-dimensional memory.

In order to solve the problems that the dielectric core part 111 in the channel hole 103 is easy to form pores due to the fact that the top end of the formed channel hole 103 is provided with a necking, and a conductive material is easy to enter the pores inside the dielectric core part 111, so that the storage performance of the three-dimensional memory is influenced. A first related art proposes that, when manufacturing a semiconductor structure, the following steps may be employed: first, as shown in fig. 26, the stacked alternating gate dielectric layers 120 and gate sacrificial layers 122 are etched to form a channel hole 103. Since the aspect ratio of the channel hole 103 is large, a constriction is formed at the top end of the channel hole 103; next, as shown in fig. 27, the top end of the channel hole 103 is etched to perform a flaring process on the top end of the channel hole 103 so that the diameter at the top end of the channel hole 103 is larger than or equal to the diameter at other positions of the channel hole 103; next, as shown in fig. 28, a barrier layer 110a, a charge storage layer 110b, a tunneling layer 110c, a channel layer 110d, and a dielectric core portion 111 are sequentially formed in the channel hole 103.

A second related art proposes that, in preparing a semiconductor structure, the following steps may be employed: first, as shown in fig. 26, the stacked alternating gate dielectric layers 120 and gate sacrificial layers 122 are etched to form channel holes 103; next, forming a functional layer in the channel hole 103, that is, sequentially forming a barrier layer 110a, a charge storage layer 110b, a tunneling layer 110c and a channel layer 110d in the channel hole 103, and etching the functional layer 110 at the top end of the channel hole 103, so that the diameter at the top end of the channel hole 103 is greater than or equal to the diameter at other positions of the channel hole 103 before forming the dielectric core 111, thereby making it possible to prevent voids from occurring inside the dielectric core 111 when filling the dielectric core 111 in the channel hole 103 in a subsequent process; next, the dielectric core portion 111 is sequentially filled in the channel hole 103.

The etching of the functional layer 110 at the top of the channel hole 103 may include the following conditions:

first, as shown in fig. 29, first, a barrier layer 110a is formed in the channel hole 103; next, as shown in fig. 30, the barrier layer 110a at the top end of the channel hole 103 is etched, and after the barrier layer 110a at the top end of the channel hole 103 is etched, the diameter of the top end of the channel hole 103 after the barrier layer 110a is formed is greater than or equal to the diameter of the other position of the channel hole 103 after the barrier layer 110a is formed; next, as shown in fig. 31, a charge storage layer 110b, a tunneling layer 110c, and a channel layer 110d are sequentially formed on the barrier layer 110 a.

And the second method comprises the following steps: firstly, a barrier layer 110a and a charge storage layer 110b are sequentially formed in a channel hole 103; next, the charge storage layer 110b at the top end of the channel hole 103 is etched, and after the charge storage layer 110b at the top end of the channel hole 103 is etched, the diameter of the top end of the channel hole 103 after the barrier layer 110a and the charge storage layer 110b are formed is larger than or equal to the diameter of the other positions of the channel hole 103 after the barrier layer 110a and the charge storage layer 110b are formed; next, a tunneling layer 110c and a channel layer 110d are sequentially formed on the charge storage layer 110 b.

And the third is that: firstly, a blocking layer 110a, a charge storage layer 110b and a tunneling layer 110c are sequentially formed in a channel hole 103; next, etching the tunneling layer 110c at the top end of the channel hole 103, and after etching the tunneling layer 110c at the top end of the channel hole 103, the diameter of the top end of the channel hole 103 after the barrier layer 110a, the charge storage layer 110b and the tunneling layer 110c are formed is greater than or equal to the diameter of the other positions of the channel hole 103 after the barrier layer 110a, the charge storage layer 110b and the tunneling layer 110c are formed; next, a channel layer 110d is formed on the tunneling layer 110 c.

And fourthly: firstly, a barrier layer 110a, a charge storage layer 110b, a tunneling layer 110c and a channel layer 110d are sequentially formed in a channel hole 103; next, the channel layer 110d at the top end of the channel hole 103 is etched, and after the channel layer 110d at the top end of the channel hole 103 is etched, the diameter of the top end of the channel hole 103 after the barrier layer 110a, the charge storage layer 110b, the tunneling layer 110c, and the channel layer 110d are formed is greater than or equal to the diameter of the other positions of the channel hole 103 after the barrier layer 110a, the charge storage layer 110b, the tunneling layer 110c, and the channel layer 110d are formed.

It should be understood that, when the blocking layer 110a, the charge storage layer 110b, the tunneling layer 110c, or the channel layer 110d at the top end of the channel hole 103 is etched, the blocking layer 110a, the charge storage layer 110b, the tunneling layer 110c, or the channel layer 110d at the top end of the channel hole 103 is not completely etched, and only the blocking layer 110a, the charge storage layer 110b, the tunneling layer 110c, or the channel layer 110d is partially etched, which is equivalent to thinning the blocking layer 110a, the charge storage layer 110b, the tunneling layer 110c, or the channel layer 110d, so that the blocking layer 110a, the charge storage layer 110b, the tunneling layer 110c, and the channel layer 110d can still perform corresponding functions at the top end of the channel hole 103.

It is understood that, when the functional layer 110 at the top end of the channel hole 103 is etched, only one of the barrier layer 110a, the charge storage layer 110b, the tunneling layer 110c and the channel layer 110d may be etched as shown in the first, second, third and fourth manners, but multiple layers of the barrier layer 110a, the charge storage layer 110b, the tunneling layer 110c and the channel layer 110d may also be etched.

Although the gate dielectric layer 120 and the gate sacrificial layer 122 located at the top of the channel hole 103 are etched again before the dielectric core 111 is formed, the above-described first related art and second related art are described; alternatively, the functional layer 110 at the top of the channel hole 103 may be etched to perform a hole expansion process to remove a necking so as to avoid a void in the formation of the dielectric core 111, but this may result in an increase in the number of process steps for manufacturing the semiconductor structure, thereby complicating the manufacturing process and increasing the manufacturing cost. In addition, the first related art and the second related art inevitably have adverse effects on the structural stability of the semiconductor structure due to etching the top end of the trench hole 103 or the functional layer 110 at the top end of the trench hole 103 again during the hole expanding process, and also consider the reliability of the etching operation, which affects the yield of the product and undoubtedly increases the manufacturing cost.

In the process of manufacturing the semiconductor structure 100 according to the embodiment of the present disclosure, the first cover layer 102 is formed on one side of the stacked structure 106, and the acid corrosion resistance of the first cover layer 102 is less than that of the stacked structure 106, so that when the channel hole 103 is planarized by using the etching solution, the etching rate of the etching solution to the first cover layer 102 is greater than that of the etching solution to the stacked structure 106, and thus it can be ensured that after the channel hole 103 is planarized by using the etching solution, the diameter of the channel hole 103 in the first cover layer 102 is greater than or equal to the diameter of the channel hole 103 in the stacked structure 106, so that the top end of the channel hole 103 can be subjected to the hole enlarging process, and the problem of the top end of the channel hole 103 being shrunk when the channel hole 103 is formed by etching is solved. Because the diameter of the top end of the channel hole 103 can be increased while the channel hole 103 is planarized by using the etching solution, and the diameter of the top end of the channel hole 103 is greater than or equal to the diameter of the other positions of the channel hole 103, when the functional layer 110 and the dielectric core 111 are sequentially formed in the channel hole 103 to form the channel structure 104, pores are prevented from being easily formed inside the dielectric core 111, and therefore, when a conductive structure is formed above the channel hole 103 in a subsequent process, a conductive material is prevented from easily entering the pores inside the channel hole 103, so that the storage of electric charges is influenced, and the storage performance of the memory is further influenced, the yield of products is increased, and the storage performance of the three-dimensional memory is ensured.

On the basis, the planarization treatment of the channel hole 103 by using the etching solution is an existing process step in the preparation of the semiconductor structure, and the existing process step is used for carrying out reaming treatment on the necking at the top end of the channel hole 103, namely, the reaming treatment is carried out on the top end of the channel hole 103 while the planarization treatment is carried out on the channel hole 103 by using the etching solution, so that no operation step is required to be added, and the preparation cost is not increased.

The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.

Claims

1. A method for fabricating a semiconductor structure, comprising:

forming a laminated structure on a substrate, wherein the laminated structure comprises a gate dielectric layer and a gate sacrificial layer which are sequentially and alternately laminated;

forming a first capping layer on the stacked structure;

etching the first covering layer and the laminated structure to form a channel hole; the channel hole sequentially penetrates through the first covering layer and the laminated structure;

corroding the side wall of the channel hole by using corrosive liquid so as to flatten the side wall of the channel hole; wherein the acid corrosion resistance of the first cover layer to the corrosive liquid is less than that of the laminated structure, and the diameter of the channel hole in the first cover layer after corrosion is greater than or equal to that of the channel hole in the laminated structure;

sequentially forming a functional layer and a dielectric core part in the channel hole to form a channel structure; wherein the functional layer is disposed on an outer wall of the dielectric core.

2. The method of claim 1, wherein forming a stacked structure on a substrate comprises:

forming a gate dielectric layer and a gate sacrificial layer which are alternately arranged in a stacked mode on the substrate;

forming a second covering layer on one side, far away from the substrate, of the gate dielectric layers and the gate sacrificial layers which are alternately stacked; the laminated structure further includes the second cover layer.

3. The method of claim 2, wherein the material of the first cover layer and the material of the second cover layer are the same, and the density of the material of the first cover layer is less than the density of the material of the second cover layer.

4. The method of claim 2, wherein the material of the first cover layer and the material of the second cover layer are different.

5. The production method according to any one of claims 1 to 4, wherein after the functional layer and the dielectric core are sequentially formed in the channel hole to form a channel structure, the production method further comprises:

removing the gate sacrificial layer to form a sacrificial gap;

and forming a gate layer in the sacrificial gap to form a stacked structure, wherein the stacked structure comprises the gate dielectric layers and the gate layer which are stacked and arranged alternately.

6. The method of claim 1, wherein prior to forming the stacked structure on the substrate, the method further comprises:

and forming an etching barrier layer on the substrate.

7. A semiconductor structure, comprising:

the stack structure comprises gate dielectric layers and gate electrode layers which are alternately stacked;

a first cover layer disposed at one side of the stacked structure;

a channel hole penetrating the first capping layer and the stack structure; wherein the diameter of the channel hole at the first covering layer is larger than or equal to that of the channel hole at the stacking structure, and the acid corrosion resistance of the first covering layer is smaller than that of the gate dielectric layer;

a channel structure disposed within the channel hole, the channel structure including a dielectric core and a functional layer; the functional layer is provided on an outer wall of the dielectric core.

8. The semiconductor structure of claim 1,

a diameter of the dielectric core at the first capping layer is greater than or equal to a diameter of the dielectric core at the stacked structure.

9. The semiconductor structure of claim 7, wherein the stacked structure further comprises a second capping layer disposed on a side of the first capping layer facing the substrate and on a side of the stack of alternately disposed gate dielectric layers and gate layers facing away from the substrate;

the acid corrosion resistance of the first cover layer is less than the acid corrosion resistance of the second cover layer.

10. The semiconductor structure of claim 9, wherein a thickness of the first capping layer is greater than or equal to a thickness of the second capping layer.

11. The semiconductor structure of claim 9 or 10, wherein the material of the first capping layer and the material of the second capping layer are the same, and the density of the material of the first capping layer is less than the density of the material of the second capping layer.

12. The semiconductor structure of claim 9 or 10, wherein the material of the first capping layer and the material of the second capping layer are different.

13. The semiconductor structure of any of claims 7-10, wherein the first capping layer has a thickness in the range of

14. The semiconductor structure of claim 7, further comprising a source layer disposed on a side of the stacked structure remote from the first capping layer and coupled to the functional layer in the channel structure.

15. A three-dimensional memory comprising a peripheral circuit and the semiconductor structure of any one of claims 7 to 14;

the peripheral circuitry is electrically coupled to the semiconductor structure.

16. A storage system comprising a controller and the three-dimensional memory of claim 15;

the controller is electrically coupled with the three-dimensional memory and is used for controlling the three-dimensional memory to store data.

17. An electronic device comprising a printed circuit board and the storage system of claim 16, the storage system coupled with the printed circuit board.