CN114725122A

CN114725122A - Semiconductor device, manufacturing method and memory system

Info

Publication number: CN114725122A
Application number: CN202210342872.0A
Authority: CN
Inventors: 李倩; 伍术; 张宇澄
Original assignee: Yangtze Memory Technologies Co Ltd
Current assignee: Yangtze Memory Technologies Co Ltd
Priority date: 2022-03-31
Filing date: 2022-03-31
Publication date: 2022-07-08

Abstract

The disclosure provides a semiconductor device, a manufacturing method and a memory system. The semiconductor device includes: a first semiconductor structure comprising a semiconductor layer, a stacked structure on the semiconductor layer, a channel structure extending through the stacked structure and in electrical contact with the semiconductor layer, and a gate line isolation structure extending through the stacked structure and into the semiconductor layer; the stacked structure comprises channel regions and isolation regions which are alternately arranged along a first direction, the channel structure is positioned in the channel regions, and the grid line isolation structure is positioned in the isolation regions; and the source contact is positioned on the isolation region and is in contact with one surface of the semiconductor layer, which is far away from the stacked structure, and the edge of the orthographic projection of the source contact on the semiconductor layer, which extends along the first direction, is not overlapped with the edge of the orthographic projection of the grid line isolation structure on the semiconductor layer, which extends along the first direction.

Description

Semiconductor device, manufacturing method and memory system

Technical Field

The disclosed embodiments relate to the field of semiconductor manufacturing, and in particular, to a semiconductor device, a manufacturing method, and a memory system.

Background

With the continuous development of semiconductor technology, memory manufacturing technology has gradually transitioned from a simple planar structure to a more complex three-dimensional structure, with integration density being increased by three-dimensionally arranging memory cells over a substrate. The technical development of such a three-dimensional memory device is one of the mainstream of international development.

However, in the manufacturing process of the three-dimensional memory device, the channel structure is usually electrically led out by forming a back source contact on the channel structure, but there is a risk of damaging the channel structure when forming the back source contact.

Disclosure of Invention

Embodiments of the present disclosure provide a semiconductor device, a manufacturing method thereof, and a memory system to solve at least one problem in the prior art.

In order to achieve the above purpose, the technical solution of the embodiment of the present disclosure is implemented as follows:

a first aspect of embodiments of the present disclosure provides a semiconductor device, including:

a first semiconductor structure comprising a semiconductor layer, a stacked structure on the semiconductor layer, a channel structure extending through the stacked structure and in electrical contact with the semiconductor layer, and a gate line isolation structure extending through the stacked structure and into the semiconductor layer;

the stacked structure comprises channel regions and isolation regions which are alternately arranged along a first direction, the channel structure is positioned in the channel regions, and the grid line isolation structure is positioned in the isolation regions;

and the source contact is positioned on the isolation region and is in contact with one surface of the semiconductor layer, which is far away from the stacked structure, and the edge of the orthographic projection of the source contact on the semiconductor layer, which extends along the first direction, is not overlapped with the edge of the orthographic projection of the grid line isolation structure on the semiconductor layer, which extends along the first direction.

According to one embodiment of the present disclosure, the source contact and the gate line isolation structure extend in a second direction perpendicular to the first direction.

According to an embodiment of the present disclosure, an edge of the orthographic projection of the source contact extending in the second direction partially overlaps an edge of the orthographic projection of the gate line isolation structure extending in the first direction.

According to an embodiment of the present disclosure, a length of the source contact in the second direction is smaller than a length of the gate line isolation structure in the second direction.

According to an embodiment of the present disclosure, the orthographic projection of the source contact is inside the orthographic projection of the gate line isolation structure.

According to an embodiment of the present disclosure, the orthographic projection of the gate line isolation structure is inside the orthographic projection of the source contact.

According to an embodiment of the present disclosure, the stacked structure includes a step region and a core region arranged along the second direction; the semiconductor layer comprises a first semiconductor layer located on the step area and a second semiconductor layer located on the core area, and the thickness of the first semiconductor layer is smaller than that of the second semiconductor layer.

According to an embodiment of the present disclosure, the semiconductor device further includes: a second semiconductor structure electrically connected to the first semiconductor structure; the second semiconductor structure includes a substrate and peripheral circuitry located on the substrate.

A second aspect of the present disclosure provides a method of manufacturing a semiconductor device, the method including:

forming a first semiconductor structure comprising a semiconductor layer, a stack structure formed on the semiconductor layer, a channel structure extending through the stack structure and in electrical contact with the semiconductor layer, and a gate line isolation structure extending through the stack structure and into the semiconductor layer;

the stacked structure comprises channel regions and isolation regions which are alternately arranged along a first direction, the channel structure is formed in the channel regions, and the grid line isolation structure is formed in the isolation regions;

and forming a source contact contacted with one surface of the semiconductor layer far away from the stacked structure on the isolation region, wherein the edge of the orthographic projection of the source contact on the semiconductor layer, which extends along the first direction, is not overlapped with the edge of the orthographic projection of the grid line isolation structure on the semiconductor layer, which extends along the first direction.

According to an embodiment of the present disclosure, the forming a source contact in contact with a side of the semiconductor layer away from the stacked structure includes: forming a dielectric layer on one surface of the semiconductor layer far away from the stacking structure; etching the dielectric layer to form a source contact opening, wherein the semiconductor layer is exposed by the source contact opening; and filling the source contact opening to form a source contact which is in contact with the semiconductor layer, wherein the source contact and the grid line isolation structure extend along a second direction which is perpendicular to the first direction.

According to an embodiment of the present disclosure, the forming a first semiconductor structure includes: forming a stacked structure on the first semiconductor layer; and forming a channel structure and a grid line isolation structure which penetrate through the stacked structure and extend into the first semiconductor layer.

According to an embodiment of the present disclosure, the stacked structure includes a step region and a core region arranged along the second direction; the method further comprises the following steps: etching and removing the first semiconductor layer on the core region to expose the tail ends of the channel structure and the grid line isolation structure in the core region; etching and removing the storage film surrounding the channel layer at the tail end of the channel structure to expose the channel layer at the tail end of the channel structure; forming a second semiconductor layer on the core region, wherein the second semiconductor layer covers the channel layer at the tail end of the channel structure and the tail end of the grid line isolation structure; the thickness of the first semiconductor layer is smaller than that of the second semiconductor layer.

According to an embodiment of the present disclosure, before the forming of the source contact contacting a side of the semiconductor layer away from the stacked structure, the method further comprises: providing a second semiconductor structure, wherein the second semiconductor structure comprises a substrate and peripheral circuits formed on the substrate; electrically connecting the first semiconductor structure and the second semiconductor structure.

A third aspect of the present disclosure provides a memory system, the memory system including: at least one of the above semiconductor devices; and a controller coupled to the semiconductor device and configured to control the semiconductor device.

The embodiment of the disclosure discloses a semiconductor device, a manufacturing method and a memory system, wherein the semiconductor device comprises: a first semiconductor structure comprising a semiconductor layer, a stacked structure on the semiconductor layer, a channel structure extending through the stacked structure and in electrical contact with the semiconductor layer, and a gate line isolation structure extending through the stacked structure and into the semiconductor layer; the stacked structure comprises channel regions and isolation regions which are alternately arranged along a first direction, the channel structure is positioned in the channel regions, and the grid line isolation structure is positioned in the isolation regions; and the source contact is positioned on the isolation region and is in contact with one surface of the semiconductor layer, which is far away from the stacked structure, and the edge of the orthographic projection of the source contact on the semiconductor layer, which extends along the first direction, is not overlapped with the edge of the orthographic projection of the grid line isolation structure on the semiconductor layer, which extends along the first direction. According to the method, the channel structure is arranged in the channel region, and the source contact is arranged on the isolation region, so that the process for forming the source contact cannot influence the channel structure, the condition that the etching of the source contact influences the planing window of the channel structure is avoided, and the yield of products can be improved to a certain extent; meanwhile, the orthographic projection edge of the source contact on the semiconductor layer is not overlapped with the orthographic projection edge of the grid line isolation structure on the semiconductor layer, so that the stress on the edge part of the grid line isolation structure can be reduced, the risk of collapse of the grid line isolation structure due to overlarge stress is reduced, and the reliability of a product is improved.

Drawings

Fig. 1 is a schematic diagram of a semiconductor device provided by an embodiment of the present disclosure;

fig. 2 is a cross-sectional view of a semiconductor device provided by an embodiment of the present disclosure;

fig. 3 is a top view of a semiconductor device provided by an embodiment of the present disclosure;

fig. 4 is a cross-sectional view of another semiconductor device provided by an embodiment of the present disclosure;

fig. 5 is a top view of another semiconductor device provided by embodiments of the present disclosure;

fig. 6 is a cross-sectional view of yet another semiconductor device provided by an embodiment of the present disclosure;

fig. 7 is a top view of yet another semiconductor device provided by an embodiment of the present disclosure;

fig. 8 is a flowchart of a method for fabricating a semiconductor device according to an embodiment of the present disclosure;

fig. 9a to 9h are schematic structural diagrams illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure;

FIG. 10 is a block diagram of a memory system provided by an embodiment of the present disclosure;

FIG. 11a is a diagram of a memory card according to an embodiment of the present disclosure;

fig. 11b is a schematic diagram of a Solid State Drive (SSD) according to an embodiment of the disclosure.

Detailed Description

Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present disclosure. It will be apparent, however, to one skilled in the art, that the present disclosure may be practiced without one or more of these specific details. In other instances, well-known features of the art have not been described in order to avoid obscuring the present disclosure; that is, not all features of an actual embodiment are described herein, and well-known functions and constructions are not described in detail.

In the drawings, the size of layers, regions, elements, and relative sizes may be exaggerated for clarity. Like reference numerals refer to like elements throughout.

It will be appreciated that spatial relationship terms, such as "under … …," "under … …," "below," "under … …," "over … …," "above," and the like, may be used herein for ease of description to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "below … …" and "below … …" can encompass both an orientation of up and down. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.

Fig. 1 is a schematic diagram of a semiconductor device provided in an embodiment of the present disclosure, and as shown in fig. 1, the semiconductor device includes a channel structure 11 and a source contact 12. In forming the source contact 12, it is necessary to etch to form a source contact opening, and then fill the source contact opening with a conductive material to form the source contact 12. Furthermore, since the channel structure 11 is required to extend into the semiconductor layer, which does not have an etch stop capability, the etching needs to be controlled during the manufacturing of the channel structure 11 to avoid etching through the semiconductor layer. This etching control process is also called "gouging". During the subsequent formation of the source contact 12, the etching of the source contact 12 may affect the gouging window 13 of the channel structure 11, thereby making the gouging process of the channel structure 11 more difficult to control. Therefore, the following technical scheme of the embodiment of the disclosure is provided.

The embodiment of the present disclosure provides a semiconductor device, fig. 2 is a cross-sectional view of the semiconductor device provided by the embodiment of the present disclosure, and fig. 3 is a top view of the semiconductor device provided by the embodiment of the present disclosure. As shown in fig. 2, the left portion of the dotted line in fig. 2 is a sectional view taken along line AA 'in fig. 3, and the right portion of the dotted line is a sectional view taken along line BB' in fig. 3. The semiconductor device includes a first semiconductor structure 100, the first semiconductor structure 100 including a semiconductor layer 110, a stack structure 120 on the semiconductor layer 110, a channel structure 130 penetrating the stack structure 120 and electrically contacting the semiconductor layer 110, and a gate line isolation structure 140 penetrating the stack structure 120 and extending into the semiconductor layer 110. The number of the channel structures 130 and the gate line isolation structures 140 in fig. 2 is merely used to exemplarily illustrate the embodiments of the present disclosure, and is not used to limit the embodiments of the present disclosure. In some embodiments, the semiconductor layer 110 may be a doped semiconductor layer, and particularly, the semiconductor layer 110 may be an N-type doped semiconductor layer. The N-type doped semiconductor layer may comprise a semiconductor material, such as silicon. In some embodiments, the N-type doped semiconductor layer comprises polysilicon formed by a deposition process. The N-type doped semiconductor layer may be doped with any suitable N-type dopant, such as phosphorus (P), arsenic (Ar), or antimony (Sb), which contributes free electrons and increases the conductivity of the intrinsic semiconductor. For example, the N-type doped semiconductor layer may be a polysilicon layer doped with an N-type dopant (e.g., P, Ar or Sb). The stack structure 120 is formed of gate layers 121 and insulating layers 122 alternately stacked. Here, the gate layer 121 and the insulating layer 122 may have the same thickness as each other or different thicknesses from each other. Each gate layer 121 may be adjoined by two insulating layers 122 on both sides, and each insulating layer 122 may be adjoined by two gate layers 121 on both sides. The gate layer 121 may extend laterally (in a direction parallel to the semiconductor layers) as a word line, terminating at one or more steps of the stack structure 120. In some embodiments, each gate layer 121 may include a gate electrode (gate line) surrounded by an adhesive layer and a gate dielectric layer. Wherein the material of the gate electrode includes, but is not limited to, W, Co, Cu, Al, polysilicon, silicide, or any combination thereof, and the material of the gate dielectric layer may include a high-K dielectric material. The material of the insulating layer 122 includes an insulating material such as silicon oxide.

As shown in fig. 3, the stacked structure 120 includes channel regions 105 and isolation regions 106 alternately arranged along a first direction (Y direction), the channel structure 130 is located in the channel region 105, and the gate line isolation structure 140 is located in the isolation region 106. As shown in fig. 2, the channel structure 130 includes a channel layer 131 and a storage film 132 surrounding the channel layer 131. The storage film 132 includes a blocking layer, a storage layer, and a tunneling layer radially inward of the channel structure.

In some embodiments, in order to form the channel structure 130, a channel hole penetrating the stack structure 120 and extending into the first semiconductor layer 101, which may be cylindrical, is formed first, and then a blocking layer, a memory layer, a tunneling layer, and a channel layer 131 are sequentially formed in the channel hole. The manufacturing process for forming the channel hole includes wet etching and/or dry etching. The memory film 132 and the channel layer 131 may be formed using one or more thin film deposition processes such as ALD, CVD, PVD, any other suitable process, or any combination thereof. In some embodiments, the remaining space of the trench hole may be partially or completely filled with a capping layer comprising an insulating material and/or an air gap. In some embodiments, the memory film 132 is a composite layer including silicon oxide/silicon nitride/silicon oxide (ONO).

The channel structure 130 extends into the semiconductor layer 110 and electrically contacts the semiconductor layer 110 through the channel layer 131. In some embodiments, the storage film 132 may terminate at a surface of the semiconductor layer 110 near a side of the stack structure 120, and the channel layer 131 may extend within the semiconductor layer 110, so that the channel structure 130 may be in electrical contact with the semiconductor layer 110 through the channel layer 131.

In some embodiments, the memory film surrounding the channel layer 131 at the end of the channel structure 130 is removed by etching to expose the channel layer 131 at the end of the channel structure 130, so that the channel structure 130 may be in electrical contact with the subsequently formed second semiconductor layer 102 through the channel layer 131. The memory film surrounding the channel layer 131 at the end of the channel structure 130 may be removed by a wet etching process to expose the channel layer 131 at the end of the channel structure 130. As described above, the channel structure 130 includes the channel layer 131 and the storage film 132, and the storage film 132 sequentially includes the blocking layer, the storage layer, and the tunneling layer inward in the radial direction of the channel structure 130. In some embodiments, the blocking layer, the memory layer, and the tunneling layer at the ends of the channel structure 130 may be selectively removed by a wet etching process without etching the channel layer 131. The etching of the memory film 132 may also be controlled by controlling the etching time and/or etching rate such that the etching does not continue to affect the remaining portion of the memory film 132 surrounded by the stacked structure 120. In one example, the memory film 132 is a composite layer including silicon oxide/silicon nitride/silicon oxide (ONO), and then the barrier layer, the memory layer, and the tunneling layer may be sequentially removed by selecting an appropriate etchant based on an etching selection ratio of silicon oxide and silicon nitride, and the memory film surrounding the channel layer may be simultaneously removed by using an etchant capable of simultaneously removing silicon oxide and silicon nitride. When etching is performed using the etching selectivity of silicon oxide and silicon nitride, silicon oxide can be selectively removed using, for example, hydrofluoric acid as an etchant, and silicon nitride can be selectively removed using, for example, phosphoric acid as an etchant.

In some embodiments, the channel layer 131 extending into the semiconductor layer 110 at the end of the channel structure 130 may be a doped channel layer. In some embodiments, the channel layer 131 at the end of the channel structure 130 is subjected to an ion implantation process to form a doped channel layer at the end of the channel structure 130. In the ion implantation process, the implantation depth of the dopant ions can be controlled by controlling the ion implantation energy. Here, the doped channel layer overlaps the stack structure 120 in the extending direction (Z direction) of the channel structure 130. In other embodiments, different doping depths, doping concentrations or doping impurity profiles (doping profiles) may be set according to the actual requirements of the semiconductor device. Wherein, the doping depth can be controlled by adjusting the acceleration energy of the ion beam; the doping concentration, i.e. the impurity dose, can then be controlled by monitoring the ion current during implantation; the doping impurity profile can be controlled by simultaneously adjusting the ion implantation energy and the ion implantation dose. Therefore, the doping is carried out by adopting the ion implantation process, the doping concentration, the doping depth and the doping impurity distribution can be more accurately controlled, and the repeatability is realized.

In some embodiments, the doped channel layer is subjected to an activation process. The activation process may include an annealing activation process (thermal active) or a laser activation process (laser active). It should be noted that the temperature of laser activation is lower than the temperature of high-temperature annealing activation, and in practical application, the activation treatment process can be selected according to practical requirements, so as to prevent the temperature of activation treatment from affecting the subsequent processes.

The doped channel layer and the doped semiconductor layer may have the same doping type. There is an overlap of the doped channel layer with the stack structure 120 in the extending direction (Z direction) of the channel structure 130. At this time, the channel layer 131 of the channel structure 130 includes two portions: a doped channel layer and an undoped channel layer, the undoped channel layer being located on a side of the doped channel layer adjacent to the second semiconductor structure 200.

In some embodiments, the doped channel layer may be an N-type doped channel layer, thereby enabling gate-induced drain leakage (GIDL) erasure. In particular, the N-type doped channel layer may include, for example, polysilicon, monocrystalline silicon, or amorphous silicon. The N-type doped channel layer may include a channel doped with a pentavalent impurity element such as P, Ar or Sb as an N-type dopant. Only four valence electrons in the pentavalent impurity atom can form covalent bonds with valence electrons in four surrounding semiconductor atoms, and the redundant one valence electron is easy to form free electrons because of no covalent bond constraint. Thus, the N-type doped channel layer is capable of providing free electrons. In some embodiments, a channel contact is disposed at an end of each channel structure 130 away from the semiconductor layer 110, and the channel contact is used to electrically extract a signal in the channel structure 130.

The gate line isolation structure 140 includes an electrical shielding layer 141 and an isolation layer 142 surrounding the electrical shielding layer 141. The gate line isolation structures 140 may divide a plurality of memory strings into different memory blocks (blocks), or divide the memory blocks into different memory fingers (fingers). In some embodiments, the isolation layer 142 may terminate at a surface of the semiconductor layer 110 near a side of the stacked structure 120, and the electrical shielding layer 141 may extend within the semiconductor layer 110. Wherein, the material of the electric shielding layer 141 may include, but is not limited to, W, Co, Cu, Al, silicide, or any combination thereof; the isolation layer 142 may be formed of an insulating material, which may include, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. Here, the material of the isolation layer 142 may be the same as that of the memory film 132, so that when the memory film 132 surrounding the channel layer 131 at the end of the channel structure 130 is removed, the isolation layer 142 surrounding the electrical shielding layer 141 at the end of the gate line isolation structure 140 is also removed to expose the electrical shielding layer 141 at the end of the gate line isolation structure 140.

The first semiconductor structure 100 further includes a source contact 150 located on the isolation region 106 and contacting a side of the semiconductor layer 110 remote from the stacked structure 120. As shown in fig. 2, the first semiconductor structure 100 further includes a dielectric layer 104, and the source contact 150 is located in the dielectric layer 104 and contacts the semiconductor layer 110 under the dielectric layer 104. In some embodiments, the source contact 150 terminates at a surface of the semiconductor layer 110 on a side away from the stacked structure 120. In other embodiments, the source contact 150 extends into the semiconductor layer 110.

As shown in fig. 3, the extending direction of the source contact 150 is the same as the extending direction of the gate line isolation structure 140. In some embodiments, the source contact 150 and the gate line isolation structure 140 both extend along a second direction (X-direction), wherein the second direction (X-direction) is perpendicular to the first direction (Y-direction).

In some embodiments, the length of the source contact 150 in the second direction (X-direction) is less than the length of the gate line isolation structure 140 in the second direction (X-direction).

Referring to fig. 2 and 3, the stacked structure 120 includes a step region 108 and a core region 107 arranged along the second direction (X direction). The step region 108 includes a plurality of steps, each of which exposes the gate layer on top. The stepped region 108 may be formed by performing a plurality of so-called "trim-etch" cycles on the stacked structure 120 toward the semiconductor layer 110. In some embodiments, the step region 108 includes a plurality of step contacts (not shown) that are in conductive contact with the gate layer exposed at the top surface of the corresponding step. It should be noted that the number of steps in the step region 108 and the number of stacked layers of the stacked structure 120 in fig. 2 are only used for illustrating the embodiments of the disclosure, and are not used for limiting the embodiments of the disclosure.

In some embodiments, the first semiconductor structure further includes a peripheral region 109. The peripheral region 109 includes a plurality of peripheral contact structures (not shown). The peripheral contact structure is used to lead out a portion to be electrically led out in a peripheral circuit of the second semiconductor structure 200 to the first semiconductor structure 100.

In some embodiments, as shown in fig. 3, the orthographic projection of each source contact 150 includes an edge 151 extending along the first direction (Y-direction) and an edge 152 extending along the second direction (X-direction). The orthographic projection of each gate line isolation structure 140 includes an edge 143 extending along the first direction (Y direction) and an edge 144 extending along the second direction (X direction). In some embodiments, only one gate line isolation structure 140 (not shown) is disposed in a portion of the isolation region 106, and the gate line isolation structure is used to divide a plurality of memory strings into different memory blocks; another portion of the isolation regions 106 is provided with a plurality of gate line isolation structures 140 arranged along the second direction, and the isolation regions can divide the memory block into different memory fingers. It is to be appreciated that the source contact 150 can be disposed on any one or more of the isolation regions 106 described above.

As shown in fig. 3, for the gate line isolation structure 140, an edge 143 of its orthographic projection extending in the first direction (Y direction) partially overlaps an edge 152 of the orthographic projection of the source contact 150 extending in the second direction (X direction), such as a region 160 in fig. 3.

As shown in fig. 2, the semiconductor layer 110 includes a first semiconductor layer 101 on the stepped region 108 and the peripheral region 109 and a second semiconductor layer 102 on the core region 107. The thickness of the first semiconductor layer 101 is smaller than the thickness of the second semiconductor layer 102, which is expressed as its length in the Z-direction in connection with fig. 2. In some embodiments, the material of the first semiconductor layer 101 and the second semiconductor layer 102 is the same, and both are doped semiconductor layers, and the doping types thereof are also the same. The first semiconductor layer 101 and the second semiconductor layer 102 are formed in different steps. In some embodiments, the stacked structure 120 and the channel structure 130 and the gate line isolation structure 140 penetrating through the stacked structure 120 and extending into the first semiconductor layer 101 are formed on the first semiconductor layer 101, and then the first semiconductor layer on the core region 107 is etched away to expose the ends of the channel structure 130 and the gate line isolation structure 140 in the core region 107; etching away the memory film surrounding the channel layer 131 at the end of the channel structure 130 to expose the channel layer 131 at the end of the channel structure 130; a second semiconductor layer 102 is formed on the core region 107, and the second semiconductor layer 102 covers the channel layer 131 at the end of the channel structure 130 and the end of the gate line isolation structure 140.

In some embodiments, at least one stop layer 103 may be further formed between the semiconductor layer 110 and the stack structure 120. The material of the stop layer 103 includes, but is not limited to, silicon oxide, silicon nitride, and polysilicon. In one embodiment, the material of the stop layer 103 is the same as the material of the semiconductor layer 110.

In some embodiments, an orthographic projection edge of the source contact 150 on the semiconductor layer 110 does not overlap with an orthographic projection edge of the gate line isolation structure 140 on the semiconductor layer 110. In some embodiments, the orthographic projection of the source contact 150 on the second semiconductor layer 102 and the orthographic projection of the gate line isolation structure 140 on the second semiconductor layer 102 are both rectangular. An orthographic projection of the source contact 150 includes an edge 151 extending along the first direction and an edge 152 extending along the second direction, the edge 151 includes two oppositely disposed edges of the orthographic projection extending along the first direction, and the edge 152 includes two oppositely disposed edges of the orthographic projection extending along the second direction; wherein the length of the edge 152 extending the orthographic projection of the source contact 150 along the second direction is greater than the length of the edge 151 extending the orthographic projection of the source contact 150 along the first direction. The orthographic projection of the gate line isolation structure 140 also includes an edge 143 extending along the first direction and an edge 144 extending along the second direction, the edge 143 includes two oppositely disposed edges of the orthographic projection extending along the first direction, and the edge 144 includes two oppositely disposed edges of the orthographic projection extending along the second direction; wherein the length of the edge 144 of the gate line isolation structure 140 extending along the second direction in the orthogonal projection is greater than the length of the edge 143 of the gate line isolation structure 140 extending along the first direction in the orthogonal projection.

According to the method, the channel structure is arranged in the channel region, and the source contact is arranged on the isolation region, so that the process for forming the source contact cannot influence the channel structure, the condition that the etching of the source contact influences the planing window of the channel structure is avoided, and the yield of products can be improved to a certain extent; meanwhile, the orthographic projection edge of the source contact on the semiconductor layer is not overlapped with the orthographic projection edge of the grid line isolation structure on the semiconductor layer, so that the stress on the edge part of the grid line isolation structure can be reduced, the risk of collapse of the grid line isolation structure due to overlarge stress is reduced, and the reliability of a product is improved.

In some embodiments, an edge 151 of the source contact 150, the orthographic projection of which extends along the first direction, does not overlap an edge 143 of the gate line isolation structure 140, the orthographic projection of which extends along the first direction. As shown in fig. 3, in the region 160, there is a partial overlap between the edge 152 where the orthographic projection of the source contact 150 extends in the second direction and the edge 143 where the orthographic projection of the gate line isolation structure 140 extends in the first direction in the region 160. As can be seen from fig. 2, the source contact 150 and two adjacent gate line isolation structures 140 are partially overlapped in the Z direction, but an edge 151 of the source contact 150 extending along the first direction (Y direction) and an edge 143 of the gate line isolation structure 140 extending along the first direction (Y direction) are not overlapped in the Z direction. The gate line isolation structure 140 has a large stress, and various structures formed thereon may further increase the stress of the gate line isolation structure 140, while the edge portion of the gate line isolation structure 140 is fragile and is prone to collapse due to the large stress, thereby causing failure of the memory. According to the invention, the overlapping of the edge 151 of the source contact 150 extending along the first direction (Y direction) and the edge 143 of the gate line isolation structure 140 extending along the first direction (Y direction) in the Z direction is avoided, so that the stress on the edge of the gate line isolation structure 140 can be reduced, the risk of edge collapse of the gate line isolation structure 140 is reduced, and the yield of the memory is improved.

In some embodiments, the first semiconductor structure 100 further includes a plurality of dummy channel structures (not shown). The dummy channel structure is located in the step region and/or the core region, and the filling material therein may be the same as or different from the channel structure 130. The dummy channel structure may serve as a support to avoid collapse of the stacked structure 120. To form a plurality of dummy channel structures, a dummy channel hole may be formed first, and the dummy channel hole may be formed in the same step as the channel hole in the process of forming the channel structure 130. In some embodiments, the dummy channel hole may be cylindrical. The dummy channel hole and the channel hole may be formed in different steps.

In some embodiments, the first semiconductor structure further comprises a first bonding layer (not shown) comprising a plurality of first bonding contacts electrically connected to the step contact, the peripheral contact structure, and the channel contact. The first bonding layer may further include an insulating material that electrically isolates the first bonding contact. The material of the first bonding contact may include, but is not limited to, W, Co, Cu, Al, silicide, or any combination thereof. The insulating material used for the first bonding contact electrical isolation may include, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof.

In some embodiments, the first semiconductor structure 100 further includes a first interconnect layer (not shown) over the first bonding layer, the first interconnect layer operable to pass electrical signals. The first interconnect layer may include an interconnect line (metal), a contact (via), and an interlevel dielectric layer, in which both the interconnect line and the contact may be formed, i.e., the first interconnect layer may include a plurality of interconnect lines and contacts located in the interlevel dielectric layer. The step contact, the peripheral contact structure and the channel contact are connected with corresponding interconnection lines in the first interconnection layer. In particular, the materials of the interconnect lines and contacts in the interconnect layer may each include, but are not limited to, W, Co, Cu, Al, silicide, or any combination thereof. The interlevel dielectric layer may comprise an insulating material including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. By way of example, the interlevel dielectric layer includes a first silicon nitride layer and a silicon oxide material filling the interconnect lines and the contact gaps.

In some embodiments, the semiconductor device further comprises a second semiconductor structure 200 electrically connected to the first semiconductor structure 100. Illustratively, the first semiconductor structure 100 may be bonded to the second semiconductor structure 200. The second semiconductor structure 200 includes a substrate and peripheral circuitry located on the substrate. The substrate may comprise silicon (e.g., single crystal silicon c-Si), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), or any other suitable material. The peripheral circuits may be any suitable digital, analog, and/or mixed signal control and sensing circuitry for operation of the semiconductor device, including but not limited to page buffers, decoders (e.g., row and column decoders), sense amplifiers, drivers (e.g., word line drivers), charge pumps, current or voltage references, or any active or passive component of circuitry (e.g., transistors, diodes, resistors, or capacitors).

The second semiconductor structure 200 further includes a second bonding layer 201, and the second bonding layer 201 may include a plurality of second bonding contacts and an insulating material electrically isolating the second bonding contacts. The material of the second bonding contact includes, but is not limited to, W, Co, Cu, Al, silicide, or any combination thereof. The insulating material used to electrically isolate the second bonding contact may include, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof.

Likewise, the second semiconductor structure 200 further includes a second interconnect layer above the peripheral circuits, the second interconnect layer for passing electrical signals of the peripheral circuits, including inputting electrical signals to the peripheral circuits and outputting electrical signals of the peripheral circuits. The second interconnect layer may include a peripheral interconnect line, a peripheral contact, and a peripheral interlevel dielectric layer, in which both the peripheral interconnect line and the peripheral contact may be formed, i.e., the second interconnect layer may include a plurality of peripheral interconnect lines and peripheral contacts in the peripheral interlevel dielectric layer. In particular, the materials of the peripheral interconnect lines and the peripheral contacts in the second interconnect layer may each include, but are not limited to, W, Co, Cu, Al, silicide, or any combination thereof. The peripheral circuit interlayer dielectric layer may comprise an insulating material including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. By way of example, the peripheral circuit interlayer dielectric layer comprises a second silicon nitride layer and a silicon oxide material which are filled in the peripheral interconnection line and the peripheral contact gap.

Fig. 4 is a cross-sectional view of another semiconductor device provided in an embodiment of the present disclosure, and fig. 5 is a top view of another semiconductor device provided in an embodiment of the present disclosure. The left portion of the dotted line in fig. 4 is a sectional view taken along line AA 'in fig. 5, and the right portion of the dotted line is a sectional view taken along line CC' in fig. 5. The semiconductor devices shown in fig. 4 and 5 are similar to those shown in fig. 2 and 3 except that the source contact is disposed at a different position. It is to be understood that details of other identical structures in both the semiconductor device shown in fig. 4 and 5 and the semiconductor device shown in fig. 2 and 3 are not repeated for convenience of description.

As shown in fig. 5, the extending direction of the source contact 150 is the same as the extending direction of the gate line isolation structure 140. In some embodiments, the source contact 150 and the gate line isolation structure 140 both extend along a second direction (X-direction), wherein the second direction (X-direction) is perpendicular to the first direction (Y-direction).

Referring to fig. 4 and 5, an orthographic projection of the source contact 150 is inside an orthographic projection of the gate line isolation structure 140, and an orthographic projection edge of the source contact 150 on the semiconductor layer 110 does not overlap with an orthographic projection edge of the gate line isolation structure 140 on the semiconductor layer 110. The orthographic projection of each source contact 150 includes an edge 151 extending along a first direction (Y-direction) and an edge 152 extending along a second direction (X-direction). The orthogonal projection of each gate line isolation structure 140 includes an edge 143 extending in the first direction (Y direction) and an edge 144 extending in the second direction (X direction). At this time, the edge 151 extending in the first direction (Y direction) and the edge 152 extending in the second direction (X direction) of the orthographic projection of the source contact 150 do not overlap with the edge 143 extending in the first direction (Y direction) and the edge 144 extending in the second direction (X direction) of the orthographic projection of the gate line isolation structure 140. In embodiments of the present disclosure, the source contact 150 may be located on the core region 107. In other embodiments, the source contact may be located on the core region 107 and/or on the stepped region 108.

Fig. 6 is a cross-sectional view of another semiconductor device provided in an embodiment of the present disclosure, and fig. 7 is a top view of another semiconductor device provided in an embodiment of the present disclosure. The left part of the dotted line in fig. 6 is a sectional view taken along line AA 'in fig. 7, and the right part of the dotted line is a sectional view taken along line DD' in fig. 7. The semiconductor devices shown in fig. 6 and 7 are similar to those shown in fig. 2 and 3 except that the source contact is disposed at a different position. It is to be understood that the details of the other identical structures in both the semiconductor device shown in fig. 6 and 7 and the semiconductor device shown in fig. 2 and 3 are not repeated for convenience of description.

As shown in fig. 6, the extending direction of the source contact 150 is the same as the extending direction of the gate line isolation structure 140. In some embodiments, the source contact 150 and the gate line isolation structure 140 both extend along a second direction (X-direction), wherein the second direction (X-direction) is perpendicular to the first direction (Y-direction).

In some embodiments, the length of the source contact 150 in the second direction (X-direction) is greater than the length of the gate line isolation structure 140 in the second direction (X-direction).

Referring to fig. 6 and 7, the orthographic projection of the gate line isolation structure 140 is inside the orthographic projection of the source contact 150, and the orthographic projection edge of the source contact 150 on the semiconductor layer 110 does not overlap with the orthographic projection edge of the gate line isolation structure 140 on the semiconductor layer 110. That is, in fig. 7, the source contact 150 completely covers the gate line isolation structure 140 located therebelow.

The orthographic projection of each source contact 150 includes an edge 151 extending in a first direction (Y direction) and an edge 152 extending in a second direction (X direction). The orthogonal projection of each gate line isolation structure 140 includes an edge 143 extending in the first direction (Y direction) and an edge 144 extending in the second direction (X direction). At this time, the edge 151 extending in the first direction (Y direction) and the edge 152 extending in the second direction (X direction) of the orthographic projection of the source contact 150 do not overlap with the edge 143 extending in the first direction (Y direction) and the edge 144 extending in the second direction (X direction) of the orthographic projection of the gate line isolation structure 140. In embodiments of the present disclosure, the source contact 150 may be located on the core region 107. In other embodiments, the source contact may be located on the core region 107 and/or on the stepped region 108.

In some embodiments, the semiconductor device is a 3D NAND memory, or the semiconductor device is a portion of a 3D NAND memory.

Fig. 8 is a flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present disclosure, where as shown in fig. 8, the method includes:

step 801, a first semiconductor structure is formed, where the first semiconductor structure includes a semiconductor layer, a stacked structure formed on the semiconductor layer, a channel structure penetrating through the stacked structure and electrically contacting the semiconductor layer, and a gate line isolation structure penetrating through the stacked structure and extending into the semiconductor layer.

Fig. 9a to 9h are schematic structural diagrams of a method for manufacturing a semiconductor device according to an embodiment of the present disclosure, and it should be noted that fig. 9a to 9h are cross-sectional views of a gate line isolation structure 140 in a core region 107. The formation process of the semiconductor device provided by the present embodiment will be described below with reference to fig. 9a to 9 h.

As shown in fig. 9a, a stack structure 120 is formed on the first semiconductor layer 101. The stack structure is formed by alternately stacking the gate layers 121 and the insulating layers 122. In some embodiments, the first semiconductor layer 101 is doped using an ion implantation process to form a doped semiconductor layer before forming the stack structure 120. In practical applications, the stacked structure 120 may be formed by a Deposition process, such as Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Plasma-Enhanced CVD (PECVD), sputtering, Metal-Organic Chemical Vapor Deposition (MOCVD), or Atomic Layer Deposition (ALD).

In some embodiments, the stacked structure is formed on a substrate, and the substrate on which the stacked structure is formed may be removed from the rear surface to expose the gate line isolation structure 140. After removing the substrate, a doped semiconductor layer may be deposited from the backside to electrically connect the sources of the plurality of channel structures, thereby increasing the conductance of the Array Common Source (ACS) of channel structures. In some embodiments, the backside thinning process is automatically stopped using one or more stop layers 103 so that the substrate can be completely removed to avoid wafer thickness uniformity control issues and reduce the manufacturing complexity of the backside process. Here, the substrate may be an elemental semiconductor material substrate (e.g., a silicon (Si) substrate, a germanium (Ge) substrate, or the like), a composite semiconductor material substrate (e.g., a silicon germanium (SiGe) substrate, or the like), or a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GeOI) substrate, or the like. The material of the substrate may also be part of a dummy wafer (e.g., a carrier substrate) made of any suitable material to reduce the manufacturing cost of the semiconductor device, such as glass, sapphire, plastic, silicon, to name a few, since the substrate may be removed in a subsequent step.

A gate line isolation structure 140 is formed to penetrate the stack structure 120 and extend into the first semiconductor layer 101. To form the gate line isolation structure 140, a gate line slit (gate line slit) may be formed in the stacked structure 120, then an isolation layer 142 may be formed on a sidewall of the gate line slit, and a conductive material may be filled to form the electrical shielding layer 141, and the electrical shielding layer 141 and the isolation layer 142 surrounding the electrical shielding layer 141 form the gate line isolation structure 140. The isolation layer 142 and the electrical shield layer 141 may be formed using one or more thin film deposition processes such as ALD, CVD, PVD, and any other suitable process or any combination thereof.

The gate layer 121 in the stacked structure 120 may also be formed through the gate line gap, which includes the following specific processes: an initial stack structure is formed, which is formed of alternately stacked insulating layers and sacrificial layers. And etching the initial stacked structure to form a gate line gap, removing the sacrificial layer in the initial stacked structure through the gate line gap to form a transverse recess, and filling a gate material in the transverse recess to form a gate electrode layer 121. The gate material includes, but is not limited to, W, Co, Cu, Al, polysilicon, silicide, or any combination thereof.

In some embodiments, after the gate line isolation structure 140 is formed, a step contact, a peripheral contact structure, and a channel contact (not shown in the drawings) are formed. The step contacts are in conductive contact with the gate layer exposed at the top surface of the corresponding step. A masking layer may be formed on the stacked structure 120 by depositing a masking material (e.g., silicon oxide or silicon nitride) on top of the stacked structure 120 using one or more thin film deposition processes such as CVD, PVD, ALD, or any combination thereof. The contact openings through the mask layer may be etched using wet and/or dry Etching (e.g., Reactive Ion Etching (RIE)) followed by filling the contact openings with a conductive material using one or more thin film deposition processes such as ALD, CVD, PVD, any other suitable process, or any combination thereof, to form step contacts, peripheral contact structures, and channel contacts. In some embodiments, a first bonding layer is formed on the stacked structure 120.

As shown in fig. 9b, the first semiconductor structure 100 in fig. 9a is flipped upside down and bonded to the second semiconductor structure 200 in fig. 9 b. In some embodiments, a first bonding layer (not shown) of the first semiconductor structure 100 facing downward is bonded in a face-to-face manner with a second bonding layer (not shown) of the second semiconductor structure 200 facing upward. In some embodiments, the first semiconductor structure and the second semiconductor structure may be bonded by metal fusion bonding. Of course, in some embodiments, the first semiconductor structure and the second semiconductor structure may be bonded by non-metal bonding, including but not limited to using an adhesive or the like. In some embodiments, a bonding layer may also be formed between the first semiconductor structure and the second semiconductor structure by hybrid bonding, i.e., metal/non-metal hybrid bonding.

In some embodiments, a treatment process, such as a plasma treatment, a wet treatment, and/or a thermal treatment, may be applied to the surfaces of the first and second bonding layers prior to bonding. After bonding, the first bonding contact in the first bonding layer and the second bonding contact in the second bonding layer are aligned and brought into contact with each other, so that the stacked structure 120 and the channel structure 130 formed therethrough in the first semiconductor structure 100 may be electrically connected to the peripheral circuit in the second semiconductor structure 200.

As shown in fig. 9c, the first semiconductor layer on the core region 107 is etched away to expose the end of the gate line isolation structure 140 in the core region 107. The first semiconductor layer remains on the stepped region 108 and the peripheral region 109. The first semiconductor layer on the core region 107 is removed from the back side of the first semiconductor layer 101, where the back side of the first semiconductor layer 101 refers to a side of the first semiconductor layer 101 away from the stacked structure 120. The first semiconductor layer on the core region 107 is removed by a wet etching process to expose the end of the gate line isolation structure 140. Due to the selectivity of the wet etching process, only the first semiconductor layer on the core region 107 can be etched and removed, and the structure below the first semiconductor layer, that is, the electrical shielding layer 141 and the isolation layer 142 of the gate line isolation structure 140, can not be etched and remain intact.

As shown in fig. 9d, the isolation layer 142 surrounding the electrical shielding layer 141 at the end of the gate line isolation structure 140 is removed by etching, and the electrical shielding layer 141 at the end of the gate line isolation structure 140 is exposed. In some embodiments, the material of the isolation layer 142 of the gate line isolation structure 140 may be the same as the material of the memory film, so that the memory film surrounding the channel layer at the end of the channel structure and the isolation layer surrounding the electric shield layer 141 at the end of the gate line isolation structure 140 may be removed in the same step.

As shown in fig. 9e, a second semiconductor layer 102 is formed on the core region 107, and the second semiconductor layer 102 covers the electrical shielding layer 141 at the end of the gate line isolation structure 140. In some embodiments, after forming the second semiconductor layer 102, the second semiconductor layer 102 is doped to form a doped semiconductor layer together with the doped first semiconductor layer. Wherein, the doping type of the doped semiconductor layer is the same as that of the doped channel layer. In some embodiments, the doped semiconductor layer may be an N-type doped semiconductor layer. In some embodiments, the second semiconductor layer 102 is doped with N-type dopants using an ion implantation process.

The first semiconductor layer (not shown) and the second semiconductor layer 102 located in the step region and the peripheral region are planarized such that an upper surface of the first semiconductor layer is flush with an upper surface of the second semiconductor layer 102. In some embodiments, the excess first or second semiconductor layer 102 is removed by a Chemical Mechanical Polishing (CMP) process such that the upper surface of the first semiconductor layer is flush with the upper surface of the second semiconductor layer 102.

And step 802, forming a source contact which is contacted with one surface of the semiconductor layer far away from the stacked structure on the isolation region, wherein the orthographic projection edge of the source contact on the semiconductor layer is not overlapped with the orthographic projection edge of the grid line isolation structure on the semiconductor layer.

As shown in fig. 9f, a dielectric layer 104 is formed on a side of the second semiconductor layer 102 away from the stacked structure 120. A dielectric layer 104 covers the second semiconductor layer 102, and the material of the dielectric layer 104 includes, but is not limited to, silicon oxide, silicon nitride, and polysilicon. Illustratively, the dielectric layer 104 may be formed using one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, or any combination thereof.

As shown in fig. 9g, the dielectric layer 104 is etched to form a source contact opening 170, the source contact opening 170 exposing the second semiconductor layer 102. Illustratively, the source contact opening 170 is formed using a dry etch process.

As shown in fig. 9h, the source contact opening 170 is filled to form the source contact 150 contacting the second semiconductor layer 102, and the extending direction of the source contact 150 is the same as the extending direction of the gate line isolation structure 140. Referring to fig. 3, an edge 151 of the source contact 150, which extends in the first direction (Y direction) in an orthogonal projection on the second semiconductor layer 102, does not overlap an edge 143 of the gate line isolation structure 140, which extends in the first direction (Y direction) in an orthogonal projection on the second semiconductor layer 102.

In some embodiments, an edge 152 of the source contact 150, the orthographic projection of which extends along the second direction (X-direction), partially overlaps an edge 143 of the gate line isolation structure 140, the orthographic projection of which extends along the first direction (Y-direction).

In some embodiments, the stacked structure 120 includes a step region 108 and a core region 107 arranged along the second direction (X direction).

It should be noted that the above description of the manufacturing method of the semiconductor device is similar to the above description of the embodiment of the semiconductor device, and has similar beneficial effects to the embodiment of the semiconductor device, and therefore, the description is omitted. For technical details that are not disclosed in the method for manufacturing the semiconductor device in the embodiment of the present disclosure, please refer to the description of the semiconductor device in the embodiment of the present disclosure for understanding.

Fig. 10 is a block diagram of a memory system according to an embodiment of the disclosure. The memory system 1000 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, Virtual Reality (VR) device, Augmented Reality (AR) device, or any other suitable electronic device having memory therein. As shown in fig. 10, the memory system 1000 may include a host 1008 and a memory system 1002, the memory system 1002 including one or more memories 1004 and a controller 1006, the memory 1004 including a memory cell array and a plurality of page buffers. The host 1008 may be a processor (e.g., a Central Processing Unit (CPU)) or a system on chip (SoC) (e.g., an Application Processor (AP)) of the electronic device. Host 1008 may be configured to send data to memory 1004 or receive data from memory 1004.

The semiconductor device of the present disclosure is the memory 1004, or a part of the memory 1004. According to some embodiments, controller 1006 is coupled to memory 1004 and host 1008, and is configured to control the memory. The controller 1006 may manage data stored in memory and communicate with a host 1008. In some implementations, the controller 1006 is designed to operate in a low duty cycle environment, such as a Secure Digital (SD) card, Compact Flash (CF) card, Universal Serial Bus (USB) flash drive, or other medium for use in electronic devices such as personal computers, digital cameras, mobile phones, and the like. In some implementations, the controller 1006 is designed for operation in a high duty cycle environment SSD or embedded multimedia card (eMMC) that serves as a data store for mobile devices such as smart phones, tablet computers, laptop computers, and the like, as well as enterprise storage. The controller 1006 may be configured to control operations of the memory 1004, such as read, erase, and program operations. The controller 1006 may also be configured to manage various functions with respect to data stored or to be stored in the memory 1004, including but not limited to bad block management, garbage collection, logical to physical address translation, wear leveling, and the like. In some implementations, the controller 1006 is also configured to process Error Correction Codes (ECC) with respect to data read from the memory 1004 or written to the memory 1004. The controller 1006 may also perform any other suitable functions, such as formatting the memory 1004. The controller 1006 may communicate with external devices (e.g., host 1008) according to a particular communication protocol. For example, the controller 1006 may communicate with external devices via at least one of various interface protocols, such as a USB protocol, an MMC protocol, a Peripheral Component Interconnect (PCI) protocol, a PCI express (PCI-E) protocol, an Advanced Technology Attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a small computer system small interface (SCSI) protocol, an Enhanced Small Disk Interface (ESDI) protocol, an Integrated Drive Electronics (IDE) protocol, a Firewire protocol, and so forth.

The controller 1006 and the one or more memories 1004 may be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Storage (UFS) package or an eMMC package). That is, the memory system 1002 can be implemented and packaged into different types of terminal electronics.

Fig. 11a is a schematic diagram of a memory card according to an embodiment of the disclosure. In one example as shown in FIG. 11a, the controller 1006 and the single memory 1004 may be integrated into the memory card 1102. The memory card 1102 may include a PC card (PCMCIA, personal computer memory card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, minisD, microsD, SDHC), UFS, and the like. The memory card 1102 may also include a memory card connector 1104 that couples the memory card 1102 with a host (e.g., host 1008 in FIG. 10).

Fig. 11b is a schematic diagram of a Solid State Drive (SSD) according to an embodiment of the disclosure. As shown in fig. 11b, controller 1006 and plurality of memories 1004 may be integrated into SSD 1106. The SSD1106 may also include an SSD connector 1108 that couples the SSD1106 with a host (e.g., host 1008 in fig. 10). In some implementations, the storage capacity and/or operating speed of SSD1106 is greater than the storage capacity and/or operating speed of memory card 1102.

It should be appreciated that reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure or characteristic described in connection with the embodiment is included in at least one embodiment of the present disclosure. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. It should be understood that, in various embodiments of the present disclosure, the sequence numbers of the above-mentioned processes do not imply an order of execution, and the order of execution of the processes should be determined by their functions and inherent logic, and should not constitute any limitation to the implementation process of the embodiments of the present disclosure. The above-mentioned serial numbers of the embodiments of the present disclosure are merely for description and do not represent the merits of the embodiments.

The methods disclosed in the several method embodiments provided in this disclosure may be combined arbitrarily without conflict to arrive at new method embodiments.

The above description is only for the specific embodiments of the present disclosure, but the scope of the present disclosure is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present disclosure, and all the changes or substitutions should be covered within the scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims

1. A semiconductor device, characterized in that the semiconductor device comprises:

2. The semiconductor device of claim 1, wherein the source contact and the gate line isolation structure extend along a second direction perpendicular to the first direction.

3. The semiconductor device according to claim 2, wherein an edge of the orthographic projection of the source contact extending in the second direction partially overlaps an edge of the orthographic projection of the gate line isolation structure extending in the first direction.

4. The semiconductor device of claim 2 or 3, wherein a length of the source contact in the second direction is less than a length of the gate line isolation structure in the second direction.

5. The semiconductor device of claim 2, wherein the orthographic projection of the source contact is inside the orthographic projection of the gate line isolation structure.

6. The semiconductor device of claim 2, wherein the orthographic projection of the gate line isolation structure is interior to the orthographic projection of the source contact.

7. The semiconductor device according to claim 2, wherein the stacked structure includes a step region and a core region arranged along the second direction; the semiconductor layer comprises a first semiconductor layer located on the step area and a second semiconductor layer located on the core area, and the thickness of the first semiconductor layer is smaller than that of the second semiconductor layer.

8. The semiconductor device according to claim 1, further comprising:

a second semiconductor structure electrically connected to the first semiconductor structure; the second semiconductor structure includes a substrate and peripheral circuitry located on the substrate.

9. A method of fabricating a semiconductor device, the method comprising:

10. The method of claim 9, wherein the forming a source contact in contact with a side of the semiconductor layer remote from the stacked structure comprises:

forming a dielectric layer on one surface of the semiconductor layer far away from the stacking structure;

etching the dielectric layer to form a source contact opening, wherein the semiconductor layer is exposed by the source contact opening;

and filling the source contact opening to form a source contact which is in contact with the semiconductor layer, wherein the source contact and the grid line isolation structure extend along a second direction which is perpendicular to the first direction.

11. The method for manufacturing a semiconductor device according to claim 10, wherein an edge of the orthographic projection of the source contact extending in the second direction partially overlaps an edge of the orthographic projection of the gate line isolation structure extending in the first direction.

12. The method of manufacturing a semiconductor device according to claim 10 or 11, wherein a length of the source contact in the second direction is smaller than a length of the gate line isolation structure in the second direction.

13. The method of claim 10, wherein the forming the first semiconductor structure comprises:

forming a stacked structure on the first semiconductor layer;

and forming a channel structure and a grid line isolation structure which penetrate through the stacked structure and extend into the first semiconductor layer.

14. The method of manufacturing a semiconductor device according to claim 13, wherein the stacked structure includes a step region and a core region arranged along the second direction; the method further comprises the following steps:

etching and removing the first semiconductor layer on the core region to expose the tail ends of the channel structure and the grid line isolation structure in the core region;

etching and removing the storage film surrounding the channel layer at the tail end of the channel structure to expose the channel layer at the tail end of the channel structure;

forming a second semiconductor layer on the core region, wherein the second semiconductor layer covers the channel layer at the tail end of the channel structure and the tail end of the grid line isolation structure; the thickness of the first semiconductor layer is smaller than that of the second semiconductor layer.

15. The method of manufacturing a semiconductor device according to claim 10, wherein the orthographic projection of the source contact is inside the orthographic projection of the gate line isolation structure.

16. The method of manufacturing a semiconductor device according to claim 10, wherein the orthographic projection of the gate line isolation structure is inside the orthographic projection of the source contact.

17. The method of claim 9, wherein prior to forming the source contact in contact with the side of the semiconductor layer remote from the stacked structure, the method further comprises:

providing a second semiconductor structure, wherein the second semiconductor structure comprises a substrate and peripheral circuits formed on the substrate;

electrically connecting the first semiconductor structure and the second semiconductor structure.

18. A memory system, the memory system comprising:

at least one semiconductor device as claimed in any one of claims 1 to 8; and a controller coupled to the semiconductor device and configured to control the semiconductor device.