CN114649438B - Preparation method of N-type HIBC solar cell - Google Patents
Preparation method of N-type HIBC solar cell Download PDFInfo
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- CN114649438B CN114649438B CN202011496014.9A CN202011496014A CN114649438B CN 114649438 B CN114649438 B CN 114649438B CN 202011496014 A CN202011496014 A CN 202011496014A CN 114649438 B CN114649438 B CN 114649438B
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- 238000002360 preparation method Methods 0.000 title claims abstract description 23
- 239000010410 layer Substances 0.000 claims abstract description 146
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 72
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims abstract description 56
- 238000002161 passivation Methods 0.000 claims abstract description 25
- 238000005530 etching Methods 0.000 claims abstract description 18
- 238000004140 cleaning Methods 0.000 claims abstract description 16
- 239000000758 substrate Substances 0.000 claims abstract description 15
- 239000000463 material Substances 0.000 claims abstract description 11
- 239000011241 protective layer Substances 0.000 claims abstract description 8
- 229910021419 crystalline silicon Inorganic materials 0.000 claims abstract description 7
- 238000004519 manufacturing process Methods 0.000 claims abstract 7
- 239000010408 film Substances 0.000 claims description 43
- 238000000034 method Methods 0.000 claims description 40
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 14
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 10
- 229910052710 silicon Inorganic materials 0.000 claims description 10
- 239000010703 silicon Substances 0.000 claims description 10
- 238000004050 hot filament vapor deposition Methods 0.000 claims description 9
- 238000003475 lamination Methods 0.000 claims description 9
- 229910052751 metal Inorganic materials 0.000 claims description 7
- 239000002184 metal Substances 0.000 claims description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 6
- 238000000151 deposition Methods 0.000 claims description 6
- 239000010409 thin film Substances 0.000 claims description 5
- 239000012670 alkaline solution Substances 0.000 claims description 4
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 3
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- 230000008021 deposition Effects 0.000 claims description 3
- 229910002804 graphite Inorganic materials 0.000 claims description 3
- 239000010439 graphite Substances 0.000 claims description 3
- 239000010453 quartz Substances 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 3
- 230000001680 brushing effect Effects 0.000 claims description 2
- 230000009286 beneficial effect Effects 0.000 abstract description 3
- 238000010586 diagram Methods 0.000 description 8
- 238000005516 engineering process Methods 0.000 description 4
- KWYUFKZDYYNOTN-UHFFFAOYSA-M Potassium hydroxide Chemical compound [OH-].[K+] KWYUFKZDYYNOTN-UHFFFAOYSA-M 0.000 description 3
- HEMHJVSKTPXQMS-UHFFFAOYSA-M Sodium hydroxide Chemical compound [OH-].[Na+] HEMHJVSKTPXQMS-UHFFFAOYSA-M 0.000 description 3
- 239000002253 acid Substances 0.000 description 2
- 239000003513 alkali Substances 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical group [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 238000010521 absorption reaction Methods 0.000 description 1
- 239000000654 additive Substances 0.000 description 1
- 230000000996 additive effect Effects 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000011031 large-scale manufacturing process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- -1 silver-aluminum Chemical compound 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic Table
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
- H01L31/0352—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Electromagnetism (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Photovoltaic Devices (AREA)
Abstract
The invention discloses a preparation method of an N-type HIBC solar cell, which belongs to the field of solar cell preparation and comprises the following steps: sequentially forming a first amorphous silicon passivation layer and an antireflection film layer on the front surface of the monocrystalline silicon wafer; the back of the monocrystalline silicon piece is covered by adopting a separable hard mask, the hard mask is covered by adopting interval arrangement, and a protruding layer is formed in a region which is not covered by the hard mask; etching and cleaning the covering area of the hard mask plate on the back surface of the monocrystalline silicon wafer, and removing the crystalline silicon substrate in the area to form a groove; printing an ink mask material on the raised layer to form an ink protective layer; sequentially forming three films in all areas of the back surface of the monocrystalline silicon piece; cleaning the back of the monocrystalline silicon piece, and stripping the printing ink protective layer; and printing an electrode. The invention has the advantages of simplifying the preparation process and being very beneficial to mass production.
Description
[ Field of technology ]
The invention relates to a preparation method of an N-type HIBC solar cell, and belongs to the field of solar cell preparation.
[ Background Art ]
At present HIBC solar cells are limited by the factors of complex process flow, higher preparation cost, narrow process technology window and the like, and cannot realize large-scale commercial application. The conventional HIBC battery needs multiple masks and etching, the process flow is long, the preparation process generally needs 15-20 steps, and the process is complex and the preparation cost is high. This complex process flow limits the improvement in HIBC cell efficiency.
[ Invention ]
The invention aims to solve the technical problem of overcoming the defects of the prior art and providing the preparation method of the N-type HIBC solar cell, which simplifies the preparation process and is very beneficial to large-scale production.
The technical problems are solved, and the invention adopts the following technical scheme:
the preparation method of the N-type HIBC solar cell comprises the following steps:
s1: selecting an N-type monocrystalline silicon wafer, treating the back surface of the monocrystalline silicon wafer as a polished surface, and treating the front surface of the monocrystalline silicon wafer as a suede;
s2: sequentially forming a first amorphous silicon passivation layer and an antireflection film layer on the front surface of the monocrystalline silicon wafer;
S3: the back of the monocrystalline silicon piece is covered by adopting a separable hard mask, the hard mask is covered by adopting interval arrangement, a protruding layer is formed in a region which is not covered by the hard mask, and the protruding layer sequentially comprises a second intrinsic amorphous silicon passivation layer, a P-type amorphous silicon layer and a first transparent conductive film TCO layer;
S4: etching and cleaning the covering area of the hard mask on the back surface of the monocrystalline silicon wafer in the step S3, and removing the crystalline silicon substrate in the area to form a groove;
S5: printing an ink mask material on the first transparent conductive film TCO layer in the step S4 to form an ink protection layer;
s6: in the step S5, all areas on the back surface of the monocrystalline silicon wafer are sequentially formed with a third intrinsic amorphous silicon passivation layer, an N-type amorphous silicon layer and a second transparent conductive film TCO layer;
S7: in the step S6, cleaning the back surface of the monocrystalline silicon piece, and stripping the printing ink protective layer;
S8: printing a metal electrode on the P-type amorphous silicon layer and the first transparent conductive film TCO layer lamination, and curing at a low temperature; and brushing a metal electrode on the lamination of the N-type amorphous silicon layer and the second transparent conductive film TCO layer, and curing at a low temperature.
The beneficial effects of the invention are that:
Firstly, compared with the traditional 15-20 steps, the preparation process of the HIBC solar cell has the advantages that the necessary steps are 8 steps, and the preparation efficiency is improved comprehensively from the aspects of the preparation process and the complexity of the preparation process, and meanwhile, the performance of the cell is not influenced.
In the invention, the process steps are simplified and the performance of the battery is maintained by adopting the hard mask plate covering technology, because the hard mask plate does not need to carry out independent printing or depositing of a mask layer on the monocrystalline silicon wafer, the damage to the silicon substrate of the monocrystalline silicon wafer is reduced, meanwhile, the hard mask plate can be separated independently, the mask layer does not need to be cleaned and removed, and the traditional cleaning steps can introduce pollution, thereby increasing the process complexity. Meanwhile, the cost is reduced, and the separable hard mask plate can be repeatedly used, so that the reliability and the stability are high.
Finally, in the invention, the N area and the P area are indirectly isolated by the method of etching the grooves on the monocrystalline silicon wafer, so that the leakage current of the battery is reduced, and the conversion efficiency is improved.
Preferably, the hard mask is integrated on a device, when the protruding layer is formed in S3, the device is used to approach the monocrystalline silicon body to attach the hard mask to the monocrystalline silicon body, and when etching and cleaning are required in S4, the hard mask is separated from the monocrystalline silicon body.
Preferably, the hard mask plate is a quartz plate or a graphite plate.
Preferably, in S4, the thickness of the removed crystalline silicon substrate is 5-10 um.
Preferably, the ink protective layer in S5 is alkaline, and the cleaning in S7 is performed using an alkaline solution.
Preferably, in the step S1, the front surface of the monocrystalline silicon wafer is prepared into a pyramid suede by a mask method or a chain etching method.
Preferably, the thickness of the first amorphous silicon passivation layer is 1-10nm, and the first amorphous silicon passivation layer is an intrinsic amorphous silicon layer formed by a PECVD method or hot filament CVD method, or is an intrinsic amorphous silicon layer and an N-type amorphous silicon layer, or is a combined layer of the intrinsic amorphous silicon layer and a P-type amorphous silicon layer.
Preferably, the front anti-reflection film layer is deposited by a PECVD method, is one or more mixed lamination layers of silicon nitride, silicon oxide and silicon oxynitride, and has a thickness of 60-150nm.
Preferably, the second intrinsic amorphous silicon passivation layer and the P-type amorphous silicon layer are deposited by PECVD or hot-wire CVD, and the thickness is 1-20nm and 1-20nm respectively; and/or the third intrinsic amorphous silicon passivation layer and the N-type amorphous silicon layer are deposited by a PECVD (plasma enhanced chemical vapor deposition) or hot filament CVD method, and the thicknesses of the third intrinsic amorphous silicon passivation layer and the N-type amorphous silicon layer are respectively 1-20nm and 1-20nm.
Preferably, the first transparent conductive film TCO layer is prepared by PVD or RPD method, the first transparent conductive film TCO layer is made of any one of ITO, IWO, IMO, AZO materials, and the thickness is 120-200nm; and/or the second transparent conductive film TCO layer is prepared by PVD or RPD method, and is made of any one of ITO, IWO, IMO, AZO materials, and the thickness is 80-150nm.
These features and advantages of the present invention will be disclosed in detail in the following detailed description and the accompanying drawings.
[ Description of the drawings ]
The invention is further described with reference to the accompanying drawings:
FIG. 1 is a schematic overall flow chart of the present invention;
FIG. 2 is a schematic diagram of the structure of the present invention after S1;
FIG. 3 is a schematic diagram of the structure of the present invention after S2;
FIG. 4 is a schematic diagram of the structure of the present invention after S3;
FIG. 5 is a schematic diagram of the structure of the present invention after S4;
FIG. 6 is a schematic diagram of the structure of the present invention after S5;
FIG. 7 is a schematic diagram of the structure of the present invention after S6;
FIG. 8 is a schematic diagram of the structure of the present invention after S7;
fig. 9 is a schematic structural diagram of the present invention after S8.
[ Detailed description ] of the invention
The technical solutions of the embodiments of the present invention will be explained and illustrated below with reference to the drawings of the embodiments of the present invention, but the following embodiments are only preferred embodiments of the present invention, and not all embodiments. Based on the examples in the implementation manner, other examples obtained by a person skilled in the art without making creative efforts fall within the protection scope of the present invention.
In the following description, directional or positional relationships such as the terms "inner", "outer", "upper", "lower", "left", "right", etc., are presented for convenience in describing the embodiments and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore should not be construed as limiting the invention.
Embodiment one:
As shown in fig. 1 to 9, the present embodiment is a method for preparing an N-type HIBC solar cell, including the following steps:
S1: selecting an N-type monocrystalline silicon piece 1, treating the back surface of the monocrystalline silicon piece 1 as a polished surface, and treating the front surface of the monocrystalline silicon piece 1 as a textured surface;
S2: forming a first amorphous silicon passivation layer 3 and an antireflection film layer 2 on the front surface of the monocrystalline silicon piece 1 in sequence;
S3: the back of the monocrystalline silicon piece 1 is covered by adopting a separable hard mask, the hard mask is covered by adopting interval arrangement, a convex layer is formed in a region which is not covered by the hard mask, and the convex layer sequentially comprises a second intrinsic amorphous silicon passivation layer 4, a P-type amorphous silicon layer 5 and a first transparent conductive film TCO layer 6;
S4: etching and cleaning the covering area of the hard mask on the back surface of the monocrystalline silicon piece 1 in the step S3, and removing the crystalline silicon substrate in the area to form a groove;
S5: printing an ink mask material on the first transparent conductive film TCO layer 6 in the step S4 to form an ink protection layer 7;
s6: in the step S5, all areas on the back surface of the monocrystalline silicon piece 1 are sequentially formed with a third intrinsic amorphous silicon passivation layer 8, an N-type amorphous silicon layer 9 and a second transparent conductive film TCO layer 10;
S7: in the step S6, the back surface of the monocrystalline silicon piece 1 is cleaned, and the printing ink protective layer 7 is peeled off;
s8: printing a metal electrode on the P-type amorphous silicon layer and the first transparent conductive film TCO layer 6 lamination, and curing at low temperature; on the stack of the N-type amorphous silicon layer 9 and the second transparent conductive film TCO layer 10, a metal electrode is brushed and cured at a low temperature.
Firstly, compared with the traditional 15-20 steps, the preparation process of the HIBC solar cell in the embodiment has the advantages that the necessary steps are 8 steps, and the preparation efficiency is improved by combining the steps of the preparation process and the complexity of the preparation process, and meanwhile, the performance of the cell is not affected.
In addition, in the embodiment, the process steps are simplified and the performance of the battery is maintained by adopting the hard mask covering technology, because the hard mask does not need to carry out independent printing or depositing of a mask layer on the monocrystalline silicon wafer, the damage to the silicon substrate of the monocrystalline silicon wafer is reduced, meanwhile, the hard mask can be independently separated later, the mask layer does not need to be cleaned, and the traditional cleaning steps can introduce pollution, so that the process complexity is increased. Meanwhile, the cost is reduced, and the separable hard mask plate can be repeatedly used, so that the reliability and the stability are high.
Finally, in the embodiment, the N area and the P area are indirectly isolated by a method of etching grooves on the monocrystalline silicon wafer, so that the leakage current of the battery is reduced, and the conversion efficiency is improved.
As preferable in the above steps, the following are respectively:
In the S1, the front surface of the monocrystalline silicon wafer 1 is a pyramid suede prepared by a mask method or a chain etching method, the front surface of the monocrystalline silicon wafer 1 is a light receiving surface, and the suede is arranged on the light receiving surface, so that the absorption of incident sunlight can be effectively improved, and the light rising current density is improved.
In S2, the first amorphous silicon passivation layer 3 is an intrinsic amorphous silicon layer formed by PECVD or hot filament CVD, or is an intrinsic amorphous silicon layer and an N-type amorphous silicon layer, or is a combination layer of an intrinsic amorphous silicon layer and a P-type amorphous silicon layer. The first amorphous silicon passivation layer 3 has a thickness of 1-10nm, such as 3nm, 5nm, 8nm, etc.
Preferably, when the first amorphous silicon passivation layer 3 is a combination layer, an intrinsic amorphous silicon layer is preferably deposited on the surface of the monocrystalline silicon wafer, and an N-type amorphous silicon layer or a P-type amorphous silicon layer is deposited on top of the intrinsic amorphous silicon layer.
In addition, for the front anti-reflection film layer 2, the material may be one or more mixed lamination layers of silicon nitride, silicon oxide and silicon oxynitride, and the thickness is 60-150nm, such as 60nm, 80nm, 100nm, 150nm, etc.
In S3, the hard mask is preferably integrated on a device, such as a CVD device, and the device is used to close the monocrystalline silicon body 1 to attach the hard mask to the monocrystalline silicon body 1 when the protruding layer is formed in S3, and the hard mask is separated from the monocrystalline silicon body 1 when etching and cleaning are required in S4.
The hard mask is generally made of a quartz plate or a graphite plate with higher purity, and patterns of relevant N areas or P areas are prepared on the hard mask in a hollowed-out mode, so that interval array arrangement is formed. For example, when a patterned amorphous silicon layer needs to be deposited, the hard mask can be directly covered on the monocrystalline silicon wafer 1, clinged to the monocrystalline silicon wafer 1, and then put into a CVD cavity together for depositing an amorphous silicon film. When the deposition is completed, an amorphous silicon thin film with a relevant pattern is formed on the single crystal silicon wafer 1.
In addition, the second intrinsic amorphous silicon passivation layer 4 and the P-type amorphous silicon layer 5 in S3 are deposited by PECVD or hot filament CVD, the thickness of each of which is 1-20nm and 1-20nm, and deposition by PECVD or hot filament CVD is a relatively common manner in the art at present, and will not be described in detail herein;
The first transparent conductive film TCO layer 6 is prepared by PVD or RPD method, the first transparent conductive film TCO layer 6 is made of any one of ITO, IWO, IMO, AZO materials, and the thickness is 120-200nm, such as 120nm, 150nm, 180nm, 200nm, etc. In this embodiment, the thickness of the TCO layer 6 of the first transparent conductive film is thicker, and no mask preparation is needed, so that the process is simplified.
In S4, specifically, the 3 film layers of the protruding layer are not deposited in the area covered by the hard mask, i.e. the area where the hard mask is not hollowed out, and still are monocrystalline silicon substrates, and the 3 film layers of the protruding layer are deposited in the area not covered by the hard mask, i.e. the area where the hard mask is hollowed out. In the step, the monocrystalline silicon wafer is taken out for etching and cleaning the hard mask, and a film layer deposited on the hard mask is not required to be cleaned in CVD equipment, and the place needing etching is the exposed silicon substrate. The etching liquid can etch the silicon substrate without damaging the lamination of the second amorphous silicon passivation layer 4, the P-type amorphous silicon layer 5 and the first transparent conductive film TCO layer 6. The general first transparent conductive film TCO layer 6 is acid and alkali resistant, and the silicon substrate can be etched by alkali, so that the exposed silicon substrate can be etched by using potassium hydroxide or sodium hydroxide with lower concentration and adding an etching additive, and the first transparent conductive film TCO layer 6 is not etched, which is also the reason why the first transparent conductive film TCO layer is thickened in the patent, preventing the TCO layer from being completely etched by etching liquid when the silicon substrate is etched. In addition, in this step, the thickness of the removed crystalline silicon substrate is 5-10 um, i.e., the depth of the recess is 5-10 um, such as 5um, 8um, 10um.
In S5, when the ink protection layer is printed, the four sides of the monocrystalline silicon piece 1 are grabbed for accurate printing, the ink material is covered on the first transparent conductive film TCO layer 6 on the back of the monocrystalline silicon piece, preferably also covered on the second amorphous silicon passivation layer 4 and the side area of the P-type amorphous silicon layer 5, and finally the ink is dried to form the ink protection layer 7, and the ink material is a compact insulating material after being dried, is acid corrosion resistant, and can be peeled off under alkaline solution. In the subsequent step S7, the ink protective layer may be peeled off using an alkaline solution for cleaning.
In S6, the three film layers are formed in a similar manner to that in S3, and the third intrinsic amorphous silicon passivation layer 8 and the N-type amorphous silicon layer 9 are deposited by PECVD or hot filament CVD methods, with thicknesses of 1-20nm and 1-20nm, respectively. The second transparent conductive thin film TCO layer 10 is prepared by PVD or RPD method, and the second transparent conductive thin film TCO layer 10 is made of any one of ITO, IWO, IMO, AZO and has a thickness of 80-150nm, such as 80nm, 100nm, 150nm.
In S8, the printed metal electrode is silver paste or silver-aluminum paste, the paste is printed on the P-type amorphous silicon layer 5 and the first transparent conductive film TCO layer 6 laminate, and the N-type amorphous silicon layer 9 and the transparent conductive film TCO layer 10 laminate, respectively, and after curing, the electrode is formed, the electrode on the P-type amorphous silicon layer 5 and the first transparent conductive film TCO layer 6 laminate is the positive electrode, and the electrode on the N-type amorphous silicon layer 9 and the transparent conductive film TCO layer 10 laminate is the negative electrode.
While the invention has been described in terms of embodiments, it will be appreciated by those skilled in the art that the invention is not limited thereto but rather includes the drawings and the description of the embodiments above. Any modifications which do not depart from the functional and structural principles of the present invention are intended to be included within the scope of the appended claims.
Claims (9)
1. The preparation method of the N-type HIBC solar cell is characterized by comprising the following steps of:
S1: selecting an N-type monocrystalline silicon wafer (1), and treating the back surface of the monocrystalline silicon wafer (1) as a polished surface and the front surface of the monocrystalline silicon wafer (1) as a suede;
S2: a first amorphous silicon passivation layer (3) and an antireflection film layer (2) are sequentially formed on the front surface of the monocrystalline silicon wafer (1), the antireflection film layer (2) is formed by deposition by a PECVD method and is one or a plurality of mixed lamination layers of silicon nitride, silicon oxide and silicon oxynitride, and the thickness is 60-150nm;
S3: the back of the monocrystalline silicon wafer (1) is covered by adopting a separable hard mask, the hard mask is covered by adopting interval arrangement, a convex layer is formed in a region which is not covered by the hard mask, and the convex layer sequentially comprises a second intrinsic amorphous silicon passivation layer (4), a P-type amorphous silicon layer (5) and a first transparent conductive film TCO layer (6);
s4: etching and cleaning the covering area of the hard mask on the back surface of the monocrystalline silicon wafer (1) in the step S3, and removing the crystalline silicon substrate in the area to form a groove;
S5: printing an ink mask material on the first transparent conductive film TCO layer (6) in the step S4 to form an ink protection layer (7);
s6: in the step S5, all areas on the back surface of the monocrystalline silicon wafer (1) are sequentially formed with a third intrinsic amorphous silicon passivation layer (8), an N-type amorphous silicon layer (9) and a second transparent conductive film TCO layer (10);
s7: in the step S6, cleaning the back surface of the monocrystalline silicon piece (1), and stripping the printing ink protective layer (7);
s8: printing a metal electrode on the lamination of the P-type amorphous silicon layer and the first transparent conductive film TCO layer (6), and curing at a low temperature; and brushing a metal electrode on the lamination of the N-type amorphous silicon layer (9) and the second transparent conductive film TCO layer (10), and curing at a low temperature.
2. The method for manufacturing an N-type HIBC solar cell as claimed in claim 1, wherein the hard mask is integrated on a device, the device is used to approach the monocrystalline silicon body (1) to adhere the hard mask to the monocrystalline silicon body (1) when the protruding layer is formed in S3, and the hard mask is separated from the monocrystalline silicon body (1) when etching and cleaning are required in S4.
3. The method for manufacturing an N-type HIBC solar cell as defined in claim 1, wherein the hard mask is a quartz plate or a graphite plate.
4. The method of claim 1, wherein the thickness of the removed crystalline silicon substrate in S4 is 5-10 um.
5. The method of claim 1, wherein the ink protective layer in S5 is alkaline and the cleaning in S7 is performed with an alkaline solution.
6. The method for manufacturing an N-type HIBC solar cell as claimed in claim 1, wherein in the step S1, the front surface of the monocrystalline silicon wafer (1) is manufactured into a pyramid suede by a mask method or a chain etching method.
7. The method for manufacturing an N-type HIBC solar cell as claimed in claim 1, wherein the first amorphous silicon passivation layer (3) has a thickness of 1-10nm and is an intrinsic amorphous silicon layer formed by PECVD or hot filament CVD, or is a combination of an intrinsic amorphous silicon layer and an N-type amorphous silicon layer, or is a combination of an intrinsic amorphous silicon layer and a P-type amorphous silicon layer.
8. The method for manufacturing an N-type HIBC solar cell as claimed in claim 1, wherein the second intrinsic amorphous silicon passivation layer (4) and the P-type amorphous silicon layer (5) are deposited by PECVD or hot filament CVD, and have thicknesses of 1-20nm and 1-20nm, respectively; and/or the third intrinsic amorphous silicon passivation layer (8) and the N-type amorphous silicon layer (9) are deposited by a PECVD (plasma enhanced chemical vapor deposition) or hot filament CVD method, and the thicknesses are respectively 1-20nm and 1-20nm.
9. The method for manufacturing an N-type HIBC solar cell according to claim 1, wherein the first transparent conductive thin film TCO layer (6) is manufactured by PVD or RPD method, and the first transparent conductive thin film TCO layer (6) is made of any one of ITO, IWO, IMO, AZO and has a thickness of 120-200nm; and/or the second transparent conductive film TCO layer (10) is prepared by PVD or RPD method, the second transparent conductive film TCO layer (10) is made of any one of ITO, IWO, IMO, AZO materials, and the thickness is 80-150nm.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
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